Composite substrate and preparation method thereof, semiconductor device, and electronic device

Abstract

The embodiments of the present application provide a composite substrate and a preparation method thereof, a semiconductor device, and an electronic device, which relate to the field of semiconductor technology and are used to solve the problem of high cost of AlxGayN-based semiconductor devices due to high cost of SiC. The composite substrate comprises: a carrier layer, a silicon carbide layer, and at least one epitaxial layer. The silicon carbide layer is arranged on the carrier layer and bonded to the carrier layer; the material of the silicon carbide layer includes single crystal silicon carbide. At least one epitaxial layer is arranged on the side of the silicon carbide layer away from the carrier layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a composite substrate and a preparation method thereof, a semiconductor device, and an electronic device. Background Art

[0002] Aluminum gallium nitride (AlxGayN, x≧0, y≧0) materials are often used to make high-voltage and high-frequency devices due to their excellent physical properties such as wide bandgap, fast electron saturation speed, and high critical breakdown field strength. Based on this, AlxGayN-based semiconductor devices have excellent switching speeds and low on-resistance, and are widely used in aerospace, wireless communications, photoelectric conversion, charging adapters and other fields. However, AlxGayN materials have no natural intrinsic crystals and have to be obtained by heteroepitaxial methods, making AlxGayN heteroepitaxial technology one of the key technologies restricting the development of the AlxGayN-based semiconductor device industry.

[0003] At present, in AlxGayN-based semiconductor devices, AlxGayN-based composite substrates include stacked AlxGayN and silicon carbide (SiC), stacked AlxGayN and aluminum oxide (Al2O3), stacked AlxGayN and silicon (Si), etc. Among them, SiC and AlxGayN have the smallest lattice mismatch and thermal mismatch. Therefore, the AlxGayN-based composite substrate including stacked AlxGayN and SiC has a low defect density and becomes an ideal structure for high-quality AlxGayN-based composite substrates.

[0004] However, due to the limitations of SiC crystal growth method and yield, the preparation cost of SiC is relatively high, resulting in a high preparation cost for composite substrates including stacked AlxGayN and SiC, which limits the widespread application of AlxGayN-based semiconductor devices in industrial and consumer products. Summary of the invention

[0005] The embodiments of the present application provide a composite substrate and a method for preparing the same, a semiconductor device, and an electronic device, which are used to solve the problem of high cost of AlxGayN-based semiconductor devices due to the high cost of SiC.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a composite substrate is provided, comprising: a carrier layer; a silicon carbide layer disposed on the carrier layer and bonded to the carrier layer; the material of the silicon carbide layer comprises single-crystal silicon carbide; and at least one epitaxial layer disposed on a side of the silicon carbide layer away from the carrier layer.

[0008] The preparation method of the composite substrate provided in the embodiment of the present application can effectively reduce cutting loss, improve yield and cutting efficiency by cutting the silicon carbide single crystal ingot by hydrogen ion implantation, and the remaining silicon carbide single crystal ingot can be reused as a silicon carbide single crystal ingot after polishing. Therefore, compared with the use of GaN single crystal substrate and SiC single crystal substrate, the preparation method of the composite substrate provided in the embodiment of the present application can improve the utilization rate of silicon carbide ingot and reduce costs. In addition, the surface of the composite substrate provided in the embodiment of the present application includes an epitaxial layer (III-V group nitride). Compared with the use of other film layers in semiconductor devices grown on non-single crystal SiC substrates, the composite substrate provided in the embodiment of the present application grows other film layers in semiconductor devices on the epitaxial layer. Due to the small lattice mismatch and thermal mismatch between the silicon carbide layer and the epitaxial layer, when other film layers are grown on the epitaxial layer, the epitaxial defect density is small, which can meet the production requirements of high-quality secondary epitaxy and semiconductor devices.

[0009] In a possible embodiment, the silicon carbide layer is directly bonded to the carrier layer, so that the distance between the silicon carbide layer and the carrier layer is small, and the thermal conductivity of the composite substrate is good.

[0010] In a possible embodiment, the thickness of the first bonding layer formed by direct contact bonding between the silicon carbide layer and the carrier layer is less than or equal to 5 nm. If the thickness of the first bonding layer is too large, the thermal conductivity of the composite substrate will be affected.

[0011] In a possible embodiment, the composite substrate further includes a transition layer, the transition layer is located between the silicon carbide layer and the carrier layer; the silicon carbide layer and the carrier layer are bonded to the transition layer respectively. The silicon carbide layer and the carrier layer are bonded through the transition layer, and the bonding effect is good and the bonding difficulty is low.

[0012] In a possible embodiment, the silicon carbide layer is bonded to the transition layer to form a second bonding layer, and the bearing layer is bonded to the transition layer to form a third bonding layer; the sum of the thicknesses of the transition layer, the second bonding layer, and the third bonding layer is less than or equal to 100 nm. If the sum of the thicknesses of the transition layer, the second bonding layer, and the third bonding layer is too large, the thermal conductivity of the composite substrate will be affected.

[0013] In a possible embodiment, the material of the epitaxial layer includes III-V nitride. The thermal mismatch and lattice mismatch between the III-V nitride and the silicon carbide layer are small.

[0014] In a possible embodiment, the material of the silicon carbide layer includes 4H crystal type or 6H crystal type silicon carbide. The thermal mismatch and lattice mismatch between the 4H crystal type or 6H crystal type silicon carbide and the epitaxial layer are small.

[0015] In a possible embodiment, the melting point of the material of the bearing layer is greater than or equal to 1260° C. This can prevent the bearing layer from melting during the annealing process and damaging its performance.

[0016] In a possible embodiment, the thickness of the silicon carbide layer is less than or equal to 350 um, which can avoid waste of resources and prevent the composite substrate from being too thick.

[0017] In a possible embodiment, the thickness of the carrier layer is less than or equal to 3000 um, which can avoid waste of resources and prevent the composite substrate from being too thick.

[0018] In a possible embodiment, the sum of the thickness of at least one epitaxial layer is less than or equal to 3000 um, which can avoid waste of resources and prevent the composite substrate from being too thick.

[0019] In a second aspect, a method for preparing a composite substrate is provided, comprising: performing hydrogen ion implantation from the back surface of a silicon carbide single crystal ingot into a silicon carbide single crystal ingot, so that the implanted ions reach a preset depth, a defect layer is formed at the preset depth, and a silicon carbide layer is formed on the side of the defect layer facing the back surface of the silicon carbide single crystal ingot; bonding the back surface of the silicon carbide single crystal ingot to a carrier layer to form a first composite structure; performing a first annealing treatment on the first composite structure, so that the silicon carbide layer is peeled off along the defect layer to form a second composite structure; the second composite structure includes a damaged layer separated from the defect layer, and a bonded silicon carbide layer and a carrier layer; performing surface treatment on a surface of the silicon carbide layer away from the carrier layer to remove the damaged layer to form a third composite structure; performing a second annealing treatment on the third composite structure to repair defects in the silicon carbide layer caused by hydrogen ion implantation; the annealing temperature of the second annealing treatment is greater than the temperature of the first annealing treatment; and forming at least one epitaxial layer on the surface of the silicon carbide layer away from the carrier layer to form a composite substrate.

[0020] The method for preparing the composite substrate provided in the embodiment of the present application can obtain the composite substrate of the first aspect, and its beneficial effects are the same as those of the composite substrate, which will not be described in detail here.

[0021] In a possible embodiment, before performing the second annealing treatment on the third composite structure, the preparation method further includes: forming a carbon protective film on the surface of the silicon carbide layer away from the carrier layer; before epitaxially growing at least one epitaxial layer on the surface of the silicon carbide layer away from the carrier layer, the preparation method further includes: removing the carbon protective film. By forming the carbon protective film on the surface of the silicon carbide layer away from the carrier layer, it is possible to avoid carbon evaporation and silicon precipitation in the silicon carbide layer due to excessively high temperature during the subsequent high-temperature annealing process, thereby causing the surface of the silicon carbide layer away from the carrier layer to become rough.

[0022] In a possible embodiment, the back surface of the silicon carbide single crystal ingot is bonded to the carrier layer, including: forming a transition layer on the back surface of the silicon carbide single crystal ingot or the carrier layer; bonding the back surface of the silicon carbide single crystal ingot to the carrier layer through the transition layer; the composite substrate also includes a transition layer located between the silicon carbide layer and the carrier layer.

[0023] In a possible embodiment, bonding the back surface of the silicon carbide single crystal ingot to the carrier layer includes: bonding the back surface of the silicon carbide single crystal ingot to the carrier layer in direct contact.

[0024] In a possible embodiment, the lattice direction of the silicon carbide single crystal ingot is along <0001> The lattice direction is deflected within a range of greater than or equal to 0° and less than or equal to 8°.

[0025] In a possible embodiment, the energy of hydrogen ion implantation is greater than or equal to 100 keV, the implantation dose is greater than or equal to 1e16 cm-2, and the ion implantation angle is within a range of greater than or equal to 5° and less than or equal to 20°. In this way, the defective layer formed can be a flat whole layer structure.

[0026] In one possible embodiment, the surface of the silicon carbide layer away from the carrier layer is surface treated to remove the damaged layer, including: using at least one of wet cleaning, plasma activation, high temperature annealing, chemical mechanical polishing, mechanical polishing, reactive ion etching, ion beam etching, or ion beam grazing incidence polishing to treat the surface of the silicon carbide layer away from the carrier layer to remove the damaged layer.

[0027] In a possible embodiment, the first annealing temperature is greater than or equal to 1000° C., and the annealing temperature of the second annealing treatment is greater than or equal to 1200° C.

[0028] In a possible embodiment, after surface treatment is performed on the surface of the silicon carbide layer away from the carrier layer, the roughness of the surface of the silicon carbide layer away from the carrier layer is less than or equal to 0.5 nm.

[0029] In a possible embodiment, the annealing environment of the first annealing treatment is at least one of N2, Ar or H2; the annealing environment of the second annealing treatment is at least one of vacuum, N2, Ar or C-containing gas.

[0030] In a third aspect, a semiconductor device is provided, comprising the composite substrate of any one of the first aspects, and a heterojunction; the heterojunction is arranged on a side of at least one epitaxial layer of the composite substrate away from the carrier layer.

[0031] In a fourth aspect, an electronic device is provided, comprising the semiconductor device and an antenna according to the third aspect; the semiconductor device is used to amplify the radio frequency signal and output it to the antenna for outward radiation.

[0032] In a fifth aspect, an electronic device is provided, comprising the semiconductor device of the third aspect and a printed circuit board; the semiconductor device is coupled to the printed circuit board; wherein the material of the carrier layer in the semiconductor device is a conductive material. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a base station provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of the structure of an AAU provided in an embodiment of the present application;

[0035] Figure 3A A schematic diagram of the structure of a charger provided in an embodiment of the present application;

[0036] Figure 3B A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0037] Figure 3C A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of a preparation process of a composite substrate provided in an embodiment of the present application;

[0039] Figure 5A A schematic diagram of a preparation process of a composite substrate provided in an embodiment of the present application;

[0040] Figure 5B A schematic diagram of a preparation process of a composite substrate provided in an embodiment of the present application;

[0041] Figure 6 A structural diagram of a composite substrate provided in an embodiment of the present application;

[0042] Fig. 7A A schematic diagram of another preparation process of a composite substrate provided in an embodiment of the present application;

[0043] Figure 7B A schematic diagram of a preparation process of another composite substrate provided in an embodiment of the present application;

[0044] Fig. 8A A structural diagram of another composite substrate provided in an embodiment of the present application;

[0045] Figure 8B A structural diagram of another composite substrate provided in an embodiment of the present application.

[0046] Reference numerals:

[0047] 1-base station; 2-charger; 101-baseband processing unit; 102-active antenna unit; 121-computing unit; 122-first transmission unit; 123-antenna unit; 1210-control unit; 1211-second transmission unit; 1212-baseband unit; 1213-power supply unit; 1221-RF unit; 1222-PA; 10-silicon carbide single crystal ingot; 11-silicon carbide layer; 12-remaining silicon carbide single crystal ingot; 20-defective layer; 21-damaged layer; 30-bearing layer; 41-first bonding layer; 42-transition layer; 43-second bonding layer; 44-third bonding layer; 50-carbon protective film; 60-epitaxial layer; 100-composite substrate; Q1-first composite structure; Q2-second composite structure; Q3-third composite structure. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0049] In the following, the terms "first", "second", etc. are used only for convenience of description and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0050] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "electrical connection" may refer to a direct electrical connection or an indirect electrical connection via an intermediate medium.

[0051] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0052] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0053] In the embodiments of the present application, directional indications such as up, down, left, right, front, and back, etc., used to explain the structure and movement of different components in the present application are relative. These indications are appropriate when the components are in the positions shown in the figures. However, if the description of the component position changes, then these directional indications will also change accordingly.

[0054] In the embodiments of the present application, the term "two-dimensional electron gas (2DEG)" means that the movement of electrons in the direction perpendicular to the interface is confined by the potential well and quantized, while their movement parallel to the surface is still free. Such free electrons in the two-dimensional direction are called two-dimensional electron gas.

[0055] In the embodiments of the present application, the term "back surface of the silicon carbide single crystal ingot" refers to the (000-1) crystal orientation plane of the silicon carbide single crystal ingot, and the "front surface of the silicon carbide single crystal ingot" refers to the (0001) crystal orientation plane of the silicon carbide single crystal ingot.

[0056] In the embodiments of the present application, the term “back surface of the silicon carbide layer” refers to the (000-1) crystal orientation plane of the silicon carbide layer, and the “front surface of the silicon carbide layer” refers to the (0001) crystal orientation plane of the silicon carbide layer.

[0057] The embodiment of the present application provides an electronic device, which may be, for example, a charger, a charging small household appliance (such as a soymilk machine, a sweeping robot), a drone, an aerospace equipment, a laser radar driver, a laser, a detector, a radar, a 5G (the 5th generation mobile network, the fifth generation mobile communication technology) communication device, and other different types of user equipment or terminal equipment; the electronic device may also be a network device such as a base station. The embodiment of the present application does not impose any special restrictions on the specific form of the electronic device.

[0058] A high electron mobility transistor (HEMT) device is a semiconductor device that is widely used as a radio frequency device or a power device due to its advantages such as high breakdown electric field, high channel electron concentration, high electron mobility and high temperature stability.

[0059] When the HEMT device is used as a radio frequency device, the structure of the electronic device is described by taking the electronic device as a base station as an example. Figure 1As shown, the base station 1 includes a baseband processing unit (BBU) 101 and an active antenna unit (AAU) 102. Among them, the BBU 101 is mainly responsible for baseband digital signal processing, such as FFT (fast fourier transform) / IFFT (inverse fast fourier transform), modulation / demodulation, channel coding / decoding, etc. Figure 2 As shown, AAU102 includes a computing unit 121, a first transmission unit 122 and an antenna unit 123. The computing unit 121 includes a control unit 1210, a second transmission unit 1211, a baseband unit 1212 and a power supply unit 1213. The control unit 1210, the second transmission unit 1211, the baseband unit 1212 and the power supply unit 1213 are electrically connected to each other. The control unit 1210 is responsible for the control of the radio frequency signal, the second transmission unit 1211 is responsible for the transmission of the radio frequency signal, the baseband unit 1212 is responsible for the conversion of digital signals and analog signals, and the baseband unit 1212 is, for example, a DAC (digital to analog converter). The DAC can convert the digital signal output by the BBU 101 into an analog signal. The power supply unit 1213 is electrically connected to the power supply 124, and is used to supply power to the control unit 1210, the second transmission unit 1211 and the baseband unit 1212 in the computing unit 121. The first transmission unit 122 is responsible for the transmission and amplification of the radio frequency signal. The first transmission unit 122 includes an RF (radio frequency) unit 1221 and a PA (power amplifier) ​​1222. The RF unit 1221 is used to convert the analog signal into a low-power radio frequency signal, and the PA 1222 is used to amplify the low-power radio frequency signal and output it to the antenna unit 123. The antenna unit 123 is responsible for radiating the radio frequency signal outward. Figure 2 As shown, the AAU 102 may include a plurality of RF units 1221, a plurality of PAs 1222, and a plurality of antenna units 123. It should be noted that the PAs 1222 may be HEMT devices.

[0060] It should be understood that when the HEMT device is used as a PA, the electronic device provided in the embodiment of the present application is not limited to Figure 1 and Figure 2 The base station shown, and any electronic device that needs to use a power amplifier to amplify a signal belong to the application scenarios of the embodiments of the present application.

[0061] When the HEMT device is used as a power device, the structure of the electronic device is described by taking the electronic device as a charger as an example. Figure 3A As shown, the charger 2 may include a power device, a resistor R, an inductor L, a capacitor C, etc. The power device may be, for example, a HEMT device. The HEMT device, the resistor R, the inductor L, and the capacitor C may be interconnected via a printed circuit board (PCB).

[0062] It should be understood that when the HEMT device is used as a power device, the electronic device provided in the embodiment of the present application is not limited to Figure 3A The charger shown, and any electronic device that requires the use of a power device belong to the application scenarios of the embodiments of the present application.

[0063] An example of a HEMT device structure is shown below: Figure 3B As shown, the normally-on HEMT device includes a substrate, an AlN (aluminum nitride) nucleation layer, a GaN (gallium nitride) buffer layer, an AlN insertion layer, an AlGaN (aluminum gallium nitride) barrier layer, a GaN cap layer, and a source (source, S), a drain (drain, D) and a gate (gate, G) arranged on the substrate.

[0064] like Figure 3C As shown, the normally-off HEMT device includes a substrate, an AlN nucleation layer, a GaN buffer layer, an AlN insertion layer, an AlGaN barrier layer, a gate cap layer, and a source (source, S), a drain (drain, D) and a gate (gate, G) arranged on the substrate.

[0065] Among them, the gate cap layer can adjust the energy band structure to deplete the electrons directly below the gate cap layer. 2DEG is in a pinch-off state without bias, and 2DEG cannot flow in the channel layer between the source S and the drain D, and the HEMT device is in a closed state.

[0066] The working principle of the HEMT device is as follows: the source S and the drain D form a conductive ohmic contact with the AlGaN barrier layer respectively, and the gate G forms a Schottky contact with the AlGaN barrier layer. The dotted line in the AlN insertion layer represents the 2DEG generated by polarization in the heterojunction formed by the AlN insertion layer and the AlGaN barrier layer in the HEMT device. The 2DEG is used to efficiently conduct electrons under the action of an electric field. The source S and the drain D are used to make the 2DEG flow in the AlN insertion layer between the source S and the drain D under the action of an electric field, and the conduction between the source S and the drain D occurs at the two-dimensional electron gas in the AlN insertion layer. The gate G is set between the source S and the drain D to allow or hinder the passage of the two-dimensional electron gas. Among them, the 2DEG has high conductivity, partly because the electrons are trapped in a very small area at the interface of the AlN insertion layer and the AlGaN barrier layer, thereby greatly improving the mobility of the electrons.

[0067] Wherein, when the HEMT device is used as a radio frequency device, the substrate in the HEMT device is a non-conductive substrate. When the HEMT device is used as a power device, the substrate in the HEMT device is a conductive substrate.

[0068] Aluminum gallium nitride (AlxGayN, x≧0, y≧0) materials are often used to make high-voltage and high-frequency devices due to their excellent physical properties such as wide bandgap, fast electron saturation velocity, and high critical breakdown field strength. Based on this, AlxGayN-based semiconductor devices have a wide range of uses in aerospace, wireless communications, photoelectric conversion, charging adapters, and other fields due to their excellent switching speed and low on-resistance.

[0069] In order to solve the problem that the cost of AlxGayN-based composite substrates including stacked AlxGayN and SiC is high due to the high cost of silicon carbide (SiC), which seriously limits the widespread application of AlxGayN-based semiconductor devices in industrial and consumer products.

[0070] A method for preparing a composite substrate is provided, wherein a GaN single crystal layer is firstly epitaxially grown on a sapphire substrate, and then the GaN single crystal layer is bonded to a supporting substrate having a stress compensation layer formed thereon, and then the sapphire substrate is peeled off to prepare a composite substrate. Figure 4 The composite substrate shown. Figure 4 As shown, the composite substrate includes a carrier substrate, a bonding dielectric layer and a GaN single crystal layer located on the carrier substrate, and a stress compensation layer on the back side of the carrier substrate.

[0071] Figure 4Although the composite substrate shown has the advantages of a GaN-based substrate, the growth of a GaN single crystal layer on a sapphire substrate still faces problems such as high technical complexity, thick growth thickness, and low yield, which makes it difficult to obtain and costly. Moreover, the stress compensation layer is a thin film dielectric layer, which has poor stability during subsequent processing, and stress aggravation or release may occur, resulting in a high defect density in the newly grown epitaxial layer, or even peeling or fragmentation of the GaN single crystal layer.

[0072] Based on this, an embodiment of the present application also provides a method for preparing a composite substrate. The composite substrate prepared by the method for preparing the composite substrate can be used to directly prepare AlxGayN-based devices with low defect density, and the preparation cost of the composite substrate is low, thereby improving the promotion and application of AlxGayN-based semiconductor devices in various fields.

[0073] The following is a description of the method for preparing the composite substrate provided in the embodiments of the present application using several examples.

[0074] Example 1

[0075] like Figure 5A As shown, the embodiment of the present application provides a method for preparing a composite substrate, comprising:

[0076] S10, such as Figure 5B As shown, hydrogen ions are implanted into the silicon carbide single crystal ingot 10 from the back surface a1 of the silicon carbide single crystal ingot 10, so that the implanted ions reach a preset depth X, a defect layer 20 is formed at the preset depth, and a silicon carbide layer 11 is formed on the side of the defect layer 20 facing the back surface a1 of the silicon carbide single crystal ingot 10.

[0077] That is, a portion of silicon carbide single-crystal ingot 10 located on the side of defect layer 20 facing back surface a1 of silicon carbide single-crystal ingot 10 serves as silicon carbide layer 11 .

[0078] In some embodiments, the lattice direction of the silicon carbide single crystal ingot 10 is along <0001> The lattice direction is deflected within a range of greater than or equal to 0° and less than or equal to 8°.

[0079] For example, the lattice direction of the silicon carbide single crystal ingot 10 is <0001> The lattice direction is not deflected (deflected 0°), and the lattice direction of the silicon carbide single crystal ingot 10 is along <0001> The lattice direction is deflected by 1°, and the lattice direction of the silicon carbide single crystal ingot 10 is along <0001> The lattice direction is deflected by 2°, and the lattice direction of the silicon carbide single crystal ingot 10 is along <0001> The lattice direction is deflected by 3°, and the lattice direction of the silicon carbide single crystal ingot 10 is along <0001> The lattice direction of the silicon carbide single crystal ingot 10 is deflected by 4° and the lattice direction is <0001> The lattice direction of the silicon carbide single crystal ingot 10 is deflected by 5° along the lattice direction. <0001> The lattice direction is deflected by 6°, and the lattice direction of the silicon carbide single crystal ingot 10 is along <0001> The lattice direction is deflected by 7°.

[0080] In this way, the lattice direction of the silicon carbide layer 11 obtained by the silicon carbide single crystal ingot 10 is also along <0001> The lattice direction is deflected within a range of greater than or equal to 0° and less than or equal to 8°, and the lattice mismatch between the silicon carbide layer 11 and the epitaxial layer is small, so that the defect density of the epitaxial growth can be reduced during subsequent epitaxial growth on the surface of the silicon carbide layer 11.

[0081] In order to ensure the formation of a complete and flat defect layer 20, in some embodiments, the energy of hydrogen ion implantation is greater than or equal to 100 keV. In some embodiments, the dose of hydrogen ion implantation is greater than or equal to 1e16 cm-2. In some embodiments, the angle of hydrogen ion implantation is within a range of greater than or equal to 5° and less than or equal to 20°. For example, the angle of hydrogen ion implantation is 10° or 15°. By adjusting the energy, dose and angle of hydrogen ion implantation, the structural morphology of the defect layer 20 can be adjusted.

[0082] That is, a defect layer 20 is formed at a preset depth X of the silicon carbide single crystal ingot 10 by hydrogen ion implantation. The defect layer 20 divides the silicon carbide single crystal ingot 10 into two parts, the part located on the defect layer 20 close to the back surface a1 of the silicon carbide single crystal ingot 10 is used as the silicon carbide layer 11, and the part located on the defect layer 20 away from the back surface a1 of the silicon carbide single crystal ingot 10 (close to the front surface a2 of the silicon carbide single crystal ingot 10) is used as the remaining silicon carbide single crystal ingot 12.

[0083] The remaining silicon carbide single crystal ingot 12 can be used as the silicon carbide single crystal ingot 10 for making the composite substrate next time after polishing. Of course, if the thickness of the remaining silicon carbide single crystal ingot 12 is just enough to be used as the silicon carbide layer 11, it can be directly used as the silicon carbide layer 11.

[0084] The thickness of the silicon carbide layer 11 can be adjusted by adjusting the preset depth X. In the process of hydrogen ion implantation, the implanted ions can be adjusted to reach the preset depth X by adjusting the energy of hydrogen ion implantation.

[0085] In some embodiments, the energy of hydrogen ion implantation is adjusted so that the thickness of the silicon carbide layer 11 is less than or equal to 350 um.

[0086] For example, the thickness of the silicon carbide layer 11 is 300 um, 250 um, 200 um, 150 um, or 100 um.

[0087] In some embodiments, the material of the silicon carbide single crystal ingot 10 includes 4H or 6H crystalline silicon carbide. In this way, the material of the silicon carbide layer 11 prepared by the silicon carbide single crystal ingot 10 also includes 4H or 6H crystalline silicon carbide. When an epitaxial layer is subsequently formed on the surface of the silicon carbide layer 11, the lattice mismatch between the silicon carbide layer 11 and the epitaxial layer is small, and the defect density of the epitaxial layer is small.

[0088] In some embodiments, the back surface a1 of the silicon carbide single crystal ingot 10 is arranged opposite to the front surface a2 of the silicon carbide single crystal ingot 10 , and the back surface a1 of the silicon carbide single crystal ingot 10 and the front surface a2 of the silicon carbide single crystal ingot 10 have the same roughness requirement.

[0089] S20, such as Figure 5B As shown, the back surface a1 of the silicon carbide single crystal ingot 10 is bonded to the carrier layer 30 to form a first composite structure Q1.

[0090] In some embodiments, the thickness of the carrier layer 30 is less than or equal to 3000 um.

[0091] For example, the thickness of the bearing layer 30 is 2500um, 2000um, 1500um, 1000um, 500um, etc.

[0092] The bearing layer 30 only needs to support the silicon carbide single crystal ingot 10 . If the bearing layer 30 is too thick, it will cause a waste of resources and increase the thickness of the composite substrate.

[0093] When preparing the composite substrate, there are two high-temperature annealing processes in the subsequent preparation process, and the second annealing temperature is higher than the first annealing temperature.

[0094] Based on this, in order to prevent the morphology of the carrier layer 30 from changing during the subsequent annealing process, in some embodiments, the melting point of the material of the carrier layer 30 is greater than the temperature of the second annealing process. For example, the melting point of the material of the carrier layer 30 is greater than or equal to 1260°C.

[0095] In some embodiments, the material of the carrier layer 30 includes a conductive substrate such as Si (silicon) and SiC (silicon carbide), an insulating substrate such as SiO2 (silicon oxide), Si3N4 (silicon nitride), Al2O3 (aluminum oxide), or a composite multilayer substrate including multiple materials above. The above materials can be single crystal, polycrystalline or amorphous structures.

[0096] Wherein, when the material of the carrier layer 30 is a conductive substrate, the composite substrate is a conductive substrate. When the material of the carrier layer 30 is an insulating substrate, the composite substrate is an insulating substrate. Therefore, by selecting the material of the carrier layer 30, the HEMT device using the composite substrate can be used as a radio frequency device or a power device.

[0097] In some embodiments, the back surface a1 of the silicon carbide single crystal ingot 10 is directly bonded to the carrier layer 30 .

[0098] That is, the back surface a1 of the silicon carbide single crystal ingot 10 faces the carrier layer 30 , and the silicon carbide single crystal ingot 10 is directly contacted and bonded to the carrier layer 30 .

[0099] It can be understood that the silicon carbide layer 11 is obtained from the silicon carbide single crystal ingot 10, and the back surface a1 of the silicon carbide single crystal ingot 10 is also the back surface c1 of the silicon carbide layer 11. Therefore, the back surface a1 of the silicon carbide single crystal ingot 10 is directly contacted and bonded with the carrier layer 30, that is, the back surface a1 of the silicon carbide layer 11 is directly contacted and bonded with the carrier layer 30. In the prepared composite substrate, the silicon carbide layer 11 is directly contacted and bonded with the carrier layer 30.

[0100] For example, the back surface a1 of the silicon carbide single crystal ingot 10 and the carrier layer 30 are cleaned and treated, and then the back surface a1 of the silicon carbide single crystal ingot 10 is directly contact-bonded to the carrier layer 30 .

[0101] The surface treatment method for the back surface a1 of the silicon carbide single crystal ingot 10 and the carrier layer 30 may include at least one of wet cleaning, activation, chemical activation, plasma activation, and metal deposition.

[0102] In addition, direct contact bonding between the back surface a1 of the silicon carbide single crystal ingot 10 and the carrier layer 30 can be performed at room temperature, high temperature, high pressure, normal pressure or vacuum, and the present embodiment of the application does not limit this.

[0103] It is understandable that the first bonding layer 41 is naturally formed during the direct contact bonding process between the back surface a1 of the silicon carbide single crystal ingot 10 and the carrier layer 30. The thickness of the first bonding layer 41 can be controlled by controlling the bonding time between the back surface a1 of the silicon carbide single crystal ingot 10 and the carrier layer 30.

[0104] In some embodiments, the thickness of the first bonding layer 41 is less than or equal to 5 nm. For example, the thickness of the first bonding layer 41 is 1 nm, 2 nm, 3 nm, or 4 nm.

[0105] Since the thickness of the first bonding layer 41 is too large, it affects the thermal conductivity of the composite substrate. Therefore, the thickness of the first bonding layer 41 is controlled to be less than or equal to 5 nm, and the thickness of the first bonding layer 41 is minimized while ensuring that the back surface a1 of the silicon carbide single crystal ingot 10 is in direct contact and bonding with the carrier layer 30.

[0106] Based on this, it can be understood that the first composite structure Q1 includes a silicon carbide single crystal ingot 10 , a first bonding layer 41 and a carrier layer 30 .

[0107] S30, such as Figure 5B As shown, the first composite structure Q1 is subjected to a first annealing treatment, so that the silicon carbide layer 11 is peeled off along the defective layer 20 to form a second composite structure Q2.

[0108] The second composite structure Q2 includes a damaged layer 21 separated from the defective layer 20, and a bonded silicon carbide layer 11 and a carrier layer 30, wherein the damaged layer 21 is located on a surface of the silicon carbide layer 11 away from the carrier layer 30 (the front surface c2 of the silicon carbide layer 11).

[0109] The first composite structure Q1 is subjected to a first annealing treatment. For example, the first composite structure Q1 may be subjected to a thermal annealing process.

[0110] In some embodiments, the annealing temperature of the first annealing treatment performed on the first composite structure Q1 may be greater than or equal to 1000° C. For example, the annealing temperature of the first annealing treatment is 1050° C., 1100° C., or 1150° C.

[0111] In some embodiments, the annealing environment of the first annealing process performed on the first composite structure Q1 is at least one of N2 (nitrogen), Ar (argon), or H2 (hydrogen).

[0112] The embodiment of the present application does not limit the annealing time of the first annealing treatment, and it can be reasonably determined according to factors such as the thickness of the defective layer 20 so that the defective layer 20 can be naturally cracked to obtain the above-mentioned second composite structure Q2.

[0113] S40, such as Figure 5B As shown, the surface (front surface c2 ) of the silicon carbide layer 11 away from the carrier layer 30 is processed to remove the damaged layer 21 , thereby forming a third composite structure Q3 .

[0114] In some embodiments, the surface (front surface c2) of the silicon carbide layer 11 away from the supporting layer 30 is processed by one or more processes including wet cleaning, plasma activation, high temperature annealing, CMP, CP, mechanical polishing, reactive ion etching, ion beam etching, or ion beam grazing incidence polishing to remove the damaged layer 21.

[0115] It can be understood that by processing the surface of the silicon carbide layer 11 away from the supporting layer 30 (the front surface c2), the damaged layer 21 can be removed, and the obtained third composite structure Q3 includes a bonded silicon carbide layer 11 and a supporting layer 30 (for example, the silicon carbide layer 11, the first bonding layer 41 and the supporting layer 30).

[0116] In some embodiments, the process for processing the surface (front surface c2) of the silicon carbide layer 11 away from the supporting layer 30 includes at least one or more of CMP, CP, and mechanical polishing to reduce the roughness of the surface (front surface c2) of the silicon carbide layer 11 away from the supporting layer 30.

[0117] In some embodiments, after surface treatment is performed on the surface of the silicon carbide layer 11 away from the carrier layer 30 , the roughness of the surface of the silicon carbide layer 11 away from the carrier layer 30 is less than or equal to 0.5 nm.

[0118] That is, the roughness of the front surface c2 of the silicon carbide layer 11 is less than or equal to 0.5 nm, so as to meet the roughness requirement of the front surface c2 of the silicon carbide layer 11 when an epitaxial layer is formed on the front surface c2 of the silicon carbide layer 11 .

[0119] S50, such as Figure 5B As shown, a carbon protective film 50 is formed on a surface (front surface c2 ) of the silicon carbide layer 11 away from the carrier layer 30 .

[0120] For example, the carbon protection film 50 may be formed on the surface (front surface c2 ) of the silicon carbide layer 11 away from the carrier layer 30 by a sputtering process.

[0121] Since too thick a carbon protective film 50 will cause a waste of resources, and too thin a carbon protective film 50 will not provide protection. In some embodiments, the thickness of the carbon protective film 50 is 10-50 nm. For example, the thickness of the carbon protective film 50 is 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm.

[0122] By forming a carbon protective film 50 on the surface (front surface c2) of the silicon carbide layer 11 away from the carrier layer 30, it is possible to avoid carbon evaporation and silicon precipitation in the silicon carbide layer 11 due to too high a temperature during the subsequent high-temperature annealing process, thereby roughening the surface (front surface c2) of the silicon carbide layer 11 away from the carrier layer 30.

[0123] S60, such as Figure 5B As shown, the third composite structure Q3 is subjected to a second annealing treatment to repair defects in the silicon carbide layer 11 caused by hydrogen ion implantation.

[0124] It can be understood that when a carbon protective film 50 is formed on the surface of the silicon carbide layer 11 away from the supporting layer 30 (the front surface c2), that is, when the preparation method of the composite substrate includes step S50, the third composite structure Q3 is subjected to a second annealing treatment, that is, the structure covered with the carbon protective film 50 on the surface of the third composite structure Q3 is treated.

[0125] The third composite structure Q3 is subjected to a second annealing treatment, for example, a thermal annealing process may be used to treat the third composite structure Q3, wherein the annealing temperature of the second annealing treatment is greater than the annealing temperature of the first annealing treatment.

[0126] In some embodiments, the annealing temperature of the second annealing treatment performed on the third composite structure Q3 may be greater than or equal to 1200° C. For example, the annealing temperature of the second annealing treatment is 1250° C., 1300° C., 1350° C., 1400° C., etc.

[0127] In some embodiments, the annealing environment for performing the second annealing process on the third composite structure Q3 is at least one of normal pressure, vacuum, N2, Ar, or C (carbon) containing gas.

[0128] The embodiment of the present application does not limit the annealing time of the second annealing treatment, as long as it can repair the defects caused by hydrogen ion implantation in the silicon carbide layer 11. In addition, the repaired defects here can be completely repaired or repaired to a certain extent, depending on actual needs.

[0129] S70, such as Figure 5B As shown, the carbon protective film 50 is removed.

[0130] For example, the carbon protection film 50 may be removed by a high temperature oxidation or plasma treatment process.

[0131] It should be noted that, in some embodiments, the method for preparing the composite substrate does not include the above step S50, that is, before the third composite structure Q3 is subjected to the second annealing treatment, the carbon protective film 50 is not formed, and the third composite structure Q3 is directly subjected to the second annealing treatment. In this way, the method for preparing the composite substrate does not include the above step S70 either.

[0132] S80, such as Figure 5B As shown, at least one epitaxial layer 60 is formed on the surface of the silicon carbide layer 11 away from the carrier layer 30 to form a composite substrate 100 .

[0133] For example, one or more epitaxial layers 60 may be formed by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) growth processes. The materials of the multiple epitaxial layers 60 may be the same, different, or not completely the same.

[0134] In some embodiments, the material of epitaxial layer 60 includes III-V nitrides.

[0135] Illustratively, the material of the epitaxial layer 60 includes AlxGayN (where x≧0, y≧0).

[0136] For example, an AlN epitaxial layer, a GaN epitaxial layer, an AlGaN epitaxial layer, or a plurality of nitride epitaxial layers are formed on the surface of the silicon carbide layer 11 away from the carrier layer 30 .

[0137] In some embodiments, the sum of the thicknesses of the at least one epitaxial layer 60 is less than or equal to 3000 um.

[0138] The sum of the thickness of at least one epitaxial layer 60 can be understood as, when one epitaxial layer 60 is formed on the surface of the silicon carbide layer 11 away from the carrier layer 30, the thickness of the epitaxial layer 60 is less than or equal to 3000um. When multiple epitaxial layers 60 are formed on the surface of the silicon carbide layer 11 away from the carrier layer 30, the sum of the thickness of the multiple epitaxial layers 60 is less than or equal to 3000um.

[0139] For example, the sum of the thicknesses of at least one epitaxial layer 60 is 2500um, 2000um, 1500um, 1000um, 500um, 400um, 300um, 200um, 100um, 90um, 80um, 70um, 60um, 50um, 40um, 30um, 20um, 10um, 9um, 8um, 7um, 6um, 5um, 4um, 3um, 2um, 1um, etc.

[0140] If the carrier layer 30 is too thick, it will cause a waste of resources and increase the thickness of the composite substrate.

[0141] The method for preparing the composite substrate provided in this example is described below with two specific embodiments.

[0142] The method for preparing the composite substrate comprises:

[0143] Non-conductive type using hydrogen ion (H+) implantation <0001> A defect layer 20 is formed at a predetermined depth X on the back surface of the 4H-oriented silicon carbide single crystal ingot 10 .

[0144] The temperature of hydrogen ion implantation is room temperature, the energy of hydrogen ion implantation is 100 keV, the dose of hydrogen ion implantation is 1e17 cm-2, and the angle of hydrogen ion implantation is 7°.

[0145] The back surface of the silicon carbide single crystal ingot 10 and the Si3N4 substrate (carrying layer 30) are cleaned with chemical liquid and blown dry; then the back surface a1 of the silicon carbide single crystal ingot 10 and the Si3N4 substrate are activated by Ar or N2 or O2 (oxygen) plasma; then the back surface a1 of the silicon carbide single crystal ingot 10 and the Si3N4 substrate are directly bonded under a vacuum environment of 200°C and 10-4mbar to form a first composite structure Q1.

[0146] Among them, the bonding pressure is 10kN and the bonding time is 120min.

[0147] The first composite structure Q1 is placed in a high temperature annealing furnace, heated to 1000°C at a rate of 20°C / s in a N2 protective environment, annealed for 60 minutes, and then cooled out of the furnace. The silicon carbide single crystal ingot 10 is automatically peeled off along the defect layer 20 to form a second composite structure Q2.

[0148] The second composite structure Q2 includes a damaged layer 21 separated from the defective layer 20, and a bonded silicon carbide layer 11 and a carrier layer 30, and the damaged layer 21 is located on the surface of the silicon carbide layer 11 away from the carrier layer 30. The remaining silicon carbide single crystal ingot 12 can be used as a silicon carbide single crystal ingot 10 for making a composite substrate next time after polishing the peeling surface.

[0149] The surface of the silicon carbide layer 11 in the second composite structure Q2 away from the bearing layer 30 is surface treated to remove the damaged layer 21 and to make the surface roughness of the silicon carbide layer 11 less than or equal to 0.5 nm, thereby obtaining a third composite structure Q3.

[0150] For example, the surface is first dry-polished with a 8000# grinding wheel to a surface roughness of 10 nm, and then the surface is ground with CMP to a surface roughness of less than or equal to 0.5 nm for the silicon carbide layer 11 .

[0151] A 20 nm thick carbon protective film 50 is sputtered on the surface of the silicon carbide layer 11 away from the carrier layer 30 ; then, the carbon protective film 50 is completely etched using oxygen-containing plasma after annealing for 60 minutes at 1200° C. in a vacuum environment.

[0152] Then, an AlN epitaxial layer and a GaN epitaxial layer are epitaxially grown in sequence on the surface of the silicon carbide layer 11 away from the carrier layer 30 to form a composite substrate 100 .

[0153] Alternatively, the method for preparing the composite substrate comprises:

[0154] Non-conductive type using hydrogen ion implantation <0001> A defect layer 20 is formed at a predetermined depth X on the back surface of a 6H-oriented silicon carbide single crystal ingot 10 .

[0155] The temperature of hydrogen ion implantation is room temperature, the energy of hydrogen ion implantation is 200 keV, the dose of hydrogen ion implantation is 1e17 cm-2, and the angle of hydrogen ion implantation is 7°.

[0156] The back surface of the silicon carbide single crystal ingot 10 and the Si3N4 substrate (carrying layer 30) are cleaned with chemical liquid and blown dry; then the back surface a1 of the silicon carbide single crystal ingot 10 and the Si3N4 substrate are activated by Ar or N2 or O2 (oxygen) plasma; then the back surface a1 of the silicon carbide single crystal ingot 10 and the Si3N4 substrate are directly bonded at room temperature and in an N2-filled environment to form a first composite structure Q1.

[0157] Among them, the bonding pressure is 15kN and the bonding time is 180min.

[0158] The first composite structure Q1 is placed in a high temperature annealing furnace and annealed by laser heating rapid thermal annealing. Under a N2 protective environment, the annealing temperature is 1100°C for 60 minutes, and then the silicon carbide single crystal ingot 10 is automatically peeled off along the defect layer 20 to form a second composite structure Q2.

[0159] First, the surface is dry-polished with a 8000# grinding wheel until the surface roughness reaches 10 nm, and then the surface is ground with CMP until the surface roughness of the silicon carbide layer 11 reaches less than or equal to 0.5 nm.

[0160] A 20nm carbon protective film 50 is sputtered on the surface of the silicon carbide layer 11 away from the carrier layer 30; then, in an annealing environment filled with CH4 / Ar mixed gas, the annealing temperature is 1350°C, and the furnace is taken out after annealing for 30 minutes; then, oxygen-containing plasma is used to completely etch the carbon protective film 50 to form a composite substrate that meets the requirements of epitaxial growth.

[0161] Then, an AlN epitaxial layer and a GaN epitaxial layer are epitaxially grown in sequence on the surface of the silicon carbide layer 11 away from the carrier layer 30 to form a composite substrate 100 .

[0162] Based on this, Figure 6 As shown, the embodiment of the present application provides a composite substrate 100, including: a silicon carbide layer 11, a carrier layer 30 and at least one epitaxial layer 60 ( Figure 6 ). An epitaxial layer 60 is used as an illustration.

[0163] The silicon carbide layer 11 is prepared by the above-mentioned silicon carbide single crystal ingot 10, and the material of the silicon carbide layer 11 includes single crystal silicon carbide, or it can be understood that the silicon carbide layer 11 is a silicon carbide single crystal wafer.

[0164] The carrier layer 30 is disposed on the back surface c1 side of the silicon carbide layer 11, and the silicon carbide layer 11 is disposed on the carrier layer 30, with the back surface c1 of the silicon carbide layer 11 facing the carrier layer 30, and the back surface c1 of the silicon carbide layer 11 is bonded to the carrier layer 30. That is, the silicon carbide layer 11 is bonded to the carrier layer 30.

[0165] In some embodiments, Figure 6 As shown, the back surface c1 of the silicon carbide layer 30 is directly bonded to the carrier layer 30. The back surface c1 of the silicon carbide layer 30 is directly bonded to the carrier layer 30 to form a first bonding layer 41.

[0166] At least one epitaxial layer 60 is disposed on a side of the silicon carbide layer 11 away from the carrier layer 30 .

[0167] Example 2

[0168] The difference between Example 2 and Example 1 is that the silicon carbide layer 11 and the carrier layer 30 are bonded via a transition layer 42 .

[0169] The present application also provides a method for preparing a composite substrate. Fig. 7A As shown, including:

[0170] S100, such as Figure 7B As shown, hydrogen ions are implanted into the silicon carbide single crystal ingot 10 from the back surface a1 of the silicon carbide single crystal ingot 10, so that the implanted ions reach a preset depth X, a defect layer 20 is formed at the preset depth, and a silicon carbide layer 11 is formed on the side of the defect layer 20 facing the back surface a1 of the silicon carbide single crystal ingot 10.

[0171] That is, a portion of silicon carbide single-crystal ingot 10 located on the side of defect layer 20 facing back surface a1 of silicon carbide single-crystal ingot 10 serves as silicon carbide layer 11 .

[0172] Step S100 may be the same as step S10 in Example 1, and reference may be made to the above related description, which will not be repeated here.

[0173] S200, such as Figure 7B As shown, transition layer 42 is formed on back surface a1 of silicon carbide single crystal ingot 10 .

[0174] Alternatively, step S200 is not executed, and the following step S200' is executed.

[0175] Alternatively, both step S200 and step S200 ′ are performed.

[0176] S200 ′, forming a transition layer 42 on the carrier layer 30 .

[0177] For example, the transition layer 42 may be formed by a sputtering process.

[0178] The material of the transition layer 42 may, for example, include insulating media such as SiO2 (silicon oxide), Si3N4 (silicon nitride), Al2O3 (aluminum oxide), or conductive media such as Si (silicon), SiC (silicon carbide), or metals such as Al (aluminum), Cu (copper), Pt (platinum), Ni (nickel), Ti (titanium), Au (gold), Cr (chromium), or a composite multilayer material including multiple materials above.

[0179] S300, such as Figure 7B As shown, the back surface a1 of the silicon carbide single crystal ingot 10 is bonded to the support layer 30 via the transition layer 42 to form a first composite structure Q1.

[0180] The second bonding layer 43 is naturally formed during the bonding process between the back surface a1 of the silicon carbide single crystal ingot 10 and the transition layer 42. The third bonding layer 44 is naturally formed during the bonding process between the carrier layer 30 and the transition layer 42.

[0181] Based on this, it can be understood that the first composite structure Q1 includes a silicon carbide single crystal ingot 10 , a second bonding layer 43 , a transition layer 42 , a third bonding layer 44 and a bearing layer 30 .

[0182] In some embodiments, the sum of the thicknesses of the transition layer 42, the second bonding layer 43 and the third bonding layer 44 is less than or equal to 100 nm. For example, the sum of the thicknesses of the transition layer 42, the second bonding layer 43 and the third bonding layer 44 is 90 nm, 80 nm, 70 nm or 60 nm.

[0183] Since the sum of the thicknesses of the transition layer 42, the second bonding layer 43 and the third bonding layer 44 is too large, the thermal conductivity of the composite substrate is affected. Therefore, the sum of the thicknesses of the transition layer 42, the second bonding layer 43 and the third bonding layer 44 is controlled to be less than or equal to 100 nm, and the sum of the thicknesses of the transition layer 42, the second bonding layer 43 and the third bonding layer 44 is minimized on the basis of ensuring that the back surface a1 of the silicon carbide single crystal ingot 10 is stably bonded to the bearing layer 30.

[0184] As can be seen from the description of Example 1, the sum of the thicknesses of the transition layer 42 , the second bonding layer 43 and the third bonding layer 44 can be controlled by controlling the bonding time between the back surface a1 of the silicon carbide single crystal ingot 10 and the carrier layer 30 .

[0185] S400, such as Figure 7BAs shown, the first composite structure Q1 is subjected to a first annealing treatment, so that the silicon carbide layer 11 is peeled off along the defective layer 20 to form a second composite structure Q2.

[0186] The process of performing the first annealing treatment on the first composite structure Q1 can refer to the description of step S30 in Example 1, except that the obtained second composite structure Q2 includes the damaged layer 21 separated from the defective layer 20, and the bonded silicon carbide layer 11, transition layer 42 and bearing layer 30.

[0187] S500, such as Figure 7B As shown, the surface (front surface c2 ) of the silicon carbide layer 11 away from the carrier layer 30 is processed to remove the damaged layer 21 , thereby forming a third composite structure Q3 .

[0188] The process of processing the front surface c2 of the silicon carbide layer 11 may refer to the description of step S40 in Example 1, except that the obtained third composite structure Q3 includes the bonded silicon carbide layer 11 , the transition layer 42 and the bearing layer 30 .

[0189] S600, such as Figure 7B As shown, a carbon protective film 50 is formed on a surface (front surface c2 ) of the silicon carbide layer 11 away from the carrier layer 30 .

[0190] Step S600 may be the same as step S50 in Example 1, and reference may be made to the relevant description, which will not be repeated here.

[0191] S700, such as Figure 7B As shown, the third composite structure Q3 is subjected to a second annealing treatment to repair defects in the silicon carbide layer 11 caused by hydrogen ion implantation.

[0192] Step S700 may be the same as step S60 in Example 1, and the relevant description may be referred to, which will not be repeated here.

[0193] S800, such as Figure 7B As shown, the carbon protective film 50 is removed.

[0194] Step S800 may be the same as step S70 in Example 1, and reference may be made to the relevant description, which will not be repeated here.

[0195] S900, such as Figure 7B As shown, at least one epitaxial layer 60 is formed on the surface of the silicon carbide layer 11 away from the carrier layer 30 to form a composite substrate 100 .

[0196] Step S900 may be the same as step S80 in Example 1, and the relevant description may be referred to, which will not be repeated here. The difference is that the obtained composite substrate further includes a transition layer 42 , and the transition layer 42 is located between the back surface a1 of the silicon carbide layer 11 and the carrier layer 30 .

[0197] Based on this, Fig. 8A As shown, the embodiment of the present application provides a composite substrate 100, including: a silicon carbide layer 11, a transition layer 42, a carrier layer 30 and at least one epitaxial layer 60 ( Fig. 8A ). An epitaxial layer 60 is used as an illustration.

[0198] The transition layer 42 is located between the back surface a1 of the silicon carbide layer 11 and the carrier layer 30 , and the silicon carbide layer 11 and the carrier layer 30 are bonded via the transition layer 42 .

[0199] For example, Figure 8B As shown, the silicon carbide layer 11 is bonded to the transition layer 42 to form a second bonding layer 43 , and the carrier layer 30 is bonded to the transition layer 42 to form a third bonding layer 44 .

[0200] The method for preparing the composite substrate provided in the embodiment of the present application performs hydrogen ion implantation on the silicon carbide single crystal ingot 10 to form an implantation defect layer 20, and then bonds with the carrier layer 30. The bonded composite structure is subjected to high temperature annealing to form a composite structure including the carrier layer 30 and the silicon carbide layer 11 and a remaining silicon carbide single crystal ingot 12. The remaining silicon carbide single crystal ingot 12 can be reused as the silicon carbide single crystal ingot 10 after polishing. After the composite structure is surface polished and annealed at high temperature, one or more epitaxial layers 60 (III-V nitride) are formed on the surface of the silicon carbide layer 11 away from the carrier layer 30 to form an AlxGayN composite substrate 100.

[0201] The method for preparing the composite substrate provided in the embodiment of the present application can effectively reduce cutting loss, improve yield and cutting efficiency by cutting the silicon carbide single crystal ingot 10 by hydrogen ion implantation, and the remaining silicon carbide single crystal ingot 12 can be reused as the silicon carbide single crystal ingot 10 after polishing. Therefore, compared with the use of GaN single crystal substrate and SiC single crystal substrate, the method for preparing the composite substrate provided in the embodiment of the present application can improve the utilization rate of silicon carbide ingots and reduce costs.

[0202] In addition, the surface of the composite substrate 100 provided in the embodiment of the present application includes an epitaxial layer 60 (III-V nitride). Compared with growing other film layers in semiconductor devices on a non-single crystal SiC substrate, when the composite substrate 100 provided in the embodiment of the present application grows other film layers in semiconductor devices on the epitaxial layer 60, since the lattice mismatch and thermal mismatch between the silicon carbide layer 11 and the epitaxial layer 60 are small, therefore, when other film layers are grown on the epitaxial layer 60, the epitaxial defect density is small, which can meet the requirements of high-quality secondary epitaxy and semiconductor device manufacturing.

[0203] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A composite substrate, characterized in that: include: A bearing layer, wherein the melting point of the material of the bearing layer is greater than or equal to 1260° C.; A silicon carbide layer, disposed on the carrier layer and bonded to the carrier layer; The material of the silicon carbide layer includes single crystal silicon carbide; the roughness of the surface of the silicon carbide layer away from the bearing layer is less than or equal to 0.5 nm, and the lattice direction of the silicon carbide layer is along <0001> The lattice direction is deflected within the range of greater than or equal to 0° and less than or equal to 8°; At least one epitaxial layer is arranged on a side of the silicon carbide layer away from the carrier layer.

2. The composite substrate according to claim 1, characterized in that The silicon carbide layer is directly contacted and bonded to the carrier layer.

3. The composite substrate according to claim 2, characterized in that The thickness of the first bonding layer formed by direct contact bonding between the silicon carbide layer and the carrier layer is less than or equal to 5 nm.

4. The composite substrate according to claim 1, characterized in that The composite substrate further includes a transition layer, which is located between the silicon carbide layer and the carrier layer; the silicon carbide layer and the carrier layer are bonded to the transition layer respectively.

5. The composite substrate according to claim 4, characterized in that The silicon carbide layer is bonded to the transition layer to form a second bonding layer, and the bearing layer is bonded to the transition layer to form a third bonding layer; The sum of the thicknesses of the transition layer, the second bonding layer and the third bonding layer is less than or equal to 100 nm.

6. The composite substrate according to any one of claims 1 to 5, characterized in that: The material of the epitaxial layer includes III-V group nitride.

7. The composite substrate according to any one of claims 1 to 5, characterized in that: The material of the silicon carbide layer includes 4H crystal type or 6H crystal type silicon carbide.

8. The composite substrate according to any one of claims 1 to 5, characterized in that: The thickness of the silicon carbide layer is less than or equal to 350um; and / or, The thickness of the bearing layer is less than or equal to 3000um; and / or, The sum of the thickness of the at least one epitaxial layer is less than or equal to 3000 um.

9. A method for preparing a composite substrate, characterized in that: include: Performing hydrogen ion implantation from the back surface of the silicon carbide single crystal ingot into the silicon carbide single crystal ingot, so that the implanted ions reach a preset depth, a defect layer is formed at the preset depth, and a silicon carbide layer is formed on a side of the defect layer facing the back surface of the silicon carbide single crystal ingot; Bonding the back surface of the silicon carbide single crystal ingot to a bearing layer to form a first composite structure; Performing a first annealing treatment on the first composite structure so that the silicon carbide layer is peeled off along the defective layer to form a second composite structure; the second composite structure includes a damaged layer separated from the defective layer, and the bonded silicon carbide layer and the bearing layer; Performing surface treatment on the surface of the silicon carbide layer away from the bearing layer to remove the damaged layer and form a third composite structure; performing a second annealing treatment on the third composite structure to repair defects in the silicon carbide layer caused by hydrogen ion implantation; The annealing temperature of the second annealing treatment is greater than the temperature of the first annealing treatment; At least one epitaxial layer is formed on a surface of the silicon carbide layer away from the carrier layer to form the composite substrate.

10. The method for preparing a composite substrate according to claim 9, characterized in that: Before performing the second annealing treatment on the third composite structure, the preparation method further comprises: forming a carbon protective film on a surface of the silicon carbide layer away from the supporting layer; Before epitaxially growing at least one epitaxial layer on the surface of the silicon carbide layer away from the carrier layer, the preparation method further comprises: removing the carbon protective film.

11. The method for preparing a composite substrate according to claim 9, characterized in that: Bonding the back surface of the silicon carbide single crystal ingot to a bearing layer, comprising: forming a transition layer on the back surface of the silicon carbide single crystal ingot or the supporting layer; Bonding the back surface of the silicon carbide single crystal ingot to the bearing layer through the transition layer; The composite substrate further includes the transition layer located between the silicon carbide layer and the carrier layer.

12. The method for preparing a composite substrate according to claim 9, characterized in that: Bonding the back surface of the silicon carbide single crystal ingot to a bearing layer, comprising: The back surface of the silicon carbide single crystal ingot is directly contacted and bonded to the supporting layer.

13. The method for preparing a composite substrate according to any one of claims 9 to 12, characterized in that: The lattice direction of the silicon carbide single crystal ingot is along <0001> The lattice direction is deflected within the range of greater than or equal to 0° and less than or equal to 8°; and / or, The energy of hydrogen ion implantation is greater than or equal to 100 keV, the implantation dose is greater than or equal to 1e16 cm-2, and the ion implantation angle is within a range of greater than or equal to 5° and less than or equal to 20°.

14. The method for preparing a composite substrate according to any one of claims 9 to 12, characterized in that: Performing surface treatment on the surface of the silicon carbide layer away from the bearing layer to remove the damaged layer includes: The surface of the silicon carbide layer away from the supporting layer is processed by at least one of wet cleaning, plasma activation, high temperature annealing, chemical mechanical polishing, mechanical polishing, reactive ion etching, ion beam etching, or ion beam grazing incidence polishing to remove the damaged layer.

15. The method for preparing a composite substrate according to any one of claims 9 to 12, characterized in that: The first annealing temperature is greater than or equal to 1000° C., and the annealing temperature of the second annealing treatment is greater than or equal to 1200° C.

16. The method for preparing a composite substrate according to any one of claims 9 to 13, characterized in that: After surface treatment is performed on the surface of the silicon carbide layer away from the carrier layer, the roughness of the surface of the silicon carbide layer away from the carrier layer is less than or equal to 0.5 nm.

17. The method for preparing a composite substrate according to any one of claims 9 to 13, characterized in that: The annealing environment of the first annealing treatment is at least one of N2, Ar or H2; The annealing environment of the second annealing treatment is at least one of vacuum, N2, Ar or C-containing gas.

18. A semiconductor device, characterized in that: The composite substrate comprises the composite substrate according to any one of claims 1 to 8, and a heterojunction; the heterojunction is arranged on a side of at least one epitaxial layer of the composite substrate away from a carrier layer.

19. An electronic device, characterized in that: It comprises the semiconductor device and antenna as described in claim 18; the semiconductor device is used to amplify the radio frequency signal and output it to the antenna for outward radiation.

20. An electronic device, characterized in that: The method comprises the semiconductor device and a printed circuit board as claimed in claim 18; wherein the semiconductor device is coupled to the printed circuit board; Wherein, the material of the carrier layer in the semiconductor device is a conductive material.

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