Multi-bit flip-flop and its control method

Abstract

The present invention provides a multi-bit flip-flop and a control method therefor. The multi-bit flip-flop includes a first flip-flop configured to output a first data output signal. The first flip-flop includes: a first selection circuit configured to send a first data signal or a first test signal to an output node of the first selection circuit as a first input signal; a first latch circuit configured to generate a first signal according to the first input signal; and a first data output stage circuit configured to generate a first data output signal according to the first signal. When the multi-bit flip-flop operates in a test mode, the first selection circuit transmits the first test signal to the output node of the first selection circuit as the first input signal, and the first data output stage circuit holds the first data output signal at a fixed voltage level. Implementing the embodiments of the present invention can reduce power consumption.

Description

Technical Field

[0001] The present invention relates to a flip - flop design, and more particularly, to a multi - bit flip - flop with power - saving characteristics and a control method thereof. Background Art

[0002] Scan chains are applied to detect various manufacturing faults in combinational logic blocks during the test process. Generally, a scan chain consists of a plurality of flip - flops connected in series, and in the normal mode, the data output terminal of each flip - flop is connected to a combinational logic circuit for normal data transfer. However, in the test mode, data transfer still occurs at the data output terminal of each flip - flop, so the combinational logic circuit is still working, resulting in unnecessary power consumption. Summary of the Invention

[0003] The present invention provides a multi - bit flip - flop and a control method thereof, which can reduce power consumption.

[0004] A multi - bit flip - flop provided by the present invention may include: a plurality of flip - flops connected to form an internal scan chain, wherein the plurality of flip - flops include a first flip - flop arranged to output a first data output signal at a first data output terminal of the multi - bit flip - flop, and the first flip - flop includes: a first selection circuit arranged to send a first data signal or a first test signal at a first data input terminal of the multi - bit flip - flop to an output node of the first selection circuit as a first input signal; a first latch circuit coupled to the output node of the first selection circuit and arranged to generate a first signal according to the first input signal; and a first data output stage circuit arranged to receive the first signal and generate the first data output signal according to the first signal; wherein, when the multi - bit flip - flop operates in the test mode, the first selection circuit is arranged to transmit the first test signal to the output node of the first selection circuit as the first input signal, and the first data output stage circuit is arranged to hold the first data output signal at a fixed voltage level regardless of the voltage level of the first test signal.

[0005] A control method provided by the present invention is applied to a multi-bit flip-flop connected with N flip-flops to form an internal scan chain. Wherein, the multi-bit flip-flop includes a scan input terminal coupled to one of the N flip-flops, and N data output terminals respectively coupled to the N flip-flops. Wherein N is a positive integer not less than 1. The control method includes: in response to receiving an external test signal at the scan input terminal of the multi-bit flip-flop, transmitting the external test signal through the internal scan chain; generating a scan output signal having a voltage level that changes with the voltage level of the external test signal, wherein the scan output signal is output from one of the N flip-flops to one of the N data output terminals; and keeping each of the (N - 1) data output signals at a fixed voltage level regardless of the voltage level of the external test signal, wherein the (N - 1) data output signals are respectively output from the remaining (N - 1) flip-flops among the N flip-flops to the remaining (N - 1) output terminals among the N data output terminals.

[0006] Another control method provided by the present invention is applied to a multi-bit flip-flop connected with N flip-flops to form an internal scan chain. Wherein, the multi-bit flip-flop includes a scan input terminal coupled to one of the N flip-flops, a scan output terminal coupled to another one of the N flip-flops, and N data output terminals respectively coupled to the N flip-flops. Wherein N is a positive integer not less than 1; the control method includes: in response to receiving an external test signal at the scan input terminal of the multi-bit flip-flop, transmitting the external test signal through the internal scan chain; generating a scan output signal having a voltage level that changes with the voltage level of the external test signal, wherein the scan output signal is output from the other flip-flop among the N flip-flops to the scan output terminal; and keeping the N data output signals at a fixed voltage level regardless of the voltage level of the external test signal, wherein the N data output signals are respectively output from the N flip-flops to the N data output terminals of the multi-bit flip-flop.

[0007] As described above, in the embodiment of the present invention, when a test signal is received, the data output signal is kept at a fixed voltage level, thereby reducing power consumption. Description of the Drawings

[0008] Figure 1 It is a schematic diagram showing a first multi-bit flip-flop (MBFF) with power-saving characteristics according to an embodiment of the present invention.

[0009] Figure 2 It is a diagram showing a first circuit design of the MBFF according to an embodiment of the present invention.

[0010] Figure 3FIG. is a diagram showing a first alternative design of a data output stage circuit having a gating function according to an embodiment of the present invention.

[0011] Figure 4 FIG. is a diagram showing a second alternative design of a data output stage circuit having a gating function according to an embodiment of the present invention.

[0012] Figure 5 FIG. is a diagram showing a third alternative design of a data output stage circuit having a gating function according to an embodiment of the present invention.

[0013] Figure 6 FIG. is a diagram showing a fourth alternative design of a data output stage circuit having a gating function according to an embodiment of the present invention.

[0014] Figure 7 FIG. is a diagram showing a fifth alternative design of a data output stage circuit having a gating function according to an embodiment of the present invention.

[0015] Figure 8 FIG. is a schematic diagram showing a second MBFF having power-saving characteristics according to an embodiment of the present invention.

[0016] Figure 9 FIG. is a diagram showing a second circuit design of an MBFF according to an embodiment of the present invention.

[0017] Figure 10 FIG. is a schematic diagram showing a third MBFF having power-saving characteristics according to an embodiment of the present invention.

[0018] Figure 11 FIG. is a diagram showing a third circuit design of an MBFF according to an embodiment of the present invention.

[0019] Figure 12 FIG. is a diagram showing a first alternative design of a scan output stage circuit having a gating function according to an embodiment of the present invention.

[0020] Figure 13 FIG. is a diagram showing a second alternative design of a scan output stage circuit having a gating function according to an embodiment of the present invention.

[0021] Figure 14 FIG. is a diagram showing a third alternative design of a scan output stage circuit having a gating function according to an embodiment of the present invention.

[0022] Figure 15 FIG. is a diagram showing a fourth alternative design of a scan output stage circuit having a gating function according to an embodiment of the present invention.

[0023] Figure 16It is a diagram showing a fifth alternative design of a scan output stage circuit with a holding function according to an embodiment of the present invention. Detailed implementation

[0024] In the specification and claims, certain terms are used to refer to specific components. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. The specification and claims do not use the difference in names as a way to distinguish components, but use the difference in functions of components as the criterion for distinction. The terms "comprising" and "including" mentioned throughout the specification and claims are open-ended terms, and should be interpreted as "including but not limited to". "Substantially" means within an acceptable error range. Those skilled in the art can solve the technical problem within a certain error range and basically achieve the technical effect. In addition, the term "coupled" herein includes any direct and indirect electrical connection means. Therefore, if it is described in the text that a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. The following describes the preferred way to implement the present invention, aiming to illustrate the spirit of the present invention rather than to limit the protection scope of the present invention. The protection scope of the present invention shall be determined by the scope defined in the claims.

[0025] The following description is the optimal embodiment expected by the present invention. These descriptions are used to illustrate the general principles of the present invention and should not be used to limit the present invention. The protection scope of the present invention should be determined based on reference to the claims of the present invention.

[0026] Figure 1 It is a schematic diagram showing a first multi-bit flip-flop (MBFF) with power-saving characteristics according to an embodiment of the present invention. In this embodiment, MBFF 100 is an N-bit scan flip-flop, where N is a positive integer not less than 1 (i.e., N≥2). The circuit layout of MBFF 100 can be a cell in the cell library used in integrated circuit (IC) design. As Figure 1As shown, the MBFF 100 has N data input terminals D1, D2, .., D(N-1) and DN, a scan input terminal SI, a test enable terminal SE, a clock input terminal CLK, and N data output terminals Q1, Q2, …, Q(N-1) and QN. In addition, the MBFF 100 includes N flip-flops (FF) 102_1, 102_2, …, 102_(N-1) and 102_N connected together to form an internal scan chain 104, that is, a scan chain formed by internally stitching the flip-flops 102_1 - 102_N as shown by the dashed line. When the MBFF 100 operates in the normal mode, the data input terminals D1 - DN are used to receive data signals and are respectively coupled to the flip-flops 102_1 - 102_N. When the MBFF 100 operates in the normal mode, the data output terminals Q1 - QN are used to output data output signals and are respectively coupled to the flip-flops 102_1 - 102_N. The scan input terminal SI is used to receive an external test signal, and the external test signal at the scan input terminal SI is transmitted through the internal scan chain 104, where the test signal of the current flip-flop 102_n (n ≠ 1) is an internal test signal obtained from the previous-stage flip-flop 102_(n-1). For example, the test signal INT2 of the flip-flop 102_2 is obtained from the flip-flop 102_1, the test signal INT3 of another flip-flop (not shown) is obtained from the flip-flop 102_2, the test signal INT(N-1) of the flip-flop 102_(N-1) is obtained from yet another flip-flop (not shown), and the test signal INTN of the flip-flop 102_N is obtained from the flip-flop 102_(N-1). Each of the flip-flops 102_1 - 102_(N-1) has data output stage circuits (labeled "L1") 210_1, 210_2, …, 210_(N-1), and these data output stage circuits have a hold function that is enabled in the test mode and disabled in the normal mode.

[0027] When the MBFF 100 operates in the normal mode, the data output stage circuit 210_1 generates a data output signal and outputs it to the data output terminal Q1, where the voltage level of the data output signal changes in response to the voltage level of the data signal at the data input terminal D1; the data output stage circuit 210_2 generates and outputs a data output signal to the data output terminal Q2, where the voltage level of the data output signal changes in response to the voltage level of the data signal at the data input terminal D2; the data output stage circuit 210_(N - 1) generates and outputs a data output signal to the data output terminal Q(N - 1), where the voltage level of the data output signal changes in response to the voltage level of the data signal at the data input terminal D(N - 1). In addition, the data output terminal QN is shared by normal data transmission and test data transmission. Therefore, the flip - flop 102_N generates a data output signal and outputs it to the data output terminal QN, where the voltage level of the data output signal changes in response to the voltage level of the data signal at the data input terminal DN.

[0028] In another case where the MBFF 100 operates in the test mode, the data output stage circuit 210_1 generates and outputs a data output signal to the data output terminal Q1, where the voltage level of the data output signal is held at a fixed voltage level regardless of the voltage level of the test signal at the scan input terminal SI; the data output stage circuit 210_2 generates a data output signal and outputs it to the data output terminal Q2, where the voltage level of the data output signal is held at a fixed voltage level independent of the test signal INT2 obtained from the flip - flop 102_1; the data output stage circuit 210_(N - 1) generates and outputs a data output signal to the data output terminal Q(N - 1), where the voltage level of the data output signal is held at a fixed voltage level regardless of the voltage level of the test signal INT(N - 1) obtained from the previous - stage flip - flop (not shown). In addition, the data output terminal QN is shared by normal data transmission and test data transmission. Therefore, the flip - flop 102_N generates a scan output signal and outputs it to the data output terminal QN, where the voltage level of the scan output signal changes in response to the voltage level of the test signal INTN (which is obtained by transmission in the internal scan chain 104 through the external test signal at the scan input terminal S1).

[0029] Figure 2 is a diagram showing a first circuit design of the MBFF according to an embodiment of the present invention. By way of example and not limitation, Figure 1 the MBFF 100 shown in Figure 2implemented by the circuit structure shown. In addition to the flip-flops 102_1 - 102_N, the MBFF 100 may further include a signal generation circuit 204 and a clock generation circuit 202. The signal generation circuit 204 receives a test enable signal STE (which is an external test enable signal) to generate another test enable signal STEB, and the test enable signal STEB is inverse to the test enable signal STE. In Figure 2 an embodiment, the signal generation circuit 204 includes an inverter. In other embodiments, the signal generation circuit 204 may be implemented by any other circuit structure capable of receiving the test enable signal STE and generating a test enable signal STEB that is inverse to the test enable signal STE.

[0030] The clock generation circuit 110 receives a clock signal SCK (which is an external clock signal received via the clock terminal CK), and generates a clock signal CLKB and a CLK1 based on the clock signal SCK, where the clock signal CLKB is the inverse of the clock signal SCK, and the clock signal CLK1 is the inverse of the clock signal CLKB. In Figure 2 an embodiment, the clock generation circuit 202 includes two inverters. In other embodiments, the clock generation circuit 202 may be implemented by any other circuit structure capable of receiving the clock signal SCK, generating a clock signal CLKB that is inverse to the clock signal SCK, and generating a clock signal CLK1 that is inverse to the clock signal CLKB.

[0031] Each of the flip - flops 102_1 - 102_(N - 1) can have the same circuit structure. For example, flip - flop 102_1 is arranged to output a data output signal S14 at the data output terminal Q1 of MBFF 100, which includes a selection circuit 206_1, a latch circuit 208_1, and a data output stage circuit 210_1; flip - flop 102_2 is arranged to output a data output signal S24 at the data output terminal Q2 of MBFF 100, which includes a selection circuit 206_2, a latch circuit 208_2, and a data output stage circuit 210_2. Regarding flip - flop 102_1, the selection circuit 206_1 is arranged to send the data signal S10 at the data input terminal D1 of MBFF 100 or the test signal S11 at the scan input terminal SI of MBFF 100 to the output node of the selection circuit 206_1 as the input signal S12; the latch circuit 208_1 is coupled to the output node of the selection circuit 206_1 and is arranged to generate a signal S13 according to the input signal S12; the data output stage circuit 210_1 is arranged to receive the signal S13 and generate a data output signal S14 according to the signal S13. In this embodiment, the selection circuit 206_1 can include an inverter and transmission gates, where each transmission gate includes a P - type transistor (e.g., a P - channel metal - oxide - semiconductor (PMOS) transistor) and an N - type transistor (e.g., an N - channel metal - oxide - semiconductor (NMOS) transistor), and is controlled by test enable signals STE and STEB. In addition, the latch circuit 208_1 can include an inverter and transmission gates, where each transmission gate includes a P - type transistor (e.g., a PMOS transistor) and an N - type transistor (e.g., an NMOS transistor), and is controlled by clock signals CLK1 and CLKB. Since the present invention does not focus on the circuit design of the selection circuit 206_1 and the latch circuit 208_1, those of ordinary skill in the art should easily understand Figure 2 the principles of the shown selection circuit 206_1 and latch circuit 208_1. Therefore, for the sake of brevity, further descriptions of the selection circuit 206_1 and the latch circuit 208_1 are omitted here.

[0032] The data output stage circuit 210_1 is equipped with a holding function, which is enabled in the test mode of the MBFF 100 and disabled in the normal mode of the MBFF 100. For example, when the MBFF 100 operates in the normal mode, the selection circuit 206_1 sends the data signal S10 to the output node of the selection circuit 206_1 to be used as the input signal S12, and the data output stage circuit 210_1 generates a data output signal S14, and the data output signal S14 has a voltage level that varies in response to the voltage level of the data signal S10. Specifically, the voltage level of the data output signal S14 changes in response to the voltage level of the signal S13, where the voltage level of the signal S13 changes in response to the voltage level of the data signal S10. When the MBFF 100 operates in the test mode, the selection circuit 206_1 sends the test signal S11 to the output node of the selection circuit 206_1 to be used as the input signal S12, and the data output stage circuit 210_1 holds the data output signal S14 at a fixed voltage level (e.g., a high voltage level or a low voltage level), regardless of the voltage level of the test signal S11. Specifically, the voltage level of the data output signal S14 does not change in response to the voltage level of the signal S13, while the voltage level of the signal S13 changes in response to the voltage level of the test signal S11.

[0033] Contrary to the first flip-flop 102_1 that receives the test signal S11 via the scan input terminal SI, the subsequent flip-flop 102_2 receives the test signal INT2 obtained from the previous-stage flip-flop 102_1 (specifically, the latch circuit 208_1 of the flip-flop 102_1). Regarding the flip-flop 102_2, the selection circuit 206_2 is arranged to send the data signal S20 at the data input terminal D2 of the MBFF 100 or the test signal INT2 obtained from the latch circuit 208_1 to the output node of the selection circuit 206_2 to be used as the input signal S22; the latch circuit 208_2 is coupled to the output node of the selection circuit 206_2 and is arranged to generate a signal S23 according to the input signal S22. The data output stage circuit 210_2 is arranged to receive the signal S23 and generate a data output signal S24 according to the signal S23. Similarly, the data output stage circuit 210_2 is equipped with the same holding function, which is enabled in the test mode of the MBFF 100 and disabled in the normal mode of the MBFF 100.

[0034] The last flip-flop 102_N is arranged to generate an output signal SN4 on the data output terminal QN of the MBFF 100, which includes a selection circuit 206_N, a latch circuit 208_N, and an output stage circuit 212. The output stage circuit 212 is implemented using an inverter 213. The selection circuit 206_N is arranged to send the data signal SN0 at the data input terminal DN of the MBFF 100 or the test signal INTN obtained from the previous-stage flip-flop to the output node of the selection circuit 206_N as the input signal SN2. The latch circuit 208_N is coupled to the output node of the selection circuit 206_N and is arranged to generate a signal SN3 according to the input signal SN2. The output stage circuit 212 is arranged to receive the signal SN3 and generate the output signal SN4 according to the signal SN3. In this embodiment, the data output terminal QN is shared by normal data transmission and test data transmission. When the MBFF 100 operates in the normal mode, the selection circuit 206_N sends the data signal SN0 to the output node of the selection circuit 206_N as the input signal SN2, and the output stage circuit 212 generates the output signal SN4 as the data output signal, which has a voltage level that changes in response to the voltage level of the data signal SN0. Specifically, the voltage level of the output signal SN4 (data output signal) changes in response to the voltage level of the signal SN3, where the voltage level of the signal SN3 changes in response to the voltage level of the data signal SN0. When the MBFF 100 operates in the test mode, the selection circuit 206_N sends the test signal INTN to the output node of the selection circuit 206_N as the input signal SN2, and the output stage circuit 212 generates the output signal SN4 as the scan output signal, which has a voltage level that changes in response to the voltage level of the test signal INTN. Specifically, the voltage level of the output signal SN4 (scan output signal) changes in response to the voltage level of the signal SN3, where the voltage level of the signal SN3 changes in response to the voltage level of the test signal INTN.

[0035] In this embodiment, each data output stage circuit having a holding function can be implemented using a NOR gate 211, where one input node of the NOR gate 211 is arranged to receive the output signal of the previous stage latch circuit, another input node of the NOR gate 211 is arranged to receive the test enable signal STE, and the output node of the NOR gate 211 is arranged to output a data output signal to the data output terminal of the MBFF100. Taking the data output stage 210_1 as an example, one input node of the NOR gate 211 receives the signal S13 at the output node N1 of the latch circuit 208_1, another input node of the NOR gate 211 receives the test enable signal STE, and the output node of the NOR gate 211 outputs the data output signal S14 to the data output terminal Q1 of the MBFF 100. When the MBFF 100 operates in the normal mode (STE = 0), the voltage level of the data output signal S14 changes in response to the voltage level of the signal S13. Specifically, the data output signal S14 is the inversion of the signal S13, where the signal S13 is the inversion of the data signal S10. When the MBFF 100 operates in the test mode (STE = 1), the voltage level of the data output signal S14 is held at a fixed voltage level (e.g., ground voltage), regardless of the voltage level of the test signal S11. Specifically, the voltage level of the data output signal S14 does not change in response to the voltage level of the signal S13, where the signal S13 is the inversion of the test signal S11.

[0036] Figure 2 The circuit structure shown is for illustrative purposes only and does not imply a limitation to the present invention. For example, the selection circuit can be implemented by any other circuit structure capable of selecting one of the normal data input and the test data input as the input signal for the subsequent latch circuit. For another example, the latch circuit can be implemented by any other circuit structure capable of processing the input signal obtained from the previous stage selection circuit to generate a signal and output the generated signal to the subsequent data output stage circuit having a holding function. For yet another example, the data output stage circuit having a holding function can be implemented by any other circuit structure capable of holding the data output signal at a fixed voltage level when the MBFF operates in the test mode.

[0037] Figure 3FIG. is a diagram showing a first alternative design of a data output stage circuit having a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1 - 210_(N - 1) may be implemented using the data output stage circuit 300. The data output stage circuit 300 employs an OR gate 302. One input node of the OR gate 302 is coupled to the output node N1 of the previous stage latch circuit. Another input node of the OR gate 302 is arranged to receive a test enable signal STE. The output node of the OR gate 302 is arranged to output a data output signal to the data output terminal Qn of the MBFF 100, where n is a positive integer selected from the range of 1 to (N - 1). When the MBFF 100 operates in the normal mode (STE = 0), the voltage level of the data output signal generated by the OR gate 302 changes in response to the voltage at the output node N1 of the previous stage latch circuit. When the MBFF 100 operates in the test mode (STE = 1), the data output signal generated by the OR gate 302 is held at a fixed voltage level (e.g., the power supply voltage), regardless of the voltage of the signal at the output node N1 of the previous stage latch circuit.

[0038] Figure 4 FIG. is a diagram showing a second alternative design of a data output stage circuit having a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1 - 210_(N - 1) may be implemented using the data output stage circuit 400. The data output stage circuit 400 employs a NAND gate 402. One input node of the NAND gate 402 is coupled to the output node N1 of the previous stage latch circuit. Another input node of the NAND gate 402 is arranged to receive a test enable signal STEB. And the output node of the NAND gate 402 is arranged to output a data output signal to the data output terminal Qn of the MBFF 100, where n is a positive integer selected from the range of 1 to (N - 1). When the MBFF 100 operates in the normal mode (STEB = 1), the voltage level of the data output signal generated by the NAND gate 402 changes in response to the voltage of the signal at the output node N1 of the previous stage latch circuit. When the MBFF 100 operates in the test mode (STEB = 0), the data output signal generated by the NAND gate 402 is held at a fixed voltage level (e.g., the power supply voltage), regardless of the voltage of the signal at the output node N1 of the previous stage latch circuit.

[0039] Figure 5FIG. is a diagram showing a third alternative design of a data output stage circuit having a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1 - 210_(N - 1) may be implemented using the data output stage circuit 500. The data output stage circuit 500 employs an AND gate 502, one input node of the AND gate 502 is coupled to the output node N1 of the previous stage latch circuit, another input node of the AND gate 502 is arranged to receive a test enable signal STEB, and the output node of the AND gate 502 is arranged to output a data output signal to the data output terminal Qn of the MBFF 100, where n is a positive integer selected from the range of 1 to (N - 1). When the MBFF 100 operates in the normal mode (STEB = 1), the voltage level of the data output signal generated by the AND gate 502 changes in response to the voltage of the signal at the output node N1 of the previous stage latch circuit. When the MBFF 100 operates in the test mode (STEB = 0), the data output signals generated by the AND gate 502 are all held at a fixed voltage level (e.g., ground voltage), regardless of the signal voltage at the output node N1 of the previous stage latch circuit.

[0040] Figure 6 FIG. is a diagram showing a fourth alternative design of a data output stage circuit having a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1 - 210_(N - 1) may be implemented using the data output stage circuit 600. The data output stage circuit 600 includes PMOS transistors 602 and 604, NMOS transistors 606 and an inverter 608. The gate of the PMOS transistor 604 receives the test enable signal STEB, the source of the PMOS transistor 604 is coupled to a reference voltage (e.g., a power supply voltage), and the drain of the PMOS transistor 604 is coupled to the input node of the inverter 608. The PMOS transistor 602 and the NMOS transistor 606 form a transmission gate. The gate of the PMOS transistor 602 receives the test enable signal STE, the source of the PMOS transistor 602 is coupled to the output node N1 of the previous stage latch circuit, and the drain of the PMOS transistor 602 is coupled to the input node of the inverter 608. The gate of the NMOS transistor 606 receives the test enable signal STEB, the drain of the NMOS transistor 606 is coupled to the output node N1 of the previous stage latch circuit, and the source of the NMOS transistor 606 is coupled to the input node of the inverter 608.

[0041] When the MBFF 100 operates in the normal mode (STE = 0 & STEB = 1), the transmission gate composed of the PMOS transistor 602 and the NMOS transistor 606 is enabled, and the PMOS transistor 604 is turned off, so that the level voltage of the data output signal at the data output terminal Qn (n is a positive integer from 1 to (N - 1)) changes in response to the voltage level of the signal at the output node N1 of the previous latch circuit. When the MBFF 100 operates in the test mode (STE = 1 & STEB = 0), the transmission gate composed of the PMOS transistor 602 and the NMOS transistor 606 is disabled, and the PMOS transistor 604 is turned on, so that the voltage level of the data output signal at the data output terminal Qn is maintained at a fixed voltage level (for example, the ground voltage), regardless of the voltage level of the signal at the output node N1 of the previous latch circuit.

[0042] Figure 7 FIG. is a diagram showing a fifth alternative design of a data output stage circuit having a holding function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1 - 210_(N - 1) can be implemented using the data output stage circuit 700. The data output stage circuit 700 includes NMOS transistors 702 and 704, PMOS transistors 706, and an inverter 708. The gate of the NMOS transistor 704 receives the test enable signal STE. The source of the NMOS transistor 704 is coupled to a reference voltage (for example, the ground voltage). The drain of the NMOS transistor 704 is coupled to the input node of the inverter 708. The PMOS transistor 706 and the NMOS transistor 702 form a transmission gate. The gate of the PMOS transistor 706 receives the test enable signal STE. The source of the PMOS transistor 706 is coupled to the output node N1 of the previous latch circuit. The drain of the PMOS transistor 706 is coupled to the input node of the inverter 708. The gate of the NMOS transistor 702 receives the test enable signal STEB. The drain of the NMOS transistor 702 is connected to the output node N1 of the previous latch circuit. The source of the NMOS transistor 702 is coupled to the input node of the inverter 708.

[0043] When the MBFF 100 operates in the normal mode (STE = 0 & STEB = 1), the transmission gate composed of the PMOS transistor 706 and the NMOS transistor 702 is enabled, and the NMOS transistor 704 is turned off. Thus, the voltage level of the data output signal at the data output terminal Qn (n is a positive integer from 1 to (N - 1)) changes in response to the voltage level of the signal at the output node N1 of the previous latch circuit. When the MBFF 100 operates in the test mode (STE = 1 & STEB = 0), the transmission gate composed of the PMOS transistor 706 and the NMOS transistor 702 is disabled, and the NMOS transistor 704 is turned on. Thus, the voltage level of the data output signal at the data output terminal Qn is maintained at a fixed voltage level (such as the power supply voltage), regardless of the voltage level of the signal at the output node N1 of the preceding latch circuit.

[0044] The MBFF 100 with N flip - flops 102_1 - 102_N connected to form an internal scan chain 104 is designed to have power - saving characteristics. For example, when an external test signal S11 is received at the scan input terminal SI in the test mode, the MBFF 100 transmits the external test signal S11 through the internal scan chain 104 and generates a scan output signal SN4. The scan output signal SN4 is output from the flip - flop 102_N to the data output terminal QN, and the voltage level of the scan output signal SN4 changes in response to the voltage level of the external test signal S11. And regardless of the voltage level of the external test signal S11, each of the (N - 1) data output signals (respectively output from the flip - flops 102_1 - 102_(N - 1) to the output terminals Q1 - Q(N - 1)) is maintained at a fixed voltage level. Since there is no signal - level transition for the (N - 1) data output signals in the test mode of the MBFF 100, the power consumption of the MBFF 100 and the downstream combinational logic can be reduced.

[0045] In Figure 1 and Figure 2 In the illustrated embodiment, the MBFF 100 has a data output terminal QN shared by normal data transmission and test data transmission. However, this is for illustrative purposes only and does not imply a limitation on the present invention. In an alternative design, the MBFF can be configured to have an additional terminal that serves as a dedicated scan output terminal for outputting the scan output signal.

[0046] Figure 8 is a schematic diagram showing a second MBFF with power - saving characteristics according to an embodiment of the present invention. In this embodiment, the MBFF 800 is an N - bit scan flip - flop, where N is a positive integer not less than 1 (i.e., N≥2). The circuit layout of the MBFF 800 can be a cell in the cell library used in IC design. AsFigure 8 As shown, the MBFF 800 has N data input terminals D1, D2, …, D(N-1) and DN, a scan input terminal SI, a test enable terminal SE, a clock input terminal CLK, N data output terminals Q1, Q2, …, Q(N-1) and QN, and a scan output terminal SQ. In addition, the MBFF 800 includes N flip-flops (FF) 802_1, 802_2, …, 802_(N-1) and 802_N, which are connected to form an internal scan chain 104. The main difference between the MBFFs 100 and 800 is that the flip-flop 802_N of the MBFF 800 has a scan output terminal SQ for outputting a scan output signal when the MBFF 800 operates in the test mode, and also has a data output stage circuit 210_N (labeled "L1") with a hold function, which is enabled in the test mode and disabled in the normal mode.

[0047] When the MBFF 800 operates in the normal mode, the data output stage circuit 210_N generates a data output signal and outputs it to the data output terminal QN, where the voltage level of the data output signal changes in response to the voltage level of the data signal at the data input terminal DN. When the MBFF 800 operates in the test mode, a scan output stage circuit (not shown) generates a scan output signal and outputs it to the scan output terminal SQ, where the voltage level of the scan output signal changes in response to the voltage level of the data signal at the data input terminal DN. In addition, the data output stage circuit 210_N generates a data output signal and outputs it to the data output terminal QN, where the voltage level of the data output signal is held at a fixed voltage level (e.g., a high voltage level or a low voltage level), regardless of the voltage level of the test signal INTN obtained from the previous flip-flop 802_(N-1).

[0048] Figure 9 is a diagram showing a second circuit design of the MBFF according to an embodiment of the present invention. By way of example and not limitation, Figure 8 the MBFF 800 shown in Figure 9 can be implemented using the circuit structure shown in Figure 2 Each of the flip-flops 802_1 - 802_(N-1) can have the same circuit structure as the circuit structure shown in Figure 2 For the sake of brevity, similar descriptions are omitted. Regarding the last flip-flop 802_N, it is arranged to output a data output signal SN4 at the data output terminal QN of the MBFF 800 and a scan output signal SN5 at the scan output terminal SQ of the MBFF 800. As shown in Figure 9 the flip-flop 802_N includes a data output stage circuit 210_N, a scan output stage circuit 902, and the above-mentioned selection circuit 206_N and latch circuit 208_N. SimilarFigure 2 The output stage circuit 212 shown, the scan output stage circuit 902 is implemented by an inverter 213. Similar to the data output stage circuits 210_1 and 210_2, the data output stage circuit 210_N is equipped with a hold function that is enabled in the test mode of the MBFF800 and disabled in the normal mode of the MBFF 800. When the MBFF 800 operates in the normal mode, the selection circuit 206_N sends the data signal SN0 to the output node of the selection circuit 206_N as the input signal SN2, and the data output stage circuit 210_N generates a data output signal SN4, and the voltage level of the data output signal SN4 changes in response to the voltage level of the data signal SN0. Specifically, the voltage level of the data output signal SN4 changes in response to the voltage level of the signal SN3, where the voltage level of the signal SN3 changes in response to the voltage level of the data signal SN0. When the MBFF 800 operates in the test mode, the selection circuit 206_N sends the test signal INTN to the output node of the selection circuit 206_N as the input signal SN2, and the data output stage circuit 210_N holds the data output signal SN4 at a fixed voltage level (e.g., high voltage level or low voltage level), regardless of the voltage level of the test signal INTN. Specifically, the voltage level of the data output signal SN4 does not change in response to the voltage level of the signal SN3, while the voltage level of the signal SN3 changes in response to the voltage level of the test signal INTN.

[0049] Figure 9 The circuit structure shown is only for illustrative purposes and does not imply a limitation on the present invention. For example, the selection circuit can be implemented by any other circuit structure capable of selecting one of a normal data input and a test data input as the input signal to the subsequent latch circuit. For another example, the latch circuit can be implemented by any other circuit structure capable of processing the input signal obtained from the previous-stage selection circuit to generate a signal and outputting the generated signal to the subsequent-stage data output stage circuit having a hold function. For yet another example, the data output stage circuit having a hold function can be implemented by any other circuit structure capable of holding the data output signal at a fixed voltage level when the MBFF operates in the test mode. Therefore, one or more of the flip-flops 802_1 - 802_N can use Figure 3 the data output stage circuit 300 shown, Figure 4 the data output stage circuit 400 shown, Figure 5 the data output stage circuit 500 shown, Figure 6 the data output stage circuit 600 shown or Figure 7 the data output stage circuit 700 shown to be implemented.

[0050] The MBFF 800 having N flip - flops 802_1 - 802_N connected to form an internal scan chain 104 is designed to have power - saving characteristics. For example, when an external test signal S11 is received at the scan input terminal SI, the MBFF 800 transmits the external test signal S11 through the internal scan chain 104, generating a scan output signal SN4 output from the flip - flop 802_N to the scan output terminal SQ. The voltage level of the scan output signal SN4 changes in response to the voltage level of the external test signal S11, and the voltage level of each of the N data output signals (respectively output from the N flip - flops 802_1 - 802_N to the N output terminals Q1 - QN) is maintained at a fixed voltage level regardless of the external test signal S11. Since there is no signal level transition in the N data output signals in the test mode of the MBFF 800, the power consumption of the MBFF 800 and the downstream combinational logic can be reduced.

[0051] In Figure 9 the illustrated embodiment, the scan output stage circuit 902 does not have a hold function. As a result, when the MBFF 800 operates in either the normal mode or the test mode, the voltage level of the scan output signal SN5 changes in response to the voltage level of the signal SN3. In an alternative design, the MBFF can be configured to have a scan output stage circuit with a hold function.

[0052] Figure 10 is a schematic diagram showing a third MBFF having power - saving characteristics according to an embodiment of the present invention. In this embodiment, the MBFF 1000 is an N - bit scan flip - flop, where N is a positive integer not less than 1 (i.e., N≥2). The circuit layout of the MBFF 1000 can be a cell in the cell library used in IC design. As Figure 10 shown, the MBFF 1000 has N data input terminals D1, D2, …, D(N - 1) and DN, a scan input terminal SI, a test enable terminal SE, a clock input terminal CLK, N data output terminals Q1, Q2, …, Q(N - 1) and QN, and a scan output terminal SQ. In addition, the MBFF 1000 includes N flip - flops (FF) 1002_1, 1002_2, …, 1002_(N - 1), 1002_N connected to form an internal scan chain 104. The main difference between the MBFF1000 and the MBFF800 is that the last flip - flop 1002_N of the MBFF 1000 has a scan output stage circuit 1004 (labeled "L2") with a hold function, and this hold function is enabled in the normal mode and disabled in the test mode.

[0053] When the MBFF 1000 operates in the normal mode, the data output stage circuit 210_N generates a data output signal and outputs it to the data output terminal QN, where the voltage level of the data output signal changes in response to the voltage level of the data signal at the data input terminal DN; the scan output stage circuit 1004 generates and outputs a scan output signal to the scan output terminal SQ, where the voltage level of the scan output signal remains at a fixed voltage level (e.g., a high voltage level or a low voltage level), regardless of the voltage level of the data signal at the data input terminal DN.

[0054] When the MBFF 1000 operates in the test mode, the scan output stage circuit 1004 generates a scan output signal and outputs it to the scan output terminal SQ, where the voltage level of the scan output signal changes in response to the voltage level of the test signal INTN obtained from the previous-stage flip-flop 1002_(N - 1). The data output stage circuit 210_N generates and outputs a data output signal to the data output terminal QN, where the voltage level of the data output signal remains at a fixed voltage level (e.g., a high voltage level or a low voltage level), regardless of the voltage level of the test signal INTN obtained from the previous-stage flip-flop 1002_(N - 1).

[0055] Figure 11 FIG. is a diagram showing a third circuit design of an MBFF according to an embodiment of the present invention. By way of example and not limitation, Figure 10 the MBFF 1000 shown in Figure 11 can be implemented using the circuit structure shown. Each of the flip-flops 1002_1 - 1002_(N - 1) may have Figure 2 or Figure 9The circuit structure shown. For the sake of brevity, further description is omitted. Regarding the last flip-flop 1002_N, it is arranged to output a data output signal SN4 at the data output terminal QN of the MBFF 1000 and output a scan output signal SN5 at the scan output terminal SQ of the MBFF 1000. The main difference between the flip-flops 802_N and 1002_N is that the flip-flop 1002_N employs a scan output stage circuit 1004 with a hold function, and this hold function is enabled in the normal mode of the MBFF 1000 and disabled in the test mode of the MBFF 1000. When the MBFF 1000 operates in the test mode, the selection circuit 206_N sends a test signal INTN to the output node of the selection circuit 206_N to be used as an input signal SN2, and the scan output stage circuit 1004 generates a scan output signal SN5, and the voltage level of the scan output signal SN5 changes in response to the voltage level of the test signal INTN. Specifically, the voltage level of the scan output signal SN5 changes in response to the voltage level of the signal SN3, where the voltage level of the signal SN3 changes in response to the voltage level of the test signal INTN. When the MBFF 1000 operates in the normal mode, the selection circuit 206_N sends a data signal SN0 to the output node of the selection circuit 206_N to be used as an input signal SN2, and the scan output stage circuit 1004 holds the scan output signal SN5 at a fixed voltage level (e.g., a high voltage level or a low voltage level), regardless of the voltage level of the data signal SN0. Specifically, the voltage level of the scan output signal SN5 does not change in response to the voltage level of the signal SN3, while the voltage level of the signal SN3 changes in response to the voltage level of the data signal SN0.

[0056] Like the data output stage circuits 210_1, 210_2, and 210_N, the scan output stage circuit 1004 is implemented by a NOR gate, where one input node of the NOR gate is arranged to receive the signal SN3 at the output node N2 of the latch circuit 208_N, another input node of the NOR gate is arranged to receive a test enable signal STEB, and the output node of the NOR gate is arranged to output the scan output signal SN5 to the scan output terminal SQ of the MBFF 1000. Thus, when the MBFF 1000 operates in the normal mode (STEB = 1), the hold function is enabled at the NOR gate. When the MBFF 100 operates in the test mode (STEB = 0), the hold function is disabled at the NOR gate.

[0057] Figure 11The circuit structure shown is for illustrative purposes only and does not imply a limitation on the present invention. For example, the selection circuit can be implemented by any other circuit structure capable of selecting one of a normal data input and a test data input as the input signal to the subsequent latch circuit. For another example, the latch circuit can be implemented by any other circuit structure capable of processing the input signal obtained from the previous-stage selection circuit to generate a signal and output the generated signal to the subsequent-stage data output stage circuit having a holding function. Yet another example, the data output stage circuit having a holding function can be implemented by any other circuit structure capable of holding the data output signal at a fixed voltage level when the MBFF operates in the test mode. Yet another example, the scan output stage circuit having a holding function can be implemented by any other circuit structure capable of holding the scan output signal at a fixed voltage level when the MBFF operates in the normal mode.

[0058] Figure 12 FIG. is a diagram showing a first alternative design of a scan output stage circuit having a holding function according to an embodiment of the present invention. For example, the scan output stage circuit 1200 can be used to implement the scan output stage circuit 1004. The scan output stage circuit 1200 employs an OR gate 1202, where one input node of the OR gate 1202 is coupled to the output node N2 of the latch circuit at the front end, another input node of the OR gate 1202 is arranged to receive a test enable signal STEB, and the output node of the OR gate 1202 is arranged to output a scan output signal to the output terminal SQ of the scan MBFF 1000. When the MBFF 1000 operates in the test mode (STEB = 0), the voltage level of the scan output signal generated by the OR gate 1202 changes in response to the voltage of the signal at the output node N2 of the latch circuit at the front end. When the MBFF 1000 operates in the normal mode (STEB = 1), the scan output signal generated by the OR gate 1202 is held at a fixed voltage level (e.g., the power supply voltage), regardless of the voltage of the signal at the output node N2 of the latch circuit at the front end.

[0059] Figure 13FIG. is a diagram showing a second alternative design of a scan output stage circuit having a hold function according to an embodiment of the present invention. For example, the scan output stage circuit 1300 can be used to implement the scan output stage circuit 1004. The scan output stage circuit 1300 employs a NAND gate 1302, where one input node of the NAND gate 1302 is coupled to the output node N2 of the previous stage latch circuit, another input node of the NAND gate 1302 is arranged to receive a test enable signal STE, and the output node of the NAND gate 1302 is arranged to output a scan output signal to the scan terminal SQ of the MBFF 1000. When the MBFF 1000 operates in the test mode (STE = 1), the voltage level of the scan output signal generated by the NAND gate 1302 changes in response to the voltage of the signal at the output node N2 of the previous stage latch circuit. When the MBFF 1000 operates in the normal mode (STE = 0), the scan output signal generated by the NAND gate 1302 is held at a fixed voltage level (e.g., the power supply voltage), regardless of the signal voltage at the output node N2 of the previous stage latch circuit.

[0060] Figure 14 FIG. is a diagram showing a third alternative design of a scan output stage circuit having a hold function according to an embodiment of the present invention. For example, the scan output stage circuit 1400 can be used to implement the scan output stage circuit 1004. The scan output stage circuit 1400 employs an AND gate 1402, where one input node of the AND gate 1402 is coupled to the output node N2 of the previous stage latch circuit, another input node of the AND gate 1402 is arranged to receive a test enable signal STE, and the output node of the AND gate 1402 is arranged to output a scan output signal to the scan output terminal SQ of the MBFF 1000. When the MBFF 1000 operates in the test mode (STE = 1), the voltage level of the scan output signal generated by the AND gate 1402 changes in response to the voltage of the signal at the output node N2 of the previous stage latch circuit. When the MBFF 1000 operates in the normal mode (STE = 0), the scan output signal generated by the AND gate 1402 is held at a fixed voltage level (e.g., the ground voltage), regardless of the voltage of the signal at the output node N2 of the previous latch circuit.

[0061] Figure 15FIG. is a diagram showing a fourth alternative design of a scan output stage circuit having a holding function according to an embodiment of the present invention. For example, the scan output stage circuit 1500 may be used to implement the scan output stage circuit 1004. The scan output stage circuit 1500 includes PMOS transistors 1502 and 1504, NMOS transistors 1506, and an inverter 1508. The gate of the PMOS transistor 1504 receives the test enable signal STE, the source of the PMOS transistor 1504 is coupled to a reference voltage (e.g., the power supply voltage), and the drain of the PMOS transistor 1504 is coupled to the input node of the inverter 1508. The PMOS transistor 1502 and the NMOS transistor 1506 form a transmission gate. The gate of the PMOS transistor 1502 receives the test enable signal STEB, the source of the PMOS transistor 1502 is coupled to the output node N2 of the previous stage latch circuit, and the drain of the PMOS transistor 1502 is coupled to the input node of the inverter 1508. The gate of the NMOS transistor 1506 receives the test enable signal STE, the drain of the NMOS transistor 1506 is connected to the output node N2 of the previous stage latch circuit, and the source of the NMOS transistor 1506 is coupled to the input node of the inverter 1508.

[0062] When the MBFF 1000 operates in the test mode (STE = 1 & STEB = 0), the transmission gate composed of the PMOS transistor 1502 and the NMOS transistor 1506 is enabled, and the PMOS transistor 1504 is turned off, so that the voltage level of the scan output signal at the scan output terminal SQ changes in response to the voltage level of the signal at the output node N2 of the previous stage latch circuit. When the MBFF 1000 operates in the normal mode (STE = 0 & STEB = 1), the transmission gate composed of the PMOS transistor 1502 and the NMOS transistor 1506 is disabled, and the PMOS transistor 1504 is turned on, so that the voltage level of the scan output signal at the scan output terminal SQ is maintained at a fixed voltage level (e.g., the ground voltage), regardless of the voltage level of the signal at the output node N2 of the previous stage latch circuit.

[0063] Figure 16FIG. is a diagram showing a fifth alternative design of a scan output stage circuit with a hold function according to an embodiment of the present invention. For example, the scan output stage circuit 1600 can be used to implement the scan output stage circuit 1004. The scan output stage circuit 1600 includes NMOS transistors 1602 and 1604, PMOS transistors 1606, and an inverter 1608. The gate of the NMOS transistor 1604 receives a test enable signal STEB, the source of the NMOS transistor 1604 is coupled to a reference voltage (e.g., ground voltage), and the drain of the NMOS transistor 1604 is coupled to the input node of the inverter 1608. The PMOS transistor 1606 and the NMOS transistor 1602 form a transmission gate. The gate of the PMOS transistor 1606 receives a test enable signal STEB, the source of the PMOS transistor 1606 is coupled to the output node N2 of the previous stage latch circuit, and the drain of the PMOS transistor 1606 is coupled to the input node of the inverter 1608. The gate of the NMOS transistor 1602 receives a test enable signal STE, the drain of the NMOS transistor 1602 is connected to the output node N2 of the previous stage latch circuit, and the source of the NMOS transistor 1602 is coupled to the input node of the inverter 1608.

[0064] When the MBFF 1000 operates in the test mode (STE = 1 & STEB = 0), the transmission gate composed of the PMOS transistor 1606 and the NMOS transistor 1602 is enabled, and the NMOS transistor 1604 is turned off, so that the voltage level of the scan output signal at the scan output terminal SQ changes in response to the voltage level of the signal at the output node N2 of the previous stage latch circuit. When the MBFF 1000 operates in the normal mode (STE = 0 & STEB = 1), the transmission gate composed of the PMOS transistor 1606 and the NMOS transistor 1602 is disabled, and the NMOS transistor 1604 is turned on, so that the scan output signal at the scan output terminal SQ is held at a fixed voltage level (e.g., the power supply voltage), regardless of the voltage level of the signal at the output node N2 of the previous stage latch circuit.

[0065] The MBFF 1000 with N flip-flops 1002_1 - 1002_N connected to form an internal scan chain 104 is designed to have power-saving characteristics. For example, when the MBFF 1000 receives an external test signal S11 at the scan input terminal SI, the MBFF 1000 transmits the external test signal S11 through the internal scan chain 104, generates a scan output signal SN5 output from the flip-flop 1002_N to the scan output terminal SQ, and the voltage level of the scan output signal SN5 changes in response to the voltage level of the external test signal S11, and each of the N data output signals (output from the N flip-flops 1002_1 - 1002_N to the N data output terminals Q1 - QN) is maintained at a fixed voltage level regardless of the voltage level of the external test signal S11. Since there is no signal level transition in the N data output signals in the test mode of the MBFF 1000, the power consumption of the MBFF 1000 and the downstream combinational logic can be reduced.

[0066] In addition, when a data signal SN0 is received at the data input terminal DN, the MBFF 1000 generates a data output signal SN4 output from the flip-flop 1002_N to the data output terminal QN, and the voltage level of the data output signal SN4 changes in response to the voltage level of the data signal SN0, and the scan output signal SN5 (output from the flip-flop 1002_N to the scan output terminal SQ) is maintained at a fixed voltage level regardless of the voltage level of the data signal SN0. Since there is no signal level transition in the scan output signal in the normal mode of the MBFF 1000, the power consumption of the MBFF 1000 and the downstream logic can be reduced.

[0067] Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined by the claims.

Claims

1. A multi-bit flip-flop, characterized in that, Comprising: A plurality of flip - flops connected to form an internal scan chain, wherein the plurality of flip - flops includes a first flip - flop arranged to output a first data output signal at a first data output terminal of the multi - bit flip - flop, and the first flip - flop includes: A first selection circuit arranged to send a first data signal or a first test signal at a first data input terminal of the multi - bit flip - flop to an output node of the first selection circuit as a first input signal; A first latch circuit coupled to the output node of the first selection circuit and arranged to generate a first signal according to the first input signal; and A first data output stage circuit arranged to receive the first signal and generate the first data output signal according to the first signal; Wherein, when the multi - bit flip - flop operates in a test mode, the first selection circuit is arranged to transmit the first test signal to the output node of the first selection circuit as the first input signal, and the first data output stage circuit is arranged to hold the first data output signal at a fixed voltage level regardless of the voltage level of the first test signal; Wherein the plurality of flip - flops further includes a second flip - flop arranged to output a second data output signal or a scan output signal at a second data output terminal of the multi - bit flip - flop, and the second flip - flop includes: A second selection circuit arranged to send a second data signal at a second data input terminal of the multi - bit flip - flop to an output node of the second selection circuit as a second input signal when the multi - bit flip - flop operates in a normal mode, or to send a second test signal to the output node of the second selection circuit as the second input signal when the multi - bit flip - flop operates in the test mode; A second latch circuit coupled to the output node of the second selection circuit and arranged to generate a second signal according to the second input signal; and A second data output stage circuit arranged to receive the second signal and generate a second data output signal or a scan output signal according to the second signal, wherein when the multi - bit flip - flop operates in the normal mode, the second data output stage circuit generates a second data output signal according to the second signal and outputs the second data output signal at the second data output terminal, and when the multi - bit flip - flop operates in the test mode, the second data output stage circuit generates a scan output signal according to the second signal and outputs the scan output signal at the second data output terminal.

2. The multi-bit flip-flop according to claim 1, wherein Is also arranged to receive a test enable signal at a test enable terminal of the multi - bit flip - flop, and the first data output stage circuit is controlled by the test enable signal to generate the first data output signal according to the first signal.

3. The multi-bit flip-flop according to claim 1, wherein Is also arranged to receive a second test enable signal, which is the inverse of the first test enable signal received at the test enable terminal of the multi - bit flip - flop, and the first data output stage circuit is controlled by the second test enable signal to generate the first data output signal according to the first signal.

4. The multi-bit flip-flop according to claim 1, characterized in that It is also arranged to receive a first test enable signal at a test enable terminal of the multi-bit flip-flop and generate a second test enable signal that is inverse to the first test enable signal, and the first data output stage circuit is controlled by the first test enable signal and the second test enable signal to generate the first data output signal according to the first signal.

5. The multi-bit flip-flop according to claim 1, characterized in that, The first test signal is an external test signal received at a scan input terminal of the multi-bit flip-flop.

6. The multi-bit flip-flop according to claim 1, characterized in that, The plurality of flip-flops further includes a third flip-flop arranged to output a third data output signal at a third data output terminal of the multi-bit flip-flop, and the third flip-flop includes: A third selection circuit arranged to send a third data signal or a third test signal at a third data input terminal of the multi-bit flip-flop to an output node of the third selection circuit as a third input signal; A third latch circuit coupled to the output node of the third selection circuit and arranged to generate the first test signal and a third signal according to the third input signal; and A third data output stage circuit arranged to receive the third signal and generate the third data output signal according to the third signal.

7. The multi-bit flip-flop according to claim 6, characterized in that, When the multi-bit flip-flop operates in the test mode, the third selection circuit is arranged to transmit the third test signal to the output node of the third selection circuit as the third input signal, and the third data output stage circuit is arranged to hold the third data output signal at a fixed voltage level regardless of the voltage level of the third test signal.

8. The multi-bit flip-flop according to claim 7, wherein It is also arranged to receive a test enable signal at a test enable terminal of the multi-bit flip-flop, and the third data output stage circuit is controlled by the test enable signal to generate the third data output signal according to the third signal.

9. The multi-bit flip-flop according to claim 7, characterized in that, It is also arranged to receive a second test enable signal, which is the inverse of the first test enable signal received at a test enable terminal of the multi-bit flip-flop, and the third data output stage circuit is controlled by the second test enable signal to generate the third data output signal according to the third signal.

10. The multi-bit flip-flop according to claim 7, wherein It is also arranged to receive a first test enable signal at a test enable terminal of the multi-bit flip-flop and generate a second test enable signal that is inverse to the first test enable signal, and the third data output stage circuit is controlled by the first test enable signal and the second test enable signal to generate the third data output signal according to the third signal.

11. The multi-bit flip-flop according to claim 1, wherein The first latch circuit is also arranged to generate a third test signal according to the first input signal, and the plurality of flip-flops further includes a third flip-flop arranged to output a third data output signal at a third data output terminal of the multi-bit flip-flop, and the third flip-flop includes: A third selection circuit arranged to send a third data signal at a third data input terminal of the multi-bit flip-flop or the third test signal obtained from the first latch circuit to an output node of the third selection circuit as a third input signal; A third latch circuit, coupled to the output node of the third selection circuit, and generating a third signal according to the third input signal; and A third data output stage circuit, arranged to receive the third signal and generate the third data output signal according to the third signal.

12. A control method, characterized in that, Applied to a multi-bit flip-flop connected with N flip-flops to form an internal scan chain, wherein the multi-bit flip-flop includes a scan input terminal coupled to one of the N flip-flops, N data input terminals respectively coupled to the N flip-flops, and N data output terminals respectively coupled to the N flip-flops, where N is a positive integer not less than 1, the control method includes: When the multi-bit flip-flop operates in the normal mode, in response to receiving N data signals at the N data input terminals of the multi-bit flip-flop, generating N data output signals whose voltage levels change with the voltage levels of the N data signals, wherein the N data output signals are output from the N flip-flops to the N data output terminals; When the multi-bit flip-flop operates in the test mode, in response to receiving an external test signal at the scan input terminal of the multi-bit flip-flop, transmitting the external test signal through the internal scan chain; generating a scan output signal whose voltage level changes with the voltage level of the external test signal, wherein the scan output signal is output from one of the N flip-flops to one of the N data output terminals; regardless of the voltage level of the external test signal, maintaining each of the (N - 1) data output signals at the remaining (N - 1) data output terminals among the N data output terminals at a fixed voltage level.

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