Interrupt processing unit, related device and method

Abstract

The present disclosure provides an interrupt processing unit, related devices and methods. The interrupt processing unit includes: a transceiver unit for receiving a first interrupt request; a decision unit for filtering the interruption-saved main program interruption point information from the main program interruption point information according to the first interrupt request; a read-write unit for writing the interruption-saved main program interruption point information into a storage unit, so that after the instruction execution unit executes the first interrupt request, the read-write unit reads the interruption-saved main program interruption point information from the storage unit, so that the instruction execution unit continues to execute the main program, and the instruction execution unit is outside the interrupt processing unit. The embodiment of the present disclosure reduces the interrupt response time of the processing unit and improves the real-time performance of the interrupt response.

Description

Technical Field

[0001] The present disclosure relates to the field of chips, and in particular, to an interrupt processing unit, a related device and a method. Background Art

[0002] An interruption refers to an emergency event notification received by the processing unit when the main program is running, which occurs outside, inside, or in the main program itself. When responding to an interruption, the processing unit generally receives an interruption request from an interruption source (outside, inside, or in the main program itself), immediately stops the main program, automatically switches to the corresponding processing program (interrupt service program), and returns to the original main program after the processing is completed. In order to have the same state as when the main program is stopped after receiving an interruption request, when the main program is stopped, the main program interruption point information (including the code address executed when the main program is interrupted, the state of the processing unit when the interruption occurs, and the register value of the caller's saved attribute that is still needed when returning to the main program) should be written into the storage unit inside or outside the processing unit. After responding to the interruption request, the main program interruption point information is read back from the storage unit so that the main program can be continued to be executed using the main program interruption point information.

[0003] In the prior art, when the main program is stopped, all the main program interruption point information is saved indiscriminately, which takes a long time, and some of the main program interruption point information, such as the register values ​​of some general caller saving attributes, may not be used at all. Saving all the main program interruption point information indiscriminately reduces the interrupt response time, which may not meet the requirements of some occasions with high interrupt response real-time requirements. For example, in automobile driving control, the main program is the program for controlling driving. During driving, various sensors (temperature sensors, oil pressure sensors, speed sensors) may periodically report the sensed temperature, oil pressure, speed and other parameters. These parameters are reported through interrupt requests. The processing unit needs to respond to these interrupt requests frequently and determine whether to take corresponding measures through the interrupt service program. If the interrupt response time is too long and the real-time performance is poor, it is unacceptable. Summary of the invention

[0004] In view of this, one purpose of the present disclosure is to reduce the interrupt response time of the processing unit and improve the real-time performance of the interrupt response.

[0005] According to one aspect of the present disclosure, there is provided an interrupt processing unit, comprising:

[0006] A transceiver unit, configured to receive a first interrupt request;

[0007] A decision unit, configured to filter the interruption-saved main program interruption point information from the main program interruption point information according to the first interruption request;

[0008] A read-write unit is used to write the interruption point information of the main program saved by the interruption into a storage unit, so that after the instruction execution unit executes the first interrupt request, the read-write unit reads the interruption point information of the main program saved by the interruption from the storage unit, so that the instruction execution unit continues to execute the main program, and the instruction execution unit is outside the interrupt processing unit.

[0009] Optionally, the main program interruption point information includes at least one or more of a main program interruption point code address, a current state of a processing unit to which the interrupt processing unit belongs, and a register value of a caller-saved attribute.

[0010] Optionally, the main program interruption point code address, the processing unit current state, and the register value of the caller saved attribute are respectively stored by the main program interruption point code address register, the processing unit current state register, and the caller saved attribute register; writing the interruption saved main program interruption point information into the storage unit includes: pushing out at least one of the interruption saved main program interruption point code address register, the processing unit current state register to be recorded, and the caller saved attribute register to be recorded to the storage unit.

[0011] Optionally, the filtering the main program interruption point information to be recorded from the main program interruption point information according to the first interruption request includes:

[0012] Adding the main program breakpoint code address and the current state of the processing unit to the main program breakpoint information saved by the interruption;

[0013] According to the type of the first interrupt request, the register value of the caller-saved attribute saved by the interrupt is filtered out from the register value of the caller-saved attribute, and the main program interrupt point information saved by the interrupt is added.

[0014] Optionally, filtering out the register values ​​of the caller-saved attributes to be saved by the interrupt from the register values ​​of the caller-saved attributes according to the type of the first interrupt request includes: filtering out the register values ​​of the caller-saved attributes to be saved by the interrupt from the register values ​​of the caller-saved attributes according to a predetermined rule and according to the type of the first interrupt request.

[0015] Optionally, the method of filtering out the register value of the caller-saved attribute of the interrupt from the register value of the caller-saved attribute according to the type of the first interrupt request includes: inputting the type of the first interrupt request into a pre-trained register value screening model for the caller-saved attribute of the interrupt, thereby obtaining the register value of the caller-saved attribute of the interrupt.

[0016] Optionally, if the transceiver unit receives a second interrupt request after receiving the first interrupt request, and the main program interruption point information saved by the interrupt corresponding to the first interrupt request has not been completely written into the storage unit, the read-write unit continues to write the unwritten part of the main program interruption point information saved by the interrupt corresponding to the first interrupt request into the storage unit so that it is shared by the first interrupt request and the second interrupt request, and the decision unit determines the execution order of the first interrupt request and the second interrupt request according to the priority of the first interrupt request and the second interrupt request, and sends the execution order and the second interrupt request to the instruction execution unit, and the instruction execution unit executes the first interrupt request and the second interrupt request according to the execution order after the main program interruption point information saved by the interrupt is completely written into the storage unit.

[0017] Optionally, determining the execution order of the first interrupt request and the second interrupt request according to the priorities of the first interrupt request and the second interrupt request includes:

[0018] If the priority of the second interrupt request is greater than the priority of the first interrupt request, the execution order is that the second interrupt request precedes the first interrupt request;

[0019] If the priority of the second interrupt request is not greater than the priority of the first interrupt request, the execution order is that the first interrupt request precedes the second interrupt request.

[0020] Optionally, if the transceiver unit receives a second interrupt request after receiving the first interrupt request, and the first interrupt request has started to execute but has not yet been completed, but the priority of the second interrupt request is greater than the priority of the first interrupt request, then the decision unit sends the second interrupt request to the instruction execution unit for execution, and the read-write unit writes the register record information and the stack position information to the storage unit, wherein the register record information is the information recorded in the register stack during the process of the execution instruction unit executing the first interrupt request, and the stack position information indicates the location where the register record information is recorded in the register stack, so that after the second interrupt request is executed, the read-write unit reads the register record information and the stack position information from the storage unit so that the first interrupt request continues to execute.

[0021] Optionally, if the transceiver unit receives a second interrupt request after receiving the first interrupt request, and the first interrupt request has started to execute but has not yet been completed, but the priority of the second interrupt request is not greater than the priority of the first interrupt request, then the decision unit will send the second interrupt request to the instruction execution unit for execution only after the first interrupt request is executed, and the main program interruption point information saved by the interrupt in the storage unit is shared by the first interrupt request and the second interrupt request, so that after the first interrupt request and the second interrupt request are executed, the read-write unit reads the main program interruption point information saved by the interrupt from the storage unit, so that the main program continues to execute.

[0022] Optionally, if the transceiver unit receives a second interrupt request after receiving the first interrupt request, and the first interrupt request has been executed but the main program interrupt point information saved by the interrupt corresponding to the first interrupt request has not been removed from the storage unit, then the decision unit sends the second interrupt request to the instruction execution unit for execution, and allows the main program interrupt point information saved by the interrupt in the storage unit to be shared by the first interrupt request and the second interrupt request, so that after the first interrupt request and the second interrupt request are both executed, the read-write unit reads the main program interrupt point information saved by the interrupt from the storage unit, so that the main program continues to execute.

[0023] According to one aspect of the present disclosure, there is provided a processing unit, comprising:

[0024] An interrupt handling unit as described above;

[0025] The instruction execution unit is used to execute the main program and the interrupt service program of the first interrupt request.

[0026] According to one aspect of the present disclosure, a system on chip is provided, comprising the processing unit as described above.

[0027] According to one aspect of the present disclosure, there is provided an interrupt processing method, comprising:

[0028] receiving a first interrupt request;

[0029] According to the first interrupt request, the main program interruption point information to be recorded is filtered from the main program interruption point information;

[0030] The main program interruption point information to be recorded is written into a storage unit, so that after the first interruption request is executed, the main program interruption point information to be recorded is read from the storage unit, so that the main program continues to be executed.

[0031] In the disclosed embodiment, when the main program is stopped in response to an interrupt request, instead of saving all the main program interruption point information indiscriminately, some main program interruption point information which is more likely to be used by the interrupt request is screened from all the main program interruption point information according to the interrupt request, that is, the main program interruption point information saved is saved in the storage unit. Compared with the prior art method of saving all the main program interruption point information indiscriminately, the saving time is reduced, thereby reducing the interrupt response time of the processing unit and improving the real-time performance of the interrupt response. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other objects, features and advantages of the present disclosure will become more apparent through the description of the embodiments of the present disclosure with reference to the following drawings, in which:

[0033] Figure 1 is an application scenario structure diagram of an automotive electrical control system applied in one embodiment of the present disclosure;

[0034] Figure 2 is an internal structure diagram of a processing unit according to an embodiment of the present disclosure;

[0035] Figure 3 is an internal structure diagram of an interrupt processing unit according to an embodiment of the present disclosure;

[0036] Figure 4 is a flowchart of an interrupt processing method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The present disclosure is described below based on embodiments, but the present disclosure is not limited to these embodiments. In the detailed description of the present disclosure below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present disclosure without the description of these details. In order to avoid confusing the essence of the present disclosure, well-known methods, processes, and procedures are not described in detail. In addition, the drawings are not necessarily drawn to scale.

[0038] The following terms are used in this article.

[0039] Interrupt: refers to the emergency event notification received by the processing unit when the main program is running, which occurs outside, inside or in the main program itself. When the processing unit responds to the interrupt, it generally receives an interrupt request from the interrupt source (outside, inside or in the processing unit or in the main program itself), immediately stops the main program, and automatically transfers to the corresponding processing program (interrupt service program). After the processing is completed, it returns to the original main program.

[0040] Main program: The program that the processing unit runs when it is not responding to an interrupt. It is generally run through the process of reading instructions, decoding instructions, and executing instructions.

[0041] Interrupt service routine: A special program used by a processing unit to respond to an interrupt request. It can also be a function set consisting of a special function entry, its child functions, grandchild functions, etc.

[0042] Interrupt response time: The time it takes for a processing unit to respond to an interrupt request from the time it receives the interrupt request.

[0043] Interrupt response real-time performance: the timeliness of the response of the processing unit after receiving an interrupt request. Generally speaking, the smaller the interrupt response time, the stronger the interrupt response real-time performance.

[0044] Interrupt request: A request for a processing unit to handle an interrupt.

[0045] Main program interruption point information: Since the processing unit needs to respond to the interrupt request and terminate the main program, in order to return to the main program after processing the interrupt, it can also have the same state as when the main program was terminated when the interrupt request was just received, and the information of the interruption time point must be recorded. This information includes the main program interruption point code address, the current state of the processing unit, the register value of the caller's saved attribute, etc.

[0046] Main program breakpoint code address: the code address that the main program executes when the main program is terminated.

[0047] Processing unit status: The status of the processing unit, including the working mode and the corresponding flag register, etc.

[0048] Caller-saved attribute: In order to distinguish whether the register is called by the parent function or by the child function, different attributes are assigned to the register, where the caller-saved attribute refers to the register being called by the parent function, and the non-caller-saved attribute refers to the register being called by the child function. In the disclosed embodiment, the register with the caller-saved attribute will be used by the processing unit when executing the main program, and the register with the non-caller-saved attribute will be used by the processing unit when executing the interrupt service program in response to an interrupt request.

[0049] Processing unit: A device that can read, decode and execute computer instructions. It can take the form of a central processing unit (CPU), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), etc. In some cases, it can also include processing units designed to improve the data processing speed in some special-purpose fields (for example, processing images, processing various operations of deep learning models, etc.) where traditional processing units are inefficient, such as graphics processing units (GPUs), neural network processing units (NPUs), etc.

[0050] Push out: Take registers out in the reverse order of the order in which they are stacked in the register stack. For example, a traditional register stack stacks registers from bottom to top, with the last register stacked on top of the first register. When taking out from a register stack, take out the stacked registers in the opposite direction, i.e., from top to bottom.

[0051] System-on-a-chip (SoC): refers to a complete system integrated on a single chip, generally including the above-mentioned processing unit, memory, and peripheral circuits.

[0052] Application scenarios of the present disclosure

[0053] The present disclosure is applied to some occasions that have high requirements for the real-time interrupt response, such as industrial control, automobile control, etc. These occasions generally generate various interrupts frequently. If the interrupt response time is very slow, it is unacceptable. For example, in automobile driving control, the main program is the program that controls driving. During driving, various sensors (temperature sensors, oil pressure sensors, speed sensors) may periodically report the sensed temperature, oil pressure, speed and other parameters. These parameters are reported through interrupt requests. The processing unit needs to respond to these interrupt requests frequently and determine whether to take corresponding measures through the interrupt service program. If the interrupt response time is too long, some accidents may not be avoided in time.

[0054] Figure 1 It is a structural diagram of an automotive electrical control system applied in one embodiment of the present disclosure.

[0055] like Figure 1In the illustrated automotive electrical control system 1, an alternator 4 is connected to an internal combustion engine 2 in the vehicle through a transmission component 5. The heat energy of the internal combustion engine 2 is converted into kinetic energy, and the rotor of the alternator 4 is rotated through the transmission component 5 to output a supply voltage and current. The automotive electrical control system 1 also includes a battery 6 and a series of vehicle electrical loads 8. The battery 6 is electrically connected to the alternator 4 through a vehicle electrical connection line 7, and the vehicle electrical load 8 is electrically connected to the alternator 4 and the battery 6 through the vehicle electrical connection line 7. The vehicle electrical load 8 may include, for example, an electrical system of a headlight system and / or an electrical system of a wiper system and / or an electrical system of a rear window defogger system, or any other type of similar electrical device that can be powered by the alternator 4 present in the motor vehicle 3. An intelligent battery sensor (IBS) 15 is electrically connected to the battery 6 to instantly sense the battery operating state, and is configured to measure and output a series of battery state parameters. A data communication line 20 connects the intelligent battery sensor 15 to the processing unit 12. The data communication line 20 may preferably but not necessarily be made in the form of a data / control bus that implements a LIN (Local Interconnect Network) protocol.

[0056] The processing unit 12 is used to run a control program that supports the normal operation of each component in the automobile, and executes an interrupt service program after receiving an interrupt request as in the embodiment of the present disclosure. The control program that supports the normal operation of each component in the automobile can, for example, determine the on / off state of each vehicle electrical load 8 connected to the AC generator 4, and determine the supply constraints defined by the power supply range for each vehicle electrical load 8 in the on state, such as the maximum and minimum values ​​of the voltage or current of the power supply range. The processing unit 12 can be configured to determine the power supply range of each vehicle electrical load 8 based on the battery status parameters. The processing unit 12 is also capable of receiving diagnostic input data of the AC generator 4 and transmitting the diagnostic input data to the vehicle dashboard 21 through the data communication line 22, so as to send a signal indicating a fault condition of the AC generator 4, for example, through the AC generator warning light (not shown) present on the vehicle dashboard 21 itself.

[0057] An intelligent alternator control module (IAM) 19 is electrically connected to the alternator 4 and is configured to diagnose the operating status of the alternator 4 and transmit alternator diagnostic data to the processing unit 12 via the data communication line 24. The intelligent alternator control module 19 is also configured to regulate an excitation / control current Ireg circulating through an inductance / excitation circuit of the alternator 4 according to a regulation voltage Vreg to generate a supply voltage V. The intelligent alternator control module 19 may be configured to transmit duty cycle indicative data of the excitation / control current Ireg of the alternator 4 to the processing unit 12.

[0058] The memory 14 is a storage component of the automobile electrical control system 1, which can store various data used by the processing unit 12 when executing the control program and responding to interrupts. The sensor 13 includes a speed sensor, an acceleration sensor, a temperature sensor, an oil pressure sensor, etc., which are respectively used to sense the speed, acceleration, temperature, oil pressure, etc. of the automobile during driving, and generate corresponding sensing signals. These sensing signals are reported to the processing unit 12 by the sensor 13 in the form of interrupt requests. After receiving these interrupt requests, the processing unit 12 terminates the main program (such as the control program for controlling the normal operation of various components in the automobile, or the automatic driving program in the unmanned vehicle), responds to the interrupt request, processes the reported sensing data, and takes corresponding countermeasures. For example, if the reported sensing data is within the normal range, no processing is required. If it is not within the normal range, abnormal processing such as braking is adopted.

[0059] Processing Unit

[0060] Figure 2 An embodiment according to the present disclosure is shown. Figure 2 Specific structural diagram of the processing unit 12.

[0061] like Figure 2 As shown, the processing unit 12 may include multiple processor cores 120, and the multiple processor cores 120 may run in parallel to jointly perform certain tasks. The multiple processor cores 120 may share a memory 14. The memory 14 is used to store instruction information and / or data information represented by data signals, such as storing data (such as calculation results) provided by the processor core 120, and may also be used to implement data exchange between the processor cores 120 or with an external storage device (or referred to as an auxiliary memory or external memory).

[0062] In some cases, the processor core 120 may need to access the memory 14 to obtain data in the memory 14 or modify the data in the memory 14. Since the access speed of the memory 14 is slow, in order to alleviate the speed difference between the processor core 120 and the memory 14, the server 140 also includes a cache memory 18 coupled to the bus, and the cache memory 18 is used to cache some data such as program data or message data in the memory 14 that may be repeatedly called. The cache memory 18 is implemented by a storage device of the type of static random access memory (SRAM) for example. The cache memory 18 can be a multi-level structure, such as a three-level cache structure with a first-level cache (L1), a second-level cache (L2) and a third-level cache (L3), or it can be a cache structure with more than three levels or other types of cache structures. In some embodiments, a portion of the cache memory 18 (such as a first-level cache, or a first-level cache and a second-level cache) can be integrated inside the processor core 120 (such as Figure 2 L1 cache, L2 cache) or integrated with the processor core 120 in the same system on chip (such as Figure 2 In the third-level cache L3).

[0063] The general process of the processing unit 12 executing instructions includes: fetching instructions from the memory 14 storing instructions, decoding the fetched instructions, executing the decoded instructions, saving the instruction execution results, etc., and this cycle continues until all instructions in the instruction sequence are executed or a shutdown instruction is encountered. In order to implement the above-mentioned execution process of instructions, the processing unit 12 may include an instruction fetch unit 124, an instruction decoding unit 125, an instruction issuing unit (not shown), an instruction execution unit 121, and an instruction retirement unit (not shown).

[0064] The instruction fetch unit 124 serves as the startup engine of the processing unit 12 and is used to transfer instructions from the memory 14 to the instruction register (which may be Figure 2 A register in the register file 26 shown is used to store instructions) and receives the next instruction fetch address or calculates the next instruction fetch address according to an instruction fetch algorithm. The instruction fetch algorithm includes, for example, increasing or decreasing the address according to the instruction length.

[0065] After fetching the instruction, the processing unit 12 enters the instruction decoding stage, and the instruction decoding unit 125 decodes the fetched instruction according to the predetermined instruction format to obtain the operand acquisition information required by the fetched instruction, thereby preparing for the operation of the instruction execution unit 121. The operand acquisition information, for example, points to an immediate number, a register or other software / hardware that can provide a source operand.

[0066] The instruction issuing unit is usually present in the high-performance processing unit 12, located between the instruction decoding unit 125 and the instruction execution unit 121, and is used for scheduling and controlling instructions to efficiently allocate each instruction to different instruction execution units 121, so that the parallel operation of multiple instructions becomes possible. After the instruction is fetched, decoded and scheduled to the corresponding instruction execution unit 121, the corresponding instruction execution unit 121 starts to execute the instruction, that is, to execute the operation indicated by the instruction and realize the corresponding function.

[0067] The instruction retirement unit (or instruction write back unit) is mainly responsible for writing the execution results generated by the instruction execution unit 121 back to the corresponding storage location (for example, the register inside the processing unit 12), so that subsequent instructions can quickly obtain the corresponding execution results from the storage location.

[0068] The memory management unit (MMU) 122 is used to implement the translation from virtual address to physical address. The memory 14 stores all the mapping table entries from virtual address to physical address. In this way, when the memory 14 is to be accessed, the virtual address in the access instruction is first converted into a physical address through the mapping table entry, and then the memory 14 is accessed according to the physical address. The internal management unit 122 stores a part of the commonly used mapping table entries from virtual address to physical address. After the data access instruction to the memory 14 is obtained by the instruction fetch unit 124, the instruction decoding unit 125 can decode the data access instruction so that the source operand of the data access instruction can be obtained. The decoded data access instruction is provided to the corresponding instruction execution unit 121, and the instruction execution unit 121 can perform corresponding operations on the source operand of the memory access instruction to obtain the virtual address corresponding to the memory access instruction, and initiate an address translation request to the memory management unit 122 with the virtual address. The memory management unit 122 responds to the address translation request and converts the virtual address in the address translation request into a physical address according to the table entry stored in itself. If the mapping address is not in the table entry stored in the memory management unit 122, the memory management unit 122 obtains the corresponding table entry from the memory 14 to obtain the corresponding physical address. After obtaining the physical address, the instruction execution unit 121 can access the memory 14 according to the obtained physical address.

[0069] The information exchange between the memory 14 and the cache memory 18 is usually organized in blocks. In some embodiments, the cache memory 18 and the memory 14 can be divided into data blocks according to the same spatial size, and the data block can be used as the minimum unit of data exchange between the cache memory 18 and the memory 14 (including one or more data of a preset length). For the sake of simplicity and clarity, the data blocks in the cache memory 18 are referred to as cache blocks (which can be called cache lines or cache lines), and different cache blocks have different cache block addresses; the data blocks in the memory 14 are referred to as memory blocks, and different memory blocks have different memory block addresses. The cache block address includes, for example, a physical address tag for locating the data block.

[0070] Due to space and resource limitations, the cache memory 18 cannot cache all the contents in the memory 14, that is, the storage capacity of the cache memory 18 is usually smaller than that of the memory 14, and the cache block addresses provided by the cache memory 18 cannot correspond to all the memory block addresses provided by the memory 14. When the processing unit 12 needs to access the memory, it first accesses the cache memory 18 via the bus to determine whether the content to be accessed has been stored in the cache memory 18. If so, the cache memory 18 hits, and the processing unit 12 directly calls the content to be accessed from the cache memory 18; if the content that the processing unit 12 needs to access is not in the cache memory 18, the processing unit 12 needs to access the memory 14 via the bus to find the corresponding information in the memory 14. Because the access rate of the cache memory 18 is very fast, when the cache memory 18 hits, the efficiency of the processing unit 12 can be significantly improved, thereby also improving the performance and efficiency of the entire processing unit 12.

[0071] In some embodiments, Figure 2As shown, the processing unit 12 may include a register file 126 (RegisterFile), and the register file 126 may include multiple registers for storing different types of data and / or instructions, and these registers may be of different types. For example, the register file 126 may include: integer registers, floating point registers, status registers, instruction registers, and pointer registers. The registers in the register file 126 may be implemented by general registers, or a specific design may be adopted according to the actual needs of the processing unit 12. The register file 126 also includes registers with caller-saved attributes and registers with non-caller-saved attributes. The registers with caller-saved attributes are registers called by the parent function. The registers with non-caller-saved attributes are registers called by the child function. In the embodiment of the present disclosure, the registers with caller-saved attributes will be used by the instruction execution unit 121 when executing the main program, and the registers with non-caller-saved attributes will be used by the instruction execution unit 121 when executing the interrupt service program in response to an interrupt request.

[0072] The interrupt processing unit 127 is a unit that saves necessary information for interrupt response and recovery. Note that it is not a unit that services interrupts. The unit that services interrupts and executes interrupt service programs is still the instruction execution unit 121. The interrupt processing unit 127 only provides necessary preparations such as parameter storage for such services. Since the instruction execution unit 121 needs to respond to an interrupt request and terminate the main program, in order to return to the main program after processing the interrupt, it can also have the same state as when the main program was terminated when the interrupt request was just received. The interrupt processing unit 127 must record various status information of the interrupt time point to the storage unit, that is, the main program interruption point information. After the instruction execution unit 121 responds to the interrupt, the main program interruption point information is read back so that the main program can continue to be executed according to the main program interruption point information. The interrupt processing unit 127 is the unit that does these preparatory work for the interrupt response. It is the main component of the improvement of the embodiment of the present disclosure.

[0073] Interrupt Processing Unit

[0074] Figure 3 FIG. 1 is an internal structure diagram of the interrupt processing unit 127 according to an embodiment of the present disclosure. Figure 3 As shown, the interrupt processing unit 127 may include a read-write unit 1271 , a decision unit 1273 , and a transceiver unit 1272 .

[0075] The transceiver unit 1272 receives a first interrupt request from an interrupt source. The interrupt source is the source of the interrupt request, which may be located outside or inside the processing unit 12 or in the main program itself. Figure 3In the example, it is embodied as sensor 13. Sensor 13 senses the temperature, oil pressure and other parameters of the car during driving, and reports them to interrupt processing unit 127 through interrupt request, so that instruction execution unit 121 can determine whether to take special treatment, etc. The interrupt request is a request for processing unit 12 to terminate the main program being executed and handle the interrupt. Figure 3 In the example, the sensor 13 periodically reports various sensed parameters through an interrupt request, and the instruction execution unit 121 suspends the main program, determines whether to take certain measures based on these sensed parameters, and then continues the processing of the main program. The main program is the program that the processing unit runs when it does not respond to an interrupt.

[0076] The decision unit 1273 filters the interruption-saved main program interruption point information from the main program interruption point information according to the first interruption request.

[0077] The main program interruption point information is the status information of the interruption time point when the processing unit 12 terminates the main program in response to the interrupt request. When the interrupt is processed, the main program will continue to run based on these status information when returning to the main program. The main program interruption point information includes at least one or more of the main program interruption point code address, the current state of the processing unit, and the register value of the caller saving attribute. The main program interruption point code address is the code address executed by the main program when the main program is terminated. After the interrupt is processed, this address must be found to continue to execute the remaining main program. The current state of the processing unit refers to the state of the processing unit when the main program is terminated, including the working mode (such as user mode) and the corresponding flag register, etc. After the interrupt is processed, it is necessary to restore to the same working mode as when the main program was terminated, and the flag register, etc. need to remain completely unchanged, that is, the environment for running the main program remains unchanged, so that there will be no running errors. Since the registers with caller-saved attributes are used by the processing unit 12 when executing the main program, and the registers with non-caller-saved attributes are used by the processing unit 12 when executing the interrupt service program in response to the interrupt request, the values ​​of the registers with caller-saved attributes also need to be recorded and restored after the interrupt is processed, otherwise errors will occur when the main program calls the values ​​of these registers when running the main program. The prior art records all these main program interruption point information indiscriminately so that they can be used when the main program resumes running, and the amount of records is very large. The embodiment of the present disclosure filters out the part of the main program interruption point information that may be used by the first interrupt request, that is, the main program interruption point information saved by the interrupt, and records it, which greatly reduces the amount of information that needs to be recorded and reduces the interrupt response time.

[0078] In one embodiment, the main program interruption point information saved by the interruption can be filtered from the main program interruption point information, which can be performed according to a predetermined rule. The predetermined rule can be a table of correspondence between the type of interruption request and the interruption point information saved by the interruption. The type of interruption request is, for example, an interruption request for reporting the sensed temperature, an interruption request for reporting the sensed oil pressure, and an interruption request for externally forcing a certain action (such as braking). The type of interruption request can be carried in the first interruption request. When the interruption request is an interruption request for reporting the sensed temperature, it is often necessary to record some specific main program interruption point information, while some main program interruption point information is not required. When the interruption request is an interruption request for reporting the sensed oil pressure, it is often necessary to record other specific main program interruption point information, while some main program interruption point information is not required. The correspondence between the type of interruption request and the interruption point information saved by the interruption is recorded in advance. When a certain type of interruption request is received later, the recorded correspondence table is searched to obtain the corresponding interruption point information saved by the interruption. The advantages of this embodiment are simple operation, high search efficiency, and are conducive to improving the real-time performance of interrupt response.

[0079] In one embodiment, the main program interruption point information saved by the interruption can be filtered from the main program interruption point information, and the main program interruption point information saved by the interruption can be filtered using a model. It is a machine learning model, such as a deep learning model. The main program interruption point information that has changed in response to different interruption requests in history is recorded, and the main program interruption point information that has changed is the main program interruption point information that needs to be recorded before responding to the interruption request. These historical interruption requests are input into the model as samples, and the model determines the main program interruption point information that needs to be recorded, and compares it with the main program interruption point information that has changed in response to the interruption request obtained in advance. If the ratio of samples that are consistent in all samples exceeds a predetermined ratio, the model training is considered successful. The type of the first interrupt request is input into the pre-trained model to obtain the interruption saved by the interruption saved by the interruption. Because it adopts the training model method, the accuracy of filtering the interruption saved by the interruption of the main program is greatly improved, which is conducive to improving the correctness of the execution of the main program after recovery.

[0080] In addition, considering that in the main program interruption point information, the main program interruption point code address is basically required to resume the main program operation under any circumstances, the current state of the processing unit is also required in most cases, and the register value of the caller-saved attribute is often partially required and partially not required, therefore, in another embodiment, the main program interruption point code address and the current state of the processing unit can all be directly added to the interruption saved main program interruption point information without selection, and the focus is on screening the register value of the caller-saved attribute. During screening, the register value of the caller-saved attribute saved by the interrupt can be screened from the register value of the caller-saved attribute according to the type of the first interrupt request, and added to the interruption saved main program interruption point information. Compared with the method of completely screening the main program interruption point information, it further improves the real-time performance of the interrupt response.

[0081] When filtering out the register values ​​of the caller-saved attributes of the interrupt from the register values ​​of the caller-saved attributes according to the type of the first interrupt request, a method similar to the aforementioned method of filtering the interrupt-saved main program interrupt point information from the main program interrupt point information can be adopted, that is, according to a predetermined rule (such as a corresponding relationship table between the interrupt request type and the register value of the caller-saved attributes of the interrupt), or a pre-trained interrupt-saved caller-saved attribute register value screening model can be used, and the type of the first interrupt request can be input into the pre-trained interrupt-saved caller-saved attribute register value screening model to obtain the register value of the caller-saved attributes of the interrupt. The training method of the interrupt-saved caller-saved attribute register value screening model is similar to the training method of the interrupt-saved main program interrupt point information screening model, and is not described in detail to save space. The former method is used to improve the real-time nature of the interrupt response; the latter method is used to make the execution effect more accurate when resuming the execution of the main program.

[0082] The read / write unit 1271 writes the interruption point information of the main program saved by the interruption into the storage unit 130. The storage unit 130 may be inside the processing unit 12, for example Figure 2 The cache memory 18 in the processing unit 12 may also be external to the processing unit 12, for example Figure 2 The decision unit 1273 then sends the first interrupt request to the instruction execution unit 121 for execution using the interrupt service program. After the instruction execution unit 121 executes the first interrupt request, it notifies the decision unit 1273. The decision unit 1273 notifies the read / write unit 1271 to read the interruption-saved main program interruption point information from the storage unit 130 and send it back to the instruction execution unit 121, so that the instruction execution unit 121 can continue to execute the main program using the interruption-saved main program interruption point information.

[0083] In one embodiment, if the instruction execution unit 121 needs to use additional main program interruption point information other than the main program interruption point information saved by the interruption during the execution of the first interruption request, that is, in addition to the main program interruption point information written into the storage unit 130 by the interruption processing unit 127, other main program interruption point information needs to be used. This means that the estimated main program interruption point information saved by the interruption is inaccurate, and it is necessary to re-record the additional main program interruption point information to be used into the storage unit 130, so that after the interruption response is completed, when the main program is resumed, all the main program interruption point information will be restored to not affect the execution of the main program. The disclosed embodiment actually provides a method of first quickly estimating the most likely main program interruption point information and pre-recording it, and then supplementing the record in small amounts when the actual needs do not match the estimation, taking into account both efficiency and accuracy.

[0084] When the instruction execution unit 121 needs to add the main program interruption point information, it notifies the decision unit 1273. The decision unit 1273 supplements the additional main program interruption point information into the interruption-saved main program interruption point information through the read-write unit 1271.

[0085] In one embodiment, the main program interruption point code address, the processing unit current state, and the register value of the caller saved attribute are stored in the main program interruption point code address register, the processing unit current state register, and the caller saved attribute register, respectively, and these registers are located in the register stack 126. When the interruption saved main program interruption point information is written into the storage unit 130, at least one of the interruption saved main program interruption point code address register, the interruption saved processing unit current state register, and the interruption saved caller saved attribute register can be pushed out to the storage unit 130.

[0086] Processing of multiple consecutive interrupt requests

[0087] I. When the interruption point information of the main program saved has not been completely written into the storage unit 130, another interruption request is received

[0088] If the transceiver unit 1272 receives a second interrupt request after receiving the first interrupt request, and the main program interruption point information corresponding to the first interrupt request has not been completely written into the storage unit 130, at this time, the main program interruption point information corresponding to the second interrupt request is actually consistent with the main program interruption point information corresponding to the first interrupt request, and the read-write unit 1271 can continue to write the unwritten part of the main program interruption point information corresponding to the first interrupt request into the storage unit 130, so as to be shared by the first interrupt request and the second interrupt request. Then, the decision unit 1273 determines the execution order of the first interrupt request and the second interrupt request according to the priority of the first interrupt request and the second interrupt request, and sends the execution order and the second interrupt request to the instruction execution unit 121. Although the instruction execution unit 121 has already received the first interrupt request at this time, since the main program interruption point information corresponding to the interruption has not been completely written into the storage unit 130, the instruction execution unit 121 has not yet processed the first interrupt request. After obtaining the execution order, the instruction execution unit 121 can execute the first interrupt request and the second interrupt request in this order. If the priority of the second interrupt request is greater than the priority of the first interrupt request, the execution order is that the second interrupt request precedes the first interrupt request, and the instruction execution unit 121 executes the second interrupt request first, and then executes the first interrupt request. If the priority of the second interrupt request is not greater than the priority of the first interrupt request, the execution order is that the first interrupt request precedes the second interrupt request, and the instruction execution unit 121 executes the first interrupt request first, and then executes the second interrupt request. After the instruction execution unit 121 executes the two interrupt requests, it notifies the decision unit 1273. The decision unit 1273 notifies the read-write unit 1271 to read the interruption point information of the main program saved by the interruption shared by the first interrupt request and the second interrupt request from the storage unit 130. The instruction execution unit 121 continues to execute the main program according to the interruption point information of the main program saved by the interruption.

[0089] In the above embodiment, when other interrupt requests are received before the interrupt point information of the main program saved by the interrupt has been completely written into the storage unit 130, interrupt requests of different priorities can be executed according to the priority and the real-time performance of the interrupt response is maximized while ensuring the priority.

[0090] II. When an interrupt request has started to execute but has not yet been completed, another interrupt request is received

[0091] If the transceiver unit 1272 receives a second interrupt request after receiving the first interrupt request, and the first interrupt request has been executed by the instruction execution unit 121 but has not yet been completed, the main program interrupt point information saved by the interrupt corresponding to the first interrupt request has been completely written into the storage unit 130. There are two situations at this time. The first situation is that the priority of the second interrupt request is greater than the priority of the first interrupt request. At this time, the instruction execution unit 121 also terminates the execution of the first interrupt request and executes the second interrupt request immediately, that is, interrupt nesting occurs. The second situation is that the priority of the second interrupt request is not greater than the priority of the first interrupt request, that is, interrupt nesting does not occur. In this case, the execution of the first interrupt request is not interrupted. It is only necessary to let the instruction execution unit 121 execute the second interrupt request after the first interrupt request is executed, and then resume the execution of the main program. The following describes these two situations respectively.

[0092] In the first case, the priority of the second interrupt request is greater than the priority of the first interrupt request, and the decision unit 1273 will immediately send the second interrupt request to the instruction execution unit 121, and the instruction execution unit 121 will stop executing the first interrupt request and immediately execute the second interrupt request. Since the second interrupt request interrupts the execution of the first interrupt request, it is necessary to record the changes caused by the executed part of the first interrupt request, and then resume the execution of the first interrupt request according to the content of this part of the record after the second interrupt request is executed. Without this part of information, the first interrupt request cannot be correctly executed after the recovery. This part of the content that needs to be recorded includes register record information and stack location information. The register record information is the information recorded in the register stack 126 during the execution of the first interrupt request by the instruction execution unit 121. Only by saving these recorded information to the storage unit 130 first, and then restoring it to the register stack 126 after the second interrupt request is executed, can the instruction execution unit 121 continue to execute the remaining part of the first interrupt request, so it is necessary to record this information to the storage unit 130. The stack location information indicates the location where the register record information is recorded in the register stack. Without this information, the register record information cannot be found correctly, so it is necessary to record this information in the storage unit 130. After the instruction execution unit 121 executes the second interrupt request, it notifies the decision unit 1273. The decision unit 1273 notifies the read-write unit 1271 to read the register record information and the stack location information from the storage unit 130 and restore them to the register stack 126, so that the instruction execution unit 121 can continue to execute the remaining part of the first interrupt request. After the instruction execution unit 121 executes the first interrupt request, it notifies the decision unit 1273. The decision unit 1273 notifies the read-write unit 1271 to read the main program interruption point information saved by the interrupt corresponding to the first interrupt request from the storage unit 130. The instruction execution unit 121 continues to execute the main program according to the main program interruption point information saved by the interrupt. The above embodiment cleverly records the information required to resume the operation of the main program and the information required to resume the execution of the first interrupt request to the storage unit 130 through nesting, and efficiently handles the situation of interrupt nesting.

[0093] In the second case, the priority of the second interrupt request is not greater than the priority of the first interrupt request. In this case, the execution of the first interrupt request is not interrupted. It is sufficient to let the instruction execution unit 121 execute the second interrupt request after the first interrupt request is executed, and then resume the execution of the main program. At this time, it can be considered that the interruption point information of the main program saved by the interruption corresponding to the second interrupt request is actually consistent with the interruption point information of the main program saved by the interruption corresponding to the first interrupt request. Therefore, the interruption point information of the main program saved by the interruption corresponding to the first interrupt request recorded in the storage unit 130 is shared by the first interrupt request and the second interrupt request. The decision unit 1273 can send the second interrupt request to the instruction execution unit 121 for execution only after the first interrupt request is executed. After the instruction execution unit 121 executes the first interrupt request, it executes the second interrupt request and then notifies the decision unit 1273. The decision unit 1273 notifies the read-write unit 1271 to read the interruption point information of the main program saved by the interruption shared by the first interrupt request and the second interrupt request from the storage unit 130. The instruction execution unit 121 continues to execute the main program according to the interruption point information of the main program saved by the interruption. In this embodiment, when a second interrupt request is received when a first interrupt request has started to execute but has not yet been completed, the main program interrupt point information saved by the interrupt corresponding to the first interrupt request can be reused for the second interrupt request, thereby reducing repeated writing to the storage unit 130 and improving the real-time nature of the interrupt response.

[0094] III. When the interrupt request has been executed but the corresponding main program interrupt point information saved by the interrupt has not been removed from the storage unit, another interrupt request is received

[0095] If the transceiver unit 1272 receives a second interrupt request after receiving the first interrupt request, and the first interrupt request has been executed but the main program interruption point information corresponding to the first interrupt request has not been removed from the storage unit, it can also be considered that the main program interruption point information corresponding to the second interrupt request is actually consistent with the main program interruption point information corresponding to the first interrupt request. Therefore, the main program interruption point information corresponding to the first interrupt request recorded in the storage unit 130 is shared by the first interrupt request and the second interrupt request. The decision unit 1273 sends the second interrupt request to the instruction execution unit 121 for execution. After the instruction execution unit 121 executes the second interrupt request, it notifies the decision unit 1273. The decision unit 1273 notifies the read-write unit 1271 to read the main program interruption point information shared by the first interrupt request and the second interrupt request from the storage unit 130. The instruction execution unit 121 continues to execute the main program according to the main program interruption point information saved by the interrupt. In this embodiment, when a second interrupt request is received after the first interrupt request has been executed but the interruption point information of the main program saved corresponding to the interruption has not been removed from the storage unit 130, the interruption point information of the main program saved corresponding to the first interrupt request can be reused for the second interrupt request, thereby reducing repeated writing to the storage unit 130 and improving the real-time performance of the interrupt response.

[0096] Interrupt handling method

[0097] like Figure 4 According to an embodiment of the present disclosure, an interrupt processing method is also provided, which comprises Figure 2 The interrupt processing unit 127 is executed, and the method includes:

[0098] Step 410: receiving a first interrupt request;

[0099] Step 420: Filter the interruption-saved main program interruption point information from the main program interruption point information according to the first interruption request;

[0100] Step 430: Write the interruption point information of the main program saved by the interruption into a storage unit, so that after the first interruption request is executed, the interruption point information of the main program saved by the interruption is read from the storage unit, so that the main program continues to be executed.

[0101] The implementation details of each step of the above method have been described in detail above in conjunction with the device embodiment, and will not be repeated here for the sake of space saving.

[0102] The commercial value of the disclosed embodiments

[0103] The disclosed embodiment saves the main program interruption point information to the storage unit as needed according to the actual usage, which minimizes the storage time of the information required to resume the main program operation and improves the real-time interrupt response. It can be used in various existing chips to greatly improve the performance of the chip and has broad market value.

[0104] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the method described in the device and system embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of other embodiments.

[0105] It should be understood that the above is a description of a specific embodiment of the present specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0106] It should be understood that an element described in singular form herein or shown in the drawings as only one does not limit the number of the element to one. In addition, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be split into multiple modules or elements.

[0107] It should also be understood that the terms and expressions used herein are for description only, and one or more embodiments of this specification should not be limited to these terms and expressions. The use of these terms and expressions does not mean to exclude any equivalent features of the illustrations and descriptions (or parts thereof), and it should be recognized that various modifications that may exist should also be included in the scope of the claims. Other modifications, changes and substitutions may also exist. Accordingly, the claims should be deemed to cover all such equivalents.

Claims

1. An interrupt processing unit, comprising: A transceiver unit, configured to receive a first interrupt request; A decision unit is used to filter the interruption-saved main program interruption point information from the main program interruption point information according to the first interruption request; including: filtering the register value of the caller-saved attribute saved by the interruption from the register value of the caller-saved attribute according to the type of the first interruption request, and adding the interruption-saved main program interruption point information; specifically: inputting the type of the first interruption request into a pre-trained interruption-saved caller-saved attribute register value screening model, thereby obtaining the register value of the caller-saved attribute saved by the interruption; A read-write unit is used to write the interruption point information of the main program saved by the interruption into a storage unit, so that after the instruction execution unit executes the first interrupt request, the read-write unit reads the interruption point information of the main program saved by the interruption from the storage unit, so that the instruction execution unit continues to execute the main program, and the instruction execution unit is outside the interrupt processing unit.

2. The interrupt processing unit according to claim 1, wherein: The main program interruption point information at least includes one or more of the main program interruption point code address, the current state of the processing unit to which the interrupt processing unit belongs, and the register value of the caller saving attribute.

3. The interrupt processing unit according to claim 2, wherein: The main program breakpoint code address, the processing unit current state, and the caller save attribute register value are stored in the main program breakpoint code address register, the processing unit current state register, and the caller save attribute register respectively; The writing of the interruption saved main program interruption point information into the storage unit comprises: pushing out at least one of the interruption saved main program interruption point code address register, the to-be-recorded processing unit current status register, and the to-be-recorded caller saved attribute register to the storage unit.

4. The interrupt processing unit according to claim 2, wherein: The step of filtering the main program interruption point information to be recorded from the main program interruption point information according to the first interruption request includes: The main program breakpoint code address and the current state of the processing unit are added to the main program breakpoint information saved by the interrupt.

5. The interrupt processing unit according to claim 4, wherein: The method of filtering out the register values ​​of the caller-saved attributes to be saved by the interrupt from the register values ​​of the caller-saved attributes according to the type of the first interrupt request includes: filtering out the register values ​​of the caller-saved attributes to be saved by the interrupt from the register values ​​of the caller-saved attributes according to a predetermined rule and the type of the first interrupt request.

6. The interrupt processing unit according to claim 1, wherein: If the transceiver unit receives a second interrupt request after receiving the first interrupt request, and if the main program interruption point information saved by the interrupt corresponding to the first interrupt request has not been completely written into the storage unit, the read-write unit continues to write the unwritten part of the main program interruption point information saved by the interrupt corresponding to the first interrupt request into the storage unit so as to be shared by the first interrupt request and the second interrupt request, and the decision unit determines the execution order of the first interrupt request and the second interrupt request according to the priority of the first interrupt request and the second interrupt request, and sends the execution order and the second interrupt request to the instruction execution unit, and the instruction execution unit executes the first interrupt request and the second interrupt request according to the execution order after the main program interruption point information saved by the interrupt is completely written into the storage unit.

7. The interrupt processing unit according to claim 6, wherein: The step of determining the execution order of the first interrupt request and the second interrupt request according to the priorities of the first interrupt request and the second interrupt request comprises: If the priority of the second interrupt request is greater than the priority of the first interrupt request, the execution order is that the second interrupt request precedes the first interrupt request; If the priority of the second interrupt request is not greater than the priority of the first interrupt request, the execution order is that the first interrupt request precedes the second interrupt request.

8. The interrupt processing unit according to claim 1, wherein: If the transceiver unit receives a second interrupt request after receiving the first interrupt request, and the first interrupt request has started to execute but has not yet been completed, but the priority of the second interrupt request is greater than the priority of the first interrupt request, then the decision unit sends the second interrupt request to the instruction execution unit for execution, and the read-write unit writes the register record information and the stack position information into the storage unit, wherein the register record information is the information recorded in the register stack during the process of the execution instruction unit executing the first interrupt request, and the stack position information indicates the location where the register record information is recorded in the register stack, so that after the second interrupt request is executed, the read-write unit reads the register record information and the stack position information from the storage unit so that the first interrupt request continues to execute.

9. The interrupt processing unit according to claim 1, wherein: If the transceiver unit receives a second interrupt request after receiving the first interrupt request, and the first interrupt request has started to be executed but has not been completed, but the priority of the second interrupt request is not greater than the priority of the first interrupt request, then the decision unit sends the second interrupt request to the instruction execution unit for execution only after the first interrupt request is executed, and the main program interruption point information saved by the interrupt in the storage unit is shared by the first interrupt request and the second interrupt request, so that after the first interrupt request and the second interrupt request are executed, the read-write unit reads the main program interruption point information saved by the interrupt from the storage unit, so that the main program continues to execute.

10. The interrupt processing unit according to claim 1, wherein: If the transceiver unit receives a second interrupt request after receiving the first interrupt request, and the first interrupt request has been executed but the interruption saved main program interruption point information corresponding to the first interrupt request has not been removed from the storage unit, the decision unit sends the second interrupt request to the instruction execution unit for execution, and allows the interruption saved main program interruption point information in the storage unit to be shared by the first interrupt request and the second interrupt request, so that after the first interrupt request and the second interrupt request are executed, the read-write unit reads the interruption saved main program interruption point information from the storage unit, so that the main program continues to execute.

11. A processing unit, comprising: An interrupt processing unit according to any one of claims 1 to 10; The instruction execution unit is used to execute the main program and the interrupt service program of the first interrupt request.

12. A system on chip comprising the processing unit according to claim 11.

13. An interrupt processing method, comprising: receiving a first interrupt request; According to the first interrupt request, the main program interruption point information saved by the interruption is filtered from the main program interruption point information; including: according to the type of the first interrupt request, the register value of the caller-saved attribute saved by the interruption is filtered from the register value of the caller-saved attribute, and the register value of the caller-saved attribute saved by the interruption is added to the main program interruption point information saved by the interruption; specifically: the type of the first interrupt request is input into a pre-trained interruption-saved caller-saved attribute register value screening model, so as to obtain the register value of the caller-saved attribute saved by the interruption; The interruption point information of the main program saved by the interruption is written into a storage unit, so that after the first interruption request is executed, the interruption point information of the main program saved by the interruption is read from the storage unit, so that the main program continues to be executed.

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