Semiconductor device and method of manufacturing the same

Abstract

In a semiconductor device, a semiconductor element (40) includes a semiconductor substrate (41), a surface electrode (42), and a protective film (46). The semiconductor substrate (41) has an active region (410) and a peripheral region (411). The surface electrode (42) includes a base electrode (420) provided on a front surface (41a) of the semiconductor substrate (41) and a connection electrode provided on the base electrode (420). The protective film (46) covers a peripheral end portion (420a) of the base electrode (420) and an outer peripheral edge (421b) of the connection electrode (421). The protective film (46) has an opening (46a) that exposes the connection electrode (421), enabling solder connection. A boundary between the outer peripheral edge (421b) of the connection electrode (421) and the protective film (46) is located at a position corresponding to the peripheral region (411) in a plan view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. Background Art

[0002] For example, JP2005-19447A discloses a semiconductor device having a semiconductor element as part of a power conversion unit. The disclosure of JP2005-19447A as the prior art document is incorporated herein by reference for the explanation of the technical elements of the present specification. Summary of the Invention

[0003] In JP2005-19447A, an emission electrode is formed on the surface of a semiconductor substrate. The emission electrode has a base electrode made of aluminum alloy and a connection electrode provided on the base electrode. The connection electrode is provided in an opening of a protective film. The position of the boundary (interface) between the outer peripheral edge of the connection electrode and the protective film corresponds to the active region of the semiconductor substrate in a plan view of the semiconductor substrate projected in the thickness direction of the semiconductor substrate.

[0004] In this configuration, in a solder bonding state, due to stresses such as power cycling or cold cycling, cracks are likely to occur in the base electrode directly below the boundary, that is, directly below the outer peripheral edge of the connection electrode. The cracks can extend to the active region of the semiconductor substrate located directly below the boundary. From the above viewpoints or from other viewpoints not mentioned, further improvement of the semiconductor device is needed.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device, which can suppress damage to the active region due to thermal stress.

[0006] According to one aspect of the present disclosure, a semiconductor device includes a semiconductor element for constituting a power conversion device. The semiconductor element includes a semiconductor substrate, a surface electrode, and a protective film. The semiconductor substrate has an active region as an element formation region, the active region being adjacent to the front surface of the semiconductor substrate; and has an outer peripheral region surrounding the active region in a plan view projected in the substrate thickness direction orthogonal to the front surface of the semiconductor substrate. The surface electrode includes a base electrode provided on the front surface of the semiconductor substrate and a connection electrode provided on the base electrode. The protective film covers the peripheral end portion of the base electrode and the outer peripheral edge of the connection electrode. The protective film defines an opening to expose the connection electrode, so that a solder connection can be formed to the connection electrode. Further, the connection electrode is arranged such that the boundary between the outer peripheral edge of the connection electrode and the protective film is located at a position corresponding to the outer peripheral region of the semiconductor substrate in a plan view in the substrate thickness direction.

[0007] In the semiconductor device according to the above aspect, the boundary between the outer peripheral edge of the connection electrode and the protective film is located at a position away from the active region. Therefore, even if thermal stress caused by, for example, power cycling and thermal cycling is concentrated in the portion directly below the boundary, the possibility of cracks developing into the active region is small. Therefore, damage to the active region by thermal stress can be restricted.

[0008] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device having a semiconductor element for constructing a power conversion device includes: preparing a semiconductor wafer having an active region adjacent to the front surface of the semiconductor wafer and a peripheral region surrounding the active region; forming a silicon oxide film on the entire front surface of the semiconductor wafer; patterning the silicon oxide film to form contact holes surrounding the active region; forming a base electrode on the entire front surface to cover the silicon oxide film; patterning the base electrode such that the base electrode has a peripheral end overlapping a peripheral portion of the contact hole of the silicon oxide film; forming a connection electrode on the entire front surface to cover the base electrode and the silicon oxide film; removing a part of the connection electrode formed on the silicon oxide film by utilizing the difference in adhesion between the connection electrode and the silicon oxide film and the base electrode, thereby forming a surface electrode including the base electrode and the connection electrode stacked on the base electrode; forming a protective film on the entire front surface to cover the surface electrode and the silicon oxide film; patterning the protective film to form an opening to expose a part of the connection electrode as a solder connection portion, and removing a part of the protective film above the dicing region; and after patterning the protective film, cutting the semiconductor wafer along the dicing region, thereby forming a semiconductor element.

[0009] In the method according to the above aspect, the silicon oxide film is formed on the entire front surface of the semiconductor wafer, excluding the portion connected to the surface electrode, that is, excluding the portion exposed from the contact hole. A part of the connection electrode formed on the silicon oxide film is removed by utilizing the difference in adhesion between the connection electrode and the base electrode and the silicon oxide film and the difference in residual stress in the film, while the part of the connection electrode formed on the base electrode is retained. In this way, the connection electrode is patterned without using a photoresist, and the boundary between the outer peripheral edge of the connection electrode and the protective film can be set at a position away from the active region. Therefore, damage to the active region caused by thermal stress can be suppressed. Description of the Drawings

[0010] The objects, features, and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings, in which the same components are denoted by the same reference numerals, where:

[0011] Figure 1is a diagram showing a schematic configuration of a vehicle drive system employing a semiconductor device according to the first embodiment;

[0012] Figure 2 is a diagram showing a plan view of a semiconductor device according to the first embodiment;

[0013] Figure 3 is a diagram showing a cross-sectional view taken along line III-III in Figure 2 ;

[0014] Figure 4 is a diagram showing a plan view of a semiconductor element according to the first embodiment;

[0015] Figure 5 is a diagram showing a cross-sectional view taken along line V-V in Figure 4 ;

[0016] Figure 6 is a diagram showing a cross-sectional view for explaining a method of manufacturing a semiconductor element;

[0017] Figure 7 is a diagram showing a cross-sectional view for explaining a method of manufacturing a semiconductor element;

[0018] Figure 8 is a diagram showing a cross-sectional view for explaining a method of manufacturing a semiconductor element;

[0019] Figure 9 is a diagram showing a cross-sectional view for explaining a method of manufacturing a semiconductor element;

[0020] Figure 10 is a diagram showing a cross-sectional view for explaining a method of manufacturing a semiconductor element;

[0021] Figure 11 is a diagram showing a cross-sectional view for explaining a method of manufacturing a semiconductor element;

[0022] Figure 12 is a diagram showing a cross-sectional view for explaining a method of manufacturing a semiconductor element;

[0023] Figure 13 is a diagram showing a cross-sectional view for explaining a method of manufacturing a semiconductor element;

[0024] Figure 14 is a diagram showing a cross-sectional view for explaining a method of manufacturing a semiconductor element;

[0025] Figure 15 is a diagram showing a cross-sectional view of a semiconductor device as a reference example;

[0026] Figure 16A diagram showing a cross-sectional view of a semiconductor device with a solder connection structure between a semiconductor element and a terminal member according to a first embodiment;

[0027] Figure 17 A diagram showing a cross-sectional view of a semiconductor device as a modified example;

[0028] Figure 18 A diagram showing a cross-sectional view of a semiconductor device according to a second embodiment;

[0029] Figure 19 A diagram showing a cross-sectional view of a semiconductor device according to a third embodiment;

[0030] Figure 20 A diagram showing a cross-sectional view of a semiconductor device according to a fourth embodiment;

[0031] Figure 21 A diagram showing a cross-sectional view of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION

[0032] Hereinafter, a plurality of embodiments will be described with reference to the accompanying drawings. In the embodiments, components that are functionally and / or structurally corresponding and / or related to each other are given the same reference numerals. For corresponding parts and / or related elements, the descriptions of other embodiments may be referred to.

[0033] The semiconductor device of the present embodiment is applied to, for example, a power conversion device for a moving body driven by a rotating electric machine. For example, the moving body is an electric vehicle (EV), a hybrid vehicle (HV), a fuel cell vehicle (FCV), an aircraft (e.g., a drone), a ship, construction machinery, or agricultural machinery. Hereinafter, an example of applying the semiconductor device to a power conversion device for a vehicle will be described.

[0034] (First Embodiment)

[0035] First, with reference to Figure 1 the schematic configuration of a vehicle drive system will be described.

[0036] <Vehicle Drive System>

[0037] As Figure 1 shown, the vehicle drive system 1 includes a DC power source 2, an electric generator 3, and a power conversion device 4.

[0038] The DC power source 2 is a DC voltage source including a rechargeable / dischargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The electric generator 3 is a three-phase AC type rotating electric machine. The electric generator 3 serves as a vehicle drive power source, i.e., an electric motor. The electric generator 3 also functions as a generator during the regeneration process. The power conversion device 4 performs electric power conversion between the DC power source 2 and the electric generator 3.

[0039] <Power conversion device>

[0040] Next, with reference to Figure 1 the circuit configuration of the power conversion device 4 will be described. The power conversion device 4 includes a smoothing capacitor 5 and an inverter 6.

[0041] The smoothing capacitor 5 smooths the DC voltage supplied from the DC power source 2. The smoothing capacitor 5 is connected to the P line 7 which is the power line on the high potential side and the N line 8 which is the power line on the low potential side. The P line 7 is connected to the positive electrode of the DC power source 2, and the N line 8 is connected to the negative electrode of the DC power source 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 at a position between the DC power source 2 and the inverter 6. Similarly, the negative electrode of the smoothing capacitor 5 is connected to the N line 8 at a position between the DC power source 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel with the DC power source 2.

[0042] The inverter 6 is a DC-to-AC conversion circuit. The inverter 6 converts the DC voltage into a three-phase AC voltage according to the switching control of a control circuit (not shown) and outputs the three-phase AC voltage to the electric generator 3. As a result, the electric generator 3 is driven to generate a predetermined torque. During vehicle regenerative braking, the inverter 6 converts the three-phase AC voltage generated by the electric generator 3 receiving the wheel rotational force into a DC voltage according to the switching control of the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional electric power conversion between the DC power source 2 and the electric generator 3.

[0043] The inverter 6 includes upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 will also be referred to as bridge arms. The upper and lower arm circuits 9 include an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8 such that the upper arm 9H is adjacent to the P line 7 and the lower arm 9L is adjacent to the N line 8. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the electric generator 3 through the output line 10. The inverter 6 has six arms. At least a part of each of the P line 7, the N line 8, and the output line 10 is provided by a conductive member such as a bus bar.

[0044] In this embodiment, the switching elements constituting each arm are provided by insulated gate bipolar transistors 11 (hereinafter referred to as IGBTs 11). A freewheeling diode 12 (hereinafter referred to as FWD 12) is anti-parallel connected to each IGBT 11. In the upper arm 9H, the collector of the IGBT 11 is connected to the P line 7. In the lower arm 9L, the emitter of the IGBT 11 is connected to the N line 8. The emitter of the IGBT 11 in the upper arm 9H and the collector of the IGBT 11 in the lower arm 9L are connected to each other. The anode of the FWD 12 is connected to the emitter of the corresponding IGBT 11, and the cathode of the FWD 12 is connected to the collector of the corresponding IGBT 11.

[0045] The power conversion device 4 may also include a converter as a power conversion circuit. In this case, the converter is a DC-to-DC conversion circuit that converts a DC voltage into a DC voltage with a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the above-mentioned upper arm and lower arm circuits 9. In this configuration, the voltage can be raised and lowered. The power conversion device 4 may include a filter capacitor for removing power supply noise from the DC power supply 2. In this case, a filter capacitor is provided between the DC power supply 2 and the converter.

[0046] The power conversion device 4 may include a drive circuit for driving the switching elements that make up the inverter 6 or the like. The drive circuit supplies a drive voltage to the gates of the IGBTs 11 of the corresponding arms based on a drive command from the control circuit. The drive circuit drives the corresponding IGBTs 11 by applying the drive voltage, that is, turns on and off the corresponding IGBTs 11. The drive circuit may also be referred to as a driver.

[0047] The power conversion device 4 may include a control circuit for the switching elements. In this case, the control circuit generates a drive command for operating the IGBT 11 and outputs the drive command to the drive circuit. The control circuit generates a drive command based on a torque request from a higher-level ECU (not shown) or signals detected by various sensors. Examples of various sensors include a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through each phase winding 3a. The rotation angle sensor detects the rotation angle of the rotor of the electric generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as the drive command. The control circuit includes, for example, a microcomputer. "ECU" is an abbreviation for "electronic control unit". "PWM" is an abbreviation for "pulse width modulation".

[0048] <Semiconductor device>

[0049] Next, with reference to Figure 2 and Figure 3 describe the schematic structure of a semiconductor device to which a semiconductor element is applied. Figure 2 is a plan view of the semiconductor device. Figure 2 is a plan view of the semiconductor device viewed from the top. Figure 3 is a cross-sectional view taken along the Figure 2 III-III line. In Figure 3 the structure of the semiconductor element 40 is simplified.

[0050] Hereinafter, the thickness direction of the semiconductor element is defined as the Z direction. The thickness direction is the direction in which the thickness of the semiconductor element or semiconductor substrate is measured and corresponds to the direction normal to the surface of the semiconductor element. The thickness direction may also be referred to as the substrate thickness direction. The direction orthogonal to the Z direction and corresponding to the alignment direction of the plurality of pads is defined as the X direction. The direction orthogonal to both the Z direction and the X direction is defined as the Y direction. Unless otherwise specified, the shape in the plan view viewed or projected in the Z direction, that is, the shape along the XY plane (including the X and Y directions) is called the planar shape. In addition, the plan view in the Z direction may be simply referred to as the plan view. The plan view is a view projected along the Z direction.

[0051] As Figure 2 and Figure 3 shown, the semiconductor device 20 includes a sealing resin body 30, a semiconductor element 40, heat sinks 50 and 60, a terminal member 70, main terminals 80 and 81, and a signal terminal 82. The semiconductor device 20 constitutes an arm. That is, two semiconductor devices 20 constitute the upper arm and the lower arm circuits 9 for one phase.

[0052] The sealing resin body 30 seals a part of the other elements constituting the semiconductor device 20. The remaining part of the other elements is exposed to the outside of the sealing resin body 30. The sealing resin body 30 is made of, for example, epoxy resin. The sealing resin body 30 is formed by, for example, a transfer molding technique. As Figure 2 shown, the sealing resin body 30 has a substantially rectangular shape in the plan view. The sealing resin body 30 has a front surface 30a and a back surface 30b opposite to the front surface 30a in the Z direction. The front surface 30a and the back surface 30b are, for example, flat surfaces.

[0053] The semiconductor element 40 is provided by a semiconductor substrate 41 on which vertical elements are formed. The semiconductor substrate 41 is made of silicon (Si), a wide-bandgap semiconductor having a wider bandgap than silicon, or the like. Examples of the wide-bandgap semiconductor include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The vertical elements are formed such that the main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate 41), that is, in the Z direction. In the present embodiment, the vertical elements include an IGBT 11 and an FWD 12 forming one arm. That is, the semiconductor element 40 has an RC (reverse conduction)-IGBT as the vertical element. The vertical element is a heat-generating element that generates heat when conducting electricity. The semiconductor element 40 may also be referred to as a semiconductor chip.

[0054] The semiconductor element 40 has a gate (not shown) formed on a semiconductor substrate 41. The gate has, for example, a trench structure. The semiconductor element 40 has main electrodes on each plate surface of the semiconductor substrate 41. The plate surface of the semiconductor substrate 41 is the surface facing the Z direction. A main current flows between the main electrodes. The main electrodes include an emitter electrode 42 formed adjacent to the front surface 41a of the semiconductor substrate 41 and a collector electrode 43 formed adjacent to the back surface 41b of the semiconductor substrate 41 opposite to the front surface 41a. The front surface 41a of the semiconductor substrate 41 is the surface adjacent to the front surface 30a of the sealing resin body 30. The emitter electrode 42 corresponds to a surface electrode.

[0055] The emitter electrode 42 also serves as the anode electrode of a diode. The collector electrode 43 also serves as the cathode electrode of a diode. The collector electrode 43 is formed on substantially the entire back surface 41b of the semiconductor substrate 41. The emitter electrode 42 is formed on a part of the front surface 41a of the semiconductor substrate 41. On the front surface 41a of the semiconductor substrate 41, a pad 44 serving as a signal electrode is formed in a region different from the region where the emitter electrode 42 is formed. The pad 44 is electrically isolated from the emitter electrode 42. The pad 44 is formed at an end of the front surface 41a of the semiconductor substrate 41, which is opposite to the region where the emitter electrode 42 is formed in the Y direction. The pad 44 is aligned with the emitter electrode 42 in the Y direction.

[0056] The pad 44 includes at least a pad for the gate. The semiconductor element 40 of the present embodiment has five pads 44. Specifically, the five pads 44 are provided for the gate, a Kelvin emitter for detecting the potential of the emitter electrode 42, current sensing, the anode potential of a temperature sensor (temperature-sensitive diode) for detecting the temperature of the semiconductor element 40, and the cathode potential. The five pads 44 are formed together at an end of the semiconductor element 40 in the Y direction, which substantially has a rectangular shape in a plan view. In addition, the five pads 44 are arranged side by side in the X direction.

[0057] Heat sinks 50 and 60 are provided to be inserted into the semiconductor element 40 along the Z direction. The heat sinks 50 and 60 are provided to face each other in the Z direction. The heat sinks 50 and 60 surround the semiconductor element 40 in a plan view. The heat sinks 50 and 60 dissipate the heat generated by the semiconductor element 40 from both sides of the semiconductor device 20 to the outside. For example, the heat sinks 50 and 60 can both be provided by a direct-bonded copper (DBC) plate, a metal plate made of, for example, Cu or a Cu alloy, etc. The heat sinks 50 and 60 can both have a coating film made of, for example, nickel or gold on their surfaces. In the present embodiment, the heat sinks 50 and 60 are metal plates made of copper as a material.

[0058] The heat sink 50 has a facing surface 50a adjacent to the semiconductor element 40 and a back surface 50b opposite to the facing surface 50a. Similarly, the heat sink 60 has a facing surface 60a and a back surface 60b. Both the heat sinks 50 and 60 have a substantially rectangular shape in a plan view. The back surfaces 50b and 60b of the heat sinks 50 and 60 are exposed from the sealing resin body 30. The back surfaces 50b and 60b may be referred to as heat radiation surfaces or exposed surfaces.

[0059] The heat sink 50 is disposed on a side adjacent to the emission electrode 42 of the semiconductor element 40 in the Z direction and is electrically connected to the emission electrode 42 via a solder 90. The heat sink 50 serves as a wiring member for electrically connecting the emission electrode 42 to another member. The heat sink 50 is connected to the emission electrode 42 via a terminal member 70. The solder 90 is inserted between the heat sink 50 and the terminal member 70 and between the terminal member 70 and the emission electrode 42, respectively. The back surface 50b of the heat sink 50 is substantially flush with the front surface 30a of the sealing resin body 30. The solder 90 is a multi-element lead-free solder containing Cu, Ni, etc. in addition to Sn.

[0060] The terminal member 70 is inserted between the semiconductor element 40 and the heat sink 50 in the Z direction and electrically interconnects the emission electrode 42 and the heat sink 50. The terminal member 70 is located in the middle of the conductive and heat conductive path between the semiconductor element 40 (emission electrode 42) and the heat sink 50. The terminal member 70 is a columnar body formed of a metal material such as Cu or a Cu alloy. The terminal member 70 may have a coating film on its surface. The terminal member 70 may be referred to as a metal block or an interconnecting member. In the present embodiment, the terminal member 70 is a columnar body having a substantially rectangular shape in a plan view.

[0061] The heat sink 60 is disposed on a side adjacent to the collector 43 of the semiconductor element 40 in the Z direction and is electrically connected to the collector 43 via a solder 90. The heat sink 60 serves as a wiring member for electrically connecting the collector 43 to another member. A solder joint is formed between the facing surface 60a of the heat sink 60 and the collector 43 of the semiconductor element 40. The back surface 60b of the heat sink 60 is substantially flush with the back surface 30b of the sealing resin body 30.

[0062] The main terminals 80 and 81 and the signal terminal 82 are external connection terminals for electrically connecting the semiconductor device 20 to an external device. The main terminals 80 and 81 are electrically connected to the main electrodes. The main terminal 80 is electrically connected to the emission electrode 42. The main terminal 80 may also be referred to as an emission terminal. The main terminal 81 is electrically connected to the collector 43. The main terminal 81 may also be referred to as a collector terminal.

[0063] The main terminal 80 is connected to the emission electrode 42 via the heat sink 50. The main terminal 80 is connected to one end of the heat sink 50 in the Y direction. The thickness of the main terminal 80 is smaller than the thickness of the heat sink 50. For example, the main terminal 80 is connected to the heat sink 50 so as to be substantially flush with the facing surface 50a. The main terminal 80 and the heat sink 50 may be provided by an integral member such that the main terminal 80 is connected to the heat sink 50. Alternatively, the main terminal 80 and the heat sink 50 may be provided by separate members and may be connected to each other such that the main terminal 80 is connected to the heat sink 50.

[0064] In the present embodiment, the main terminal 80 is integrally provided with the heat sink 50 as part of a lead frame. The main terminal 80 extends from the heat sink 50 in the Y direction and protrudes outward from the side surface 30c of the sealing resin body 30. The main terminal 80 has a bent portion in the middle of the portion covered by the sealing resin body 30 and protrudes from near the center in the Z direction on the side surface 30c.

[0065] The main terminal 81 is electrically connected to the collector 43 via the heat sink 60. The main terminal 81 is connected to one end of the heat sink 60 in the Y direction. The thickness of the main terminal 81 is smaller than the thickness of the heat sink 60. For example, the main terminal 81 is connected to the heat sink 60 so as to be substantially flush with the facing surface 60a. The main terminal 81 and the heat sink 60 may be provided by an integral member such that the main terminal 81 is connected to the heat sink 60. Alternatively, the main terminal 81 and the heat sink 60 may be provided by separate members and may be connected to each other such that the main terminal 81 is connected to the heat sink 60.

[0066] In the present embodiment, the main terminal 81 is integrally provided with the heat sink 60 as part of a lead frame separate from the lead frame of the main terminal 80. The main terminal 81 extends from the heat sink 60 in the Y direction and protrudes outward from the same side surface 30c as the main terminal 80. The main terminal 81 also has a bent portion in the middle of the portion covered by the sealing resin body 30 and protrudes from near the center in the Z direction on the side surface 30c. The two main terminals 80 and 81 are arranged side by side in the X direction.

[0067] The signal terminal 82 is electrically connected to the pad 44 of the semiconductor element 40. In the present embodiment, the signal terminal 82 is connected to the pad 44 via the bonding wire 91. The signal terminal 82 extends in the Y direction and protrudes from the side surface 30d of the sealing resin body 30. The side surface 30d is a surface opposite to the side surface 30c in the Y direction. The semiconductor device 20 of the present embodiment includes five signal terminals 82 corresponding to the five pads 44. For example, the signal terminals 82 are formed in a lead frame shared with the heat sink 60 and the main terminal 81. The signal terminals 82 are electrically separated from each other by cutting tie bars (not shown).

[0068] As described above, in the semiconductor device 20, the semiconductor element 40 that constitutes one arm is sealed by the sealing resin body 30. The sealing resin body 30 integrally seals the semiconductor element 40, a part of the heat sink 50, a part of the heat sink 60, the terminal member 70, a part of each of the main terminals 80 and 81, and a part of each of the signal terminals 82.

[0069] In the Z direction, the semiconductor element 40 is disposed between the heat sinks 50 and 60. The semiconductor element 40 is inserted between the heat sinks 50 and 60 that face each other. As a result, the heat of the semiconductor element 40 can be dissipated from both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of the heat sink 50 is substantially coplanar with the front surface 30a of the sealing resin body 30. The back surface 60b of the heat sink 60 is substantially coplanar with the back surface 30b of the sealing resin body 30. Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be improved.

[0070] <Semiconductor element>

[0071] Next, the semiconductor element 40 will be described with reference to Figure 4 and Figure 5 is a plan view of the semiconductor element 40 viewed from the front surface side. In Figure 4 is a plan view of the semiconductor element 40 viewed from the front surface side. In Figure 4 the outer peripheral edge 420b of the base electrode 420 and the outer peripheral edge 421b of the connection electrode 421 are indicated by dashed lines, and the inner peripheral edge of the silicon oxide film 45 is indicated by dashed lines of alternating lengths. In addition, the outer peripheral edge 410a of the active region 410, that is, the boundary between the active region 410 and the outer peripheral region 411, is indicated by a double-dot dash line. Figure 5 is a cross-sectional view taken along the line V-V in Figure 4 In the following description, "inner side" and "outer side" indicate the relative positional relationship with the center of the active region 410 of the semiconductor element 40 as the reference position. The region closer to the center is the inner side, and the region farther from the center is the outer side.

[0072] The semiconductor substrate 41 has a substantially rectangular shape in a plan view. The semiconductor substrate 41 has an active region 410 in the surface layer adjacent to the front surface 41a. The active region 410 is a region where elements are formed, and will also be referred to as an element formation region. The active region 410 will also be referred to as the main region. Although not shown, the active region 410 is formed together with a part of the RC-IGBT adjacent to the front surface 41a. For example, in the active region 410, the trench gate, base region, emitter region of the IGBT 11, and the anode region of the FWD 12 are formed. In Figure 5 the active region 410 is shown by a dashed line.

[0073] The semiconductor substrate 41 has an outer peripheral region 411 that surrounds the active region 410. InFigure 5 In Figure 5 , the boundary between the active region 410 and the peripheral region 411 is indicated by alternately long and short dashed lines. The peripheral region 411 is the region outside the outer peripheral edge 410a of the active region 410 in the plan view. Although not shown, a high-voltage-resistant structure portion such as a guard ring is formed in the peripheral region 411.

[0074] In the semiconductor substrate 41, the collector region of the IGBT 11 and the cathode region of the FWD 12 are formed in the surface layer adjacent to the back surface 41b. The back surface 41b is opposite to the front surface 41a in the Z direction. The collector 43 is formed on substantially the entire back surface 41b of the semiconductor substrate 41.

[0075] The semiconductor element 40 further includes a silicon oxide film 45 and a protective film 46. The silicon oxide film 45 is an interlayer insulating film formed on the front surface 41a of the semiconductor substrate 41. The silicon oxide film 45 is formed in an annular shape so as to surround the active region 410. The silicon oxide film 45 is formed in the peripheral region 411 on the front surface 41a. The silicon oxide film 45 has a contact hole for connecting the emission electrode 42 to the semiconductor substrate 41. The end face of the silicon oxide film 45 provides an open end 45a and defines the contact hole. The open end 45a is located at a position more outward than the outer peripheral edge 410a of the active region 410. The residual stress in the film of the silicon oxide film 45 is compressive stress.

[0076] In the present embodiment, the silicon oxide film 45 extends more outward than the outer peripheral edge of the protective film 46. The silicon oxide film 45 has an exposed portion 45b exposed from the protective film 46. The exposed portion 45b includes a dicing region. The silicon oxide film 45 is formed on the front surface 41a of the semiconductor substrate 41 in almost the entire region excluding the connection portion (contact) of the emission electrode 42, that is, in almost the entire region excluding the portion exposed from the contact hole.

[0077] The emission electrode 42 has a multilayer structure. The emission electrode 42 has a base electrode 420 and a connection electrode 421. The pad 44 also has a structure similar to that of the emission electrode 42.

[0078] In the emission electrode 42 having a multilayer structure, the base electrode 420 is a metal layer formed adjacent to the semiconductor substrate 41. The base electrode 420 may also be referred to as a lower electrode, a lower layer electrode, a wiring electrode, a first metal layer, etc. The base electrode 420 is connected to the front surface 41a of the semiconductor substrate 41 and the silicon oxide film 45. The base electrode 420 has a higher adhesion to the silicon oxide film 45 than the connection electrode 421. The base electrode 420 is formed by using a material containing, for example, aluminum (Al) as a main component. In the present embodiment, the material is an aluminum alloy, such as AlSi or AlSiCu.

[0079] The base electrode 420 extends upward to a position above the peripheral region 411 and includes the active region 410 in the plan view. The base electrode 420 is connected to the emission region, the base region, and the anode region. The peripheral end portion 420a of the base electrode 420 is stacked and disposed on the silicon oxide film 45. The peripheral end portion 420a is provided on the peripheral portion of the open end 45a of the silicon oxide film 45. The peripheral end portion 420a has an annular shape in the plan view and is disposed above the peripheral region 411. The outer peripheral edge 420b of the base electrode 420 is located on the silicon oxide film 45.

[0080] In order to improve the bonding strength with the solder 90 and improve the wettability with respect to the solder 90, the connection electrode 421 is stacked and disposed on the base electrode 420. The connection electrode 421 may also be referred to as a cover electrode, an upper electrode, an upper layer electrode, and a second metal layer. The connection electrode 421 includes at least one metal layer. The metal layer constituting the connection electrode 421 contains a material with an adhesion to the silicon oxide film 45 lower than that of the base electrode 420, and the material includes at least one of, for example, Ni, Pd, Au, Pt, and Ag. The in-film residual stress of the connection electrode 421 is a tensile stress.

[0081] The connection electrode 421 of the present embodiment includes at least a nickel (Ni) layer. Nickel is harder than the aluminum alloy forming the base electrode 420. The connection electrode 421 may further include a gold (Au) layer on the Ni layer. For example, the Au layer inhibits the oxidation of the Ni layer, thereby improving the wettability with the solder. Since gold diffuses into the solder during the soldering process, the gold layer exists in the state before soldering and does not exist in the solder connection state.

[0082] Similar to the base electrode 420, the connection electrode 421 extends above the peripheral region 411 while including the active region 410 in the plan view. The peripheral end portion 421a of the connection electrode 421 is stacked and disposed on the peripheral end portion 420a of the base electrode 420. The peripheral end portion 421a is disposed on the silicon oxide film 45 via the peripheral end portion 420a. The peripheral end portion 421a has an annular shape in the plan view and is disposed above the peripheral region 411. The outer peripheral edge 421b of the connection electrode 421 is located on the silicon oxide film 45. The peripheral end portion 420a corresponds to the first peripheral end portion, and the peripheral end portion 421a corresponds to the second peripheral end portion.

[0083] In the present embodiment, the connection electrode 421 is arranged to substantially coincide with the base electrode 420 in the plan view. The positions of the outer peripheral edges �20b and 421b substantially coincide with each other throughout the periphery. The outer peripheral edges 420b and 421b are located at a position more outward than the open end 45a of the silicon oxide film 45.

[0084] The protective film 46 is an insulating film provided on the front surface 41a of the semiconductor substrate 41 so as to cover the peripheral end portions of the emission electrode 42 and the silicon oxide film 45. As the material of the insulating film, for example, polyimide, silicon nitride film, etc. can be used. The protective film 46 has an opening 46a that defines the connection region between the emission electrode 42 and the solder 90. The opening 46a allows the emission electrode 42 to be exposed so that solder bonding with the solder 90 can be performed. The protective film 46 has an opening 46b that provides a connection region for the pad 44. Each of the openings 46a and 46b is a through hole that penetrates the protective film 46 in the Z direction. In the emission electrode 42 (connection electrode 421), a joint portion is formed between the exposed portion 421c exposed from the opening 46a of the protective film 46 and the solder 90.

[0085] In this embodiment, the protective film 46 is made of polyimide. The protective film 46 covers the peripheral end portion 420a of the base electrode 420 and the peripheral end portion 421a of the connection electrode 421. The protective film 46 covers the portion of the silicon oxide film 45 that does not include the exposed portion 45b. The protective film 46 is not provided in the dicing region in a predetermined region starting from the outer periphery of the semiconductor substrate 41. The shape of the opening 46a, that is, the shape of the opening end 46c that defines the opening 46a of the protective film 46 is substantially rectangular in a plan view. The opening end 46c may also be referred to as the inner peripheral edge. The opening end 46c is located at a position more inward than the outer peripheral end portion 410a of the active region 410.

[0086] <Method for manufacturing a semiconductor element>

[0087] Next, a method for manufacturing a semiconductor device will be described with reference to Figures 6 to 14 Specifically, a method for manufacturing a semiconductor element. Figures 6 to 14 is a cross-sectional view showing the manufacturing process of the semiconductor element corresponding to Figure 5 The semiconductor element. Figure 6 shows the step of forming a silicon oxide film, Figure 7 shows the step of patterning the silicon oxide film. Figure 8 shows the step of forming a base electrode, Figure 9 shows the step of patterning the base electrode. Figure 10 shows the step of forming a connection electrode, Figure 11 and Figure 12 shows the step of patterning the connection electrode. Figure 13 shows the step of forming a protective film, Figure 14 shows the step of forming a collector.

[0088] First, an element (RC-IGBT) is formed in a semiconductor substrate in a wafer state by ion implantation or the like. Hereinafter, the semiconductor substrate in a wafer state will be referred to as a semiconductor wafer. Then, as Figure 6As shown, for example, a silicon oxide film 45 is formed by a CVD technique. In this case, the silicon oxide film 45 is formed to cover the entire front surface 41a of the semiconductor wafer 41W. Accordingly, the silicon oxide film 45 is also formed on the dicing region 412 of the semiconductor wafer 41W. Considering dicing, the thickness of the silicon oxide film 45 in the dicing region 412 can be made thinner than that in other regions. The silicon oxide film 45 can be formed by a CVD technique and a thermal oxidation technique. The dicing region 412 can also be referred to as a scribe line.

[0089] Next, as Figure 7 shown, the silicon oxide film 45 is patterned. For example, a photoresist is applied to the surface of the silicon oxide film 45 and patterned by exposure, and etching is performed using the photoresist as a mask, thereby patterning the silicon oxide film 45. Specifically, a contact hole 45c for connecting the emission electrode 42 to the semiconductor wafer 41W is formed in the silicon oxide film 45. In this case, the contact hole 45c is formed to include the active region 410 in a plan view.

[0090] In this way, in the silicon oxide film 45, a portion corresponding to the contact portion of the emission electrode 42 is removed, and another portion is left. In the peripheral region 411, the silicon oxide film 45 is intentionally left not only in the region where the patterned base electrode 420 is stacked thereon, but also in the region outside the stacked region.

[0091] Next, as Figure 8 shown, the base electrode 420 (aluminum alloy film) is formed into a film by, for example, a sputtering technique or a vapor deposition technique. In this case, the base electrode 420 is formed on the entire front surface 41a so as to cover the silicon oxide film 45.

[0092] Next, as Figure 9 shown, the base electrode 420 is patterned. For example, a photoresist is applied to the surface of the base electrode 420 and patterned by exposure, and etching is performed using the photoresist as a mask, thereby patterning the base electrode 420. As a result, a portion of the base electrode 420 located inside the above-mentioned outer peripheral edge 420b is left. That is, a portion inside the opening end 45a of the silicon oxide film 45 and the peripheral end portion 421a stacked on the silicon oxide film 45 are left.

[0093] After the base electrode 420 is formed, plasma treatment can be performed as a pretreatment for forming the connection electrode 421. Specifically, a fluorine-based gas such as CF4 is used as the gas for plasma treatment. Then, as Figure 9As shown by the arrow in [the figure], a fluorine-based gas is jetted onto the surface of the base electrode 420 and the surface of the silicon oxide film 45 exposed from the base electrode 420. As a result, after removing the oxide film on the surface of the base electrode 420, fluorine adheres to the surfaces of the base electrode 420 and the silicon oxide film 45 to form a fluoride layer (not shown).

[0094] By continuously forming the fluoride layer in a vacuum, most of the oxygen on the base electrode 420 is replaced by fluorine, and fluorine and oxygen are mixed and present on the base electrode 420. On the other hand, a layer with a high concentration of fluorine is formed on the surface of the silicon oxide film 45. As a gas for plasma treatment, oxygen can be used together with the fluorine-based gas. Using oxygen can extend the lifetime of fluorine radicals.

[0095] Next, as Figure 10 shown, the connection electrode 421 (Ni film) is formed into a film by, for example, a sputtering technique or a thin film deposition technique. In this case, the base electrode 420 / connection electrode 421 is formed on the entire front surface 41a so as to cover the base electrode 420 and the silicon oxide film 45.

[0096] Next, as Figure 11 shown, the connection electrode 421 is patterned. In Figure 11 , the nozzle 100 is scanned along the front surface 41a to spray water onto the connection electrode 421. The nozzle 100 is scanned to sprinkle water over the entire front surface 41a. In this case, the pressure of the water (water pressure) is set within a range in which the connection electrode 421 can be peeled off from the silicon oxide film 45, and the semiconductor wafer 41W, the base electrode 420, and the connection electrode 421 on the base electrode 420 are not damaged. For example, the water pressure is set in the range of 0.2 to 20 MPa.

[0097] The adhesion of the connection electrode 421 (Ni layer) to the silicon oxide film 45 is lower than that of the base electrode 420 (Al alloy layer). In addition, since the metal used for the electrode material has a larger linear expansion coefficient than the substrate (e.g., Si), the in-film residual stresses of both the base electrode 420 and the connection electrode 421 are tensile stresses. On the other hand, since silicon dioxide has a smaller linear expansion coefficient than the substrate (Si), the in-film residual stress of the silicon oxide film 45 is a compressive stress. Due to the low adhesion of the connection electrode 421 to the silicon oxide film 45 and the stress difference, when water is sprayed, the portion 421d of the connection electrode 421 directly stacked on the silicon oxide film 45 is peeled off from the silicon oxide film 45.

[0098] In this embodiment, specifically, the pretreatment (plasma treatment) is performed as described above. For example, when the connection electrode 421 is formed by a sputtering technique, due to the heat generated during film formation, fluorine in the fluoride layer on the base electrode 420 moves to the connection electrode 421. Since the base electrode 420 and the connection electrode 421 are metallically bonded, the connection electrode 421 has a higher adhesion to the base electrode 420. Therefore, even when water is sprayed, the connection electrode 421 is not easily peeled off from the base electrode 420.

[0099] On the other hand, in the fluorine layer on the surface layer of the silicon oxide film 45, a portion with a weak bonding force is generated. Therefore, the adhesion of the connection electrode 421 to the silicon oxide film 45 is low. Therefore, when water is sprayed, the bond between carbon and fluorine is broken, making it easy for the connection electrode 421 (portion 421d) to be peeled off from the silicon oxide film 45 together with the fluorine layer.

[0100] As described above, the connection electrode 421 on the silicon oxide film 45 is removed by taking advantage of the difference in the adhesion of the connection electrode 421 to the base electrode 420 and the silicon oxide film 45. Therefore, as Figure 12 shown, the connection electrode 421 is patterned. The connection electrode 421 on the base electrode 420 remains, so the connection electrode 421 has an arrangement that substantially coincides with that of the base electrode 420 in a plan view. The peripheral end portion 421a of the connection electrode 421 is stacked and arranged on the peripheral end portion 420a of the base electrode 420, and the outer peripheral edge 421b substantially coincides with the outer peripheral edge 420b.

[0101] Next, as Figure 13 shown, a protective film 46 is formed. For example, liquid polyimide is applied to the front surface 41a of the semiconductor wafer 41W and spin-coated to form the protective film 46 on the entire front surface 41a. Then, a photoresist is applied to the surface of the protective film 46 and patterned by exposure, and etching is performed using the photoresist as a mask to pattern the protective film 46. As a result, openings 46a and 46b are formed in the protective film 46. In addition, the dicing area 412 is opened to separate the plurality of semiconductor elements formed on the semiconductor wafer 41W. By opening the dicing area 412, the exposed portion 45b of the silicon oxide film 45 is exposed as an exposed part.

[0102] Next, as Figure 14 shown, a collector 43 is formed on the back surface 41b of the semiconductor wafer 41W by, for example, a sputtering technique. Then, the semiconductor wafer 41W is cut into individual chips along the dicing area 412, although not shown. In this way, the semiconductor element 40 as described above can be produced.

[0103] <Summary of the First Embodiment>

[0104] Figure 15 It is a cross-sectional view showing a reference example. In the reference example, elements identical or related to those in the present embodiment are denoted by adding "r" to the tail of the reference numerals in the present embodiment. Figure 15 It shows a solder connection structure between the emission electrode 42r and the terminal member 70r.

[0105] Also in the semiconductor device 20r of the reference example, similar to the present embodiment, the emission electrode 42r of the semiconductor element 40r has a base electrode 420r and a connection electrode 421r. The connection electrode 421r is provided on the surface of the portion where the base electrode 420r is exposed from the opening 46ar of the protective film 46r. The connection electrode 421r is provided only in the opening 46ar and is not covered by the protective film 46r. The outer peripheral edge 421br of the connection electrode 421 contacts the opening end 46cr of the protective film 46r. The connection electrode 421r includes, for example, a coating film. The connection electrode 421r is formed after forming the protective film 46r to cover the base electrode 420r and patterning it to form the opening 46ar.

[0106] In the semiconductor element 40r, the boundary (interface) between the protective film 46r and the connection electrode 421r is located above the base electrode 420r. There is an active region 410r directly below this boundary. In such a configuration, thermal stress caused by, for example, power cycling or cold cycling concentrates on the portion directly below the boundary, that is, the portion directly below the outer peripheral edge 421br, as indicated by the dashed arrow. Therefore, cracks may occur in the portion directly below the boundary of the base electrode 420r. The cracks can grow into the active region 410r existing directly below the boundary. The thermal stress is generated due to the difference in the linear expansion coefficients between the semiconductor element 40r (semiconductor substrate 41r) and a metal member such as the terminal member 70r. In this case, "directly below" means that the position of the lower element coincides with that of the upper element in the Z direction, and does not necessarily mean that the lower element is in direct contact with the upper element.

[0107] Specifically, in the configuration of the reference example, the outer peripheral end portion of the solder 90r substantially coincides with the opening end 46cr of the protective film 46r. That is, the boundary between the solder 90r and the protective film 46r substantially coincides with the boundary between the connection electrode 421r and the protective film 46r. Therefore, the positions of the outer peripheral edge 421br, the opening end 46cr, and the outer peripheral end portion of the solder 90r overlap each other in a plan view, that is, in the Z direction, making the thermal stress more concentrated on the portion directly below the boundary.

[0108] Figure 16 It shows the semiconductor device 20 of the present embodiment. For convenience, Figure 16 It shows a solder connection structure between the semiconductor element 40 and the terminal member 70. Figure 16 Corresponding toFigure 15 As shown in Figure 16 , the connection electrode 421 extends upward to a position that overlaps with the outer peripheral region 411 in the Z direction in the plan view. The peripheral end portion 421a of the connection electrode 421 is covered with the protective film 46. In the plan view, the outer peripheral edge 421b of the connection electrode 421 is provided at a position overlapping with the outer peripheral region 411 of the semiconductor substrate 41, that is, the boundary (interface) between the outer peripheral edge 421b and the protective film 46. That is, the boundary between the outer peripheral edge 421b and the protective film 46 is located at a position corresponding to the outer peripheral region 411 of the semiconductor substrate 41 in the Z direction.

[0109] In this way, in the plan view, the boundary between the outer peripheral edge 421b and the protective film 46 is provided at a position away from the active region 410. Therefore, even if thermal stress due to, for example, power cycling or cold / hot cycling concentrates in the portion directly below the boundary, cracks are less likely to develop into the active region 410. Therefore, damage to the active region 410 by thermal stress can be suppressed.

[0110] In this embodiment, the position of the boundary between the outer peripheral edge 421b of the connection electrode 421 and the protective film 46 is offset outward relative to the position of the boundary between the solder 90 and the protective film 46. As a result, the thermal stress is dispersed. Therefore, the thermal stress acting directly below the boundary between the outer peripheral edge 421b and the protective film 46 can be reduced.

[0111] The position of the outer peripheral edge 421b of the connection electrode 421 can be set within the range overlapping with the outer peripheral region 411. For example, as in the Figure 17 shown modification, the position of the outer peripheral edge 421b can be offset relative to the outer peripheral edge 420b of the base electrode 420. Figure 17 is a cross-sectional view of this modification and corresponds to Figure 16 . The outer peripheral edge 421b is located at a position closer to the inside than the outer peripheral edge 420b. In the plan view, the boundary between the outer peripheral edge 421b and the protective film 46 is provided at a position away from the active region 410. Therefore, damage to the active region 410 by thermal stress can be restricted.

[0112] On the other hand, in the present embodiment, the connection electrode 421 is provided so as to substantially coincide with the base electrode 420 in a plan view. The positions of the outer peripheral edges 420b and 421b substantially coincide with each other over the entire periphery. In this configuration, the base electrode 420 is not located directly below the boundary between the outer peripheral edge 421b and the protective film 46. Therefore, cracks can be suppressed from occurring in the portion directly below the boundary of the base electrode 420 due to thermal stress concentration. The silicon oxide film 45 exists directly below the boundary. Even if thermal stress is concentrated on the portion directly below the boundary of the silicon oxide film 45, the silicon oxide film 45 is a brittle material and does not undergo plastic fracture due to repetition. Therefore, damage to the semiconductor substrate 41 by thermal stress can be restricted.

[0113] In the present embodiment, in particular, the silicon oxide film 45 is formed on the entire front surface 41a of the semiconductor wafer 41W except for the portion connected to the emission electrode 42. Then, by utilizing the difference in the adhesion of the connection electrode 421 to the base electrode 420 and the silicon oxide film 45 and the difference in the residual stress in the film, the portion of the connection electrode 421 on the silicon oxide film 45 is removed, while the portion of the connection electrode 421 on the base electrode 420 is left. When the connection electrode 421 is peeled off from any position on the silicon oxide film 45, the connection electrode 421 can be peeled off from the silicon oxide film 45 from the peeling position as a starting point while the connection electrode 421 on the silicon oxide film 45 remains connected. Therefore, the connection electrode 421 can be patterned without using a resist.

[0114] In the present embodiment, in particular, plasma treatment is performed after forming the base electrode 420 and before forming the connection electrode 421. A fluorine-based gas is used in the plasma treatment. As a result, after removing the oxide film on the surface of the base electrode 420, fluorine adheres to the surfaces of the base electrode 420 and the silicon oxide film 45 to form a fluoride layer on the surfaces of the base electrode 420 and the silicon oxide film 45. Due to the formation of the fluorine layer, the difference in adhesion to the connection electrode 421 becomes larger, and the connection electrode 421 on the silicon oxide film 45 can be easily peeled off.

[0115] When peeling off the connection electrode 421 (Ni layer) on the silicon oxide film 45, water can be sprayed while the substantially disk-shaped semiconductor wafer 41W rotates about its central axis. As a result, water can be applied substantially uniformly to the front surface 41a of the semiconductor wafer 41W. In this way, spin cleaning can be used.

[0116] Other liquids (such as organic solvents) can be used instead of water. A gas such as air can be sprayed instead of water. By using the pressure of the liquid or gas, the portion of the connection electrode 421 having lower adhesion can be peeled off.

[0117] In addition, the connection electrode 421 on the silicon oxide film 45 can be peeled off by wet cleaning. In this case, an etching solution containing sulfuric acid (e.g., sulfuric acid hydrogen peroxide) can be used. Sulfuric acid hydrogen peroxide is a mixed solution of sulfuric acid and hydrogen peroxide.

[0118] (Second Embodiment)

[0119] The second embodiment is a modification of the previous embodiment as the basic configuration and may include the description of the previous embodiment. In the previous embodiment, the boundary between the solder 90 and the protective film 46, i.e., the open end 46c of the protective film 46, is provided at a position overlapping with the active region 410, i.e., at a position corresponding to the active region 410 in the Z direction. Alternatively, the open end 46c of the protective film 46 may be located at a position more outside than the active region 410.

[0120] Figure 18 is a cross-sectional view of the semiconductor device 20 according to the present embodiment. Figure 18 Also shown is the solder connection structure between the semiconductor element 40 and the terminal member 70 as in Figure 16 . In a plan view, the open end 46c of the protective film 46 is located at a position more outside than the outer peripheral edge 410a of the active region 410. The open end 46c is located at a position overlapping with the outer peripheral region 411, i.e., at a position corresponding to the outer peripheral region 411 in the Z direction. As a result, directly below the boundary between the solder 90 and the protective film 46, there is no active region 410, but there is an outer peripheral region 411. Other configurations are similar to those of the previous embodiment (e.g., see Figure 16 ).

[0121] <Summary of the Second Embodiment>

[0122] As described above, thermal stress caused by, for example, power cycling or cold cycling also concentrates on the boundary between the solder 90 and the protective film 46. In the present embodiment, in addition to the boundary between the outer peripheral edge 421b of the connection electrode 421 and the protective film 46, the boundary between the solder 90 and the protective film 46 is also located at a position overlapping with the outer peripheral region 411. Therefore, damage to the active region 410 due to thermal stress can be more effectively suppressed.

[0123] Since the boundary between the solder 90 and the protective film 46 is provided outside the active region 410 in the planar direction, the size of the semiconductor element 40 increases in the direction orthogonal to the Z direction. According to the configuration described in the previous embodiment, damage to the active region 410 due to thermal stress can be suppressed while reducing the size of the semiconductor element 40.

[0124] The configuration of the present embodiment can be combined with the modifications shown in the previous embodiment.

[0125] (Third Embodiment)

[0126] This embodiment is a modification of the previous embodiment as the basic structure, and the description of the previous embodiment can be incorporated. In the previous embodiment, the connection electrode 421 has a single-layer structure. Alternatively, the connection electrode 421 may have a multi-layer structure.

[0127] Figure 19 is a cross-sectional view of the semiconductor device 20 according to this embodiment. Figure 19 Also shown is the solder connection structure between the semiconductor element 40 and the terminal member 70 as in Figure 16 . The connection electrode 421 has a two-layer structure. The connection electrode 421 has a lower layer 4210 as the layer in contact with the base electrode 420 and an upper layer 4211 as the layer in contact with the solder 90.

[0128] The lower layer 4210 is a layer made of metal, and has a lower adhesion to the silicon oxide film 45 than to the base electrode 420. The lower layer 4210 has a higher adhesion to the base electrode 420 and the upper layer 4211 than to the silicon oxide film 45. The upper layer 4211 is a layer made of metal and has better solderability than the lower layer 4210. In this embodiment, a platinum (Pt) layer is used as the lower layer 4210 and a nickel layer is used as the upper layer 4211. The lower layer 4210 (Pt) also functions as a barrier layer to prevent the solder 90 from alloying with Sn. The lower layer 4210 and the upper layer 4211 are formed by sputtering technology and vapor deposition technology. Other structures are similar to those of the previous embodiment (for example, see Figure 16 ).

[0129] <Summary of the Third Embodiment>

[0130] In this embodiment, the connection electrode 421 has a multi-layer structure. The lower layer 4210 of the connection electrode 421 has a low adhesion to the silicon oxide film 45, and the upper layer 4211 has excellent binding ability with the solder 90. Therefore, the connection electrode 421 on the silicon oxide film 45 can be easily peeled off while ensuring high binding strength. Although Pt is a hard material that is difficult to etch, the lower layer 4210 and the upper layer 4211 on the silicon oxide film 45 can be removed by utilizing the difference in the adhesion of the lower layer 4210 to the base electrode 420 and the silicon oxide film 45. Therefore, the connection electrode 421 on the base electrode 420 can be left.

[0131] The above describes an example in which the lower layer 4210 is a Pt layer and the upper layer 4211 is a Ni layer. However, the lower layer 4210 and the upper layer 4211 are not limited to this example. For example, the lower layer 4210 may be a Pd layer. The Pd layer also functions as a barrier layer. Alternatively, the lower layer 4210 may be a Pt layer, and the upper layer 4211 may be an Ag layer. The linear expansion coefficient of Ag is as high as 19 ppm / °C. Therefore, tensile stress increases, and the entire connecting electrode 421 is easily peeled off.

[0132] The connection electrode 421 is not limited to a double-layer structure. The connection electrode 421 may have a multilayer structure of three or more layers. For example, an intermediate layer (not shown) serving as a barrier layer may be provided between the lower layer 4210 and the upper layer 4211. As the intermediate layer, for example, a Ti layer may be used.

[0133] The configuration of this embodiment can be combined with the modification shown in the first embodiment and the configuration shown in the second embodiment.

[0134] (Fourth embodiment)

[0135] This embodiment is a modification of the previous embodiment as a basic configuration and can be incorporated into the description of the previous embodiment. In the previous embodiment, the connection electrode 421 has only a layer (or multiple layers) formed by removing (stripping) a portion disposed on the silicon oxide film. Alternatively, the connection electrode 421 may have a plating layer disposed in the opening 46a after forming the protective film 46.

[0136] Figure 20 is a cross-sectional view showing a semiconductor device 20 according to the present embodiment. ​ It also shows that ​ The solder connection structure between the semiconductor element 40 and the terminal member 70 is similar to the third embodiment (see ​ ), the connection electrode 421 has a two-layer structure. The connection electrode 421 has a lower layer 4212 as a layer in contact with the base electrode 420 and an upper layer 4213 as a layer in contact with the solder 90.

[0137] The lower layer 4212 is formed on the base electrode 420 by the same method as that used to form the connection electrode 421 described in the previous embodiment. The upper layer 4213 is formed in the opening 46a by plating technology. The upper layer 4213 is stacked on the base electrode 420 exposed from the opening 46a of the protective film 46. In this embodiment, a Ni layer formed by sputtering technology is used as the lower layer 4212, and a Ni layer formed by electroless plating technology is used as the upper layer 4213. The upper layer 4213 is thicker than the lower layer 4212.

[0138] <Overview of Fourth Embodiment>

[0139] As described above, the connection electrode 421 of the present embodiment has an upper layer 4213 as a plating layer. In a plan view, the boundary between the outer peripheral edge of the upper layer 4213 and the protective film 46 is located above the base electrode 420 and the active region 410. Even if thermal stress concentrates at the boundary between the outer peripheral edge of the upper layer 4213 and the protective film 46, the lower layer 4212 (Ni layer) directly below this boundary is harder than the base electrode 420 (aluminum alloy). In addition, since the boundary between the outer peripheral edge of the lower layer 4212 and the protective film 46 is located at a position more outward than the active region 410, the thermal stress is dispersed. Therefore, the occurrence of cracks in the base electrode 420 and damage to the active region 410 can be suppressed.

[0140] When the plating layer is directly formed on the base electrode, it is necessary to use an etching process to remove the oxide film on the surface of the base electrode. When the oxide film is removed, the surface of the base electrode becomes uneven due to the corrosion of aluminum. The corroded part has a concave shape, and thermal stress tends to concentrate thereon. On the other hand, in the present embodiment, the upper layer 4213 as the plating layer is formed on the base electrode 420 (aluminum alloy layer) via the lower layer 4212. Therefore, the step of removing the oxide film is not required, and the unevenness of the surface of the base electrode 420 can be suppressed.

[0141] The structure of the present embodiment can be combined with the modifications shown in the first embodiment and the structure shown in the second embodiment.

[0142] (Fifth Embodiment)

[0143] This embodiment is a modification of the previous embodiment as the basic structure and can be incorporated into the description of the previous embodiment. In the previous embodiment, a part of the connection electrode 421 is covered by the protective film 46. Alternatively, a connection electrode provided only in the opening 46a of the protective film 46 can be used.

[0144] ​ is a cross-sectional view of the semiconductor device 20 according to the present embodiment. ​ Also shown is the solder connection structure between the semiconductor element 40 and the terminal member 70 as in ​ The connection electrode 421 is only arranged in the opening 46a of the protective film 46, which is different from the previous embodiment. The connection electrode 421 is provided on the base electrode 420 exposed from the opening 46a. The connection electrode 421 is, for example, a Ni layer formed by plating technology.

[0145] The outer peripheral edge 421b of the connection electrode 421 contacts the opening end 46c of the protective film 46. The boundary (interface) between the connection electrode 421 and the protective film 46 is set at a position overlapping with the outer peripheral region 411 in a plan view.

[0146] <Summary of the Fifth Embodiment>

[0147] In the present embodiment, the boundary between the connection electrode 421 and the protective film 46 is located at a position outside the outer peripheral edge 410a of the active region 410. Therefore, even if thermal stress caused by power cycling and cold cycling, etc., concentrates on the portion directly below the boundary, cracks are less likely to develop into the active region 410. Therefore, damage to the active region 410 by thermal stress can be suppressed.

[0148] In the structure of the present embodiment, the outer peripheral edge of the solder 90 substantially coincides with the open end 46c of the protective film 46. Therefore, in a plan view, the outer peripheral edge 421b, the open end 46c, and the outer peripheral edge of the solder 90 overlap each other. When a triple point is formed, thermal stress is more likely to concentrate on the portion directly below the triple point. However, in the present embodiment, since the boundary between the connection electrode 421 and the protective film 46 is located at a position outside the active region 410, damage to the active region 410 by thermal stress can be suppressed.

[0149] (Other embodiments)

[0150] The disclosure in this specification and the drawings is not limited to the exemplary embodiments. The present disclosure includes the above embodiments and modifications by those skilled in the art based on the above embodiments. For example, the present disclosure is not limited to the combination of components and / or elements shown in the embodiments. The present disclosure can be implemented in various combinations. The present disclosure can have additional parts that can be added to the embodiments. The present disclosure includes the omission of components and / or elements in the embodiments. The present disclosure includes the replacement or combination of components and / or elements between one embodiment and another embodiment. The technical scope of the disclosure is not limited to the description of the embodiments. The several technical scopes disclosed are represented by the description of the claims and should be interpreted to include all modifications within the meaning and scope equivalent to the description of the claims.

[0151] The disclosure of this specification, the drawings, etc. is not limited by the description of the claims. The disclosure in this specification, the drawings, etc. includes the technical idea described in the claims and further extends to various technical ideas broader than the technical idea in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, the drawings, etc., not limited to the description of the claims.

[0152] Descriptions of elements or layers that are “disposed on,” “connected to,” or “coupled to” may mean that the element or layer is disposed directly on, connected directly to, or coupled directly to another element or layer, or that intervening elements or layers may be present therebetween. Conversely, when an element or layer is described as being “disposed directly on,” “connected directly to,” or “coupled directly to” another element or layer, there are no intervening elements or layers therebetween. Other terms used to describe the relationship between elements (e.g., “between” versus “directly between” and “adjacent” versus “directly adjacent”) should be interpreted similarly. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the term A and / or B includes only A, only B, or both A and B. Similarly, the term “at least one of A and B” includes only A, only B, or both A and B.

[0153] Spatial relative terms, such as “inner,” “outer,” “rear,” “bottom,” “lower,” “top,” “upper,” etc., are used herein for ease of description to describe the relationship of one element or feature to another element or feature. In addition to the orientation depicted in the figures, the spatial relative terms may also include different orientations of the device during use or operation. For example, when the device in the figures is flipped, an element described as “below” or “beneath” another element or feature is then oriented “above” or “over” the other element or feature. Thus, the term “below” may include both above and below. The device may be oriented in another direction (rotated 90 degrees or any other orientation), and the spatial relative terms used herein are interpreted accordingly.

[0154] The vehicle drive system 1 is not limited to the above-described configurations. For example, a vehicle drive system 1 having one electric generator 3 is illustrated. However, the present disclosure is not limited to such an example. The vehicle drive system 1 employing the semiconductor device of the present disclosure may have a plurality of electric generators. A power conversion device 4 including an inverter 6 as a power converter is illustrated. However, the power conversion device 4 is not limited to this example. For example, the power conversion device 4 may include a plurality of inverters. The power conversion device 4 may include at least one inverter and at least one converter. The power conversion device 4 may include only converters.

[0155] The configuration of the semiconductor device 20 is not limited to the above examples. The semiconductor device 20 may include at least a semiconductor element 40.

[0156] A semiconductor element 40 having an emission electrode 42 on a front surface 41a and a collector electrode 43 on a back surface 41b as main electrodes is illustrated. However, the configuration of the semiconductor element 40 is not limited to the described example. The semiconductor element 40 may have main electrodes only on the front surface 41a.

[0157] An opening 46a having a rectangular shape in a plan view has been illustrated. However, the shape of the opening 46a is not limited to the described example.

[0158] A semiconductor element 40 having an RC-IGBT as an element has been illustrated. However, the semiconductor element 40 is not limited to such an example. The switching element and the diode may be provided in separate chips. The IGBT has been given as an example of the switching element. However, the switching element is not limited to the IGBT. For example, the switching element may be a MOSFET.

[0159] A structure in which the back surfaces 50b and 60b of the heat sinks 50 and 60 are exposed from the sealing resin body 30 has been illustrated. However, the configuration of the semiconductor device 20 is not limited to such an example. At least one of the back surfaces 50b and 60b may be covered with the sealing resin body 30. At least one of the back surfaces 50b and 60b may be covered with an insulating member (not shown) different from the sealing resin body 30. A semiconductor device 20 including the sealing resin body 30 has been illustrated. However, the configuration of the semiconductor device 20 is not limited to such an example. The semiconductor device 20 may not have the sealing resin body 30.

[0160] A semiconductor device 20 including only one semiconductor element 40 constituting one arm has been illustrated. However, the configuration of the semiconductor device 20 is not limited to such an example. The semiconductor device 20 may include a plurality of semiconductor elements 40 that constitute the upper arm and the lower arm circuits 9 of one phase. The semiconductor device 20 may include a plurality of semiconductor elements 40 that constitute the upper arm and the lower arm circuits 9 for a plurality of phases.

[0161] A signal terminal 82 connected to a pad 44 via a bonding wire 91 has been illustrated. However, the connection of the signal terminal 82 may not be limited to such an example. For example, the signal terminal 82 may be connected to the pad 44 via solder.

Claims

1. A semiconductor device for a power conversion device, comprising: Semiconductor device (40), comprising: a semiconductor substrate (41) having an active region (410) and a peripheral region (411) as element formation regions, the active region (410) being arranged adjacent to a front surface (41a) of the semiconductor substrate (41), and in a plan view projected in a substrate thickness direction orthogonal to the front surface (41a) of the semiconductor substrate (41), the peripheral region (411) surrounding the active region (410); a surface electrode (42) including a base electrode (420) provided on the front surface (41a) of the semiconductor substrate (41) and a connection electrode (421) provided on the base electrode (420); and a protective film (46) covering a peripheral end portion (420a) of the base electrode (420) and an outer peripheral edge (421b) of the connection electrode (421), the protective film (46) defining an opening (46a) for exposing the connection electrode (421) to enable solder connection to the connection electrode (421), wherein, in the plan view in the substrate thickness direction, a boundary between the outer peripheral edge (421b) of the connection electrode (421) and the protective film (46) is located at a position corresponding to the peripheral region (411) of the semiconductor substrate (41), wherein the semiconductor device (40) includes a silicon oxide film (45) provided in an entire region of the front surface (41a) of the semiconductor substrate (41) excluding a connection region where the front surface (41a) and the surface electrode (42) are connected to each other, the peripheral end portion (420a) of the base electrode (420) being a first peripheral end portion, the first peripheral end portion (420a) being stacked on a portion of the silicon oxide film (45) covered by the protective film (46), and the connection electrode (421) having a second peripheral end portion (421a), the second peripheral end portion being stacked on the first peripheral end portion (420a) and covered by the protective film (46), wherein the connection electrode (421) is arranged to coincide with the base electrode (420) in the plan view.

2. The semiconductor device according to claim 1, wherein the protective film (46) has an opening end (46c) defining the opening (46a), and in the plan view, the opening end (46c) is located at a position more inward than the outer peripheral edge (421b) of the connection electrode (421) and corresponding to the active region.

3. The semiconductor device according to claim 1, wherein the protective film (46) has an opening end (46c) defining the opening (46a), and in the plan view, the opening end (46c) is located at a position corresponding to the peripheral region (411).

4. The semiconductor device according to claim 1, wherein the silicon oxide film (45) has compressive stress as the residual stress in the film, and the connection electrode (421) has tensile stress as the residual stress in the film.

5. The semiconductor device according to claim 1, wherein the connection electrode (421) includes at least one metal layer, and the at least one metal layer contains at least one of Ni, Pd, Au, Pt, and Ag.

6. A method for manufacturing a semiconductor device having a semiconductor element (40) for a power conversion device (6), the method comprising: Prepare a semiconductor wafer (41W) having an active region (410) adjacent to the front surface (41a) of the semiconductor wafer (41W) and a peripheral region (411) surrounding the active region (410); form a silicon oxide film (45) on the entire front surface (41a) of the semiconductor wafer (41W); pattern the silicon oxide film (45) to form a contact hole (45c) surrounding the active region (410); form a base electrode (420) on the entire front surface (41a) to cover the silicon oxide film (45); pattern the base electrode (420) such that the base electrode (420) has a peripheral end portion (420a) overlapping the peripheral portion of the contact hole of the silicon oxide film (45); form a connection electrode (421) on the entire front surface to cover the base electrode and the silicon oxide film; remove a part of the connection electrode (421) formed on the silicon oxide film by utilizing the difference in the adhesion of the connection electrode to the silicon oxide film and the base electrode, such that the connection electrode (421) on the base electrode (420) remains and coincides with the base electrode (420) in a plan view, thereby forming a surface electrode (42) including the base electrode (420) and the connection electrode (421) stacked on the base electrode (420); form a protective film (46) on the entire front surface (41a) to cover the surface electrode (42) and the silicon oxide film (45), wherein, in a plan view along the wafer thickness direction, the boundary between the outer peripheral edge (421b) of the connection electrode (421) and the protective film (46) is located at a position corresponding to the peripheral region (411) of the semiconductor wafer (41W); pattern the protective film (46) to form an opening (46a), thereby exposing a part of the connection electrode (421) as a solder connection portion, and remove a part of the protective film (46) above the dicing region (412); and after patterning the protective film (46), cut the semiconductor wafer (41W) along the dicing region (412), thereby producing the semiconductor element (40).

7. The method according to claim 6, wherein when removing the part of the connection electrode, a liquid or gas is sprayed onto the part of the connection electrode to remove it.

8. The method according to claim 6 or 7, further comprising: After forming the base electrode, plasma treatment is performed on the base electrode and the silicon oxide film using a fluorine-based gas, wherein forming the connection electrode is performed after performing the plasma treatment.

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