Pulse modulation control system, device and method

Abstract

The present application relates to a pulse modulation control system, device and method, the processor and pulse modulation interface module, wherein the processor is based on the RISC-V open source instruction set architecture, used to receive user operation instructions, and generate data signals based on the operation instructions; the pulse modulation interface module is connected to the processor, used to receive the data signal, and output a preset waveform based on the data signal. Based on the RISC-V open source instruction set architecture, users can customize operations, improve the efficiency and flexibility of the pulse modulation process, and achieve power consumption optimization.

Description

Technical Field

[0001] The present application relates to the field of pulse modulation, and in particular to a pulse modulation control system, device and method. Background Art

[0002] Pulse width modulation (PWM) is a very effective technology that uses the digital output of a microprocessor to control analog circuits. It is widely used in many fields from measurement, communication to power control and conversion.

[0003] However, the microprocessors used in traditional pulse width modulation control systems are mostly x86 and ARM architectures. As general-purpose architectures, these two architectures do not have instructions specifically for PWM, and the control efficiency is low. It often requires multiple instructions to complete a PWM output operation.

[0004] Moreover, in order to maintain backward compatibility during the use and development of commercial architectures, x86 and ARM architectures have to retain many outdated definitions, resulting in a large number of instructions and serious instruction redundancy. Using them to design new processors will inevitably result in larger area and power consumption. In addition, the use of commercial architectures also involves high patent and licensing fees. Summary of the invention

[0005] Based on this, it is necessary to provide a pulse modulation control system, device and method to address the problems in the above-mentioned background technology. Based on the RISC-V open source instruction set architecture, users can customize operations, improve the efficiency and flexibility of the pulse modulation process, and achieve power consumption optimization.

[0006] One aspect of the present application provides a pulse modulation control system, including a processor and a pulse modulation interface module, wherein the processor is based on the RISC-V open source instruction set architecture, and is used to receive user operation instructions and generate a data signal based on the operation instructions; the pulse modulation interface module is connected to the processor, and is used to receive the data signal and output a preset waveform based on the data signal.

[0007] In the pulse modulation control system in the above embodiment, a processor based on the RISC-V open source instruction set architecture is set to receive user operation instructions, and a data signal is generated based on the operation instructions, thereby controlling the pulse modulation interface module to output a preset waveform. Based on the RISC-V open source instruction set architecture, users can customize operations, improve the efficiency and flexibility of the pulse modulation process, and achieve power consumption optimization.

[0008] In one embodiment, the processor includes a basic instruction submodule and an extended instruction submodule, wherein the basic instruction submodule is used to implement the standard instruction set defined by the RISC-V standard; the extended instruction submodule is used to implement a user-defined custom instruction set.

[0009] In one embodiment, the customized instruction includes a pulse modulation control instruction, and the pulse modulation control instruction is used to generate a parameter data signal for controlling a pulse modulation parameter.

[0010] In one embodiment, the pulse modulation interface module includes sixteen pulse modulation channels, and any one of the pulse modulation channels includes a register group, a counter and a direction controller, wherein the register group is connected to the processor, and the register group is used to receive and store the parameter data signal; the counter is connected to the register group, and is used to obtain the start signal and the data signal, start counting based on the start signal and the data signal, and generate a phase signal; the direction controller is connected to both the register group and the counter, and is used to obtain the data signal and the phase signal, and output the preset waveform based on the data signal and the phase signal.

[0011] In one embodiment, the parameter data signal includes a first parameter data signal, a second parameter data signal, a third parameter data signal and a fourth parameter data signal; the register group includes a pulse waveform control bit, a starting phase control bit, a duty cycle control bit and a waveform period control bit, wherein the pulse waveform control bit occupies 1 bit for storing the first parameter data signal; the starting phase control bit occupies 1 byte for storing the second parameter data signal; the duty cycle control bit occupies 1 byte for storing the third parameter data signal; the waveform period control bit occupies 2 bytes for storing the fourth parameter data signal.

[0012] The stage signal includes a trigger signal, a first stage control signal and a second stage control signal, and the counter includes a first counter, a second counter and a third counter, wherein the first counter is connected to both the starting phase control bit and the direction controller, and is used to obtain the start signal and the second parameter data signal value, start counting based on the start signal and the second parameter data signal value, and generate the trigger signal and the first stage control signal; the second counter is connected to both the duty cycle control bit and the first counter, and is used to obtain the trigger signal and the third parameter data signal value, start counting based on the trigger signal and the third parameter data signal value, and output the second stage control signal; the third counter is connected to the pulse waveform control bit, and is used to obtain the first parameter data signal value, start timing based on the first parameter data signal value, and control the pulse modulation control system to stop.

[0013] In one embodiment, the preset waveform includes a convex waveform and a concave waveform, and the direction controller is configured as follows:

[0014] Acquire the first parameter data signal and the first stage control signal, and generate the convex waveform or the concave waveform based on the first parameter data signal and the first stage control signal;

[0015] The first parameter data signal and the second stage control signal are acquired, and the concave waveform or the convex waveform is generated based on the first parameter data signal and the second stage control signal.

[0016] In one embodiment, the pulse modulation control system also includes an interface controller and a first interface module, wherein the interface controller is connected to the basic instruction submodule for executing the standard instruction set; the first interface module is connected to the interface controller for realizing data transmission and control of external devices.

[0017] In one embodiment, the first interface module includes at least one of a UART interface, a QSPI interface, an I2S interface, an I2C interface, a GPIO interface and a JTAG interface.

[0018] Another aspect of the present application provides a pulse modulation control device, including the pulse modulation control system described in any one of the embodiments of the present application.

[0019] The pulse modulation control device in the above embodiment receives user operation instructions by setting a processor based on the RISC-V open source instruction set architecture, and generates a data signal based on the operation instruction, thereby controlling the pulse modulation interface module to output a preset waveform. Based on the RISC-V open source instruction set architecture, users can customize operations, improve the efficiency and flexibility of the pulse modulation process, and optimize power consumption.

[0020] Another aspect of the present application provides a pulse modulation control method, comprising the following steps:

[0021] Get user operation instructions;

[0022] A processor based on the RISC-V open source instruction set architecture generates a data signal based on the user operation instruction;

[0023] The data signal is received based on a pulse modulation interface module, and a preset waveform is output according to the data signal.

[0024] The pulse modulation control method in this application uses the characteristics of the customizable instruction set of the RISC-V core to design a set of instructions specifically for PWM control, which can generate PWM waveforms with a single instruction. The efficiency of multi-instruction operation is much higher than that of traditional x86 and ARM architectures, and the controller of the RISC-V architecture is lighter and has low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 This is a schematic diagram of the structure of a pulse modulation control system provided in the first embodiment of the present application;

[0027] Figure 2 This is a schematic diagram of the structure of a pulse modulation control system provided in the second embodiment of the present application;

[0028] Figure 3 This is a schematic diagram of the structure of a pulse modulation control system provided in the third embodiment of the present application;

[0029] Figure 4 A schematic diagram of a pulse modulation channel structure provided in the fourth embodiment of the present application;

[0030] Figure 5 A schematic diagram of pulse modulation control instruction parameters provided in the fifth embodiment of the present application;

[0031] Figure 6 A schematic diagram of a pulse modulation channel structure provided in the sixth embodiment of the present application;

[0032] Figure 7 This is a schematic diagram of the structure of a pulse modulation control system provided in the seventh embodiment of the present application;

[0033] Figure 8 This is a schematic diagram of the structure of a pulse modulation control system provided in the eighth embodiment of the present application;

[0034] Fig. 9 A schematic flow chart of a pulse modulation control method provided in one embodiment of the present application;

[0035] Fig.10 A flow chart of a pulse modulation control method provided in another embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0038] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0039] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0040] In this application, unless otherwise clearly specified and limited, the terms "connected", "connection" and the like should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0041] In the processor field, the current mainstream architectures are x86 and ARM architectures. After decades of development, the architecture documents of modern x86 and ARM architectures are hundreds of thousands of pages long and have many versions. One of the main reasons is that the development process of its architecture is also accompanied by the continuous development and maturity of modern processor architecture technology. As a commercial architecture, in order to maintain the backward compatibility of the architecture, it has to retain many outdated definitions, or when defining new architecture parts, in order to be able to use existing technical parts, it becomes extremely lengthy over time. However, as an instruction set, RISC-V can be used freely for any purpose compared to most instruction sets, allowing anyone to design, manufacture and sell RISC-V chips and software. It takes into account both the amount and speed of data transmission, and is an excellent architecture for the heterogeneous IoT era. A series of ecosystems derived from it are becoming increasingly perfect. RISC-V also has the following advantages: open source, low CPU design cost, any innovation in hardware produced through collaboration will create huge economic benefits; simple, with only more than 40 basic instruction sets, meeting the high code volume requirements of embedded and IoT; flexible, with a large amount of coding space and 4 user instructions reserved for expanding the instruction set. Although RISC-V is not the first open source instruction set, it is significant because its design makes it suitable for modern computing devices. The designers took into account performance and power efficiency in these uses. The instruction set also has a lot of supporting software, which solves the usual weaknesses of new instruction sets.

[0042] In one embodiment of the present application, Figure 1 As shown, a pulse modulation control system 100 is provided, including a processor 10 and a pulse modulation interface module 20, wherein the processor 10 is based on the RISC-V open source instruction set architecture, and is used to receive user operation instructions and generate data signals based on the operation instructions; the pulse modulation interface module 20 is connected to the processor 10, and is used to receive the data signal and output a preset waveform based on the data signal.

[0043] In the pulse modulation control system 100 in the above embodiment, a processor 10 based on the RISC-V open source instruction set architecture is set to receive user operation instructions, and a data signal is generated based on the operation instructions, thereby controlling the pulse modulation interface module 20 to output a preset waveform. Based on the RISC-V open source instruction set architecture, users can customize operations, improve the efficiency and flexibility of the pulse modulation process, and optimize power consumption.

[0044] In one embodiment, if Figure 2As shown, the processor 10 includes a basic instruction submodule 11 and an extended instruction submodule 12, wherein the basic instruction submodule 11 is used to implement the standard instruction set defined by the RISC-V standard; the extended instruction submodule 12 is used to implement a user-defined custom instruction set.

[0045] Specifically, the biggest difference between the RISC-V architecture and other mature commercial architectures is that it is a modular architecture. In this application, the CPU that complies with the RISC-V ISA standard includes a basic instruction submodule 11, which is used to implement the standard instruction set defined by the RISC-V standard. The standard instruction set includes RV32I, RV32E, RV64I and RV128I, wherein RV32I is a 32-bit integer instruction set, RV32E is a subset of RV32I, used for small embedded scenarios, RV64I is a 64-bit integer instruction set, compatible with RV32I, and RV128I is a 128-bit integer instruction set, compatible with RV64I and RV32I; the CPU that complies with the RISC-V ISA standard also includes an extended instruction submodule 12, which is used to implement a user-defined custom instruction set. The RISC-V architecture is not only compact and powerful, but its different parts can also be organized together in a modular way, thereby trying to meet various different applications through a unified architecture. This modularity is not available in the x86 and ARM architectures. The open source of RISC-V ISA means that corresponding chip architectures can be created for different application scenarios. With the help of corresponding customized instruction tools, application acceleration can be made more efficient, and the multi-core heterogeneous characteristics also promote power consumption optimization.

[0046] In one embodiment, the customized instruction includes a pulse modulation control instruction, and the pulse modulation control instruction is used to generate a parameter data signal for controlling a pulse modulation parameter.

[0047] Specifically, based on the extended instruction set in the RISC-V open source instruction set architecture, users can customize instructions and apply them in pulse modulation technology. Users can specify pulse modulation control instructions according to their needs. The pulse modulation control instructions are used to generate parameter data signals for controlling pulse modulation parameters. The pulse modulation parameters include pulse length, duty cycle, starting phase, waveform, etc.

[0048] In one embodiment, if Figure 3 and Figure 4As shown, the pulse modulation interface module 20 includes sixteen pulse modulation channels, and any one of the pulse modulation channels includes a register group, a counter and a direction controller, wherein the register group is connected to the processor, and the register group is used to receive and store the parameter data signal; the counter is connected to the register group, and is used to obtain the start signal and the data signal, start counting based on the start signal and the data signal, and generate a phase signal; the direction controller is connected to both the register group and the counter, and is used to obtain the data signal and the phase signal, and output the preset waveform based on the data signal and the phase signal.

[0049] Specifically, the pulse modulation interface module 20 includes sixteen pulse modulation channels PWM0, PWM1, PWM2, ... PWM15, each PWM channel includes a register group, a counter and a direction controller. It is connected to the processor through the register group, and is used to receive the pulse modulation control instruction and store the parameter data signal, and output the preset waveform after being processed by the counter and direction controller.

[0050] In one embodiment, the parameter data signal includes a first parameter data signal, a second parameter data signal, a third parameter data signal and a fourth parameter data signal; the register group includes a pulse waveform control bit, a starting phase control bit, a duty cycle control bit and a waveform period control bit, wherein the pulse waveform control bit occupies 1 bit for storing the first parameter data signal; the starting phase control bit occupies 1 byte for storing the second parameter data signal; the duty cycle control bit occupies 1 byte for storing the third parameter data signal; the waveform period control bit occupies 2 bytes for storing the fourth parameter data signal.

[0051] Among them, the stage signal includes a trigger signal, a first stage control signal and a second stage control signal, and the counter includes a first counter, a second counter and a third counter, wherein the first counter is connected to both the starting phase control bit and the direction controller, and is used to obtain the start signal and the second parameter data signal value, start counting based on the start signal and the second parameter data signal value, and generate the trigger signal and the first stage control signal; the second counter is connected to both the duty cycle control bit and the first counter, and is used to obtain the trigger signal and the third parameter data signal value, start counting based on the trigger signal and the third parameter data signal value, and output the second stage control signal; the third counter is connected to the pulse waveform control bit, and is used to obtain the first parameter data signal value, start timing based on the first parameter data signal value, and control the pulse modulation control system to stop.

[0052] As an example, Figure 5 As shown, through the RISC-V custom instruction set, a set of pulse modulation control instructions setPWMn (s, a, b, c) are defined, where s, a, b, c are pulse modulation control instructions for generating parameter data signals for controlling pulse modulation parameters. a corresponds to the first parameter data signal for controlling the starting position of the preset waveform, b corresponds to the second parameter data signal for controlling the duty cycle of the preset waveform, c corresponds to the third parameter data signal for controlling the wavelength of the preset waveform, and s corresponds to the fourth parameter data signal for controlling the preset waveform. Specifically, when s is 0, a convex waveform is generated, and when s is 1, a concave waveform is generated. By setting the instruction parameters s, a, b and c, the preset waveform corresponding to the parameter data can be generated. The traditional x86 and ARM architectures use multiple instructions to implement pulse modulation, and it takes 5 to 10 instructions to complete the output of a pulse, and it also takes up the processor process. The present invention uses custom instructions, and cooperates with the PWM controller, and only one instruction is needed to complete the generation of a pulse, and it does not take up the processor process.

[0053] As an example, Figure 6 As shown, the register includes a pulse waveform control bit, a start phase control bit, a duty cycle control bit and a waveform period control bit, and the register is used to store parameter data signals, wherein the pulse waveform control bit occupies 1 bit (1 bit) and is used to store the first parameter data signal a; the start phase control bit occupies 1 byte (8 bits) and is used to store the second parameter data signal b; the duty cycle control bit occupies 1 byte (8 bits) and is used to store the third parameter data signal c; the waveform period control bit occupies 2 bytes (16 bits) and is used to store the fourth parameter data signal s. The counter includes a first counter, a second counter and a third counter.

[0054] Specifically, when the user issues the operation instruction setPWMn(s,a,b,c), the register group reads the data parameters a,b,c,s and transmits them to the first counter, the second counter, the third counter and the direction controller respectively. At the same time, a start signal is sent to the first counter, and the first counter and the third counter start counting at the same time. The first counter outputs the first stage control signal in the counting stage, and controls the direction controller to output the same logic level as s, that is, when s=0, it outputs 0, and when s=1, it outputs 1. After the first counter counts to a, it ends counting and outputs a trigger signal, and the second counter starts counting. The second counter outputs the second stage control signal in the counting stage, and controls the direction controller to output the opposite logic level of s, that is, when s=0, it outputs 1, and when s=1, it outputs 0. The second counter ends when it counts to b, and the direction controller outputs the same logic level as s. The third counter counts to c and counts the entire counting cycle, outputs an end mark, indicating that the operation instruction setPWMn(s,a,b,c) is completed, and outputs the preset waveform.

[0055] In one embodiment, the preset waveform includes a convex waveform and a concave waveform, and the direction controller is configured as follows:

[0056] Acquire the first parameter data signal and the first stage control signal, and generate the convex waveform or the concave waveform based on the first parameter data signal and the first stage control signal;

[0057] The first parameter data signal and the second stage control signal are acquired, and the concave waveform or the convex waveform is generated based on the first parameter data signal and the second stage control signal.

[0058] Specifically, the direction controller controls the waveform of the output pulse based on the first parameter data signal and the stage control signal, wherein the first parameter data signal s is stored in the pulse waveform control bit of the register group, and the stage signal is issued by the counter control. As an example, when the first parameter data signal s=0 and the direction controller obtains the first stage signal, the direction controller outputs a convex waveform; when the first parameter data signal s=0 and the direction controller obtains the second stage signal, the direction controller outputs a concave waveform; when the first parameter data signal s=1 and the direction controller obtains the first stage signal, the direction controller outputs a concave waveform; when the first parameter data signal s=1 and the direction controller obtains the second stage signal, the direction controller outputs a convex waveform. The present application can perform pulse width modulation control by setting a parameter instruction based on RISC-V, which greatly simplifies the pulse width modulation control process and reduces costs.

[0059] In one embodiment, if Figure 7 As shown, the pulse modulation control system 100 also includes an interface controller 30 and a first interface module 40, wherein the interface controller 30 is connected to the basic instruction submodule 11 for executing the standard instruction set; the first interface module 40 is connected to the interface controller 30 for realizing data transmission and control of external devices.

[0060] Specifically, the first interface module may be a commonly used interface of the processor, used to perform other functions except pulse modulation control, and the interface controller may be an I / O controller.

[0061] In one embodiment, if Figure 8 As shown, the first interface module includes at least one of a UART interface, a QSPI interface, an I2S interface, an I2C interface, a GPIO interface and a JTAG interface.

[0062] Specifically, UART is a universal asynchronous receiver-transmitter interface, QSPI is a six-wire serial peripheral interface, I2S is an integrated circuit built-in audio bus, I2C is a two-wire synchronous serial bus, GPIO is a general-purpose input and output interface, and JTAG is a joint test bus. They are operated by the common instruction set of the RISC-V core through an I / O controller. The PWM interface group is coordinated by the extended instruction set X to realize the operation of the waveform generator.

[0063] Another aspect of the present application provides a pulse modulation control device, including the pulse modulation control system described in any one of the embodiments of the present application.

[0064] The pulse modulation control device in the above embodiment receives user operation instructions by setting a processor based on the RISC-V open source instruction set architecture, and generates a data signal based on the operation instruction, thereby controlling the pulse modulation interface module to output a preset waveform. Based on the RISC-V open source instruction set architecture, users can customize operations, improve the efficiency and flexibility of the pulse modulation process, and optimize power consumption.

[0065] Another aspect of the present application provides a pulse modulation control method, such as Fig. 9 As shown, the method includes:

[0066] Step 202: Obtain user operation instructions;

[0067] Step 204: A processor based on the RISC-V open source instruction set architecture generates a data signal based on the user operation instruction;

[0068] Step 206: Receive the data signal based on the pulse modulation interface module, and output a preset waveform according to the data signal.

[0069] The pulse modulation control method in this application uses the characteristics of the customizable instruction set of the RISC-V core to design a set of instructions specifically for PWM control, which can generate PWM waveforms with a single instruction. Compared with the traditional x86 and ARM architectures, the multi-instruction operation efficiency is much higher, and the controller of the RISC-V architecture is lighter and has lower power consumption.

[0070] As an example, taking advantage of the customizable instruction set of the RISC-V core, a set of instructions setPWMn(s,a,b,c) specifically for PWM control is designed, where s,a,b,c are pulse modulation control instructions used to generate parameter data signals that control pulse modulation parameters. a corresponds to the first parameter data signal used to control the starting position of the preset waveform, b corresponds to the second parameter data signal used to control the duty cycle of the preset waveform, c corresponds to the third parameter data signal used to control the wavelength of the preset waveform, and s corresponds to the fourth parameter data signal used to control the preset waveform. Specifically, when s is 0, a convex waveform is generated, and when s is 1, a concave waveform is generated. Specifically, the process of operating instructions to control PWM generation is as follows: Fig.10 As shown, the controller executes the setPWMn(s,a,b,c) instruction, sends the s,a,b,c parameter data signals to the register group, and outputs the preset waveform after being processed by the counter and direction controller.

[0071] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0072] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present invention.

[0073] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A pulse modulation control system, characterized in that: include: A processor, the processor is based on the RISC-V open source instruction set architecture, and is used to receive user operation instructions and generate a data signal based on the operation instructions; A pulse modulation interface module, the pulse modulation interface module is connected to the processor, and is used to receive the data signal and output a preset waveform based on the data signal; The processor comprises: The basic instruction submodule is used to implement the standard instruction set defined by the RISC-V standard; Extended instruction submodule, used to implement user-defined custom instruction sets; The customized instructions include: A pulse modulation control instruction, wherein the pulse modulation control instruction is used to generate a parameter data signal for controlling a pulse modulation parameter; the parameter data signal includes a first parameter data signal, a second parameter data signal, a third parameter data signal and a fourth parameter data signal; The pulse modulation interface module includes sixteen pulse modulation channels, and any one of the pulse modulation channels includes: A register group, connected to the processor, and used for receiving and storing the parameter data signal; a counter connected to the register group, used to obtain a start signal and the parameter data signal, start counting based on the start signal and the parameter data signal, and generate a stage signal; the stage signal includes a trigger signal, a first stage control signal and a second stage control signal; a direction controller connected to the register group and the counter, and configured to obtain the parameter data signal and the phase signal, and output the preset waveform based on the parameter data signal and the phase signal; The preset waveform includes a convex waveform and a concave waveform, and the direction controller is configured as follows: Acquire the first parameter data signal and the first stage control signal, and generate the convex waveform or the concave waveform based on the first parameter data signal and the first stage control signal; The first parameter data signal and the second stage control signal are acquired, and the concave waveform or the convex waveform is generated based on the first parameter data signal and the second stage control signal.

2. The pulse modulation control system according to claim 1, characterized in that: The register set includes: a pulse waveform control bit, the pulse waveform control bit occupies 1 bit and is used to store the first parameter data signal; A starting phase control bit, which occupies 1 byte and is used to store the second parameter data signal; A duty cycle control bit, which occupies 1 byte and is used to store the third parameter data signal; A waveform period control bit, which occupies 2 bytes and is used to store the fourth parameter data signal; The counter comprises: a first counter connected to both the start phase control bit and the direction controller, configured to obtain a start signal and a value of the second parameter data signal, start counting based on the start signal and the value of the second parameter data signal, and generate the trigger signal and the first stage control signal; a second counter connected to the duty cycle control bit and the first counter, configured to obtain a trigger signal and a value of the third parameter data signal, start counting based on the trigger signal and the value of the third parameter data signal, and output the second stage control signal; A third counter is connected to the pulse waveform control bit, and is used to obtain the value of the first parameter data signal, start timing based on the value of the first parameter data signal, and control the pulse modulation control system to stop.

3. The pulse modulation control system according to claim 1, characterized in that: Also includes: An interface controller, connected to the basic instruction submodule, for executing the standard instruction set; The first interface module is connected to the interface controller and is used to realize data transmission and control of external devices.

4. The pulse modulation control system according to claim 3, characterized in that: The first interface module includes at least one of a UART interface, a QSPI interface, an I2S interface, an I2C interface, a GPIO interface and a JTAG interface.

5. A pulse modulation control device, characterized in that: include: A pulse modulation control system according to any one of claims 1 to 4.

6. A pulse modulation control method, characterized in that: The method comprises: Get user operation instructions; A processor based on the RISC-V open source instruction set architecture generates a data signal based on the user operation instruction; Receive the data signal based on the pulse modulation interface module, and output a preset waveform according to the data signal; The processor comprises: The basic instruction submodule is used to implement the standard instruction set defined by the RISC-V standard; Extended instruction submodule, used to implement user-defined custom instruction sets; The customized instructions include: A pulse modulation control instruction, wherein the pulse modulation control instruction is used to generate a parameter data signal for controlling a pulse modulation parameter; the parameter data signal includes a first parameter data signal, a second parameter data signal, a third parameter data signal and a fourth parameter data signal; The pulse modulation interface module includes sixteen pulse modulation channels, and any one of the pulse modulation channels includes: A register group, connected to the processor, and used for receiving and storing the parameter data signal; a counter connected to the register group, used to obtain a start signal and the parameter data signal, start counting based on the start signal and the parameter data signal, and generate a stage signal; the stage signal includes a trigger signal, a first stage control signal and a second stage control signal; a direction controller connected to the register group and the counter, and configured to obtain the parameter data signal and the phase signal, and output the preset waveform based on the parameter data signal and the phase signal; The preset waveform includes a convex waveform and a concave waveform, and the direction controller is configured as follows: Acquire the first parameter data signal and the first stage control signal, and generate the convex waveform or the concave waveform based on the first parameter data signal and the first stage control signal; The first parameter data signal and the second stage control signal are acquired, and the concave waveform or the convex waveform is generated based on the first parameter data signal and the second stage control signal.

Images