Pixel and method for driving pixel

Abstract

A pixel of the present invention includes: a light emitting diode, the light emitting diode includes an anode connected to a first node; a first capacitor, the first capacitor includes a first electrode connected to the first node and a second electrode connected to a second node; a first transistor, the first transistor includes a gate electrode connected to the second node, a first electrode connected to a third node, and a second electrode connected to a fourth node; and a second transistor, the second transistor includes a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to a third node.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to pixels and methods of driving pixels. Background Art

[0002] As information technology develops, the importance of display devices as a connection medium between users and information has become prominent. Due to the importance of display devices, the use of various display devices such as liquid crystal display devices, organic light emitting display devices, and plasma display devices has increased.

[0003] Each pixel of the display device may include at least one light emitting diode. As the period of use increases, the light emitting diode may degrade. The degraded light emitting diode may require more driving current to present the same brightness. Summary of the invention

[0004] Technical issues

[0005] An object to be solved is to provide a pixel capable of self-compensating for degradation of a light emitting diode and a method of driving the pixel.

[0006] Furthermore, an object to be solved is to provide a pixel and a method of driving the pixel capable of improving black expression by reducing leakage current, realizing low-frequency driving, and reducing power consumption.

[0007] Technical Solution

[0008] According to an embodiment of the present disclosure, a pixel may include a light-emitting diode, a first capacitor, a first transistor, and a second transistor, wherein the light-emitting diode includes an anode connected to a first node, the first capacitor includes a first electrode connected to the first node and a second electrode connected to a second node, the first transistor includes a gate electrode connected to the second node, a first electrode connected to a third node, and a second electrode connected to a fourth node, and the second transistor includes a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the third node.

[0009] The pixel may further include a third transistor including a gate electrode coupled to the second scan line, a first electrode coupled to the initialization line, and a second electrode coupled to the first node.

[0010] The pixel may further include a fourth transistor including a gate electrode coupled to the emission line, a first electrode coupled to the fourth node, and a second electrode coupled to the first node.

[0011] The pixel may further include a fifth transistor including a gate electrode coupled to the emission line, a first electrode coupled to a first power line, and a second electrode coupled to the third node.

[0012] The pixel may further include a sixth transistor including a gate electrode coupled to a third scan line, a first electrode coupled to the fourth node, and a second electrode coupled to the initialization line.

[0013] The pixel may further include a seventh transistor including a gate electrode coupled to the first scan line, a first electrode coupled to the second node, and a second electrode coupled to the fourth node.

[0014] The pixel may further include a second capacitor including a first electrode coupled to the first power line and a second electrode coupled to the second node.

[0015] The pixel may further include an eighth transistor including a gate electrode coupled to the third scan line, a first electrode coupled to the second node, and a second electrode coupled to the fourth node.

[0016] The pixel may also include a seventh transistor and an eighth transistor, the seventh transistor including a gate electrode connected to the first scan line, a first electrode, and a second electrode connected to the fourth node, and the eighth transistor including a gate electrode connected to the first scan line, a first electrode connected to the first electrode of the seventh transistor, and a second electrode connected to the second node.

[0017] The pixel may further include a second capacitor including a first electrode coupled to the first power line and a second electrode coupled to the second node.

[0018] The pixel may further include a sixth transistor including a gate electrode coupled to the first scan line, a first electrode coupled to the initialization line, and a second electrode coupled to the fourth node.

[0019] The pixel may also include a seventh transistor and an eighth transistor, the seventh transistor including a gate electrode connected to the first scan line, a first electrode connected to the second node, and a second electrode connected to the initialization line, and the eighth transistor including a gate electrode connected to a third scan line, a first electrode connected to the second node, and a second electrode connected to the initialization line.

[0020] The pixel may further include a sixth transistor, a seventh transistor and an eighth transistor, the sixth transistor including a gate electrode connected to a third scan line, a first electrode, and a second electrode connected to the initialization line, the seventh transistor including a gate electrode connected to the first scan line, a first electrode connected to the second node, and a second electrode connected to the first electrode of the sixth transistor, and the eighth transistor including a gate electrode connected to the first scan line, a first electrode connected to the first electrode of the sixth transistor, and a second electrode connected to the fourth node.

[0021] The pixel may further include a second capacitor including a first electrode coupled to the first power line and a second electrode coupled to the second node.

[0022] A driving method for a pixel according to an embodiment of the present disclosure is provided, wherein in the driving method for the pixel, the pixel may include a light emitting diode, a first capacitor, a first transistor, and a second transistor, the light emitting diode includes an anode connected to a first node, the first capacitor includes a first electrode connected to the first node and a second electrode connected to a second node, the first transistor includes a gate electrode connected to the second node, a first electrode connected to a third node, and a second electrode connected to a fourth node, the second transistor includes a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the third node, and the driving method may include: connecting the second node to an initialization line and turning on the second transistor; disconnecting the second node from the initialization line when the second transistor is turned on; turning off the second transistor; and connecting the first node to the initialization line when the second transistor is turned off.

[0023] The pixel may further include a third transistor including a gate electrode coupled to the second scan line, a first electrode coupled to the initialization line, and a second electrode coupled to the first node, and the third transistor may be turned on when the first node is coupled to the initialization line.

[0024] The pixel may further include a fourth transistor and a fifth transistor, the fourth transistor including a gate electrode connected to the emission line, a first electrode connected to the fourth node, and a second electrode connected to the first node, the fifth transistor including a gate electrode connected to the emission line, a first electrode connected to the first power line, and a second electrode connected to the third node, and the driving method may further include: turning off the third transistor; and turning on the fourth transistor and the fifth transistor when the third transistor is turned off.

[0025] A driving method for a pixel according to an embodiment of the present disclosure is provided, wherein in the driving method for the pixel, the pixel may include a light-emitting diode, a first capacitor, a first transistor, and a second transistor, the light-emitting diode includes an anode connected to a first node, the first capacitor includes a first electrode connected to the first node and a second electrode connected to a second node, the first transistor includes a gate electrode connected to the second node, a first electrode connected to a third node, and a second electrode connected to a fourth node, the second transistor includes a gate electrode connected to a first scan line, a first electrode connected to a data line, and a second electrode connected to the third node, and the driving method may include: connecting the second node to an initialization line when the second transistor is turned off; disconnecting the second node from the initialization line; turning on the second transistor when the second node is disconnected from the initialization line; turning off the second transistor; and connecting the first node to the initialization line when the second transistor is turned off.

[0026] The pixel may further include a third transistor including a gate electrode coupled to the second scan line, a first electrode coupled to the initialization line, and a second electrode coupled to the first node, and the third transistor may be turned on when the first node is coupled to the initialization line.

[0027] The pixel may further include a fourth transistor and a fifth transistor, the fourth transistor including a gate electrode connected to the emission line, a first electrode connected to the fourth node, and a second electrode connected to the first node, the fifth transistor including a gate electrode connected to the emission line, a first electrode connected to the first power line, and a second electrode connected to the third node, and the driving method may further include: turning off the third transistor; and turning on the fourth transistor and the fifth transistor when the third transistor is turned off.

[0028] Beneficial Effects

[0029] The pixel and the method of driving the pixel according to the present disclosure can self-compensate for the degradation of the light emitting diode.

[0030] Furthermore, the pixel and the method of driving the pixel according to the present disclosure can improve black expression, realize low-frequency driving, and reduce power consumption by reducing leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0032] Figure 2 is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0033] Figure 3 is a diagram showing a pixel according to the first embodiment of the present disclosure.

[0034] Figures 4 to 11 It is used to describe the drive Figure 3 FIG. 4 is an example of a pixel method.

[0035] Fig.12 is a diagram showing a pixel according to a second embodiment of the present disclosure.

[0036] Fig.13 is a diagram showing a pixel according to a third embodiment of the present disclosure.

[0037] Fig.14 is a diagram showing a pixel according to a fourth embodiment of the present disclosure.

[0038] Fig.15 is a diagram for describing a driving method according to an embodiment of the present disclosure.

[0039] Fig.16 is a diagram showing a pixel according to a fifth embodiment of the present disclosure.

[0040] Fig.17 is a diagram showing a pixel according to a sixth embodiment of the present disclosure.

[0041] Fig.18 is a diagram showing a pixel according to a seventh embodiment of the present disclosure.

[0042] Fig.19 is a diagram showing a pixel according to an eighth embodiment of the present disclosure.

[0043] Fig. 20 is a diagram showing a pixel according to a ninth embodiment of the present disclosure.

[0044] Fig.21 is a diagram illustrating a pixel according to a tenth embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in various forms and is not limited to the embodiments described herein.

[0046] In the accompanying drawings, parts not related to the present disclosure will be omitted to explain the present disclosure more clearly. Reference should be made to the accompanying drawings, in which similar reference numerals are used throughout different drawings to refer to similar parts. Therefore, the aforementioned reference numerals may be used in other drawings.

[0047] For reference, for the sake of explanation, the size of each component and the thickness of the line showing the component are arbitrarily represented, and the present disclosure is not limited to those shown in the drawings. In the drawings, the thickness of the components may be exaggerated to clearly show several layers and regions.

[0048] Figure 1 is a diagram showing a display device according to an embodiment of the present disclosure, and Figure 2 is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0049] Reference Figure 1 The display device 10 according to an embodiment of the present disclosure may include a timing controller 11 , a data driver 12 , a scan driver 13 , an emission driver 14 , and a pixel circuit 15 .

[0050] The timing controller 11 may receive grayscale values ​​and control signals for an image frame from an external processor. The timing controller 11 may render grayscale values ​​in response to the specifications of the display device 10. For example, the external processor may provide a red grayscale value, a green grayscale value, and a blue grayscale value for each unit point. However, for example, in the case where the pixel circuit 15 has a pentile structure, since adjacent unit points may share pixels, the pixels may not correspond one-to-one to the corresponding grayscale values. In this case, it is necessary to render grayscale values. If the pixels correspond one-to-one to the corresponding grayscale values, the operation of rendering grayscale values ​​may not be required. Rendered or unrendered grayscale values ​​may be provided to the data driver 12. In addition, the timing controller 11 may provide control signals suitable for the specifications of the corresponding components to the data driver 12, the scan driver 13, the emission driver 14, etc. to represent the image frame.

[0051] The data driver 12 may use the grayscale value and the control signal to generate a data voltage to be supplied to the data lines D1, D2, D3, ..., and Dn. For example, the data driver 12 may sample the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data lines D1 to Dn on a pixel row basis. Here, n may be an integer greater than 0.

[0052] The scan driver 13 may receive a clock signal, a scan start signal, etc. from the timing controller 11 and generate a scan signal to be supplied to the scan lines S1, S2, S3, . . . , and Sm. Here, m may be an integer greater than 0.

[0053] Further references Figure 2 , the scan lines S1 to Sm may include first scan lines GW1, GW2, . . . , and GWm, second scan lines GB1, GB2, . . . , and GBm, and third scan lines GI1, GI2, . . . , and GIm.

[0054] In an embodiment, the scan driver 13 may include a first scan driver 131 configured to sequentially supply first scan signals each having an on-level pulse to the first scan lines GW1, GW2, ..., and GWm, a second scan driver 132 configured to sequentially supply second scan signals each having an on-level pulse to the second scan lines GB1, GB2, ..., and GBm, and a third scan driver 133 configured to sequentially supply third scan signals each having an on-level pulse to the third scan lines GI1, GI2, ..., and GIm. Each of the first scan driver 131, the second scan driver 132, and the third scan driver 133 may include a scan stage circuit configured in the form of a shift register. The first scan driver 131, the second scan driver 132, and the third scan driver 133 may each generate a scan signal by sequentially transmitting a scan start signal in the form of an on-level pulse to a next scan stage circuit under the control of a clock signal.

[0055] In an embodiment, at least some of the first scan driver 131, the second scan driver 132, and the third scan driver 133 may be integrally formed depending on a method of driving pixels. Figure 4 In the driving method of , when the on-level pulses of the second scanning signal and the third scanning signal are equal in length and only different in phase, the second scanning driver 132 and the third scanning driver 133 can be formed integrally. Fig.15 In the driving method, when the on-level pulses of the first scan signal to the third scan signal are equal in length and only different in phase, the first scan driver 131, the second scan driver 132 and the third scan driver 133 may be integrally formed.

[0056] The emission driver 14 may receive a clock signal, an emission stop signal, etc. from the timing controller 11, and generate an emission signal to be provided to the emission lines E1, E2, E3, ..., and Eo. For example, the emission driver 14 may sequentially provide emission signals each having an off-level pulse to the emission lines E1 to Eo. For example, each emission stage circuit of the emission driver 14 may be made in the form of a shift register, and may generate an emission signal in such a manner that an emission stop signal in the form of an off-level pulse is sequentially transmitted to the next emission stage circuit under the control of a clock signal. o may be an integer greater than 0.

[0057] The pixel circuit 15 includes pixels. Each pixel PXij may be connected to a corresponding data line, a corresponding scan line, and a corresponding emission line. In addition, the pixel PXij may be connected to a common first power line and a second power line. Here, i and j may be integers greater than 0. The pixel PXij may refer to a pixel whose scan transistor is connected to the i-th scan line and the j-th data line.

[0058] Figure 3 is a diagram showing a pixel according to the first embodiment of the present disclosure.

[0059] Reference Figure 3 , the pixel PXija according to the first embodiment of the present disclosure includes transistors T1a to T7a, capacitors C1a and C2a, and a light emitting diode LDa.

[0060] In this embodiment, although the transistor is shown as a P-type transistor (e.g., PMOS), those skilled in the art can form a pixel circuit with the same function by using an N-type transistor (e.g., NMOS). In addition, those skilled in the art can form a pixel circuit with the same function by combining a P-type transistor and an N-type transistor. In the following, it is assumed that the transistor is formed by a P-type transistor.

[0061] The light emitting diode LDa may include an anode connected to the first node N1a, and a cathode connected to the second power line ELVSSL. The light emitting diode LDa may be an organic light emitting diode, an inorganic light emitting diode, a quantum dot light emitting diode, etc. In addition, in the present embodiment, it is shown that the pixel PXija includes one light emitting diode LDa, but in another embodiment, the pixel PXija may include two or more light emitting diodes LDa. Two or more light emitting diodes LDa may be connected in parallel or in series with each other. In the following embodiments, it is assumed that the pixel includes one light emitting diode.

[0062] The first capacitor C1a may include a first electrode coupled to the first node N1a, and a second electrode coupled to the second node N2a.

[0063] The first transistor T1a may include a gate electrode coupled to the second node N2a, a first electrode coupled to the third node N3a, and a second electrode coupled to the fourth node N4a. The first transistor T1a may be referred to as a "driving transistor".

[0064] The second transistor T2a may include a gate electrode coupled to the first scan line GWi, a first electrode coupled to the data line Dj, and a second electrode coupled to the third node N3a. The second transistor T2a may be referred to as a "scan transistor" or a "switching transistor".

[0065] The third transistor T3a may include a gate electrode coupled to the second scan line GBi, a first electrode coupled to the initialization line INTL, and a second electrode coupled to the first node N1a. The third transistor T3a may be referred to as an "anode initialization transistor".

[0066] The fourth transistor T4a may include a gate electrode coupled to the emission line Ei, a first electrode coupled to the fourth node N4a, and a second electrode coupled to the first node N1a. The fourth transistor T4a may be referred to as an "emission transistor".

[0067] The fifth transistor T5a may include a gate electrode coupled to the emission line Ei, a first electrode coupled to the first power line ELVDDL, and a second electrode coupled to the third node N3a. The fifth transistor T5a may be referred to as an "emission transistor". Figure 3 2 shows that the same emission line Ei is coupled to the gate electrode of the fourth transistor T4a and the gate electrode of the fifth transistor T5a. However, according to an embodiment, different emission lines may be coupled to the gate electrode of the fourth transistor T4a and the gate electrode of the fifth transistor T5a.

[0068] The sixth transistor T6a may include a gate electrode coupled to the third scan line GIi, a first electrode coupled to the fourth node N4a, and a second electrode coupled to the initialization line INTL. The sixth transistor T6a may be referred to as a "gate initialization transistor."

[0069] The seventh transistor T7a may include a gate electrode coupled to the first scan line GWi, a first electrode coupled to the second node N2a, and a second electrode coupled to the fourth node N4a. The seventh transistor T7a may be referred to as a "diode-connected transistor."

[0070] The second capacitor C2a may include a first electrode coupled to the first power line ELVDDL, and a second electrode coupled to the second node N2a.

[0071] The first power line ELVDDL may be applied with a first power voltage. The second power line ELVSSL may be applied with a second power voltage. The magnitude of the first power voltage and the magnitude of the second power voltage may vary depending on the driving method. For example, in the emission period P14 of the pixel PXija (see Fig.10 ), the magnitude of the first power supply voltage may be greater than the magnitude of the second power supply voltage. In the following, repeated description of the magnitudes of the first power supply voltage and the second power supply voltage will be omitted.

[0072] The initialization line INTL may be applied with an initialization voltage. The magnitude of the initialization voltage may vary depending on the driving method. For example, the gate initialization period P11 of the pixel PXija (see Figure 4 ) may be small enough to allow the first transistor T1a to be in the threshold voltage compensation period P12 of the pixel PXija (see Figure 6 ) is turned on in at least a portion of the pixel PXija. Figure 4) may be smaller than the threshold voltage compensation period P12 of the pixel PXija (see Figure 6 ) in the data voltage DTij (see Figure 6 ) size. In addition, for example, the anode initialization period P13 of the pixel PXija (see Figure 8 ) may be equal to or less than the second power supply voltage. On the other hand, the anode initialization period P13 of the pixel PXija (see Figure 8 ) may be greater than the second power supply voltage. However, in this case, the initialization voltage may be less than the sum of the emission threshold voltage of the light emitting diode LDa and the second power supply voltage. Hereinafter, repeated description of the initialization voltage will be omitted.

[0073] Figures 4 to 11 It is used to describe the drive Figure 3 FIG. 4 is an example of a pixel method.

[0074] Reference Figure 4 and Figure 5 , in the first period P11, a first scan signal having an on level (e.g., a logic low level) may be applied to the first scan line GWi. In this case, a third scan signal having an on level may be applied to the third scan line GIi. In this case, a second scan signal having an off level (e.g., a logic high level) may be applied to the second scan line GBi. In this case, an emission signal having an off level may be applied to the emission line Ei. In this case, a data voltage DT(i-1)j for a previous pixel row may be applied to the data line Dj. The previous pixel row may mean a pixel in which the i-1th first scan line is coupled to the gate electrode of the scan transistor.

[0075] Therefore, in the first period P11 , the transistors T1 a , T2 a , T6 a , and T7 a may be turned on, and the transistors T3 a , T4 a , and T5 a may be turned off.

[0076] The data line Dj may be coupled to the second node N2a through transistors T2a, T1a, and T7a. In addition, the initialization line INTL may be coupled to the second node N2a through transistors T6a and T7a. In this case, due to the difference in load between the data line Dj and the initialization line INTL, the voltage of the second node N2a may become the initialization voltage. The first period P11 may be referred to as a gate initialization period.

[0077] Reference Figure 6 and Figure 7, in the second period P12, a first scan signal with an on level may be applied to the first scan line GWi. In this case, a third scan signal with an off level may be applied to the third scan line GIi. In this case, a second scan signal with an off level may be applied to the second scan line GBi. In this case, an emission signal with an off level may be applied to the emission line Ei. In this case, a data voltage DTij for the pixel PXija may be applied to the data line Dj.

[0078] Therefore, in the second period P12, the transistors T1a, T2a, and T7a may be turned on, and the transistors T3a, T4a, T5a, and T6a may be turned off.

[0079] The data line Dj may be coupled to the second node N2a through transistors T2a, T1a, and T7a. Therefore, the voltage of the second node N2a may become a compensation voltage obtained by subtracting the threshold voltage of the first transistor T1a from the data voltage DTij (refer to Equation 1).

[0080] [Equation 1]

[0081] VN2a=DTij-Vtrth

[0082] Here, VN2a denotes a voltage of the second node N2a, DTij denotes a data voltage DTij, and Vtrth denotes a threshold voltage of the first transistor T1a.

[0083] Due to process deviation or degradation, the threshold voltages of the first transistors T1a of the pixels PXija may be different from each other. Through the second period P12, the threshold voltages of the first transistors T1a different from each other may be compensated individually. The second period P12 may be referred to as a threshold voltage compensation period.

[0084] In the second period P12, the voltage of the first node N1a may be as follows (refer to Equation 2).

[0085] [Equation 2]

[0086] VN1a=ELVSS+Vldth

[0087] Here, VN1a denotes a voltage of the first node N1a, ELVSS denotes a voltage of the second power line ELVSSL, and Vldth denotes an emission threshold voltage of the light emitting diode LDa.

[0088] At this time, the light emitting diode LDa is in a non-emission state because it is not supplied with a driving current, but the light emitting diode LDa is charged with an emission threshold voltage due to a driving current supplied from a previous frame.

[0089] Due to process deviation or degradation, the emission threshold voltages of the light emitting diodes LDa of the pixels PXija may be different from each other. After charging the emission threshold voltage, the light emitting diodes LDa may emit light.

[0090] Reference Figure 8 and Fig. 9 , in the third period P13, a first scan signal with an off level may be applied to the first scan line GWi. In this case, a third scan signal with an off level may be applied to the third scan line GIi. In this case, a second scan signal with an on level may be applied to the second scan line GBi. In this case, an emission signal with an off level may be applied to the emission line Ei. In this case, a data voltage DT(i+1)j for the next pixel row may be applied to the data line Dj. The next pixel row may mean a pixel where the i+1th first scan line is coupled to the gate electrode of the scan transistor.

[0091] Therefore, in the third period P13 , the transistors T1 a and T3 a may be turned on, and the transistors T2 a , T4 a , T5 a , T6 a , and T7 a may be turned off.

[0092] Since the first node N1a is coupled to the initialization line INTL through the third transistor T3a, the voltage of the first node N1a becomes the initialization voltage. In an embodiment, if the initialization voltage has the same magnitude as the second power supply voltage, the voltage charged in the light emitting diode LDa is initialized to 0V. In an embodiment, if the initialization voltage is greater than the second power supply voltage, the light emitting diode LDa may be pre-charged with a predetermined voltage. In an embodiment, if the initialization voltage is less than the second power supply voltage, a reverse bias voltage may be applied to the light emitting diode LDa, thereby extending the service life of the light emitting diode LDa. The third period P13 may be referred to as an anode initialization period.

[0093] Here, the voltage of the first node N1a changes as follows (refer to Equation 3).

[0094] [Equation 3]

[0095] dVN1a=VINT-(ELVSS+Vldth)

[0096] Here, dVN1a denotes a voltage variation of the first node N1a, VINT denotes an initialization voltage of the initialization line INTL, ELVSS denotes a voltage of the second power line ELVSSL, and Vldth denotes an emission threshold voltage of the light emitting diode LDa.

[0097] In this case, the voltage of the second node N2a is changed based on the voltage change of the first node N1a and the capacitance ratio of the first capacitor C1a and the second capacitor C2a (refer to Equation 4).

[0098] [Equation 4]

[0099]

[0100] Here, dVN2a represents a voltage change of the second node N2a, CC1a represents a capacitance of the first capacitor C1a, CC2a represents a capacitance of the second capacitor C2a, and dVN1a represents a voltage change of the first node N1a.

[0101] Therefore, the voltage of the second node N2a can be expressed by the following Equation 5.

[0102] [Equation 5]

[0103] VN2a=DTij-Vtrth+dVN2a

[0104] Here, VN2a represents the voltage of the second node N2a, DTij represents the data voltage DTij, Vtrth represents the threshold voltage of the first transistor T1a, and dVN2a represents the voltage variation of the second node N2a.

[0105] Reference Fig.10 and Fig.11 , in the fourth period P14, the first scan signal with an off level may be applied to the first scan line GWi. In this case, the third scan signal with an off level may be applied to the third scan line GIi. In this case, the second scan signal with an off level may be applied to the second scan line GBi. In this case, the emission signal with an on level may be applied to the emission line Ei.

[0106] Therefore, in the fourth period P14, the transistors T1a, T4a, and T5a may be turned on, and the transistors T2a, T3a, T6a, and T7a may be turned off.

[0107] Therefore, a path in which the driving current flows in the order of the first power line ELVDDL, the fifth transistor T5a, the first transistor T1a, the fourth transistor T4a, the light emitting diode LDa and the second power line ELVSSL can be formed. The light emitting diode LDa can emit light according to the driving current. The fourth period P14 can be referred to as an emission period.

[0108] The magnitude of the driving current may be determined according to a voltage difference between the second node N2a and the third node N3a. The voltage of the third node N3a may be substantially the same as the first power supply voltage.

[0109] [Equation 6]

[0110]

[0111] Here, Ids represents a driving current flowing between a drain electrode and a source electrode of the first transistor T1a, up represents the mobility of the first transistor T1a, Cox represents a capacitance formed by a channel, an insulating layer, and a gate electrode of the first transistor T1a, W represents a width of a channel of the first transistor T1a, L represents a length of the channel of the first transistor T1a, ELVDD represents a first power supply voltage, VN2a represents a voltage of a second node N2a, and Vtrth represents a threshold voltage of the first transistor T1a.

[0112] With further reference to Equation 4 and Equation 5, Equation 6 may be expressed as in Equation 7 below.

[0113] [Equation 7]

[0114]

[0115] Since all variables and constants in Equation 7 have been described, their description will not be repeated.

[0116] As the light emitting diode LDa degrades, the emission threshold voltage Vldth increases. In other words, in order for the light emitting diode LDa after degradation to emit light with the same brightness as the light emitting diode LDa before degradation, the light emitting diode LDa after degradation requires a larger driving current than the light emitting diode LDa before degradation. Referring to Equation 7, it can be seen that the driving current Ids increases as the emission threshold voltage Vldth increases. If necessary, the increase in the driving current Ids can be adjusted according to the pixel PXija by adjusting the capacitance ratio of the first capacitor C1a and the second capacitor C2a. Therefore, according to this embodiment, the degradation of the light emitting diode LDa can be compensated by the pixel PXija itself.

[0117] In addition, the pixel PXija includes two transistors T7a and T6a located in the first leakage current path from the second node N2a to the initialization line INTL. The pixel PXija has the advantage of effectively reducing the first leakage current while maintaining the same number of transistors as the conventional 7T1C pixel. When the leakage current is reduced, the black performance can be enhanced, low-frequency driving can be achieved, and power consumption can be reduced.

[0118] Fig.12 is a diagram showing a pixel according to a second embodiment of the present disclosure.

[0119] Reference Fig.12The pixel PXijb according to the second embodiment of the present disclosure includes transistors T1b, T2b, T3b, T4b, T5b, T6b, T7b and T8b, capacitors C1b and C2b, and a light emitting diode LDb. The first transistor T1b has a first electrode coupled to a third node N3b and a second electrode coupled to the light emitting diode LDb at the first node N1b through a fourth transistor T4b.

[0120] Since the pixel PXijb has the same Figure 3 The pixels PXija are substantially the same components, so their repeated description will be omitted.

[0121] The seventh transistor T7b may include a gate electrode coupled to the first scan line GWi, a first electrode, and a second electrode coupled to the fourth node N4b.

[0122] The eighth transistor T8b may include a gate electrode coupled to the first scan line GWi, a first electrode coupled to the first electrode of the seventh transistor T7b, and a second electrode coupled to the second node N2b.

[0123] Since the pixel PXijb includes the three transistors T6b, T7b, and T8b located in the first leakage current path from the second node N2b to the initialization line INTL, the first leakage current path can be effectively blocked.

[0124] Fig.13 is a diagram showing a pixel according to a third embodiment of the present disclosure.

[0125] Reference Fig.13 The pixel PXijc according to the third embodiment of the present disclosure includes transistors T1c, T2c, T3c, T4c, T5c, T6c, T7c and T8c, capacitors C1c and C2c, and a light emitting diode LDc. The first transistor T1c has a first electrode coupled to a third node N3c and a second electrode coupled to the light emitting diode LDc at the first node N1c through a fourth transistor T4c.

[0126] Since the pixel PXijc has the same Figure 3 The pixels PXija are substantially the same components, so their repeated description will be omitted.

[0127] The sixth transistor T6c may include a gate electrode coupled to the third scan line GIi, a first electrode, and a second electrode coupled to the initialization line INTL.

[0128] The seventh transistor T7c may include a gate electrode coupled to the first scan line GWi, a first electrode coupled to the second node N2c, and a second electrode coupled to the first electrode of the sixth transistor T6c.

[0129] The eighth transistor T8c may include a gate electrode coupled to the first scan line GWi, a first electrode coupled to the first electrode of the sixth transistor T6c, and a second electrode coupled to the fourth node N4c.

[0130] Since the pixel PXijc includes the three transistors T4c, T7c, and T8c located in the second leakage current path from the second node N2c to the second power line ELVSSL, the second leakage current path can be effectively blocked.

[0131] Fig.14 is a diagram showing a pixel according to a fourth embodiment of the present disclosure, and Fig.15 is a diagram for describing a driving method according to an embodiment of the present disclosure.

[0132] Reference Fig.14 The pixel PXijd according to the fourth embodiment of the present disclosure includes transistors T1d, T2d, T3d, T4d, T5d, T6d, T7d and T8d, capacitors C1d and C2d, and a light emitting diode LDd. The first transistor T1d has a first electrode coupled to the third node N3d and a second electrode coupled to the light emitting diode LDd at the first node N1d through the fourth transistor T4d.

[0133] Since the pixel PXijd has the same Figure 3 The pixels PXija are substantially the same components, so their repeated description will be omitted.

[0134] The eighth transistor T8d may include a gate electrode coupled to the third scan line GIi, a first electrode coupled to the second node N2d, and a second electrode coupled to the fourth node N4d.

[0135] The pixel PXijd can be based on Fig.15 According to the driving method of Fig.15 In the driving method, the on-level pulses of the first scanning signal to the third scanning signal may have the same length and different phases. Therefore, as described above, since the first scanning driver 131, the second scanning driver 132 and the third scanning driver 133 may be integrally formed, the area occupied by the scanning driver 13 and its construction cost may be reduced.

[0136] Fig.15 The first period P21, the second period P22, the third period P23 and the fourth period P24 correspond to Figure 4 , Figure 6 , Figure 8 and Fig.10 In addition to the first scan signal applied to the first scan line GWi having an off level in the first period P21, Fig.15 The driving method and Figures 4 to 11 The driving method is essentially the same. Therefore, Fig.15 Repeated description of the driving method.

[0137] For reference, the pixel PXijd can be Figures 4 to 11 Driven by the driving method.

[0138] Fig.16 is a diagram showing a pixel according to a fifth embodiment of the present disclosure.

[0139] Reference Fig.16 The pixel PXije according to the fifth embodiment of the present disclosure includes transistors T1e, T2e, T3e, T4e, T5e, T6e, T7e and T8e, a first capacitor C1e and a light emitting diode LDe. The first transistor T1e has a first electrode coupled to a third node N3e and a second electrode coupled to the light emitting diode LDe at the first node N1e through a fourth transistor T4e.

[0140] Since the pixel PXije has the same Figure 3 The pixels PXija are substantially the same components, so their repeated description will be omitted.

[0141] The seventh transistor T7e may include a gate electrode coupled to the first scan line GWi, a first electrode, and a second electrode coupled to the fourth node N4e.

[0142] The eighth transistor T8e may include a gate electrode coupled to the first scan line GWi, a first electrode coupled to the first electrode of the seventh transistor T7e, and a second electrode coupled to the second node N2e.

[0143] Since the pixel PXije includes the three transistors T6e, T7e and T8e located in the first leakage current path from the second node N2e to the initialization line INTL, the first leakage current path can be effectively blocked.

[0144] In addition, the pixel PXije does not include a second capacitor. The first capacitor C1e performs a voltage holding function of the second node N2e. Therefore, since one capacitor can be removed from an existing pixel, the pixel PXije has an advantage in that the area occupied by the pixel PXije can be reduced compared to other embodiments.

[0145] Fig.17 is a diagram showing a pixel according to a sixth embodiment of the present disclosure.

[0146] Reference Fig.17 The pixel PXijf according to the sixth embodiment of the present disclosure includes transistors T1f, T2f, T3f, T4f, T5f, T6f, T7f and T8f, a first capacitor C1f and a light emitting diode LDf. The first transistor T1f has a first electrode coupled to a third node N3f and a second electrode coupled to the light emitting diode LDf at the first node N1f through a fourth transistor T4f.

[0147] Since the pixel PXijf has the same Figure 3 The pixels PXija are substantially the same components, so their repeated description will be omitted.

[0148] The sixth transistor T6f may include a gate electrode coupled to the first scan line GWi, a first electrode coupled to the initialization line INTL, and a second electrode coupled to the fourth node N4f.

[0149] The seventh transistor T7f may include a gate electrode coupled to the first scan line GWi, a first electrode coupled to the second node N2f, and a second electrode coupled to the initialization line INTL.

[0150] The eighth transistor T8f may include a gate electrode coupled to the third scan line GIi, a first electrode coupled to the second node N2f, and a second electrode coupled to the initialization line INTL.

[0151] Since the pixel PXijf includes three transistors T4f, T6f, T7f or T8f located in the second leakage current path from the second node N2f to the second power line ELVSSL, the second leakage current path can be effectively blocked.

[0152] In addition, the pixel PXijf does not include a second capacitor. The first capacitor C1f performs a voltage holding function of the second node N2f. Therefore, since one capacitor can be removed from an existing pixel, the pixel PXijf has an advantage in that the area occupied by the pixel PXijf can be reduced compared to other embodiments.

[0153] In addition, the pixel PXijf can be based on Fig.15 According to the driving method of Fig.15In the driving method, the on-level pulses of the first scanning signal to the third scanning signal may have the same length and different phases. Therefore, as described above, since the first scanning driver 131, the second scanning driver 132 and the third scanning driver 133 may be integrally formed, the area occupied by the scanning driver 13 and its construction cost may be reduced.

[0154] Fig.18 is a diagram showing a pixel according to a seventh embodiment of the present disclosure.

[0155] Fig.18 The pixel PXija' is shaped so that the second capacitor C2a is Figure 3 The pixels PXija excludes.

[0156] Even if the pixel PXija' does not include the second capacitor, the first capacitor C1a performs the voltage holding function of the second node N2a. Therefore, since one capacitor can be removed from the existing pixel, the pixel PXija' is advantageous in that the area occupied by the pixel PXija' can be reduced compared to other embodiments.

[0157] Fig.19 is a diagram showing a pixel according to an eighth embodiment of the present disclosure.

[0158] Fig.19 The pixel PXijc' is shaped so that the second capacitor C2c is Fig.13 The pixels PXijc are excluded.

[0159] Even if the pixel PXijc' does not include the second capacitor, the first capacitor C1c performs a voltage holding function of the second node N2c. Therefore, since one capacitor can be removed from an existing pixel, the pixel PXijc' is advantageous in that an area occupied by the pixel PXijc' can be reduced compared to other embodiments.

[0160] Fig. 20 is a diagram showing a pixel according to a ninth embodiment of the present disclosure.

[0161] Fig. 20 The pixel PXijd' is shaped so that the second capacitor C2d is Fig.14 The pixels PXijd are excluded.

[0162] Even if the pixel PXijd' does not include the second capacitor, the first capacitor C1d performs a voltage holding function of the second node N2d. Therefore, since one capacitor can be removed from an existing pixel, the pixel PXijd' is advantageous in that an area occupied by the pixel PXijd' can be reduced compared to other embodiments.

[0163] Fig.21is a diagram illustrating a pixel according to a tenth embodiment of the present disclosure.

[0164] Fig.21 The pixel PXijf' is shaped so that the second capacitor C2f' is added to Fig.17 Pixel PXijf.

[0165] When the case where the second capacitor C2f' is added is compared with the case where only the first capacitor C1f is provided, the former can more firmly (without distortion) maintain the compensation voltage of the second node N2f recorded in the threshold voltage compensation period.

[0166] The detailed description of the present disclosure described with reference to the accompanying drawings is illustrative only, which is only used for the purpose of describing the present disclosure, and is not used to limit the meaning or scope of the present disclosure as defined by the attached claims. Therefore, it will be understood by those skilled in the art that various modifications and equivalents thereof are possible. Accordingly, the limits and scope of the present disclosure should be determined by the technical spirit of the attached claims.

Claims

1. A pixel comprising: a light emitting diode including an anode directly coupled to the first node; a first capacitor including a first electrode directly coupled to the first node and a second electrode coupled to a second node; a first transistor including a gate electrode coupled to the second node, a first electrode coupled to a third node, and a second electrode coupled to a fourth node; a second transistor including a gate electrode coupled to the first scan line, a first electrode coupled to the data line, and a second electrode coupled to the third node; a sixth transistor including a gate electrode coupled to a third scan line, a first electrode coupled to the fourth node, and a second electrode coupled to an initialization line; a seventh transistor including a gate electrode coupled to the first scan line, a first electrode coupled to the second node, and a second electrode coupled to the fourth node; as well as A second capacitor includes a first electrode coupled to the first power line and a second electrode coupled to the second node.

2. The pixel according to claim 1, further comprising: A third transistor includes a gate electrode coupled to the second scan line, a first electrode coupled to the initialization line, and a second electrode coupled to the first node.

3. The pixel according to claim 2, further comprising: A fourth transistor includes a gate electrode coupled to the emission line, a first electrode coupled to the fourth node, and a second electrode coupled to the first node.

4. The pixel according to claim 3, further comprising: A fifth transistor includes a gate electrode coupled to the emission line, a first electrode coupled to the first power line, and a second electrode coupled to the third node.

5. The pixel according to claim 1, further comprising: An eighth transistor includes a gate electrode coupled to the third scan line, a first electrode coupled to the second node, and a second electrode coupled to the fourth node.

6. The pixel according to claim 1, further comprising: An eighth transistor is coupled between the first electrode of the seventh transistor and the second node, and includes a gate electrode coupled to the first scan line.

7. The pixel according to claim 1, further comprising: An eighth transistor is coupled between the first electrode of the sixth transistor and the fourth node, the eighth transistor including a gate electrode coupled to the first scan line.

8. A method for driving a pixel, wherein: The pixels include: a light emitting diode including an anode coupled to the first node; a first capacitor including a first electrode coupled to the first node and a second electrode coupled to a second node; a first transistor including a gate electrode coupled to the second node, a first electrode coupled to a third node, and a second electrode coupled to a fourth node; a second transistor including a gate electrode coupled to the first scan line, a first electrode coupled to the data line, and a second electrode coupled to the third node; and a second capacitor including a first electrode coupled to the first power line and a second electrode coupled to the second node, and The driving method comprises: coupling the second node to an initialization line and turning on the second transistor; disconnecting the second node from the initialization line when the second transistor is turned on; turning off the second transistor; and The first node is coupled to the initialization line in a state where the second transistor is turned off.

9. The driving method according to claim 8, wherein: The pixel further includes a third transistor including a gate electrode coupled to the second scan line, a first electrode coupled to the initialization line, and a second electrode coupled to the first node, and When the first node is coupled to the initialization line, the third transistor is turned on.

10. The driving method according to claim 9, wherein: The pixel also includes: a fourth transistor including a gate electrode coupled to an emission line, a first electrode coupled to the fourth node, and a second electrode coupled to the first node; and a fifth transistor including a gate electrode coupled to the emission line, a first electrode coupled to the first power line, and a second electrode coupled to the third node, and The driving method further includes: turning off the third transistor; and The fourth transistor and the fifth transistor are turned on in a state where the third transistor is turned off.

11. A method for driving a pixel, wherein: The pixels include: a light emitting diode including an anode coupled to the first node; a first capacitor including a first electrode coupled to the first node and a second electrode coupled to a second node; a first transistor including a gate electrode coupled to the second node, a first electrode coupled to a third node, and a second electrode coupled to a fourth node; a second transistor including a gate electrode coupled to the first scan line, a first electrode coupled to the data line, and a second electrode coupled to the third node; and a second capacitor including a first electrode coupled to the first power line and a second electrode coupled to the second node, and The driving method comprises: connecting the second node to an initialization line when the second transistor is turned off; disconnecting the second node from the initialization line; Turning on the second transistor in a state where the second node is disconnected from the initialization line; turning off the second transistor; and The first node is coupled to the initialization line in a state where the second transistor is turned off.

12. The driving method according to claim 11, wherein: The pixel further includes a third transistor including a gate electrode coupled to the second scan line, a first electrode coupled to the initialization line, and a second electrode coupled to the first node, and When the first node is coupled to the initialization line, the third transistor is turned on.

13. The driving method according to claim 12, wherein: The pixel also includes: a fourth transistor including a gate electrode coupled to an emission line, a first electrode coupled to the fourth node, and a second electrode coupled to the first node; and a fifth transistor including a gate electrode coupled to the emission line, a first electrode coupled to the first power line, and a second electrode coupled to the third node, and The driving method further includes: turning off the third transistor; and The fourth transistor and the fifth transistor are turned on in a state where the third transistor is turned off.

14. A pixel comprising: a light emitting diode including an anode directly coupled to the first node; a first capacitor including a first electrode directly coupled to the first node and a second electrode coupled to a second node; a first transistor including a gate electrode coupled to the second node, a first electrode coupled to a third node, and a second electrode coupled to a fourth node; a second transistor including a gate electrode coupled to the first scan line, a first electrode coupled to the data line, and a second electrode coupled to the third node; a third transistor including a gate electrode coupled to the second scan line, a first electrode coupled to the initialization line, and a second electrode coupled to the first node; a fourth transistor including a gate electrode coupled to the emission line, a first electrode coupled to the fourth node, and a second electrode coupled to the first node; a fifth transistor including a gate electrode coupled to the emission line, a first electrode coupled to the first power line, and a second electrode coupled to the third node; a sixth transistor including a gate electrode coupled to a third scan line, a first electrode coupled to the fourth node, and a second electrode coupled to the initialization line; as well as A seventh transistor includes a gate electrode coupled to the first scan line, a first electrode coupled to the second node, and a second electrode coupled to the fourth node.

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