Silicon nitride circuit substrate and electronic component module

Abstract

The present invention provides a silicon nitride circuit substrate, which comprises a silicon nitride substrate, a first copper layer provided on one surface of the silicon nitride substrate, and a second copper layer provided on the other surface of the silicon nitride substrate, wherein the fracture toughness value Kc of the silicon nitride substrate is 5.0 MPa·m 0.5 Above, 10.0MPa·m 0.5 Hereinafter, the linear expansion coefficient of the silicon nitride substrate is denoted as α B ( / °C), the Young's modulus of the silicon nitride substrate is set to E B (GPa), the linear expansion coefficient of the first copper layer is α A ( / °C), the linear expansion coefficient of the second copper layer is α C ( / °C), the thermal shock parameter HS1 and the thermal shock parameter HS2 are each 1.30 GPa or more and 2.30 GPa or less.

Description

Technical Field

[0001] The present invention relates to a silicon nitride circuit substrate and an electronic component module. Background Art

[0002] As circuit substrates used in power modules, ceramic substrates such as aluminum oxide, beryllium oxide, silicon nitride, and aluminum nitride are used from the perspectives of thermal conductivity, cost, and safety. These ceramic substrates are used as circuit substrates by joining metal circuit layers and heat dissipation layers such as copper or aluminum. Compared with metal substrates with resin substrates and resin layers as insulating materials, the above-mentioned ceramic substrates have excellent insulation and heat dissipation properties, and are therefore used as substrates for mounting electronic components with high heat dissipation properties.

[0003] In power module applications such as elevators, vehicles, and hybrid vehicles, the following ceramic circuit substrate is used: a metal circuit board is bonded to the surface of the ceramic substrate with solder, and then a semiconductor element is mounted at a predetermined position on the metal circuit board. In recent years, with the high integration, high frequency, and high output of semiconductor elements, the heat generated from semiconductor elements has increased. In response to this, ceramic substrates such as aluminum nitride sintered bodies and silicon nitride sintered bodies with high thermal conductivity are used. Among them, silicon nitride substrates with high mechanical reliability, excellent mechanical strength, and toughness are particularly sought after as ceramic substrates for mounting electronic components.

[0004] In addition, in electronic component modules, etc., thermal stress is repeatedly applied to the ceramic circuit substrate. Therefore, if the ceramic substrate cannot withstand the thermal stress, micro cracks will appear in the ceramic substrate, or when the heat load cycle is continuously applied in a state where the micro cracks have appeared, the metal circuit layer will peel off from the ceramic substrate, resulting in poor bonding strength or poor thermal resistance, and there is a problem of reduced operational reliability as an electronic device.

[0005] Therefore, for example, Patent Document 1 describes that the fracture toughness value of a silicon nitride substrate is set to 6.5 MPa·m 1 / 2 The invention described in Patent Document 1 discloses that a three-point bending strength of 500 MPa or more and a fracture toughness value of 6.5 MPa·m 1 / 2 The above silicon nitride substrate can suppress the occurrence of cracks due to thermal stress.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2002-201075

[0009] However, in electronic component modules, etc., high output and high integration are continuously developed, and the thermal stress repeatedly applied to the ceramic circuit substrate tends to increase further. According to the previous technology, the ceramic substrate cannot withstand the thermal stress, for example, micro cracks are generated, or the metal circuit layer is peeled off from the ceramic substrate, which may cause poor bonding strength or poor thermal resistance. The reliability of electronic component modules formed by mounting electronic components such as semiconductor elements on such ceramic circuit substrates is insufficient. Summary of the invention

[0010] Problems to be solved by the invention

[0011] In view of the above problems, an object of the present invention is to obtain a silicon nitride circuit substrate capable of improving reliability and yield as an electronic component module.

[0012] Means for solving problems

[0013] According to the present invention, there are provided the silicon nitride circuit board and the electronic component module described below.

[0014] That is, according to the present invention, there is provided a silicon nitride circuit substrate comprising:

[0015] Silicon nitride substrate;

[0016] A first copper layer disposed on one side of the silicon nitride substrate; and

[0017] A second copper layer is provided on the other side of the silicon nitride substrate.

[0018] The fracture toughness value Kc of the silicon nitride substrate is 5.0 MPa·m 0.5 Above, 10.0MPa·m 0.5 the following,

[0019] The linear expansion coefficient of the silicon nitride substrate is α B ( / °C), the Young's modulus of the silicon nitride substrate is set to E B (GPa), the linear expansion coefficient of the first copper layer is α A ( / °C), the linear expansion coefficient of the second copper layer is α C ( / ℃),

[0020] The thermal shock parameter HS1 represented by the following formula (1) and the thermal shock parameter HS2 represented by the following formula (2) are each 1.30 GPa or more and 2.30 GPa or less.

[0021] Formula (1) HS1=(α A -α B )×E B ×(350-(-78))

[0022] Formula (2) HS2=(α C -α B )×E B ×(350-(-78))

[0023] According to the present invention, there is provided an electronic component module comprising a silicon nitride circuit substrate, an electronic component mounted on the silicon nitride circuit substrate, and a sealing resin portion sealing the silicon nitride circuit substrate and the electronic component.

[0024] The silicon nitride circuit substrate is the silicon nitride circuit substrate mentioned above.

[0025] Effects of the Invention

[0026] Since the silicon nitride circuit board of the present invention is configured as described above, it is possible to obtain an electronic component module having a low incidence of poor bonding strength or poor thermal resistance when thermal stress is applied and having high reliability and yield as an electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] [ Figure 1 ] is a top view of the silicon nitride circuit substrate involved in this embodiment.

[0028] [ Figure 2 ] is a cross-sectional view of the silicon nitride circuit substrate involved in this embodiment.

[0029] [ Figure 3 ] is a cross-sectional view of the electronic component module involved in this embodiment.

[0030] [ Figure 4 ] is an enlarged cross-sectional view of a portion of the electronic component module involved in this embodiment. DETAILED DESCRIPTION

[0031] Hereinafter, the embodiments of the present invention will be described using the accompanying drawings. It should be noted that in all the accompanying drawings, the same components are marked with the same reference numerals, and the description is appropriately omitted. In addition, the drawings are schematic diagrams and are not consistent with the actual dimensional ratios.

[0032] First, the structure of the silicon nitride substrate according to the present embodiment will be described.

[0033] <Configuration of Silicon Nitride Circuit Board of the Present Embodiment>

[0034] Regarding the silicon nitride circuit substrate of this embodiment, the Figure 1 and Figure 2 Provide explanation. Figure 1 is a top view of a silicon nitride circuit substrate according to this embodiment. Figure 2 It is a cross-sectional view of the silicon nitride circuit substrate according to the present embodiment.

[0035] like Figure 2 As shown, the silicon nitride circuit board 100 according to the present embodiment includes a silicon nitride substrate 10, a first copper layer 30, and a second copper layer 20. The silicon nitride substrate 10 and the second copper layer 20 are stacked with the solder layer 12 sandwiched therebetween, and the silicon nitride substrate 10 and the first copper layer 30 are stacked with the solder layer 13 sandwiched therebetween.

[0036] It should be noted that in the present embodiment, the so-called "silicon nitride-copper composite" refers to a state before a circuit pattern is formed, which is a state in which the first copper layer 30, the solder layer 13, the silicon nitride substrate 10, the solder layer 12, and the second copper layer 20 are stacked. In addition, the so-called "silicon nitride circuit substrate" refers to a state in which a circuit pattern is formed on the "silicon nitride-copper composite", and may also be a state in which electronic components such as the electronic component 40 are mounted on a portion of the copper layer on which the circuit pattern is formed.

[0037] As described above, the silicon nitride circuit substrate involved in this embodiment is a silicon nitride circuit substrate comprising a silicon nitride substrate 10, a first copper layer 30 provided on one surface of the silicon nitride substrate 10, and a second copper layer 20 provided on the other surface of the silicon nitride substrate. The fracture toughness value Kc of the silicon nitride substrate 10 is 5.0 MPa·m 0.5 Above, 10.0MPa·m 0.5 Hereinafter, the linear expansion coefficient of the silicon nitride substrate 10 is denoted as α B ( / °C), the Young's modulus of the silicon nitride substrate 10 is set to E B (GPa), the linear expansion coefficient of the first copper layer 30 is α A ( / °C), the linear expansion coefficient of the second copper layer 20 is α C When ( / °C), the thermal shock parameter HS1 represented by the following formula (1) and the thermal shock parameter HS2 represented by the following formula (2) are each set to 1.30 GPa or more and 2.30 GPa or less.

[0038] Formula (1) HS1=(α A -α B )×E B ×(350-(-78))

[0039] Formula (2) HS2=(α C -α B )×E B ×(350-(-78))

[0040] In the above formula, HS1 and HS2 are the product of the difference in linear expansion coefficients of the stacked silicon nitride substrate 10 and the second copper layer 20, and the silicon nitride substrate 10 and the first copper layer 30, and the Young's modulus of the silicon nitride substrate 10, and the temperature, and are parameters associated with the thermal stress that can be accumulated between the silicon nitride substrate 10 and the second copper layer 20, and between the silicon nitride substrate 10 and the first copper layer 30.

[0041] For example, as the silicon nitride substrate 10, a substrate having a linear expansion coefficient α B =4.0×10 -6 ( / ℃), Young's modulus E B = 250 (GPa) of silicon nitride substrate, the linear expansion coefficient of the first copper layer 30 is α A =17.3×10 -6 ( / °C), the linear expansion coefficient α of the second copper layer 20 C =17.3×10 -6 ( / ℃), HS1=(α A -α B )×E B ×(350-(-78))=1.42(GPa), HS2=(α C -α B )×E B ×(350-(-78))=1.42(GPa).

[0042] The fracture toughness value Kc of the silicon nitride substrate 10 is more preferably 5.5 MPa·m 0.5 Above, 9.0MPa·m 0.5 In addition, the thermal shock parameter HS1 represented by the formula (1) and the thermal shock parameter HS2 represented by the formula (2) are more preferably 1.30 GPa or more and 1.80 GPa or less.

[0043] The thermal shock parameter HS1 represented by equation (1), the thermal shock parameter HS2 represented by equation (2), and the fracture toughness value Kc of the silicon nitride substrate 10 can be adjusted by controlling the types of constituent materials used in the manufacture of the silicon nitride circuit substrate, the manufacturing conditions, etc.

[0044] According to the present embodiment, by setting the above-mentioned thermal shock parameters HS1 and HS2, and the fracture toughness value Kc of the silicon nitride substrate 10 within the above-mentioned numerical range, and making the residual stress accumulated in the silicon nitride circuit substrate and the degree of crack progression in the silicon nitride substrate within a specific range, it is possible to prevent the occurrence of damage and peeling due to the progression of cracks, thereby achieving a silicon nitride circuit substrate that can reduce poor bonding strength or poor thermal resistance when making an electronic component module.

[0045] It can be understood from the results of the examples described below that when the thermal shock parameter HS1 represented by the formula (1) and the thermal shock parameter HS2 represented by the formula (2) are set to 1.80 GPa or less, a silicon nitride circuit substrate with particularly improved reliability and yield can be obtained.

[0046] It should be noted that the fracture toughness value Kc of the silicon nitride substrate 10 can be measured by the IF method based on JIS R1607. That is, a Vickers indenter is pressed into the surface of the silicon nitride substrate at 2 kgf, and the fracture toughness value of the silicon nitride substrate is evaluated based on the length of the diagonal line of the Vickers indentation and the length of the crack extending from each end.

[0047] The linear expansion coefficients (α B , α C、 α A , ) can be obtained based on JIS R1618 using a thermomechanical analyzer (TMA). It should be noted that in the present invention, the linear expansion coefficient (α B , α C , α A , ) represent the linear expansion coefficient (linear expansion coefficient) of each copper plate and each silicon nitride substrate at 25°C to 400°C.

[0048] The Young's modulus (E B ) can be measured by a static flexure method based on JIS R1602.

[0049] Hereinafter, each structure of the silicon nitride circuit board according to the present embodiment will be described in more detail.

[0050] <Silicon Nitride Substrate>

[0051] The silicon nitride substrate 10 involved in this embodiment has the function of supporting the first copper layer 30 and the second copper layer 20. Here, the silicon nitride substrate 10 is rectangular when viewed from its thickness direction. In addition, the thickness of the silicon nitride substrate 10 is set to a range of 0.2 mm or more and 1.5 mm or less, and in this embodiment, it is set to 0.32 mm. It should be noted that the shape of the silicon nitride substrate 10 is an example in this embodiment, and as long as the function of the present invention can be exerted, it may be different from the case of this embodiment.

[0052] As described above, the fracture toughness value Kc of the silicon nitride substrate 10 according to the present embodiment is 5.0 MPa·m 0.5 Above, 10.0MPa·m 0.5 Below, more preferably 5.5 MPa·m 0.5 Above, 9.0MPa·m 0.5 the following.

[0053] In addition, the Young's modulus E of the silicon nitride substrate 10 according to the present embodiment is B It is preferably 250 GPa or more and 320 GPa or less, and more preferably 250 GPa or more and less than 300 GPa.

[0054] In addition, the linear expansion coefficient α of the silicon nitride substrate 10 according to the present embodiment is B Preferably 1.5×10 -6 / ℃ or above, 4.0×10 -6 / °C or less, more preferably 1.5×10 -6 / ℃ or above and less than 2.5×10 -6 / ℃.

[0055] By adjusting the physical properties of the silicon nitride substrate 10 as described above, it is easy to adjust the thermal shock parameters HS1 and HS2 to the above numerical range, and in addition, poor bonding strength or poor thermal resistance can be further reduced.

[0056] It should be noted that the silicon nitride substrate 10 can be manufactured using a known method. The fracture toughness value Kc and Young's modulus E of the silicon nitride substrate 10 are B , linear expansion coefficient α B The temperature can be adjusted by controlling the method for producing the silicon nitride substrate 10 , specifically, the composition of raw materials, firing conditions (heating rate, holding temperature, holding time, cooling rate, etc.), etc. The method for producing the silicon nitride substrate 10 is described below.

[0057] <First Copper Layer and Second Copper Layer>

[0058] The first copper layer 30 and the second copper layer 20 are polygonal when viewed from the thickness direction. The thickness of the first copper layer 30 and the second copper layer 20 is set to a range of 0.5 mm or more and 2.0 mm or less, and more preferably 0.8 mm or more and 1.2 mm or less. In the present embodiment, as an example, it is set to 0.8 mm. It should be noted that the shape of the first copper layer 30 and the second copper layer 20 is an example in the present embodiment, and as long as the function of the present invention can be exerted, it may be different from the case of the present embodiment.

[0059] The linear expansion coefficients of the first copper layer 30 and the second copper layer 20 involved in this embodiment vary according to the type of copper, but do not vary greatly. Therefore, the linear expansion coefficient of the copper layer in this embodiment is 17.3×10 -6 ( / ℃).

[0060] By adjusting the physical properties of the first copper layer 30 and the second copper layer 20 as described above, it is easy to adjust the thermal shock parameters HS1 and HS2 to the above numerical range, which can further reduce poor bonding strength or poor thermal resistance.

[0061] The average crystal grain size of the copper crystals in the first copper layer 30 is preferably 50 μm or more and 500 μm or less, and more preferably 100 μm or more and 300 μm or less.

[0062] When the silicon nitride circuit substrate according to the present embodiment is made into an electronic component module as described later, the electronic component 40 is mounted on the first copper layer 30 via a bonding layer such as a solder layer 31, and the first copper layer 30 is sandwiched by the solder layer, the electronic component, and the silicon nitride substrate 10, and is subjected to thermal stress caused by the difference in thermal expansion coefficient with these materials, but by making the average crystal grain size of the copper crystals in the first copper layer 30 within the above numerical range, poor bonding strength or poor thermal resistance can be further reduced. Although the above mechanism is not clear, it is presumed that the reason is that by making the average crystal grain size of the copper crystals in the first copper layer 30 within the above numerical range, grain boundary sliding of the copper crystals in the first copper layer 30 occurs appropriately, and the stress is moderately relaxed.

[0063] The average crystal grain size of the copper crystals in the second copper layer 20 is preferably 50 μm or more and 500 μm or less, and more preferably 100 μm or more and 300 μm or less.

[0064] When the silicon nitride circuit substrate according to the present embodiment is made into an electronic component module as described later, a heat sink is bonded to the second copper layer 20 via a bonding layer such as a solder layer, and the second copper layer 20 is sandwiched between the solder layer and the heat sink and the silicon nitride substrate 10, and is subjected to thermal stress caused by the difference in thermal expansion coefficient with these materials, but poor bonding strength or poor thermal resistance can be further reduced by making the average crystal grain size of the copper crystals in the second copper layer 20 within the above numerical range. Although the above mechanism is not clear, it is presumed that the reason is that by making the average crystal grain size of the copper crystals in the second copper layer 20 within the above numerical range, grain boundary sliding of the copper crystals in the second copper layer 20 occurs appropriately, and stress is moderately relieved.

[0065] It should be noted that the average crystal grain size in the first copper layer 30 and the second copper layer 20 can be adjusted by controlling the type of copper plate constituting the copper layer and the manufacturing conditions of the silicon nitride circuit board.

[0066] In addition, the average crystal grain size of the copper crystals in the first copper layer 30 and the second copper layer 20 can be obtained by the method described in the examples.

[0067] <Brazing filler metal layer>

[0068] The brazing material layer 12 and the brazing material layer 13 according to the present embodiment are respectively arranged between the silicon nitride substrate 10 and the first copper layer 30 and between the silicon nitride substrate 10 and the second copper layer 20, so that the first copper layer 30 or the second copper layer 20 is bonded to the silicon nitride substrate 10. The thickness of the brazing material layer 12 and the brazing material layer 13 is typically set in the range of 3 μm or more and 40 μm or less, and more preferably 4 μm or more and 25 μm or less.

[0069] It should be noted that the silicon nitride circuit substrate according to the present embodiment may have a plating layer on the first copper layer 30 and the second copper layer 20. The plating layer may be formed of a known material, for example, Ag or Ni-P.

[0070] As for the composition of the solder layer 12 and the solder layer 13, it can be composed of a silver-copper solder containing at least one active metal selected from titanium, zirconium, hafnium, niobium, tantalum, vanadium, aluminum, and tin in the solder. As for the proportion of Ag, Cu, and Sn or In, preferably, it includes: 85.0 mass parts or more and 95.0 mass parts or less of Ag; 5.0 mass parts or more and 13.0 mass parts or less of Cu; 0.4 mass parts or more and 3.5 mass parts or less of Sn or In. By setting it within the above numerical range, the melting temperature of the solder is prevented from rising excessively, and bonding can be performed at a moderate temperature, the thermal stress caused by the difference in thermal expansion coefficient during bonding can be reduced, and the heat cycle resistance can be improved.

[0071] The amount of active metals such as titanium added may be, for example, 1.5 parts by mass or more and 5.0 parts by mass or less relative to 100 parts by mass of the total of Ag, Cu, and Sn or In. By appropriately adjusting the amount of active metal added, wettability with the ceramic plate can be further improved, and the occurrence of poor bonding can be further suppressed.

[0072] Next, use Figure 3 and Figure 4 The embodiment of the silicon nitride circuit substrate according to the present embodiment will be described further. Figure 3 is a cross-sectional view of the electronic component module according to this embodiment. Figure 4 This is an enlarged cross-sectional view of a portion of the electronic component module according to the present embodiment.

[0073] As described above, the silicon nitride circuit substrate 100 according to the present embodiment is a silicon nitride circuit substrate including a silicon nitride substrate 10, a first copper layer 30 disposed on one surface of the silicon nitride substrate 10, and a second copper layer 20 disposed on the other surface of the silicon nitride substrate 10. Figure 3 As shown, the semiconductor device is used in a state sealed by a sealing resin portion 50 .

[0074] In addition, in the present embodiment, the surface of the second copper layer 20 opposite to the surface on which the silicon nitride substrate 10 is provided has an uncovered region which is not covered by the sealing resin portion 50 .

[0075] In this embodiment, the silicon nitride circuit substrate can be formed in a form in which the surface of the second copper layer 20 opposite to the surface provided with the silicon nitride substrate 10 is directly bonded to the heat sink or through a bonding material layer. Figure 3 In the example of the present embodiment shown, the second copper layer 20 is bonded to the heat sink 60 via the bonding material layer 21 .

[0076] That is, in the present embodiment, the second copper layer 20 is bonded to the heat sink 60 via the bonding material layer 21 , and the surface of the second copper layer 20 facing the heat sink 60 has an uncovered region that is not covered by the sealing resin portion 50 .

[0077] According to the present embodiment, even when the silicon nitride circuit substrate is used in a form that still has a portion covered by the sealing resin portion 50 having a different linear expansion coefficient and an uncovered area, and even when the second copper layer 20 in the silicon nitride circuit substrate is used in a form that is also bonded to the heat sink 60 having a different linear expansion coefficient, by adjusting the thermal shock parameters HS1 and HS2 and the fracture toughness value of the silicon nitride substrate 10, poor bonding strength or poor thermal resistance can be reduced.

[0078] In the present embodiment, the first copper layer 30 is a copper layer formed into a circuit pattern. It should be noted that the electronic component 40 is bonded to the first copper layer 30 via the solder layer 31, and the first copper layer 30 and the electronic component 40 are connected to the external connection terminal 70 through the lead frame and the bonding wire 71 for external connection. In the present embodiment, as an example, an example of connecting to the external connection terminal 70 via the bonding wire 71 is shown. In addition, the external connection terminal 70 may also be directly connected to the substrate without the bonding wire 71. In this case, the external connection terminal 70 may be bonded, for example, by soldering or ultrasonic bonding.

[0079] It should be noted that the electronic component 40 is an electronic component such as a semiconductor element, and various semiconductor elements such as IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal Oxide Semiconductor Field Effect Transistor), FWD (Free Wheeling Diode), etc. can be selected according to the desired function.

[0080] The solder layer 31 joining the electronic component 40 may be made of, for example, Sn—Sb, Sn—Ag, Sn—Cu, Sn—In, or Sn—Ag—Cu solder materials (so-called lead-free solder materials).

[0081] The external connection terminals 70 are formed of, for example, copper or a copper alloy, and the bonding wires 71 are formed of, for example, copper, a copper alloy, aluminum, gold, or the like.

[0082] The sealing resin portion 50 can be formed by curing a sealing resin portion forming resin composition.

[0083] The type of the sealing resin portion forming resin composition is not particularly limited, and a resin composition commonly used in the technical field, such as a transfer molding resin composition, a compression molding resin composition, and a liquid sealing material, can be used.

[0084] The sealing resin portion-forming resin composition preferably contains a thermosetting resin, preferably contains one or more selected from epoxy resins, phenolic resins, cyanate resins, bismaleimide triazine resins, acrylic resins, and silicone resins, and more preferably contains at least epoxy resin.

[0085] The sealing resin portion forming resin composition may further contain a curing agent, a filler, and the like.

[0086] As the filling material, fused silica (spherical silica), crystalline silica, aluminum oxide, silicon carbide, silicon nitride, aluminum nitride, boron nitride, beryllium oxide, zirconium oxide and other powders or beads obtained by making them into spherical shapes, glass fibers, aramid fibers, carbon fibers and the like can be cited. The filling material can be used alone or in combination of two or more. As a resin composition for forming the sealing resin portion, for example, an epoxy resin to which SiO2 filler is added can be used.

[0087] In addition, in the present embodiment, the second copper layer 20 is a heat sink bonding copper layer.

[0088] In the present embodiment, the second copper layer 20 is bonded to the heat sink 60 via the bonding material layer 21 .

[0089] It should be noted that the heat sink 60 is formed of a material having a high thermal conductivity, such as aluminum, copper, or an alloy thereof, and is preferably formed of aluminum or an aluminum alloy.

[0090] The electronic component module according to the present embodiment includes the silicon nitride circuit substrate 100 , the electronic component 40 mounted on the silicon nitride circuit substrate 100 , and the sealing resin portion 50 sealing the silicon nitride circuit substrate 100 and the electronic component 40 .

[0091] In the electronic component module according to the present embodiment, the surface of the second copper layer 20 opposite to the surface on which the silicon nitride substrate 10 is provided protrudes further away from the silicon nitride substrate 10 than the sealing resin portion 50. Figure 4 As shown in the figure, when the surface of the sealing resin part 50 facing the heat sink 60 is the sealing resin part lower surface 51 and the surface of the second copper layer 20 facing the heat sink 60 is the second copper layer lower surface 22, there is a height difference between the sealing resin part lower surface 51 and the bonding material layer 21, and the second copper layer lower surface 22 is designed to protrude relative to the sealing resin part lower surface 51. With such a design, in the process of bonding the silicon nitride circuit substrate 100 to the heat sink 60, that is, in the process of bonding the second copper layer lower surface 22 (uncovered area not covered by the sealing resin part 50) to the heat sink 60, when the silicon nitride circuit substrate 100 and the heat sink 60 are pressed and contacted, the second copper layer lower surface 22 first contacts the heat sink 60, so that the sealing resin part 50 does not hinder the bonding, the second copper layer lower surface 22 can be smoothly bonded to the heat sink 60, and the reliability of the bonding between the second copper layer 20 and the heat sink 60 can be improved.

[0092] <Method for Manufacturing Silicon Nitride Circuit Substrate>

[0093] The silicon nitride circuit substrate according to the present embodiment can be manufactured by the following method.

[0094] First, prepare a silicon nitride substrate 10 having desired physical properties. The silicon nitride substrate 10 can be obtained by the following manufacturing method. That is, using a ball mill, raw material powders containing silicon nitride powder, Y2O3, MgO and other sintering aids, an organic solvent, and an organic binder, a plasticizer, etc. added as needed are uniformly mixed to form a raw material slurry. After the obtained raw material slurry is degassed and thickened, it is formed into a sheet using a scraper method to obtain a molded body. After the obtained sheet molded body is cut, it is degreased at 400-800°C, and then sintered in a nitrogen atmosphere at 1700-1900°C in a sintering furnace for 1 to 10 hours, thereby obtaining the silicon nitride substrate 10.

[0095] Here, the fracture toughness value Kc and Young's modulus E of the silicon nitride substrate 10 are B , linear expansion coefficient α B The fracture toughness value Kc can be adjusted by controlling the manufacturing conditions such as the manufacturing method of the silicon nitride substrate 10, specifically, the raw material blending, firing conditions, etc. Although it also depends on the raw material blending and the balance with other manufacturing conditions, the fracture toughness value Kc can be controlled by adjusting the firing conditions (heating rate, holding temperature, holding time, cooling rate, etc.). As an example, if the firing temperature is increased, the fracture toughness value Kc increases, and if the firing temperature is decreased, the fracture toughness value Kc decreases. In addition, the Young's modulus E BFor example, it can be controlled by adjusting the firing conditions (heating rate, holding temperature, holding time, cooling rate, etc.). As an example, if the firing temperature is increased, the Young's modulus E B If the firing temperature is lowered, the Young's modulus E B In addition, although it also depends on the balance with other manufacturing conditions, the linear expansion coefficient α B For example, it becomes smaller when the amount of the sintering aid added increases, and becomes larger when the amount of the sintering aid added decreases.

[0096] Next, Ag-Cu alloy paste, for example, to which Ti as an active metal is added, is printed on both sides of the silicon nitride substrate 10 as a brazing material containing an active metal, and a rectangular copper plate substantially the same as the silicon nitride substrate 10 is heated and bonded to both sides at a temperature of 600° C. to 900° C. Here, as the copper plate, an oxygen-free copper plate is preferably used, and a rolled copper plate is more preferably used. By bonding the copper plates to both sides of the silicon nitride substrate 10 via the brazing material, a silicon nitride-copper composite can be obtained.

[0097] Next, the first copper layer 30 is etched to form a circuit pattern. A photoresist (not shown) is laminated on the upper surface of 30. In this case, a liquid photoresist may be applied.

[0098] Next, in order to form a circuit pattern on the photoresist, pattern exposure based on the circuit pattern is performed. In this case, a film on which a negative image of the circuit pattern is formed can be placed in close contact with the photoresist, and the photoresist can be exposed by so-called batch exposure, or the photoresist can be exposed using a so-called direct-drawing exposure device (not using the above film).

[0099] Next, the exposed photoresist is etched according to the circuit pattern.

[0100] Next, the remaining photoresist is removed.

[0101] At this time, the second copper layer 20 may not be subjected to etching treatment, and may be patterned in the same manner. The second copper layer 20 and the first copper layer 30 after the circuit pattern is formed may be further plated.

[0102] In the above manner, the silicon nitride circuit substrate 100 having the circuit pattern formed thereon is manufactured.

[0103] Next, the electronic component 40 is mounted on the first copper layer 30 via the solder layer 31. In the present embodiment, the first copper layer 30 and the electronic component 40 are soldered together using a Sn-Sb-based, Sn-Ag-based, Sn-In-based, or Sn-Ag-Cu-based solder material.

[0104] Next, the electronic component module is resin-sealed using a sealing resin to form a sealing resin portion 50. Resin sealing can be performed using a known method, for example, resin sealing can be performed by transfer molding. In addition, in the resin sealing process, for example, the lower surface 22 of the second copper layer of the electronic component module is pressed against a plastic material in advance to perform resin sealing, thereby allowing an uncovered area not covered by the sealing resin portion 50 to remain on the surface of the second copper layer 20 that is opposite to the surface on which the silicon nitride substrate 10 is provided (i.e., the lower surface 22 of the second copper layer), and the lower surface 22 of the second copper layer can be made to protrude relative to the lower surface 51 of the sealing resin portion.

[0105] In the above manner, an electronic component module is manufactured.

[0106] It should be noted that the present invention is not limited to the above-described embodiments, and modifications and improvements within the scope that can achieve the purpose of the present invention are included in the present invention.

[0107] Example

[0108] Hereinafter, the present invention will be described in detail with reference to Examples, but the present invention is not limited at all to the description of these Examples.

[0109] Prepare HS1, HS2 and fracture toughness value K using the following method C A plurality of different silicon nitride circuit substrates were subjected to a heat cycle test described below.

[0110] <Silicon Nitride Substrate>

[0111] By adjusting the raw material blend and firing conditions, we can prepare various linear expansion coefficients α B , Young's modulus E B , fracture toughness value K C Silicon nitride substrates B-1 to B-10 (148 mm × 200 mm × 0.32 mm).

[0112] <Copper Plate for First Copper Layer and Second Copper Layer>

[0113] The linear expansion coefficient is 17.3×10 -6 / ℃, rolled copper plate with a thickness of 0.8mm.

[0114] <Method for Manufacturing Silicon Nitride Circuit Substrate>

[0115] Silicon nitride circuit boards 1 to 10 were produced using the silicon nitride substrates and copper plates in combination shown in Table 1.

[0116] First, as a brazing material (containing an active metal), a brazing material including 3.5 parts by mass of titanium hydride powder (manufactured by TOHO TECHNICAL Co., Ltd.: TCH-100) is prepared relative to a total of 100 parts by mass of 89.5 parts by mass of Ag powder (manufactured by Fukuda Metal Foil Powder Co., Ltd.: Ag-HWQ 2.5 μm), 9.5 parts by mass of Cu powder (manufactured by Fukuda Metal Foil Powder Co., Ltd.: Cu-HWQ 3 μm), and 1.0 part by mass of Sn powder (manufactured by Fukuda Metal Foil Powder Co., Ltd.: Sn-HPN 3 μm).

[0117] The brazing material, binder resin and solvent are mixed to obtain a brazing material paste, which is applied to both surfaces of a silicon nitride substrate by screen printing so that the dry thickness on each surface becomes about 10 μm.

[0118] Then, copper plates were laminated on both sides of the silicon nitride substrate. -3 The silicon nitride substrate and the copper plate are heated at 780°C for 30 minutes in a vacuum below Pa, and the silicon nitride substrate and the copper plate are bonded by brazing. Thus, a silicon nitride-copper composite formed by bonding the silicon nitride substrate and the copper plate by brazing is obtained. Furthermore, a resist is printed on the copper layer of the obtained silicon nitride-copper composite, and a circuit pattern is formed by etching with a ferric chloride solution to obtain a silicon nitride circuit substrate.

[0119] The average crystal grain size of copper in the silicon nitride circuit board 1 was evaluated by the following method. As a result, the average crystal grain size of copper crystals in the first copper layer was 250 μm, and the average crystal grain size of copper crystals in the second copper layer was 255 μm.

[0120] <Evaluation Method of Copper Plate and Silicon Nitride Substrate>

[0121] (1) Linear expansion coefficient of copper plate and silicon nitride substrate (α B )

[0122] Based on JIS R 618, the linear expansion coefficient (linear expansion coefficient) of each copper plate and each silicon nitride substrate at 25° C. to 400° C. was measured using a thermomechanical analyzer (TMA).

[0123] (2) Young's modulus of silicon nitride substrate (E B )

[0124] The measurement was performed by a static bending method based on JIS R 1602. The test piece had a shape of 3 mm×4 mm×40 mm.

[0125] (3) Fracture toughness value of silicon nitride substrate (K C )

[0126] The measurement was performed by the IF method based on JIS R 1607. That is, a Vickers indenter was pressed into the surface of the silicon nitride substrate at 2 kgf, and the fracture toughness value of the silicon nitride substrate was evaluated based on the length of the diagonal line of the Vickers indentation and the length of the crack extending from each end.

[0127] <Evaluation Method of Average Crystal Grain Size of Copper>

[0128] The average crystal grain size of copper in the first copper layer and the second copper layer in the silicon nitride circuit board was determined by the following method.

[0129] First, a "cross section" for measurement is obtained through the following steps.

[0130] (1) The ceramic circuit substrate obtained in each of the examples and comparative examples was cut along a cross section perpendicular to the main surface and passing through the center of gravity of the substrate. A band saw was used for the cutting.

[0131] (2) The cut silicon nitride circuit substrate is embedded with resin to produce a resin-embedded body.

[0132] (3) The cross section of the composite body in the produced resin-embedded body is polished using diamond abrasive grains.

[0133] The cross section of the polished silicon nitride circuit substrate was measured by electron backscatter diffraction.

[0134] Specifically, first, near the approximate center of the first copper layer or the second copper layer after grinding, under the condition of an accelerating voltage of 15 kV, in a 50-fold observation field, an analysis based on the electron backscatter diffraction (EBSD) method is performed to obtain data. In the EBSD method, an SU6600 field emission scanning microscope made by Hitachi High-Tech Co., Ltd. and an analysis device made by TSL Solutions Co., Ltd. are used.

[0135] The measured data were visualized using OIM Data Analysis 7.3.0 software manufactured by TSL Solutions Co., Ltd. to create a crystal orientation map. The crystal orientation map was analyzed using image processing software to determine the average crystal grain size of the copper crystals in the copper layer.

[0136] In the above, as the image processing software, Image-Pro PlusShape Stack version 6.3 manufactured by Media Cybernetics was used. It should be noted that in the calculation of the average crystal grain size, the intercept method was used to draw 10 or more straight lines of a specified length in parallel on an observation image, and the average value of the straight line length of the portion where the straight line crosses the copper crystal grain was obtained as the average crystal grain size of the copper crystal (these are values ​​calculated by automatic processing by the software).

[0137] <Thermal Cycle Test and Reliability Evaluation>

[0138] First, a bonding substrate as a test object at room temperature (for example, 20° C.) is moved into an environment at 150° C. and maintained in the environment at 150° C. for 15 minutes (first step).

[0139] Next, the bonded substrate was moved from the 150° C. environment to the −55° C. environment and maintained in the −55° C. environment for 15 minutes (second step).

[0140] Then, the first step and the second step were repeated alternately 2000 times.

[0141] Next, the presence or absence of peeling of the copper layer was observed by ultrasonic flaw detection.

[0142] The evaluation criteria are shown below.

[0143] ○: No peeling occurred.

[0144] △: Peeling slightly occurred.

[0145] Specifically, with the silicon nitride circuit board 2 where peeling occurred as a reference, the case where peeling was observed but the degree was equal to that of the silicon nitride circuit board 2 or the case where peeling was observed but the degree was less than that of the silicon nitride circuit board 2 was evaluated as △.

[0146] ×: Peeling occurs a lot.

[0147] Specifically, the case where the occurrence of peeling was observed and more peeling than that of the silicon nitride circuit board 2 was evaluated as ×, with the silicon nitride circuit board 2 where the occurrence of peeling was observed being used as a reference.

[0148] The evaluation results are summarized in Table 1.

[0149] [Table 1]

[0150]

[0151] As shown in Table 1, in the silicon nitride circuit substrate involved in the embodiment in which the fracture toughness value, and HS1 and HS2 are controlled within the range specified by the present invention, peeling occurs less frequently, and in particular, in the silicon nitride circuit substrate involved in the embodiment in which HS1 and HS2 are below 1.80 GPa, no peeling occurs.

[0152] As can be understood from the above, in order to stably obtain a silicon nitride circuit substrate with high reliability, selection of the material constituting the copper layer and the material of the silicon nitride substrate is important.

[0153] This application claims the benefit of priority based on Japanese patent application No. 2019-066151, filed on March 29, 2019, the disclosure of which is incorporated herein in its entirety.

[0154] Description of Reference Numerals

[0155] 10 Silicon Nitride Substrate

[0156] 12 Solder layer

[0157] 13 Brazing material layer

[0158] 20 Second copper layer

[0159] 21 Bonding material layer

[0160] 22 Lower surface of the second copper layer

[0161] 30 First copper layer

[0162] 31 Solder layer

[0163] 40 Electronic components

[0164] 50 Sealing resin part

[0165] 51 Sealing resin portion bottom surface

[0166] 60 Radiator

[0167] 70 External connection terminals

[0168] 71 Bonding wire

[0169] 100 Silicon Nitride Circuit Substrate

Claims

1. A silicon nitride circuit substrate comprising: Silicon nitride substrate; A first copper layer disposed on one side of the silicon nitride substrate; and A second copper layer is provided on the other side of the silicon nitride substrate, The fracture toughness value Kc of the silicon nitride substrate is 5.0 MPa·m 0.5 Above, 10.0MPa·m 0.5 the following, The linear expansion coefficient of the silicon nitride substrate is set to α B ( / °C), the Young's modulus of the silicon nitride substrate is set to E B (GPa), the linear expansion coefficient of the first copper layer is α A ( / °C), the linear expansion coefficient of the second copper layer is α C ( / ℃), The thermal shock parameter HS1 represented by the following formula (1) and the thermal shock parameter HS2 represented by the following formula (2) are each 1.30 GPa or more and 1.80 GPa or less. Equation (1) HS1=(α A -a B )×E B ×(350-(-78)) Equation (2) HS2 = (α C - α B ) × E B × (350 - (-78)).

2. The silicon nitride circuit substrate according to claim 1, wherein: The average crystal grain size of the copper crystals in the first copper layer is 50 μm or more and 500 μm or less.

3. The silicon nitride circuit substrate according to claim 1 or 2, wherein: The average crystal grain size of the copper crystals in the second copper layer is 50 μm or more and 500 μm or less.

4. The silicon nitride circuit substrate according to claim 1 or 2, wherein: The Young's modulus E of the silicon nitride substrate B It is above 250GPa and below 320GPa.

5. The silicon nitride circuit substrate according to claim 1 or 2, wherein: The linear expansion coefficient α of the silicon nitride substrate B 1.5×10 -6 / ℃ or above, 4.0×10 -6 / ℃ below. 6 . The silicon nitride circuit substrate according to claim 1 , which is used in a state of being sealed by a sealing resin portion.

7. The silicon nitride circuit substrate according to claim 6, wherein: The aspect is an aspect in which a surface of the second copper layer opposite to a surface on which the silicon nitride substrate is provided has an uncovered region which is not covered by the sealing resin portion.

8. The silicon nitride circuit substrate according to claim 6, wherein: The embodiment is an embodiment in which a surface of the second copper layer opposite to a surface on which the silicon nitride substrate is provided is bonded to the heat sink directly or through a bonding material layer.

9. The silicon nitride circuit substrate according to claim 1 or 2, wherein: The first copper layer is a copper layer formed into a circuit pattern.

10. The silicon nitride circuit substrate according to claim 1 or 2, wherein: The second copper layer is a heat sink bonding copper layer.

11. An electronic component module comprising: a silicon nitride circuit substrate, an electronic component mounted on the silicon nitride circuit substrate, and a sealing resin portion sealing the silicon nitride circuit substrate and the electronic component, in, The silicon nitride circuit substrate is the silicon nitride circuit substrate according to any one of claims 1 to 10.

12. The electronic component module according to claim 11, wherein A surface of the second copper layer opposite to a surface provided with the silicon nitride substrate protrudes in a direction away from the silicon nitride substrate relative to the sealing resin portion.

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