Semiconductor device, method for manufacturing semiconductor device and processing system

Abstract

The present disclosure generally relates to a method of forming a semiconductor device, a semiconductor device, and a processing chamber. The method includes: forming a source / drain region in a processing system; forming a doped semiconductor layer on the source / drain region in the processing system; forming a metal silicide layer; forming a dielectric material; forming a trench in the dielectric material; and filling the trench with a conductor. The source / drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking a vacuum. A semiconductor device includes a plurality of layers, and the semiconductor device has a reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Implementations of the present disclosure enable the formation of source / drain contacts with reduced contact resistance by using an integrated process that allows various operations for forming source / drain contacts to be performed within the same processing system.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to an apparatus and method, and more particularly, to a semiconductor device, a method of fabricating a semiconductor device, and a processing system. Background Art

[0002] Transistors are basic device elements of modern digital processors and memory devices, and have found applications in high-power electronic products. Currently, there are multiple semiconductor device (e.g., transistor) designs or types that can be used for different applications. Various transistor types include, for example, field effect transistors (FETs), bipolar junction transistors (BJTs), junction field effect transistors (JFETs), metal oxide semiconductor field effect transistors (MOSFETs), vertical channel or trench field effect transistors, and super junction or multi-drain transistors. A type of transistor that has appeared in the MOSFET family of transistors is a fin field effect transistor (FinFET).

[0003] FinFET can be manufactured on a bulk semiconductor substrate (e.g., a silicon substrate) and includes a fin-like structure that extends in a length direction along the surface of the substrate and in a height direction perpendicular to the surface of the substrate. The fin has a narrow width (e.g., less than 250 nanometers). The fin can pass through an insulating layer. A gate structure including a conductive gate material and a gate insulator can be formed above the region of the fin. The upper portion of the fin is doped on either side of the gate structure to form a source / drain region adjacent to the gate.

[0004] FinFETs have good electrostatic properties for complementary MOSFETs scaled to smaller sizes. Because the fin is a three-dimensional structure, the channel of the transistor can be formed on three surfaces of the fin, allowing FinFETs to exhibit high current switching capabilities for a given surface area occupied on the substrate. Because the channel and device can be elevated from the substrate surface, there can be reduced electric field coupling between adjacent devices compared to conventional planar MOSFETs.

[0005] A key challenge in semiconductor design, manufacturing and operation is contact resistance. For example, the source and drain regions of a FinFET device may be eroded by the etching process used to form the source / drain contact trenches, resulting in increased contact resistance. As a result of increased contact resistance, the performance of circuit devices, including transistors and other device structures formed on a semiconductor substrate, is reduced.

[0006] Therefore, there is a need for improved semiconductor processing methods for forming semiconductor devices having reduced contact resistance. Summary of the invention

[0007] Embodiments of the present disclosure generally relate to a semiconductor device, a method of manufacturing a semiconductor device, and a processing system. The method results in a semiconductor device having reduced contact resistance. The method can be performed in the processing system.

[0008] In one embodiment, a method for forming a semiconductor device is provided. The method includes: forming a source / drain region in a substrate; forming a doped semiconductor layer on the source / drain region; forming a metal silicide layer on the doped semiconductor layer in the processing system; forming a dielectric material on the metal silicide layer; forming a trench in the dielectric material to expose a portion of the metal silicide layer; and filling the trench with a conductor. The source / drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking a vacuum.

[0009] In another embodiment, a semiconductor device is provided, comprising: a source / drain region extending from a semiconductor structure; a doped semiconductor layer disposed on and surrounding the source / drain region; a metal silicide layer disposed on and surrounding the source / drain region; and a conductor disposed on the metal silicide layer.

[0010] In yet another embodiment, a processing system is provided. The processing system includes: a transfer chamber; a plurality of processing chambers coupled to the transfer chamber; and a controller. The controller is configured to trigger a process to be performed in the processing system, the process including: forming a source / drain region; forming a doped semiconductor layer on the source / drain region; and forming a metal silicide layer on the doped semiconductor layer. The source / drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking a vacuum. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to be able to understand in detail the manner of the above-mentioned features of the present disclosure, the present disclosure briefly summarized above may be described in more detail by reference to embodiments (some of which are shown in the accompanying drawings). However, it should be noted that the accompanying drawings only illustrate exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, and other equivalent embodiments may be allowed.

[0012] Figure 1 is a flow chart of method operations for forming a semiconductor device according to one embodiment.

[0013] FIG. 2A to FIG. 2H A cross-sectional view of a substrate according to one embodiment is shown.

[0014] Figure 3 A schematic top view of a processing system according to one embodiment is shown.

[0015] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without repetition. DETAILED DESCRIPTION

[0016] Embodiments described herein include a method of forming a semiconductor device, a semiconductor device, and a processing system. The method includes: forming a source / drain region; forming a doped semiconductor layer; forming a metal silicide layer on the doped semiconductor layer; forming a dielectric material; forming a trench in the dielectric material; and filling the trench with a conductor. The source / drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking a vacuum. A semiconductor device can be formed by this method. The semiconductor device includes a plurality of layers, and the semiconductor device has a reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. The dopant concentration of the doped semiconductor layer is higher than the dopant concentration of the source / drain region, and the higher dopant concentration results in a reduced contact resistance. The embodiments disclosed herein can be used for (but not limited to) semiconductor devices with reduced contact resistance.

[0017] The above is a general introduction to the technology described in the present disclosure. It is contemplated that the concepts of the present disclosure can be implemented for planar transistor devices or three-dimensional transistor devices, such as fin field effect transistors (FinFETs), horizontal gate all around (HGAA) FETs, vertical gate all around (VGAA) FETs, nanowire channel FETs, strained semiconductor devices, etc.

[0018] As used herein, the term "about" refers to a deviation of + / - 10% from the nominal value. It should be understood that such deviations can be included in any value provided herein.

[0019] Figure 1 is a flow chart of method 100 operations for forming a semiconductor device according to one embodiment. FIG. 2A to FIG. 2H A cross-sectional view of a substrate 200 according to one embodiment is shown. Figure 1 and Figures 2A to 2D The operations of method 100 are described, but those skilled in the art will appreciate that any system configured to perform these method operations in any order falls within the scope of the embodiments described herein. Note that method 100 can be used to form any other semiconductor structures not presented herein. Those skilled in the art will recognize that the complete process for forming semiconductor devices and related structures is not shown in the figures or described herein.

[0020] The method 100 begins at operation 102 by placing a substrate 200 into a processing chamber. In one example, the processing chamber is an etching chamber. Figure 2A As shown, the substrate 200 includes a semiconductor layer 202, at least one semiconductor structure 204 extending from the semiconductor layer 202, and a dielectric material 206 disposed between adjacent semiconductor structures 204 on the semiconductor layer 202. The semiconductor structure 204 can be a semiconductor fin. The semiconductor layer 202 can be made of silicon, germanium, silicon germanium, III / V compound semiconductors, gallium arsenide (GaAs) and / or indium gallium arsenide (InGaAs), or other semiconductor materials. The semiconductor layer 202 can be doped with a p-type or n-type dopant. For example, the semiconductor layer 202 is doped with a p-type dopant such as boron (B), or with an n-type dopant such as phosphorus (P) and / or arsenic (As). The semiconductor structure 204 can be made of the same material as the semiconductor layer 202. The semiconductor structure 204 can be integrated with the semiconductor layer 202. The dielectric material 206 may include shallow trench isolation (STI) regions and may be made of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon carbonitride (SiCN), mixtures thereof, or any other suitable dielectric material.

[0021] At operation 104, a portion of at least one semiconductor structure 204 is removed, exposing a surface 207 of a remaining portion of the semiconductor structure 204. The surface 207 of the semiconductor structure 204 may be recessed from the surface 209 of the dielectric material 206, such as Figure 2B In other embodiments, the surface 207 is coplanar with the surface 209 of the dielectric material 206. The portion of the semiconductor structure 204 may be removed by an etching process performed in an etching chamber.

[0022] At operation 106, source / drain regions 208 are formed on the surface 207 of the semiconductor structure 204. The source / drain regions 208 may be source regions or drain regions, such as Figure 2C As shown. The source / drain region 208 may include a merged source and drain region 208. In either example, the source / drain region 208 is made of a semiconductor material epitaxially grown on the surface 207 of the semiconductor structure 204. The source / drain region 208 may be formed in an epitaxial deposition chamber of a processing system. The substrate 200 may include a plurality of gates (not shown) disposed across the source / drain region 208.

[0023] In one embodiment that can include or be combined with one or more embodiments described herein, the source / drain region 208 is made of silicon, germanium, silicon germanium, or a III / V compound semiconductor such as gallium arsenide (GaAs) and / or indium gallium arsenide (InGaAs) or any other suitable semiconductor. The source / drain region 208 can be doped with a p-type or n-type dopant. In one example, the source / drain region 208 is doped with a p-type dopant such as B. Alternatively, the source / drain region 208 is doped with an n-type dopant such as P and / or As. The source / drain region 208 can be made of a metal silicide, such as titanium silicide, tungsten silicide, molybdenum silicide, ruthenium silicide, cobalt silicide, or any combination of the foregoing materials.

[0024] The metal silicide source / drain region 208 has a reduced resistance compared to the semiconductor source / drain region 208. The source / drain region 208 is selectively epitaxially grown on the surface 207 of the semiconductor structure 204, and due to different growth rates on different surface planes, facets 210, 212, 214, 216 can be formed, so that the source / drain region 208 has a diamond shape, such as Figure 2C shown.

[0025] A pre-cleaning process may be performed on the surface 207 of the semiconductor structure 204 before forming the source / drain regions 208. The pre-cleaning process is performed to remove contaminants, such as carbon or oxide contaminants, on the surface 207 of the semiconductor structure 204. The pre-cleaning process may include any suitable etching process, such as dry etching, wet etching, or a combination of the above etching. The pre-cleaning process may be isotropic or directional. In one example, the pre-cleaning process is performed in a processing chamber using a remote plasma source. An example processing chamber suitable for performing the pre-cleaning process is the AKTIV Pre-Clean ® available from Applied Materials, Inc., Santa Clara, California, USA. TM Chamber or Alternatively, the pre-clean process is performed in an etch chamber, such as an etch chamber using an inductively coupled plasma (ICP) source. An exemplary etch chamber may be a modified decoupled plasma nitridation (DPN) chamber available from Applied Materials, Inc. of Santa Clara, California, USA. However, it is contemplated that other appropriately configured chambers from other manufacturers may also be implemented to perform the pre-clean process.

[0026] In operation 108, if Figure 2DAs shown, in a processing system, a doped semiconductor layer 220 is formed on the source / drain region 208. The doped semiconductor layer 220 can be formed by a selective epitaxial deposition process. The doped semiconductor layer 220 is formed in the same processing system as the source / drain region 208. In one example, the doped semiconductor layer 220 is formed in the same epitaxial deposition chamber as the source / drain region 208. In another example, the doped semiconductor layer 220 is formed in a different epitaxial deposition chamber of the processing system. Because the source / drain region 208 and the doped semiconductor layer 220 are formed in the same processing system, there is no vacuum break between processes (e.g., operations 106 and 108). Therefore, no pre-cleaning process is required between processes.

[0027] The doped semiconductor layer 220 is formed on the facets 210, 212, 214, 216, but not on the dielectric material 206. Because the doped semiconductor layer 220 is formed by an epitaxial deposition process, the doped semiconductor layer 220 conformally covers the facets 210, 212, 214, 216 of the source / drain region 208. In other words, the conformal doped semiconductor layer 220 wraps around the source / drain region 208. The selective epitaxial deposition process may be performed while the substrate is maintained at a temperature below about 450° C. The doped semiconductor layer 220 may be made of the same material as the source / drain region 208, except that the dopant concentration in the doped semiconductor layer 220 is substantially higher than the dopant concentration in the source / drain region 208. For example, the doped semiconductor layer 220 may be made of germanium tin (GeSn) doped with B and / or gallium (Ga), silicon germanium (SiGe) doped with B, germanium (Ge) doped with B and / or Ga, or silicon doped with P and / or As. In one example, the doped semiconductor layer 220 includes a first layer and a second layer, and the first layer is a silicon layer doped with As, and the second layer is a silicon layer doped with P.

[0028] According to one embodiment, the doped semiconductor layer 220 is formed by a dopant soaking process. During the dopant soaking process, the outer portion of the source / drain region 208 (such as from each facet 210, 212, 214, 216 to a predetermined depth) is converted into the doped semiconductor layer 220. For example, during the dopant soaking process, the facets 210, 212, 214, 216 of the source / drain region 208 are exposed to one or more gases containing one or more dopants, such as Ga, B, P and / or As. The doped semiconductor layer 220 may have a thickness in a range of about 1 angstrom to about 10 nm. The dopant concentration in the source / drain region 208 is less than the dopant concentration in the doped semiconductor layer 220. The increased dopant concentration in the doped semiconductor layer 220 reduces the contact resistance.

[0029] The doped semiconductor layer 220 may be formed in a reduced pressure (RP) epitaxial chamber available from Applied Materials, Inc. of Santa Clara, Calif. However, it is contemplated that other suitably configured chambers from other manufacturers may also be implemented to perform selective epitaxial deposition or dopant soak processes to form the doped semiconductor layer 220.

[0030] In operation 110, if Figure 2E As shown, in the processing system, a metal silicide layer 222 is formed on the doped semiconductor layer 220. In one example, the metal silicide layer 222 is formed by a chemical vapor deposition (CVD) process. In another example, the metal silicide layer 222 is formed by an epitaxial deposition process. For example, as a result of the selective epitaxial deposition process, the metal silicide layer 222 is formed on the doped semiconductor layer 220 and not on the dielectric material 206. Because the metal silicide layer 222 is formed by the epitaxial deposition process, the metal silicide layer 222 conformally covers the small faces 210, 212, 214, 216 of the source / drain region 208. In other words, the conformal metal silicide layer 222 wraps around the source / drain region 208.

[0031] The metal silicide layer 222 may include titanium silicide, cobalt silicide, ruthenium silicide, tungsten silicide, molybdenum silicide, any combination of the above materials, or other suitable metal silicides. In one example, the metal silicide layer 222 is formed in the same processing chamber as the doped semiconductor layer 220. In another example, the metal silicide layer 222 is formed in a different processing chamber of the processing system, such as an epitaxial deposition chamber. Because the doped semiconductor layer 220 and the metal silicide layer 222 are formed in the same processing system, the vacuum is not broken between these processes (e.g., operations 108 and 110). No pre-cleaning process is required between these processes.

[0032] An optional capping layer may be formed on the metal silicide layer 222. The capping layer may include a dielectric. The capping layer may be made of a nitride or oxide material, such as titanium nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, manganese oxide, or any combination of the foregoing materials. In some embodiments, the capping layer is formed by nitriding the metal silicide layer 222, and the capping layer is a metal silicon nitride layer. The nitridation process may include exposing the metal silicide layer 222 to a nitrogen-containing plasma or a nitrogen-containing ambient environment so that nitrogen atoms chemically react with atoms located on the exposed surface of the metal silicide layer 222 to form a surface nitride layer (e.g., a capping layer). The nitridation process may be performed in a plasma chamber using a plasma source (e.g., an inductively coupled plasma (ICP) source, a capacitively coupled plasma (CCP) source, or a combination of the foregoing plasma sources). The nitridation process may be performed in a modified decoupled plasma nitridation (DPN) chamber available from Applied Materials, Inc. of Santa Clara, California, USA, or other suitable chambers.

[0033] In operation 112, if Figure 2F As shown, a contact etch stop layer (CESL) 224 is formed on the dielectric material 206 and the metal silicide layer 222. The CESL 224 is made of, for example, a dielectric material such as silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

[0034] In operation 114, if Figure 2F As shown, a dielectric material 226 is formed on the CESL 224. The dielectric material 226 may be an interlayer dielectric and may be made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof.

[0035] In operation 116, if Figure 2G As shown, a trench 228 is formed in the dielectric material 226 to expose a portion of the metal silicide layer 222 disposed on the facets 210, 212. The trench 228 is formed by removing a portion of the dielectric material 226 and the CESL 224 disposed on the facets 210, 212 of the source / drain region 208, and exposing a portion of the metal silicide layer 222. The trench 228 can be formed by any suitable removal process. In one example, the trench 228 is formed by a reactive ion etching (RIE) process. The trench 228 can be formed in an RIE chamber or other suitable etching chamber.

[0036] In operation 118, if Figure 2HAs shown, a conductor 230 is formed in the trench 228 to fill the trench 228. The conductor 230 is made of a conductive material such as a metal. In one example, the conductor 230 includes cobalt. The conductor 230 can be formed by one or more deposition processes. For example, the conductor 230 is formed by first forming a seed layer and then forming a bulk filler on the seed layer. The seed layer and the bulk filler are made of the same material. The conductor 230 can be formed by any suitable deposition method, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). Therefore, the method 100 results in the formation of a semiconductor device 290.

[0037] Operations 106, 108, and 110 are performed to reduce the contact resistance of the source / drain contacts in the transistor. In some implementations, one or more of operations 108 and 110 may be omitted while still achieving reduced contact resistance.

[0038] In one embodiment that can include or be combined with one or more embodiments described herein, operation 106 is performed and then operation 112 is performed without performing operations 108 and 110. For example, after the metal silicide source / drain regions 208 are formed, the CESL 224 is formed on the source / drain regions 208 without forming the doped semiconductor layer 220 and the metal silicide layer 222 between the source / drain regions 208 and the CESL 224.

[0039] Figure 3 1 shows a schematic top view of a processing system 300 according to one embodiment. The processing system 300 is configured to perform the method 100. Examples of processing systems that can be appropriately modified according to the teachings provided herein include the APPLICATION MATERIALS, Inc., Santa Clara, California, USA. or Integrated Processing System or Other Suitable Processing System It is contemplated that other processing systems, including processing systems from other manufacturers, may also be adapted to benefit from the aspects described herein.

[0040] As shown, the processing system 300 includes a plurality of processing chambers 302, 314, 316, a first transfer chamber 304, a pass-through chamber 306, a second transfer chamber 310, a factory interface (FI) 320, a pod 330, and a system controller 380. The plurality of processing chambers 302 are coupled to the first transfer chamber 304. The first transfer chamber 304 is also coupled to a first pair of pass-through chambers 306. The first transfer chamber 304 has a centrally disposed transfer robot (not shown) for transferring substrates between the pass-through chamber 306 and the processing chamber 302. The pass-through chamber 306 is coupled to the second transfer chamber 310, which is coupled to a processing chamber 314 configured to perform a pre-cleaning process and a processing chamber 316 configured to perform a selective epitaxial deposition process (operations 106, 108, 110). The second transfer chamber 310 has a centrally disposed transfer robot (not shown) for transferring substrates between a set of load lock chambers 312 and a processing chamber 314 or a processing chamber 316. A factory interface 320 is connected to the second transfer chamber 310 through the load lock chamber 312. The factory interface 320 is coupled to one or more cassettes 330 located on opposite sides of the load lock chamber 312. The cassettes 330 are generally front opening cassettes (FOUPs) that can enter and exit a clean room.

[0041] During operation, the substrate is first transferred to the processing chamber 314, where a pre-cleaning process is performed to remove contaminants, such as carbon or oxide contaminants, from the exposed surface of the semiconductor structure. The substrate is then transferred to the processing chamber 316, where operations 106, 108, and 110 are performed. In some embodiments, the processing chamber 314 and / or the processing chamber 316 can be switched with any one of the one or more processing chambers 302. In some embodiments, operations 106, 108, 110 are performed in different processing chambers 302. For example, operation 106 is performed in a first processing chamber 302, operation 108 is performed in a second processing chamber 302, and operation 110 is performed in a third processing chamber 302.

[0042] Subsequently, the substrate is transferred to one or more processing chambers 302, where operations 112 to 118 are performed. Because all operations 106, 108, 110, 112, 114, 116, 118 are performed within the same processing system 300, vacuum is not broken when transferring the substrate to each chamber, which reduces the chance of contamination and improves the quality of the deposited epitaxial film.

[0043] The system controller 380 is coupled to the processing system 300 to control the processing system 300 or components thereof. For example, the system controller 380 controls the operation of the processing system 300 using direct control of the chambers 302, 304, 306, 310, 312, 314, 316, the factory interface 320, and the cassette 330 of the processing system 300. In another example, the system controller 380 controls individual controllers associated with the chambers 302, 304, 306, 310, 312, 314, 316, the factory interface 320, and the cassette 330. In operation, the system controller 380 enables data collection and feedback from the various chambers to coordinate the performance of the processing system 300. In some embodiments, the feedback, the collected data, and / or any data related to system performance or control can be displayed on the GUI display 360.

[0044] The system controller 380 generally includes a central processing unit (CPU) 382, ​​a memory 384, and support circuits 386. The CPU 382 can be one of any form of general purpose processor that can be used in an industrial facility. The memory 384, a non-transitory computer readable medium or machine readable storage device, can be accessed by the CPU 382 and can be one or more of the following memories: such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage device. The support circuits 386 are coupled to the CPU 382 and can include cache memory, clock circuits, input / output subsystems, power supplies, and the like. The system controller 380 is configured to execute the method 100 stored in the memory 384. The various embodiments disclosed in the present disclosure can generally be implemented under the control of the CPU 382 by executing computer instruction code stored in the memory 384 (or the memory of a particular processing chamber) as, for example, a computer program product or software program. That is, the computer program product is tangibly embodied on the memory 384 (or non-transitory computer-readable medium or machine-readable storage device). When the CPU 382 executes the computer instruction code, the CPU 382 controls the chamber to perform operations according to various embodiments.

[0045] As described above, the method includes: forming a source / drain region in a processing system, forming a doped semiconductor layer on the source / drain region in the processing system, forming a metal silicide layer on the doped semiconductor layer in the processing system, forming a dielectric material on the metal silicide layer, forming a trench in the dielectric material to expose a portion of the metal silicide layer, and filling the trench with a conductor. The source / drain region, the doped semiconductor layer, and the metal silicide layer are formed without breaking a vacuum. The semiconductor device includes a plurality of layers, and the semiconductor device has a reduced contact resistance. The processing system is configured to perform the method and form the semiconductor device.

[0046] Embodiments of the present disclosure enable the formation of source / drain contacts with reduced contact resistance using an integrated process that allows various operations for forming source / drain contacts to be performed within the same processing system. In some embodiments, after forming the source / drain regions, a doped semiconductor layer is formed on the source / drain regions. The dopant concentration of the doped semiconductor layer is higher than the dopant concentration of the source / drain regions, and the higher dopant concentration results in reduced contact resistance.

[0047] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope of the disclosure is determined by the claims that follow.

Claims

1. A method for forming a semiconductor device, the method comprising: forming source / drain regions on the substrate; forming a doped semiconductor layer on the source / drain region; forming a metal silicide layer on the doped semiconductor layer, wherein the source / drain region, the doped semiconductor layer and the metal silicide layer are formed without breaking a vacuum; forming a dielectric material on the metal silicide layer; forming a trench in the dielectric material to expose a portion of the metal silicide layer; as well as The trench is filled with a conductor.

2. The method of claim 1, wherein the method is performed in a single processing system. The method of claim 1 , wherein the doped semiconductor layer wraps around the source / drain regions. The method of claim 1 , wherein the metal silicide layer surrounds the source / drain regions.

5. The method of claim 1, further comprising: A pre-cleaning process is performed before forming the source / drain regions.

6. The method of claim 1, further comprising: A contact etch stop layer is formed on the metal silicide layer, wherein the dielectric material is formed on the contact etch stop layer.

7. A semiconductor device comprising: a source / drain region extending from the semiconductor structure; A doped semiconductor layer is disposed on the source / drain region and surrounds the source / drain region; A metal silicide layer, disposed on the doped semiconductor layer and covering and surrounding the source / drain region; a contact etch stop layer disposed on a portion of the metal silicide layer, the contact etch stop layer comprising a dielectric material; as well as The conductor is disposed on the metal silicide layer. 8 . The semiconductor device of claim 7 , wherein the source / drain regions comprise silicon, germanium, silicon germanium, or a Group III / V compound semiconductor.

9. The semiconductor device of claim 8, wherein the source / drain regions are doped with a dopant. 10 . The semiconductor device of claim 9 , wherein the dopant concentration of the doped semiconductor layer is higher than the dopant concentration of the source / drain regions.

11. The semiconductor device of claim 7, wherein the source / drain regions include metal silicide. 12 . The semiconductor device of claim 7 , wherein the doped semiconductor layer comprises germanium tin doped with boron and gallium, silicon germanium doped with boron, germanium doped with boron and gallium, or silicon doped with phosphorus and arsenic.

13. The semiconductor device according to claim 7, wherein the metal silicide layer comprises titanium silicide, cobalt silicide, ruthenium silicide, tungsten silicide or molybdenum silicide.

14. A processing system comprising: transfer chamber; a plurality of processing chambers coupled to the transfer chamber; and A controller configured to cause a process to be performed in the processing system, the process comprising: forming source / drain regions; forming a doped semiconductor layer on the source / drain region; forming a metal silicide layer on the doped semiconductor layer; forming a dielectric material on the metal silicide layer; forming a trench in the dielectric material to expose a portion of the metal silicide layer; and The trench is filled with a conductor, wherein the source / drain regions, the doped semiconductor layer and the metal silicide layer are formed without breaking a vacuum.

15. The processing system of claim 14, wherein the process further comprises: A capping layer is formed on the metal silicide layer, wherein the capping layer comprises a dielectric material.

16. The processing system of claim 15, further comprising a pre-cleaning chamber.

17. The processing system of claim 14, wherein the process further comprises: A contact etch stop layer is formed on the metal silicide layer, wherein the dielectric material is formed on the contact etch stop layer.

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