Continuous-time linear equalizer circuit with programmable gain

Abstract

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes an input port, an output port, a first differential transistor pair coupled to the input port and the output port, and a second differential transistor pair. The CTLE circuit further includes a first degeneration impedance circuit coupled between the first differential transistor pair and ground. The first degeneration impedance includes a switchable component to change the impedance of the first degeneration impedance circuit. The CTLE circuit also includes a second degeneration impedance circuit coupled between the second differential transistor pair and ground. The second degeneration impedance includes a switchable component to change the impedance of the second degeneration impedance circuit, wherein a resistive portion of the impedance of the first degeneration impedance circuit is equal to the impedance of the second degeneration impedance circuit.

Description

Technical Field

[0001] The invention relates to a continuous time linear equalization circuit with programmable gain. Background Art

[0002] Wired communication refers to data transmission via wire-based communication technology. Generally speaking, wired communication is considered the most stable of all types of communication services. Broadband wired data communication systems such as Universal Serial Bus (USB), High Definition Multimedia Interface (HDMI), DisplayPort (DP), Peripheral Component Interconnect Express (PCIe), Thunderbolt, Converged Input Output (CIO), and any other high-speed broadband wired communication require multiple processing stages within their electronic circuit systems.

[0003] Broadband data communication system circuitry may include several stages including modules for equalizing, amplifying, and / or re-driving the signals for each data channel. Often one stage cannot provide sufficient gain or equalization. In such multi-stage systems, it may be necessary to use intermediate buffers between each stage. However, oftentimes, buffers consume even more power than equalizers, amplifiers, and drivers, making designs with fewer buffer blocks more advantageous in the system, especially when used in low voltage (i.e., about 1.8V or less) systems. What is needed is an efficient continuous time linear equalizer circuit (CTLE). Summary of the invention

[0004] In one embodiment, a continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes an input port, an output port, a first differential transistor pair coupled to the input port and the output port, and a second differential transistor pair. The CTLE circuit further includes a first degeneration impedance circuit coupled between the first differential transistor pair and ground. The first degeneration impedance includes a switchable component to change the impedance of the first degeneration impedance circuit. The CTLE circuit also includes a second degeneration impedance circuit coupled between the second differential transistor pair and ground. The second degeneration impedance includes a switchable component to change the impedance of the second degeneration impedance circuit, wherein a resistive portion of the impedance of the first degeneration impedance circuit is equal to the impedance of the second degeneration impedance circuit.

[0005] In another embodiment, a continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes an input port, an output port, a first differential transistor pair coupled to the input port, a second differential transistor pair coupled to the input port and the output port, a third differential transistor pair coupled to the input port and the output port, and a fourth differential transistor pair coupled to the input port and the output port. The CTLE further includes a first degeneration impedance circuit coupled between an emitter or source of the first differential transistor pair and an emitter or source of the fourth differential transistor pair. The first degeneration impedance includes a switchable component to change the impedance of the first degeneration impedance circuit. The CTLE also includes a second degeneration impedance circuit coupled between an emitter or source of the second differential transistor pair and an emitter or source of the third differential transistor pair. The second degeneration impedance includes a switchable component to change the impedance of the second degeneration impedance circuit, wherein a resistive portion of the impedance of the first degeneration impedance circuit is equal to the impedance of the second degeneration impedance circuit.

[0006] In some examples, the emitters or sources of the first, second, third, and fourth differential transistor pairs are coupled to ground via current sinks / sources, and the first degeneration impedance and the second degeneration impedance are configured such that a total current flowing through each of the emitters or sources of the first, second, third, and fourth differential transistor pairs is constant.

[0007] In some examples, the switchable component in the first degeneration impedance and the switchable component in the second degeneration impedance are configured to be driven such that a value of a resistive portion of the first degeneration impedance is equal to a value of the resistive portion of the second degeneration impedance.

[0008] In some embodiments, the second degeneration impedance is a second-order or third-order degeneration impedance including a capacitor, a resistor, and an inductor, and the first degeneration impedance circuit includes a plurality of resistors coupled in parallel to each other. Each of the plurality of resistors is coupled to an external controllable switch to electrically remove each of the plurality of resistors from the first degeneration impedance circuit. The second degeneration impedance circuit includes a plurality of resistors coupled in parallel to each other. Each of the plurality of resistors is coupled to an external controllable switch to electrically remove each of the plurality of resistors from the second degeneration impedance circuit.

[0009] In some examples, the first degeneration impedance circuit and the second degeneration impedance circuit include an equal number of switchable resistors. The switchable components of the first degeneration impedance circuit and the switchable components of the second degeneration impedance circuit are driven by the same control signal.

[0010] In some examples, the switchable components of the first and second degeneration impedance circuits are operable by a control signal comprising a number of control lines equal to the number of switchable components in the first degeneration impedance circuit. The control signal is used to control a DC gain of the CTLE.

[0011] The CTLE circuit is configured such that a total current flowing through the first degeneration impedance circuit and the second degeneration impedance circuit remains constant regardless of the states of the switchable components in the first and second degeneration impedances. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The frequency response of a continuous time linear equalizer (CTLE) circuit is shown.

[0013] Figure 2 A circuit diagram of a CTLE circuit is shown in accordance with one or more embodiments.

[0014] Figure 3 A circuit diagram of a fully differential CTLE circuit is shown in accordance with one or more embodiments.

[0015] Throughout the description, similar reference numerals may be used to identify similar elements. DETAILED DESCRIPTION

[0016] It will be readily appreciated that the components of the embodiments as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of the various embodiments represented in the figures is not intended to limit the scope of the present disclosure, but is merely representative of the various embodiments. Although various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0017] The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the present invention. The described embodiments are considered in all respects to be illustrative only and not restrictive. Therefore, the scope of the present invention is indicated by the appended claims rather than by the specific embodiments thereof. All changes within the meaning and scope of the equivalents of the claims are included within the scope of the claims.

[0018] References throughout this specification to features, advantages, or similar language do not imply that all features and advantages that may be achieved with the present invention are or are included in any single embodiment of the present invention. Rather, language referring to features and advantages should be understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussion of features and advantages and similar language throughout this specification may, but does not necessarily, refer to the same embodiment.

[0019] In addition, the described features, advantages and characteristics of the present invention may be combined in any suitable manner in one or more embodiments. In view of the description herein, those skilled in the relevant art will recognize that the present invention may be practiced without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of the present invention.

[0020] References throughout this specification to "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0021] Embodiments herein describe a continuous time linear equalizer (CTLE) with programmable DC gain and equalizer gain for high-speed wired data communication. The equalizer has independent control of DC gain and equalizer gain. The equalizer gain can be programmed by adjusting the weights of two signal paths via the input DC bias of the control equalizer. One of the two signal paths has a maximum peaking gain, and the other has a minimum peaking gain. On the other hand, the DC / flat gain is adjusted by turning on / off the resistor element in the emitter / source degeneration resistor group. The equalizer is characterized by a single-stage design. As a result, the equalizer exhibits low noise and low power operation with a minimum layout area. Among others, the embodiments described herein can be used for a universal serial bus (USB) system, a display port (DP) system, a PCIe (Peripheral Component Interconnect Express) system, a thunderbolt interface system, or another communication system or any other wired high-speed communication standard.

[0022] As data rates increase, high-speed CTLEs with programmable DC and equalizer gains become very important in communication systems to support various communication channels, such as microwave transmission strips, coaxial cables of different lengths. However, a conventional CTLE can only change its equalizer gain by changing its DC gain, which is defined as the gain difference between the maximum gain over frequency and the DC gain (low-frequency output gain). This requires an additional gain stage to adjust the DC gain to the target value. The CTLE described in this article avoids the need for an additional gain stage and provides all programmability in one stage, which is beneficial for low-noise and low-power applications.

[0023] Figure 1 Show Figure 2 and Figure 3100. The equalizer gain 104 of a CTLE is defined as the gain difference between the maximum gain and the DC gain of the CTLE. Conventional CTLEs change their equalizer gain by changing their DC gain, thus requiring an additional programmable gain stage to control the overall DC gain. Since the equalizer gain is controlled by changing the peaking gain, the embodiments of the CTLE described herein change its DC gain 102 independently of the equalizer gain in a single stage.

[0024] Figure 2 A single-ended implementation of the CTLE 200 is shown. The CTLE 200 includes an impedance R L , the impedance R L Can be a complex impedance or a resistive impedance. R L One end is coupled to the power supply / ground and flows through R L The current is i L CTLE 200 includes two transistor pairs, each pair includes transistor g m1 and g m2 The CTLE 200 includes two emitter degeneration impedances 202, 204. The first degeneration impedance 202 includes a resistor R E0 The first degenerate impedance 202 also includes a plurality of resistors R coupled in parallel with each other. E1 , R E2 …R Ex . Resistor R E2 ...R Ex Each of the resistors R is coupled to ground via a switch. E1 It can also be coupled to ground via a switch. However, in some embodiments, the resistor R E1 Can be coupled to ground without a switch in between. Resistor R E0 With resistor R E2 ...R Ex The second degenerate impedance 204 includes a resistor structure that is the same or similar to that shown in the first degenerate impedance 202. However, the capacitor Ce may be connected to the resistor R E0 The inductor Le and capacitor Ce2 are coupled in parallel and can be connected in series with the parallel resistor R E2 …R Ex The first degenerate impedance 202 may have the same value as the second degenerate impedance 204.

[0025] exist Figure 2 In the depicted embodiment, the CTLE 200 receives an input signal V at an input terminal 208. cm +V in , and outputs the output signal at the output terminal 206. The input signal includes a direct current (DC) component or a bias V cm and the input data signal component V in , which may be, for example, a high-speed input signal component. The DC component of the input signal V cm The positive and negative polarities are set by the maximum available current flowing through the first and second sets of transistors 210, 212, 214, 216 in one embodiment. The peaking gain of the CTLE 200 (i.e., the highest amplitude of the gain curve of the linear equalizer) can be adjusted by adjusting the DC component V cm To program, the DC component V cm is received at the input 208 of the CTLE 200 and applied to the first and second sets of transistors 210, 212, 214, 216. The output signal includes a DC component or bias V cm,out and the output data signal component V out In some embodiments, CTLE 200 includes a continuous time linear equalizer system that can attenuate the input signal V cm +V in The low-frequency signal component of the input signal V is amplified at about the Nyquist frequency cm +V in component, and filter out the input signal V cm +V in of higher frequency.

[0026] In some embodiments, the transistors in each group of transistors 210, 212, 214, 216 have the same structure or are identical. In an embodiment, the transistors in each group of transistors 210, 212, 214, 216 are of the same type, have the same design specifications, have the same size, and are made of the same substrate material with the same processing technology. For example, the transistors in each group of transistors 210, 212, 214, 216 are manufactured in batches of the same model. In some embodiments, the transconductance g m1 Equivalent to transconductance g m2 .exist Figure 2In the depicted embodiment, the gate terminals or base terminals of the transistors in each group of transistors 210, 212, 214, 216 are connected together. Specifically, the gate terminals or base terminals of the first group of transistors 210, 212 are connected together and connected to the input terminal 208, while the gate terminals or base terminals of the second group of transistors 214, 216 are connected together and connected to the input terminal 208. Figure 2 In the depicted embodiment, the peaking gain of the CTLE 200 can be adjusted by adjusting the DC component V cm To program, the transconductance of at least one transistor in the first and second groups of transistors 210, 212, 214, 216 changes.

[0027] The resistor 218 is electrically connected to the power supply voltage Vdd, the output terminal 206, and the transistors 210, 214. The first and second degeneration impedances 202, 204 are electrically connected between the first and second groups of transistors 210, 212, 214, 216 and at least one fixed voltage (e.g., ground). The first and second degeneration impedances 202, 204 may be electrically connected between the emitter terminals or source terminals of the first and second groups of transistors 210, 212, 214, 216 and the fixed voltage (e.g., ground). For example, if the first and second groups of transistors 210, 212, 214, 216 are implemented as bipolar junction transistors (BJTs), the first and second degeneration impedances 202, 204 are electrically connected between the emitter terminals of the first and second groups of transistors 210, 212, 214, 216 and the fixed voltage (e.g., ground). In another example, if the first and second sets of transistors 210 , 212 , 214 , 216 are implemented as field effect transistors (FETs), the first and second degeneration impedances 202 , 204 are electrically connected between source terminals of the first and second sets of transistors 210 , 212 , 214 , 216 and ground.

[0028] Two resistors R with impedances 202 and 204 E0 , R E1 , R E2 , …, R Ex Always match. In some examples, the two impedances 202, 204 are R E1 The coupled switches are controlled by the same control signal (CTRL). Similarly, the R E2 The coupled switches are controlled by the same signal (CTRL). The control signal CTRL may include a plurality of lines, the number of which is equal to the number of switches in the degenerate impedance circuit 202, and each line drives two switches. For example, one line may drive the R E2 For example, the two impedances 202, 204 may have the same number of switchable resistors RE2 ..R Ex , and is configured to connect or disconnect a specific resistor (e.g., R E2 ) and is configured to connect or disconnect a specific resistor (e.g., R E2 ) are controlled by the same signal. Therefore, if the resistor R in impedance 202 E2 At time T connected to ground, the resistor R in impedance 204 E2 Also connected to ground at time T. In another example, the first degenerate impedance 202 and the second degenerate impedance 204 are configured so that the resistive impedance portion in the first degenerate impedance 202 and the second degenerate impedance 204 remains the same at time T. The sum of the two currents iE1 and iE2 flowing through the first degenerate impedance 202 and the second degenerate impedance is constant. Through the switchable resistive components in the impedance 202 and the impedance 204, the CTLE 200 can change its DC gain independently of its equalizer gain. The DC gain of the CTLE 200 is controlled by switching on / off the resistor elements in the first degenerate impedance 202 and / or the second degenerate impedance 204. In some examples, an external controller (not shown) can be used to drive the switches in the first degenerate impedance 202 and the second degenerate impedance 204. On the other hand, the equalizer gain of the CTLE 200 is controlled by the DC bias (Vcm) of the input. The current iE1 or iE2 changes when Vcm changes. The signal output content degraded by the first degeneration impedance 202 in the iE1 path has zero or minimum peaking gain. The output content degraded by the second degeneration impedance 204 in the iE2 path has maximum peaking gain. By controlling the percentage of iE1 or iE2 to the sum of iE1 and iE2, the CTLE 200 can have an equalizer gain between the minimum equalizer gain and the maximum equalizer gain achieved by two paths (e.g., a path including the first degeneration impedance 202 and a path including the second degeneration impedance 204).

[0029] Figure 3 A fully differential CTLE 300 is shown. The CTLE 300 includes an input port 306. A bias voltage V is applied to the input signal. cm , and CTLE 300 generates V at the output port out The fully differential CTLE 300 is an electrical double of the CTLE 200. The CTLE 300 includes transistor pairs 308, 310, 312, 314. Thus, the CTLE 300 includes four transistor pairs, each transistor pair including transistors g m1 , g m2 The transistor g in the transistor pair 308 and 310 is m1The bases of the transistors g and g in the transistor pair 308 and 310 are driven by the same first terminal of the first input signal. m2 The base of transistor g is driven by the same second terminal of the first input signal. Similarly, transistor g in transistor pair 312, 314 m1 The base of the transistors g in the transistor pair 312, 314 is driven by the same first terminal of the second input signal, and the transistors g in the transistor pair 312, 314 are driven by the same first terminal of the second input signal. m2 The bases of transistors g in all transistor pairs 308, 310, 312, 314 are driven by the same second terminal of the second input signal. m1 , g m2 The emitter of is coupled to ground, and the coupling path to ground carries the same current I eq .

[0030] CTLE 300 includes a first degeneration impedance 302 coupled between the emitter of transistor pair 308 and the emitter of transistor pair 314. First degeneration impedance 302 includes a resistor R E0 , R E1 , R E0 The first degenerate impedance 302 also includes a pair of resistors coupled to each other via a switch. A plurality of such resistor pairs are connected in series with the resistor R E0 , R E1 , R E0 The switch can be turned on and off to adjust the DC gain of the CTLE 300. The CTLE 300 also includes a second degeneration impedance 304. The second degeneration impedance 304 is similar in structure to the first degeneration impedance 302, but a capacitor Ce is coupled in parallel with each of the RE0 resistors. In some examples, the R E1 The coupled switches are controlled by the same control signal CTRL as described above. Similarly, the R E2 The coupled switches are controlled by the same signal. For example, the two impedances 302, 304 may have the same number of switchable resistors R E2 ..R Ex , and is configured to connect or disconnect a specific resistor (e.g., R E2 ) and is configured to connect or disconnect a specific resistor (e.g., R E2 ) are controlled by the same signal. Therefore, if the resistor R in impedance 302 E2 At time T connected to ground, the resistor R in impedance 304 E2 Also connected to ground at time T.

[0031] CTLE 300 further includes a capacitor Ce2, an inductor Le2, and a capacitor Ce2 in series (where the values ​​of components denoted by the same reference numerals are the same or substantially the same). In a second degeneration impedance 304, Ce2, Le2, Ce2 in series are coupled with a resistor RE1. The second degeneration impedance is coupled between the emitters of the transistors in transistor pair 310 and transistor pair 312. The output port is coupled to the collector of transistor gm2 in transistor pair 310 and the collector of transistor gm2 in transistor pair 312. It can be noted that Figure 2 and 3 The BJT shown in FIG. 1 can be replaced by an NMOS transistor. The CTLE 200 and CTLE 300 discussed above are capable of adjusting the DC gain independently of the equalizer gain, such as Figure 1 As shown. Alternatively, the entire architecture can use CMOS PNP BJTs instead of NPN BJTs, where the terminals of resistor 218 will be grounded. In this case, the PNP BJTs can be replaced by PMOS transistors.

[0032] Although the operations of the methods are shown and described in a particular order herein, the order of operations of each method may be changed so that certain operations may be performed in reverse order, or so that certain operations may be performed at least partially simultaneously with other operations. In another embodiment, instructions or sub-operations of different operations may be implemented in an intermittent and / or alternating manner.

[0033] It should also be noted that at least some operations of the methods described herein may be implemented using software instructions stored on a computer usable storage medium for execution by a computer.As an example, an embodiment of a computer program product includes a computer usable storage medium for storing a computer readable program.

[0034] The computer usable or computer readable storage medium may be an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system (or device or means). Examples of non-transitory computer usable and computer readable storage media include semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk and optical disk. Current examples of optical disks include compact disk with read-only memory (CD-ROM), compact disk with read / write (CD-R / W) and digital video disk (DVD).

[0035] Alternatively, embodiments of the present invention may be implemented entirely in hardware or in an implementation scheme comprising both hardware and software elements. In embodiments using software, the software may include but is not limited to firmware, resident software, microcode, etc.

[0036] Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. The scope of the invention is to be defined by the claims appended hereto and their equivalents.

Claims

1. A continuous time linear equalization (CTLE) circuit, characterized in that: include: Input port; Output port; a first differential transistor pair coupled to the input port and the output port; a second differential transistor pair; a first degeneration impedance circuit coupled between the first differential transistor pair and ground, wherein the first degeneration impedance includes a switchable component to change an impedance of the first degeneration impedance circuit; as well as a second degeneration impedance circuit coupled between the second differential transistor pair and ground, wherein the second degeneration impedance includes a switchable component to change an impedance of the second degeneration impedance circuit, wherein a resistive portion of the impedance of the first degeneration impedance circuit is equal to the impedance of the second degeneration impedance circuit; The switchable component of the first degeneration impedance circuit and the switchable component of the second degeneration impedance circuit are driven by a same control signal.

2. The CTLE circuit according to claim 1, characterized in that: The switchable component in the first degeneration impedance and the switchable component in the second degeneration impedance are configured to be driven such that a value of a resistive portion of the first degeneration impedance is equal to a value of the resistive portion of the second degeneration impedance.

3. The CTLE circuit according to claim 1, characterized in that: The second degeneration impedance is a second-order or third-order degeneration impedance including a capacitor, a resistor, and an inductor.

4. The CTLE circuit according to claim 1, characterized in that: The first degeneration impedance circuit includes a plurality of resistors coupled in parallel to each other.

5. The CTLE circuit according to claim 4, characterized in that: Each resistor of the plurality of resistors is coupled to an externally controllable switch to electrically remove the each resistor of the plurality of resistors from the first degenerative impedance circuit.

6. The CTLE circuit according to claim 1, characterized in that: The second degenerate impedance circuit includes a plurality of resistors coupled in parallel to each other.

7. The CTLE circuit according to claim 1, characterized in that: The first degeneration impedance circuit and the second degeneration impedance circuit include an equal number of switchable resistors.

8. The CTLE circuit according to claim 1, characterized in that: The switchable components of the first and second degeneration impedance circuits are operable by a control signal comprising a number of control lines equal to the number of switchable components in the first degeneration impedance circuit.

9. A continuous time linear equalization (CTLE) circuit, characterized in that: include: Input port; Output port; a first differential transistor pair coupled to the input port; a second differential transistor pair coupled to the input port and the output port; a third differential transistor pair coupled to the input port and the output port; a fourth differential transistor pair coupled to the input port and the output port; a first degeneration impedance circuit coupled between an emitter or source of the first differential transistor pair and an emitter or source of the fourth differential transistor pair, wherein the first degeneration impedance comprises a switchable component to change an impedance of the first degeneration impedance circuit; as well as a second degeneration impedance circuit coupled between an emitter or source of the second differential transistor pair and an emitter or source of the third differential transistor pair, wherein the second degeneration impedance comprises a switchable component to change an impedance of the second degeneration impedance circuit, wherein the resistive portion of the impedance of the first degeneration impedance circuit is equal to the impedance of the second degeneration impedance circuit; The switchable component of the first degeneration impedance circuit and the switchable component of the second degeneration impedance circuit are driven by a same control signal.

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