On-die ECC with error counters and internal address generation

Abstract

The present invention relates to on-die ECC using error counters and internal address generation, and to a memory subsystem implementation for managing error correction information. A memory device performs error detection internally on a range of memory locations and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating the difference between the internal count and a baseline number of errors preset for the memory device. The memory device is capable of providing the error result to an associated host of the system so as to expose only the accumulated number of errors without exposing internal errors from before being incorporated into the system. The memory device is enabled to generate an internal address to execute a command received from a memory controller. The memory device is enabled to reset the counter after a first pass through a storage area in which errors are counted.

Description

[0001] This application is a divisional application, and the invention name of the parent case is "ECC on the die using error counter and internal address generation", the application date is May 27, 2016, and the application number is 201680024940.1.

[0002] Related use cases

[0003] This application is a non-provisional patent application based on U.S. Provisional Patent Application No. 62 / 168,828 filed on May 31, 2015. This application claims the priority benefit of that provisional application. The provisional application is incorporated herein by reference. Technical Field

[0004] Embodiments of the present invention relate generally to memory devices, and more particularly to memories providing selective internal error correction information.

[0005] Copyright Notice / License

[0006] Portions of the disclosure of this patent document may contain material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. The copyright notice applies to all data described below and in the drawings and to any software described below: Copyright © 2015, Intel Corporation. All rights reserved. Reproduction without permission Background Art

[0007] Computing devices use memory devices to store data and code for processors to run their operations. As memory devices decrease in size and increase in density, they encounter more errors during processing, which is called a yield problem. Therefore, memory devices encounter increased bit failures even with modern processing technology. To mitigate bit failures, modern memory devices provide internal error correction mechanisms, such as ECC (error correction code). ECC data is generated internally in the memory device and used internally in the memory device. Internal error correction in the memory device can be used as a supplement to any system-wide error correction or error mitigation that the system is configured to use in the data exchange between the memory device and the memory controller.

[0008] SBEs (single bit errors) corrected by a memory device appear to a memory controller or host system as if no errors exist. Therefore, if additional errors accumulate in a memory device after manufacturing, the memory device will continue to perform ECC, and the increased number of failures of the memory device may not be visible to the host system. Memory devices traditionally require identification of information related to internal error correction to provide information related to error accumulation. However, exposing error correction information can provide proprietary information related to process and manufacturing, such as internal error information or details related to internal error correction. There is currently no mechanism to reveal information related to error accumulation within a memory device without exposing information related to internal error correction. Summary of the invention

[0009] A synchronous dynamic random access memory (SDRAM) device according to a first aspect of the present invention comprises:

[0010] a memory array; and

[0011] An error checking and correction (ECC) circuit is configured to perform ECC operations on a plurality of rows of a memory array, the ECC circuit comprising a counter configured to accumulate an error count to be incremented in response to detecting an error in any of the plurality of rows, wherein the ECC circuit is configured to generate an error result as a difference between the accumulated error count and a non-zero error threshold to be reached before incrementing the error result.

[0012] A system having a memory device according to a second aspect of the present invention comprises:

[0013] a memory controller; and

[0014] A plurality of synchronous dynamic random access memory (SDRAM) devices coupled in parallel, wherein the SDRAM devices include:

[0015] a memory array; and

[0016] an error checking and correction (ECC) circuit to perform ECC operations on a plurality of rows of the memory array, the ECC circuit including a counter to accumulate an error count to be incremented in response to detecting an error in any of the plurality of rows, wherein the ECC circuit is to generate an error result as a difference between the accumulated error count and a non-zero error threshold to be reached before incrementing the error result;

[0017] Wherein the SDRAM device provides internal error correction for data independently of error correction based on parity bits provided by the memory controller.

[0018] A method for managing error correction information in a memory according to a third aspect of the present invention comprises:

[0019] Initiating an error checking and correction (ECC) operation on a plurality of rows of a memory array using an ECC circuit within a synchronous dynamic random access memory (SDRAM) device;

[0020] accumulating an error count to be incremented in response to detecting an error in any of the plurality of rows; and

[0021] An error result is generated as the difference between the accumulated error count and a non-zero error threshold to be reached before the error result is incremented. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The following description includes a discussion of the accompanying drawings with descriptions given by way of example of implementations of embodiments of the present invention. The accompanying drawings should be understood as being by way of example rather than by way of limitation. As used herein, references to one or more "embodiments" are to be understood as describing specific features, structures and / or characteristics included in at least one implementation of the present invention. Therefore, phrases such as "in one embodiment" or "in an alternative embodiment" that appear herein describe various embodiments and implementations of the present invention, and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0023] Figure 1 is a block diagram of an embodiment of a system having a memory device capable of exposing internal error correction bits for use by an external memory controller.

[0024] Figure 2 is a block diagram of an embodiment of a system having a memory device capable of exposing internal error correction bits for use by an external memory controller.

[0025] Figure 3 is a block diagram of an embodiment of a system in which a memory device generates internal addresses for executing received commands.

[0026] Figure 4 is a flow chart of an embodiment of a process for managing internal ECC information, including generating internal addresses.

[0027] Figure 5 is a block diagram of an embodiment of a computing system in which a memory device that generates internal addresses can be implemented.

[0028] Figure 6 is a block diagram of an embodiment of a mobile device in which a memory device capable of generating internal addresses is implemented.

[0029] Below is a description of certain details and implementations, including a description of the accompanying drawings, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. DETAILED DESCRIPTION

[0030] As described herein, a memory subsystem implements management error correction information. The memory device performs error correction internally on a range of memory locations and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating the difference between the internal count and a baseline number of errors preset for the memory device. The memory device is capable of providing the error result to an associated host of the system so as to expose only the accumulated number of errors without exposing internal errors from before being incorporated into the system. In one embodiment, the memory device is capable of generating an internal address to execute a command received from a memory controller. In one embodiment, the memory device is capable of resetting the counter after a first pass through a storage area in which errors are counted.

[0031] In one embodiment, a memory device generates an internal address to execute a command received from a memory controller. The memory device performs error correction to correct single-bit errors (SBEs) in accessed data and generates an error count indicating the number of corrected SBEs exceeding a baseline number of SBEs preset for the memory device. The memory device provides the error count to the memory controller so as to expose only the number of SBEs accumulated after manufacturing. In one embodiment, the memory device is capable of resetting the counter after a first pass through a storage area in which errors are counted.

[0032] References to memory devices can apply to different memory types and specifically to any memory having a bank architecture. Memory devices generally refer to volatile memory technology. Volatile memory is a memory whose state (and therefore the data stored thereon) is uncertain when power is interrupted to the device. Non-volatile memory refers to a memory whose state is determined even when power is interrupted to the device. Dynamic volatile memory requires refreshing the data stored in the device to maintain the state. An example of dynamic volatile memory includes DRAM (dynamic random access memory) or some variants such as synchronous DRAM (SDRAM). The memory subsystem described herein may be compatible with a variety of memory technologies, such as DDR4 (DDR version 4, an initial specification released by JEDEC in September 2012), LPDDR4 (Low Power Double Data Rate (LPDDR) version 4, JESD209-4, initially released by JEDEC in August 2014), WIO2 (Wide I / O 2 (WideIO2), JESD229-2, initially released by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235, initially released by JEDEC in October 2013), DDR5 (DDR version 5, currently being discussed by JEDEC), HBM2 (HBM version 2, currently being discussed by JEDEC), and / or other technologies derived or extended from such specifications.

[0033] Current designs of DRAM devices for technologies such as WIO2 and LPDDR4 include extra bits internally to store error correction data (e.g., ECC (error correction code) information). For internal ECC, DRAMs detect and correct single-bit errors (SBE) internally using single error correction (SEC) which utilizes 8 dedicated ECC bits per 128 data bits. The external data transfer size and internal prefetch size are both 128 bits in the case of LPDDR4 and WIO2. However, for internal ECC, these designs traditionally lack a method to track error accumulation in the DRAM, which makes the device prone to accumulating errors until the number of errors overwhelms the ability of the on-die or internal ECC to correct the SBE. If too many errors accumulate, the device will pass data with uncorrected errors to the memory controller, causing a failure.

[0034] If the DRAM does not perform internal error correction, the system may be able to perform system-level error correction, but all errors within the DRAM will be visible. Exposing information related to all errors will expose internal error information, which can reveal information that is proprietary to the memory device manufacturer and is generally considered not to be expected to be shared within the industry. As described herein, the system can provide a relative error count to indicate how many errors have been accumulated since the memory device was shipped or deployed in the system. Relative errors as described herein can indicate how many errors have been accumulated over a baseline number of errors. The baseline number of errors of the memory device is the number of errors detected during manufacturing testing. The accumulation of errors can be determined as by counting the total number of errors compared to the baseline number. However, it should be noted that even the internal errors detected during manufacturing can be proprietary information, and the device manufacturer can configure this number internally and configure the memory device to only expose the accumulated difference.

[0035] Typically, during normal operation, a DDR4 DRAM device implemented for internal ECC does not signal that a single-bit error has been corrected. In one embodiment, during manufacturing, the total number of single-bit errors on the device is permanently stored in the memory device. For example, the number of errors can be stored in an error threshold register. The stored error threshold count represents the total number of single-bit errors detected during manufacturing testing. In one embodiment, the error threshold register is not directly readable by a user and / or host system. In one embodiment, the memory device includes an error counter that counts SBEs together with a comparator that compares the result of the error counter to the error threshold register.

[0036] In one embodiment, the memory device includes an address generator to generate an internal address for the received command. Therefore, the memory device can control which locations of the memory device are to be accessed and when to access. The memory device can then internally manage error detection and count the number of errors relative to the baseline number of errors. The internally generated address enables the memory device to internally reset the error accumulation counter and prevent the internal error count from continuing to increase. Without resetting the counter after the first pass through the memory space, the user can potentially run the error test twice (where the errors continue to accumulate), and then simply divide the number of errors in half to expose information related to internal errors and internal error correction. By resetting the counter, each time the error test is run, the same number of errors will be revealed, even when running continuously.

[0037] In one embodiment, the error counter is cleared during reset. In one embodiment, the error counter is enabled by setting a mode register bit (e.g., MRx bit A[y]) and is initially cleared. Once enabled, the counter can increment for each read that detects a single-bit error. A single pass through the array is allowed by only allowing the DRAM to generate addresses for reading the array. Once a single pass through all memory locations is completed, in one embodiment, the control logic reads the relative error count result and resets the counter. In one embodiment, the relative error count can be stored in a multi-function register, which can then be read out by the host (e.g., a memory controller). For example, the memory device can store the relative error count in a multi-function register (e.g., MPR3, page 3 register). In one embodiment, the register or other storage location includes a count representing the difference between the number of errors detected since the register was enabled and the stored error count. In one embodiment, in addition to reporting the accumulated errors, the memory device can also report the address of one or more rows containing the highest number of errors. In one embodiment, the memory device can report how many errors are contained in the row with the highest number of errors. In one embodiment, an on-die or DRAM internal counter can generate an internal address for a read error pass through a memory resource or memory device array. At the beginning of a read error pass through the array, the relative error count result register can be cleared. After a pass through the array, the relative count can be read out from the DRAM. In one embodiment, if a second pass is attempted, the error result register is cleared before the second pass begins.

[0038] Figure 1 1 is a block diagram of an embodiment of a system having a memory device that can expose internal error correction bits for use by an external memory controller. System 100 includes elements of a memory subsystem in a computing device. Host 110 represents a host computing platform that runs an operating system (OS) and applications. The OS and applications run operations that cause memory accesses. Host 110 includes a processor or processing unit that can be a single-core or multi-core processor. System 100 can be implemented as a SOC or implemented using independent components. When multiple memory devices 120 are included in system 100, each memory device can manage its internal ECC independently from the host or from other memory devices.

[0039] Memory controller 112 represents control logic that generates memory access commands in response to the execution of operations by (one or more) processors. In one embodiment, system 100 includes multiple memory controllers. In one embodiment, system 100 includes one or more memory controllers per channel, where the channels are coupled to access multiple memory devices. Each channel is a separate access path to the memory, so multiple different memory accesses can occur in parallel on different channels. In one embodiment, memory controller 112 is a component of host 110, such as logic implemented on the same die or package space as the host processor. Therefore, the memory controller can be implemented as a component of the same die as the host processor, or coupled to the host processor in the system on a chip (SoC) configuration.

[0040] Memory devices 120 represent memory resources of system 100 and can be, for example, DRAM devices. Memory devices 120 each include a plurality of memory arrays 122. Memory arrays 122 represent logic in which memory devices 120 store data bits. Memory devices 120 include I / O logic 126, which represents interconnect logic that enables memory devices to be coupled to memory controller 112. I / O logic 126 can include a command / address bus (commonly referred to as a C / A bus, CMD / ADDR bus, or ADD / CMD bus). I / O logic 126 can also include a data bus and other signal lines. I / O logic 126 can include signal lines, connectors, drivers, transceivers, termination controls, and / or other logic that enables communication between a memory controller and a memory device.

[0041] In one embodiment, the memory device 120 includes an ECC 124, which represents logic and memory that implements internal error correction. Thus, the ECC 124 represents the ability of the memory device 120 to generate and use internal error correction bits. In one embodiment, the ECC 124 is an integral part of an internal controller within the memory device 120 (not specifically shown). Such an internal controller controls the operation of the memory device, such as the receipt and processing of commands and the execution of commands, including controlling the timing of the operation of executing commands and returning data in response to requests from a memory controller (external to the memory device). In one embodiment, the ECC 124 can be implemented in whole or in part as a circuit separate from the internal controller. In one embodiment, the ECC 124 enables the memory device 120 to perform reads of various memory locations in a range of addresses and detect and correct SBEs, and increment an error count for each SBE corrected.

[0042] In one embodiment, the memory controller 112 generates a command or request to count the ECC to determine the accumulated errors from the memory device 120. For clarity in the description, it is considered that the ECC 124 handles such requests and can generate counts in response to such requests. The ECC 124 can cause the memory to perform a series of operations to detect errors in response to an error test command received from the memory controller. For example, the ECC 124 can include or have access to a counter that is incremented to track detected errors in the read memory location. As described herein, the memory device 120 can generate a sequence run through the memory locations of the memory space or a range of memory address locations to be tested for errors.

[0043] In one embodiment, ECC 124 determines the number of errors in the memory space and generates a count of corrected errors. In one embodiment, ECC 124 generates a relative error count by calculating the difference between the number of detected errors and a known number of errors preset for the memory device before deployment. For example, the preset errors can be a threshold or baseline number generated during manufacturing testing to detect the number of errors present in the device during manufacturing. In one embodiment, ECC 124 includes or has access to comparator logic that can calculate the difference based on the threshold.

[0044] In one embodiment, when the ECC 124 receives successive commands to perform error testing, it will determine when the entire memory space of the memory array has been tested and can reset the error count. Thus, each time an error check is performed, the ECC 124 can restart the error count, and the difference between the generated count and a preset number of threshold or reference numbers indicating errors for the device will also restart each time. In one embodiment, the ECC 124 can also reset the error count in response to a start condition when the memory subsystem is reset.

[0045] Figure 2 is a block diagram of an embodiment of a system having a memory device capable of exposing internal error correction bits for use by an external memory controller. System 200 is Figure 1 1. The system 200 illustrates an example of an embodiment of the system 100. The system 200 illustrates address generation logic 240 within a memory device 220 that generates addresses for internal operations in response to commands received from a memory controller 210. The memory device 220 and the memory controller 210 communicate via an I / O interface (not specifically shown) between the devices.

[0046] The address generation 240 can include an address counter that is used by an internal controller (not specifically shown) within the memory device 220 to determine which address space to address an operation, such as a read to detect an error. Traditionally, the memory controller generates the address for ECC testing, and the memory device simply runs the command provided at the address indicated by the memory controller. However, with the address generation 240 within the memory device 220, the memory controller can simply generate the command or request for the ECC test and allow the memory device itself to generate the address internally. The address generation 240 can include a mechanism (e.g., a counter) to track the addresses being tested. Therefore, the memory device itself can manage the error correction testing.

[0047] The memory device 220 includes a data storage device 222, which represents a storage space in the memory device 220, where the memory device writes data received from the memory controller 210 and accesses stored data to send to the memory controller 210. In one embodiment, the memory device 220 includes ECC logic 230. ECC logic 230 represents logic used by the memory device to calculate error correction. For example, the ECC logic 230 can enable the memory device 220 to detect and correct SBEs for data taken from memory locations within a range of addresses being tested. The ECC logic 230 can represent the application of error correction within the memory device to control from within the memory device 220 to outside the memory controller 210. The ECC logic 230 can be implemented at least partially within a processor device, such as by an internal controller of the memory device 220. In one embodiment, the ECC logic 230 is implemented in full or in part within a circuit separate from the internal controller.

[0048] In one embodiment, the ECC control logic 230 includes or uses information stored in the memory 220. More specifically, the ECC control logic 230 can use a threshold 232 that represents a baseline number of errors for the memory device 220. In one embodiment, a BIOS (basic input / output system) or other logic can determine the baseline number of errors and write the number for permanent storage in a register or other storage location in the memory device 220. By using the threshold 232, the ECC control logic 230 can generate an error output that indicates the number of accumulated errors without exposing the baseline number. For example, the error output can indicate the number of corrected SBEs that exceeds a baseline number of SBEs preset for the memory device.

[0049] In one embodiment, the ECC control logic 230 includes or uses a counter 234, which is a counter that indicates how many errors are present (e.g., how many SBEs are detected and corrected) in the data storage device 222. The counter 234 can be reset by the ECC control logic 230 on each pass through the data storage space to determine how many errors are present. Thus, the counter 234 can accumulate a count for each error detected, but will not continue to accumulate errors once the entire storage space has been checked. In one embodiment, checking the storage space again will cause the ECC control logic 230 to determine that the address generator 240 has reached the maximum address of the storage space, and thus will reset the counter 234 in response to detecting that the counter has rolled over. The counter rolls over when the address generator 240 completes all addresses and returns to the starting address.

[0050] In one embodiment, ECC control logic 230 can generate an error output, which includes an indication of the row with the highest number of accumulated errors. Therefore, in one embodiment, ECC control logic 230 accumulates errors on a per-row basis and identifies the row with the highest number of errors. For example, counter 234 can include multiple counters. Counter 234 can include counters for each row, all of which can be totaled to obtain the total number of detected errors. Counter 234 can include a global counter that accumulates all errors of all rows and a row counter that is reset at the end of each row. This independent row count can be compared with the highest row count, and if the count exceeds the current highest count, the new count can be stored in a storage location, and the address of the row can also be stored. In one embodiment, if the count is the same as the highest count, the count will not be changed, but multiple row addresses will be stored. When providing an error result to memory controller 210, ECC control logic 230 can report the total number of accumulated errors and the indication of the row with the highest error count. Reporting the row with the highest error count can include reporting the count of the row and the address of one or more rows with the highest count. In one embodiment, reporting the row with the highest error count includes reporting the row address instead of a count of the number of errors.

[0051] In one embodiment, the memory device 220 includes a register 224, which represents one or more storage locations or registers where the ECC control logic 230 can store error counts and / or error reporting data. For example, the ECC control logic 230 can record the total number of accumulated errors that exceed a threshold of the memory device 220 in the register 224. In one embodiment, the register 224 includes a mode register or a multi-function register or other storage location. In one embodiment, the register 224 can include or point to other storage locations storing row address information indicating one or more rows with the highest number of errors. In one embodiment, the register 224 represents a storage device within the memory device 220 accessible to the memory controller 210, which enables the memory controller 210 to access the reporting data. In one embodiment, the memory device 220 sends the reporting data to the memory controller 210.

[0052] In one embodiment, the memory controller 210 includes ECC 212, which represents ECC logic for use at the system level in the system 200. It will be understood that the ECC control logic 230 is logic within each memory device coupled to the memory controller 210, which ECC 212 represents logic within the memory controller 210 that performs ECC on data received from the respective memory devices. By performing ECC operations on the data and then passing the data to the memory controller, the results of the operations of the ECC control logic 230 can be transparent to the memory controller 210. In one embodiment, the ECC 212 is logic included within the circuitry of the memory controller 210. In one embodiment, the ECC 212 is logic external to the memory controller circuitry that is accessible to the memory controller and can perform one or more operations related to ECC within the system 200. For example, in one embodiment, the ECC 212 can include ECC circuitry in a processor or SoC coupled to the memory controller 210.

[0053] However, the memory controller 210 can also provide ECC for the system 200 that is based not only on data from the memory device 220, but also on data from multiple connected memory devices. Thus, not only can the error count from the memory device 220 provide information about the useful life of the memory device itself as described herein, but it can also operate as metadata for the memory controller 210 for system-level ECC implementations. By understanding the corrected errors from the memory device level, the memory controller can adjust its error correction operations.

[0054] Figure 33 is a block diagram of an embodiment of a system in which a memory device generates an internal address for executing a received command. System 300 is one embodiment of ECC control logic in accordance with system 100 and / or system 200. It will be appreciated that system 300 can be an integral part of the logic of the system and can include additional logic (not specifically shown). For example, system 300 can represent logic specifically for exposing errors exceeding a threshold without specifically illustrating logic used to perform error detection or receive and process commands.

[0055] In one embodiment, the ECC control logic receives a command to initiate an ECC test. In one embodiment, the ECC control logic is an integral part of an on-die controller within a memory device. The controller controls the operation of the memory device, including generating internal commands and / or control signals to cause the operations required to execute the commands received by the memory device. The control logic can generate a reset signal at the start and pass the signal to a row-column address generator 310 within the memory device. The start can be any time the device is powered on and initialized and any time the host computer system is configured to perform an ECC test to determine the number of accumulated errors. The reset signal at the start can be a binary (true / false) signal indicating whether to reset the counter.

[0056] In one embodiment, the on-die controller can generate an increment signal. The increment signal can signal a subsequent operation about the increment of an operation. In one embodiment, the on-die controller provides the increment signal as an input to the address generator 310. The address flip detector 320 can determine when the increment of the counter causes the counter to restart at the initial address. The address flip detector 320 can generate an output indicating a flip. In one embodiment, the output is a binary (true / false) signal indicating a flip condition.

[0057] In one embodiment, the address flip detector 320 provides its output to the XOR logic 330. In one embodiment, the ECC control logic also provides a start reset signal as an input to the XOR logic 330. The XOR logic 330 is capable of performing an XOR ("exclusive OR") operation on two input signals and outputs a binary output when either condition is true. In one embodiment, the system 300 resets the error counter 340 if either condition is true. Thus, consider the following conditions as examples: wherein if the system is initialized, the counter is reset; or if the address of the internal address generator flips to start again at the initial address, the counter is reset.

[0058] In addition to the reset operation, the error counter 340 can receive an error detection signal as an input. Error detection logic (not specifically shown) detects errors in memory locations and can generate a binary signal indicating the error. In one embodiment, the error counter 340 receives the error indication signal and increments the error count each time an error is detected. Thus, the error counter 340 can accumulate errors, and the system 300 can reset the error count at the start of a reset and address rollover conditions.

[0059] The error threshold 350 represents a threshold number or a baseline number of errors expected for a memory device in which the system 300 is incorporated. The error threshold 350 can be set by manufacturing testing and does not change during the useful life of the memory device. The comparator 360 can determine the difference between the error threshold 350 and the error counter 340. The count in the error counter 340 that exceeds the error threshold 350 is provided to the result register 370. It will be appreciated that by storing only the difference between the error threshold 350 and the error counter 340, the system can report only the accumulated errors without exposing information related to internal errors. In one embodiment, the result register 370 is readable by the host system to determine the number of errors accumulated over the useful life of the memory device, excluding the number of errors present at the time of manufacture of the device.

[0060] In one embodiment, the system 300 includes storage for one or more rows of data that have a highest number of errors in addition to or as part of the result register 370. In one embodiment, the system 300 stores address information for one or more rows and reports the addresses to an associated memory controller. In one embodiment, if a row is determined to have or equal the highest number of errors, the address generator 310 records the address of the row.

[0061] Figure 44 is a flow chart of an embodiment of a process for managing internal ECC information, including generating internal addresses. Process 400 enables ECC logic within a memory device to manage internal ECC information, which can be selectively exposed to an associated memory controller / host. A manufacturer manufactures a memory device (402) and performs manufacturing testing on the device (404). In one embodiment, the testing includes testing that uses internal ECC to determine the number of errors present in a new device, and can configure internal error correction for the device when it is deployed or incorporated into a computing device. The manufacturer can store the number of errors as a threshold or baseline number for the memory device (408). The manufacturer can store the number in a register or other memory or storage location within the memory device. The memory device will use the threshold number as a benchmark for determining how many errors are accumulated over the useful life of the memory device. It will be understood that each memory device can have different thresholds based on individual testing of the device.

[0062] In one embodiment, the threshold value applies to a range of memory locations to be tested. In one embodiment, the range of memory locations is the entire available address space for the memory device. In one embodiment, the range of memory locations is a subset of the available address space for the memory device. In one embodiment, during operation when the memory device is incorporated into a system, the memory device receives an access command (410). In one embodiment, such a command can include a command to perform an error test on a range of address space (e.g., the entire memory address space or a subset of the memory address space). In one embodiment, in response to the command and / or in response to initiating an error detection test, the memory device resets an address counter that generates an internal address and resets an error count (412). By resetting the error count before starting the error detection test, the memory device can prevent double count errors if the memory test is required to be performed multiple times.

[0063] In one embodiment, the memory device generates internal addresses for operations to be executed to run the requested command(s) (414). In one embodiment, the memory device determines whether an internally generated address rollover has occurred (416). In one embodiment, in response to an address rollover (the "yes" branch of 416), the memory device can reset an error count (418). If an address rollover has not occurred (the "no" branch of 416), the address has not been previously checked for errors during the current cycle of the error count. By internally generating addresses and detecting rollovers, the memory device can prevent counting the same error twice for a memory location and provide a more accurate count of errors. Thus, address rollover detection can occur each time a selected memory address space is tested.

[0064] In one embodiment, internal ECC logic within the memory device identifies and corrects the SBE in response to the requested command(s) (420). In one embodiment, the requested command is an error test command that triggers the memory device to sequence through the identified range of memory locations or through all memory locations. In one embodiment, the error test command is controlled by the memory device and the memory device reads each memory location within the range of memory locations. When reading the contents of the locations, the memory device can perform ECC on the contents and perform SBE correction using known techniques.

[0065] In one embodiment, the detection of errors is tracked on a per-row basis to determine the row or rows within the memory device that have the highest number of errors. This per-row error tracking can be achieved by using multiple counters to track the total errors and the errors per row. In one embodiment, in addition to storing the total accumulated errors, the highest number of errors per row is also stored. For example, the highest number of errors can be stored, and then a test or subsequent row can cause a comparison of the errors of the current row with the stored highest count. In one embodiment, the address information of the row or rows detected as having the highest number of errors is also stored. If the error count of the current row is equal to the highest count, the address information of the current row can be stored. If the error count of the current row is higher than the stored highest count, the count can be overwritten, and any address information can also be replaced by the address information of the current row. After passing through all rows in the range of addresses, the count should include the count of the highest number of errors per row, and can include the address information of the row or rows to which the count applies.

[0066] The ECC logic can accumulate the total number of errors each time the test is performed. Over the life of the memory device, the number of errors may increase as the device ages. In one embodiment, if the last address in the range to be tested has not been reached (the "no" branch of 422), the memory device can increment the address and repeat the test for another memory location. In one embodiment, if the last address in the range to be tested has been reached (the "yes" branch of 422), the ECC logic compares the number of SBEs corrected or detected during the operational test to a stored threshold value (which indicates the number present from the time of manufacture or the number of errors present before the memory device was incorporated into the system) (424). The ECC logic can store the difference between the currently detected errors and the threshold number (426). The stored difference can be referred to as an error result, error count, or error report.

[0067] In one embodiment, the ECC logic of the memory device stores the error results in a register accessible to the host. For example, the memory device can store the error results in a mode register, a multi-function register, or other registers or storage locations, which can be accessed by the memory controller or comparable logic of the host. If there is a difference in the count, the memory device has formed more errors, and if the number of errors becomes too large, the host system can be notified. For example, the memory device can store the difference in a register or other memory location accessible to the host device. In one embodiment, the memory device can be configured to provide the number to the host periodically. Although sharing information related to the accumulated errors in the service life of the memory device, because the memory device controls address generation and counters for error detection, it can reveal the errors accumulated since manufacturing without revealing total error information. In one embodiment, the ECC logic of the memory device also reports the address information of the row with the highest number of errors and / or the count of the errors of the row with the highest number of errors.

[0068] In one embodiment, the memory device records that completion of the test of the range of memory locations has occurred, for example, when a cycle or pass through all addresses within the range of memory locations has been completed. In one embodiment, the system resets the count of detected errors at the start or initiation of the memory subsystem. In one embodiment, the count of errors to be reset is an internal count of errors that is compared to a threshold or baseline number of errors. In one embodiment, the count of errors is an error result that can be reset from a register or memory location that stores the result.

[0069] Figure 5 5 is a block diagram of an embodiment of a computing system in which a memory device generating an internal address can be implemented. System 500 represents a computing device according to any embodiment described herein, and can be a laptop computer, a desktop computer, a server, a game or entertainment control system, a scanner, a copier, a printer, a routing or switching device, or other electronic device. System 500 includes a processor 520, which provides processing, operation management, and execution of instructions for system 500. Processor 520 can include any type of microprocessor, central processing unit (CPU), processing core, or other processing hardware to provide processing for system 500. Processor 520 controls the overall operation of system 500, and can be or include one or more programmable general or special purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or a combination of such devices.

[0070] The memory subsystem 530 represents the main memory of the system 500 and provides temporary storage for the code to be executed by the processor 520 or the data values ​​to be used in the running routine. The memory subsystem 530 can include one or more memory devices, such as read-only memory (ROM), flash memory, one or more types of random access memory (RAM) or other memory devices or a combination of such devices. Among other things, the memory subsystem 530 also stores and hosts an operating system (OS) 536 to provide a software platform for the execution of instructions in the system 500. In addition, other instructions 538 are stored and executed from the memory subsystem 530 to provide the logic and processing of the system 500. The OS 536 and instructions 538 are executed by the processor 520. The memory subsystem 530 includes a memory device 532, in which it stores data, instructions, programs or other items. In one embodiment, the memory subsystem includes a memory controller 534, which is a memory controller that generates commands and issues commands to the memory device 532. It will be understood that the memory controller 534 can be a physical part of the processor 520.

[0071] Processor 520 and memory subsystem 530 are coupled to bus / bus system 510. Bus 510 is an abstraction that represents any one or more independent physical buses, communication lines / interfaces and / or point-to-point connections connected by appropriate bridges, adapters and / or controllers. Therefore, bus 510 can include, for example, one or more of a system bus, a peripheral component interconnect (PCI) bus, a hypertransport or industrial standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (commonly referred to as "Firewire"). The bus of bus 510 can also correspond to an interface in network interface 550.

[0072] The system 500 also includes one or more input / output (I / O) interfaces 540, a network interface 550, one or more internal mass storage devices 560, and a peripheral interface 570 coupled to the bus 510. The I / O interface 540 can include one or more interface components through which a user interacts with the system 500 (e.g., video, audio, and / or alphanumeric interfaces). The network interface 550 provides the system 500 with the ability to communicate with remote devices (e.g., servers, other computing devices) over one or more networks. The network interface 550 can include an Ethernet adapter, a wireless interconnect component, a USB (Universal Serial Bus), or other wired or wireless standard-based or proprietary interface.

[0073] Storage 560 can be or include any conventional media for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, or optical disks or optical discs, or a combination. Storage 560 holds code or instructions and data 562 in a permanent state (i.e., values ​​are retained despite power interruptions to system 500). Storage 560 can be generally considered "memory," but memory 530 is operational or operating memory to provide instructions to processor 520. While storage 560 is non-volatile, memory 530 can include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to system 500).

[0074] Peripheral interface 570 can include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that are relatedly connected to system 500. A related connection is a connection in which system 500 provides a software and / or hardware platform on which operations run and with which a user interacts.

[0075] In one embodiment, the memory subsystem 530 includes internal ECC logic 580, which represents the logic for managing the internal ECC for the memory 532 according to any embodiment described herein. In one embodiment, the internal ECC 580 generates an address for performing a pass through read to perform error testing. The internal ECC 580 can generate a relative count indicating how many errors have been accumulated since the device was manufactured. Therefore, the number of errors can be exposed to show how many errors have been formed since the device was manufactured. In one embodiment, the internal ECC 580 can include logic to reset an internal counter (which provides error accumulation information).

[0076] Figure 6 600 is a block diagram of an embodiment of a mobile device in which a memory device capable of generating an internal address is implemented. Device 600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart phone, a wireless-enabled e-reader, a wearable computing device, or other mobile device. It will be understood that generally some of the components are shown, but not all of the components of such a device are shown in device 600.

[0077] The device 600 includes a processor 610 that performs the primary processing operations of the device 600. The processor 610 can include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing components. The processing operations performed by the processor 610 include the operation of an operating platform or operating system (on which applications and / or device functions run). The processing operations include operations related to I / O (input / output) with a human user or with other devices, operations related to power management, and / or operations related to connecting the device 600 to another device. The processing operations can also include operations related to audio I / O and / or display I / O.

[0078] In one embodiment, device 600 includes an audio subsystem 620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. Audio functionality can include speaker and / or headphone outputs and microphone inputs. Devices for such functionality can be integrated into device 600 or connected to device 600. In one embodiment, a user interacts with device 600 by providing audio commands (which are received and processed by processor 610).

[0079] The display subsystem 630 represents hardware (e.g., display device) and software (e.g., driver) components that provide visual and / or tactile display for user interaction with computing device. The display subsystem 630 includes a display interface 632, which includes a specific screen or hardware device used to provide display to the user. In one embodiment, the display interface 632 includes logic that is separate from the processor 610 and performs at least some processing related to the display. In one embodiment, the display subsystem 630 includes a touch screen device that provides both output and input to the user. In one embodiment, the display subsystem 630 includes a high-definition (HD) display that provides output to the user. High definition can refer to a display with a pixel density of about 100 PPI (pixels per inch) or greater, and can include formats such as full HD (e.g., 1080p), retina display, 4K (ultra-high definition or UHD), etc.

[0080] I / O controller 640 represents hardware devices and software components related to interaction with a user. I / O controller 640 is operable to manage hardware that is part of audio subsystem 620 and / or display subsystem 630. In addition, I / O controller 640 illustrates connection points for additional devices connected to device 600 through which a user can interact with the system. For example, devices that can be attached to device 600 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices for use with specific applications such as a card reader or other device.

[0081] As mentioned above, the I / O controller 640 can interact with the audio subsystem 620 and / or the display subsystem 630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the device 600. In addition, audio output can be provided as an alternative or in addition to display output. In another example, if the display subsystem includes a touch screen, the display device also acts as an input device, which can be managed at least in part by the I / O controller 640. Additional buttons or switches can also be present on the device 600 to provide I / O functions managed by the I / O controller 640.

[0082] In one embodiment, I / O controller 640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning systems (GPS), or other hardware that can be included in device 600. Input can be part of direct user interaction, as well as providing environmental input to the system to affect its operation (e.g., filtering for noise, adjusting the display for brightness detection, applying a flash to a camera, or other features). In one embodiment, device 600 includes power management 650, which manages battery power usage, charging of the battery, and features related to power saving operation.

[0083] The memory subsystem 660 includes (one or more) memory devices 662 for storing information in the device 600. The memory subsystem 660 can include non-volatile (if the power state of the memory device is not changed by interruption) and / or volatile (if the power state of the memory device is uncertain by interruption) memory devices. The memory 660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the operation of the applications and functions of the system 600. In one embodiment, the memory subsystem 660 includes a memory controller 664 (which can also be considered as an integral part of the control of the system 600, and can potentially be considered as an integral part of the processor 610). The memory controller 664 includes a scheduler that generates commands and issues commands to the memory device 662.

[0084] Connectivity 670 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable device 600 to communicate with external devices. External devices may be stand-alone devices (e.g., other computing devices, wireless access points or base stations) as well as peripherals (e.g., headsets, printers, or other devices).

[0085] Connectivity 670 can include multiple different types of connectivity. In summary, device 600 is illustrated as having cellular connectivity 672 and wireless connectivity 674. Cellular connectivity 672 generally refers to cellular network connectivity provided by a wireless operator, such as via GSM (Global System for Mobile Communications) or variations or derivatives, CDMA (Code Division Multiple Access) or variations or derivatives, TDM (Time Division Multiplexing) or variations or derivatives, LTE (Long Term Evolution - also known as "4G") or other cellular service standards. Wireless connectivity 674 refers to wireless connectivity that is not cellular, and can include personal area networks (e.g., Bluetooth), local area networks (e.g., WiFi), and / or wide area networks (e.g., WiMax) or other wireless communications. Wireless communication refers to the transfer of data using modulated electromagnetic radiation through a non-solid medium. Wired communication is performed over a solid communication medium.

[0086] Peripheral connections 680 include hardware interfaces and connectors and software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be appreciated that device 600 can be a peripheral device ("to" 682) to other computing devices as well as have peripheral devices ("from" 684) connected thereto. Device 600 typically has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) content on device 600. Additionally, a docking connector can allow device 600 to connect to certain peripherals that allow device 600 to control content output, such as to an audio-visual or other system.

[0087] In addition to proprietary docking connectors or other proprietary connection hardware, the device 600 can also make peripheral connections 680 via generic or standards-based connectors. Generic types can include Universal Serial Bus (USB) connectors (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High-Definition Multimedia Interface (HDMI), FireWire, or other types.

[0088] In one embodiment, the memory subsystem 660 includes internal ECC logic 690, which refers to logic that manages the internal ECC for the memory 662 according to any embodiment described herein. In one embodiment, the internal ECC 690 generates addresses for performing a pass through read to perform error testing. The internal ECC 690 can generate a relative count indicating how many errors have been accumulated since the device was manufactured. Therefore, the number of errors can be exposed to show how many errors have been formed since the device was manufactured. In one embodiment, the internal ECC 690 can include logic that resets the internal counter (which provides error accumulation information).

[0089] In one aspect, a method for managing error correction information in a memory includes: performing error detection within a range of memory locations within a memory device; incrementing an internal count for each error detected; generating an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device, the preset being based on the number of errors detected for the memory device prior to incorporation into a system; and providing the error result to an associated host of the system so as to expose only the number of errors accumulated after the memory device is incorporated into the system.

[0090] In one embodiment, performing error detection includes performing a series of operations to detect errors in response to an error test command received from a host. In one embodiment, performing error detection on a range of memory locations includes performing error detection on an entire memory device. In one embodiment, performing error detection also includes generating an address internally in the memory device for the range of memory locations. In one embodiment, incrementing an internal count for each error detected also includes incrementing a count for each single bit error (SBE) detection and correction performed in the range of memory locations. In one embodiment, a baseline number of errors includes a number of errors detected during manufacturing testing of the memory device. In one embodiment, providing error results also includes storing error results in a register for access by the host. In one embodiment, providing error results also includes indicating a row with a highest number of errors. In one embodiment, indicating a row with a highest number of errors includes reporting an address of the row and the number of errors in the row. In one embodiment, resetting the internal count when the range of memory locations is completed is also included.

[0091] In one aspect, a memory device with internal error correction includes: error detection logic within the memory device that performs internal error detection on a range of memory locations; a counter that increments an internal count for each error detected; comparator logic that generates an error result indicative of a difference between the internal count and a baseline number of errors preset for the memory device, the preset being based on the number of errors detected for the memory device prior to incorporation into a system; and a register that stores an error report for access by an associated host without exposing the baseline number.

[0092] In one embodiment, the error detection logic performing internal error detection is capable of performing a series of operations to detect errors in response to an error test command received from an associated host. In one embodiment, the error detection logic performing internal error detection for a range of memory locations is capable of performing error detection for the entire memory device. In one embodiment, the error detection logic performing internal error detection is capable of generating addresses within the memory device internally for the range of memory locations. In one embodiment, the counter that increments the internal error count includes a counter that increments the internal count for each single bit error (SBE) detection and correction performed in the range of memory locations. In one embodiment, the baseline number of errors includes the number of errors detected during manufacturing testing of the memory device. In one embodiment, the counter is also capable of resetting the internal count when the range of memory locations is completed. In one embodiment, error detection logic that identifies the row with the highest number of errors and a storage device that stores an indication of the row with the highest number of errors are also included. In one embodiment, the indication includes the address of the row and the number of errors in the row. In one embodiment, the storage device includes a register.

[0093] In one aspect, a system includes: a memory controller coupled to a memory device, the memory controller capable of generating error detection commands to the coupled memory device; a memory device coupled to the memory controller, the memory device including input / output (I / O) logic that receives the command from the memory controller; ECC (error correction code) logic capable of internally performing ECC within the memory device to correct single-bit errors (SBEs) detected in data retrieved from a range of memory locations, generating an error count indicating a number of corrected SBEs that exceeds a baseline number of SBEs preset for the memory device, and providing the error count to the memory controller without exposing the baseline number.

[0094] A system wherein the memory device is a memory device according to any embodiment of the memory device aspect set forth above. In one aspect, an apparatus comprises means for executing operations of a method for managing error correction information according to any embodiment of the method aspect. In one aspect, an article of manufacture comprises a computer-readable storage medium having content stored thereon, which when accessed causes execution of operations of a method for managing error correction information according to any embodiment of the method aspect.

[0095] In one aspect, a second method for managing error correction information in a memory includes: fetching data in a memory device in response to a read access request from an associated memory controller; performing internal error correction in the memory device to correct single-bit errors (SBEs) detected in the fetched data; generating an error count indicating a number of corrected SBEs that exceeds a baseline number of SBEs preset for the memory device based on manufacturing testing; and providing the error count to the memory controller so as to expose only the number of SBEs accumulated after manufacturing.

[0096] In one embodiment, the read access request is part of an error detection test routine generated by the memory controller. In one embodiment, performing internal error correction further comprises internally generating an address within the memory device for fetching data. In one embodiment, providing an error count comprises storing the error count in a register for access by the memory controller. In one embodiment, further comprises resetting the error count upon completion of a range of memory locations. In one embodiment, further comprises resetting the error count upon initiation of the memory device. In one embodiment, further comprises: identifying a row with a highest number of SBEs; and providing an indication of the row with the highest number of SBEs. In one embodiment, the indication comprises the address of the row and the number of errors in the row.

[0097] In one aspect, a memory device with internal error correction includes: logic within the memory device that fetches data in response to a read access request from an associated memory controller and performs internal error correction to correct single-bit errors (SBEs) detected in the fetched data; a counter that increments an error count indicating a number of corrected SBEs that exceeds a baseline number of SBEs preset for the memory device based on manufacturing testing; and logic that provides the error count to the memory controller so as to expose only the number of SBEs accumulated after manufacturing.

[0098] The second memory device further comprises features for operating in accordance with any embodiment of the second method aspect. In one aspect, an apparatus comprises means for performing operations of operating a method for managing error correction information in accordance with any embodiment of the second method aspect. In one aspect, an article of manufacture comprises a computer-readable storage medium having content stored thereon, which when accessed causes execution of operations of operating a method for managing error correction information in accordance with any embodiment of the second method aspect.

[0099] In one aspect, a third method for managing error correction information in a memory includes: receiving a command at a memory device from an associated memory controller; generating an address internally with the memory device to perform an operation to execute the command; performing internal error correction in the memory device to correct single-bit errors (SBEs) detected in fetched data; generating an error count indicating a number of corrected SBEs that exceeds a baseline number of SBEs preset for the memory device based on manufacturing testing; and providing the error count to the memory controller to expose only the number of SBEs accumulated after manufacturing.

[0100] In one embodiment, performing error detection includes performing a series of operations to detect errors in response to an error test command received from a host. In one embodiment, performing error detection on a range of memory locations includes performing error detection on an entire memory device. In one embodiment, performing error detection also includes generating an address within the memory device for the range of memory locations. In one embodiment, generating an error count includes incrementing a count for each single bit error (SBE) detection and correction performed in the range of memory locations that exceeds a benchmark. In one embodiment, generating an error count also includes incrementing a count for each SBE detection and correction performed, comparing the count to a benchmark, and storing only the number of SBEs that exceed the benchmark. In one embodiment, the benchmark number of errors includes the number of errors detected during manufacturing testing of the memory device. In one embodiment, providing an error count also includes storing the error count in a register for access by the host. In one embodiment, further includes resetting the error count upon completion of the range of memory locations. In one embodiment, further includes: identifying a row with a highest number of SBEs; and providing an indication of the row with the highest number of SBEs. In one embodiment, the indication includes the address of the row and the number of errors in the row.

[0101] In one aspect, a memory device with internal error correction includes: logic within the memory device to receive commands from an associated memory controller, generate addresses with the memory device internally to perform operations to execute the commands, and perform internal error correction to correct single-bit errors (SBEs) detected in fetched data; a counter to generate an error count indicating a number of corrected SBEs that exceeds a baseline number of SBEs preset for the memory device based on manufacturing testing; and logic to provide the error count to the memory controller so as to expose only the number of SBEs accumulated after manufacturing.

[0102] The third memory device further comprises features for operation in accordance with any embodiment of the third method aspect. In one aspect, an apparatus comprises means for performing operations for operating a method for managing error correction information in accordance with any embodiment of the third method aspect. In one aspect, an article of manufacture comprises a computer-readable storage medium having content stored thereon, which when accessed causes execution of operations for operating a method for managing error correction information in accordance with any embodiment of the third method aspect.

[0103] The flowcharts illustrated herein provide examples of sequences of various process actions. Flowcharts can indicate operations to be run by software or firmware routines and physical operations. In one embodiment, a flowchart can illustrate the state of a finite state machine (FSM) (which can be implemented in hardware and / or software). Although shown in a specific sequence or order, the order of actions can be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood only as examples, and the process can be performed in different orders, and some actions can be performed in parallel. In addition, in various embodiments, one or more actions can be omitted; therefore, not all actions are required in every embodiment. Other process flows are possible.

[0104] To the extent that various operations or functions are described herein, they can be described or defined as software code, instructions, configurations, and / or data. Content can be directly executable ("object" or "executable" form) source code or differential code ("incremental" or "patch" code). The software content of the embodiments described herein can be provided via a manufactured product having content stored thereon or via a method of operating a communication interface to send data via a communication interface. A machine-readable storage medium enables a machine to perform the functions or operations described, and includes any mechanism for storing information in a form accessible to a machine (e.g., a computing device, an electronic system, etc.), such as a recordable / unrecordable medium (e.g., a read-only memory (ROM), a random access memory (RAM), a disk storage medium, an optical storage medium, a flash memory device, etc.). A communication interface includes any mechanism for interfacing with any of hardwired, wireless, optical, etc. media to communicate with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface can be configured by providing configuration parameters and / or sending a signal to prepare the communication interface to provide a data signal describing the software content. The communication interface can be accessed via one or more commands or signals sent to the communication interface.

[0105] The various components described herein can be components for performing the operations or functions described herein. The various components described herein include software, hardware, or a combination of these. The components can be implemented as software modules, hardware modules, dedicated hardware (e.g., dedicated hardware, application specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hard-wired circuit systems, etc.

[0106] In addition to what is described herein, various modifications can be made to the disclosed embodiments and implementations of the present invention without departing from their scope. Therefore, the descriptions and examples herein should be interpreted as illustrative rather than restrictive. The scope of the present invention should be measured only with reference to the following claims.

Claims

1. A random access memory RAM device, comprising: Memory array; an error count register for storing error results for access by an associated memory controller; as well as an error checking and correcting ECC module for performing internal error checking and correcting ECC operations to check and correct errors for a plurality of rows of a memory array, wherein the error checking and correcting ECC module is for internally generating address information to address the plurality of rows for the internal error checking and correcting ECC operations, the error checking and correcting ECC module comprising a counter for accumulating an error count, the error count to be incremented in response to detecting the error in any of the plurality of rows, wherein the error checking and correcting ECC module is for generating an error result as a difference between the accumulated error count and a non-zero error threshold and storing the error result in the error count register, wherein the error threshold represents a preset number of errors to be excluded from the error result.

2. The random access memory (RAM) device of claim 1, wherein the ECC module is configured to perform the internal ECC operation in response to an error detection test initiated by the random access memory (RAM) device.

3. The random access memory (RAM) device according to claim 1, wherein the error checking and correcting (ECC) module is used to perform the internal error checking and correcting (ECC) operation to check and correct errors for the plurality of rows of the memory array within a bounded address space.

4. The random access memory (RAM) device of claim 1, wherein the ECC module is configured to perform the internal ECC operation on all rows of the memory array.

5. The random access memory (RAM) device of claim 1, wherein the error checking and correcting (ECC) module is configured to automatically reset the accumulated error count in response to detecting an address rollover to a previously tested address.

6. The random access memory RAM device of claim 1, wherein the error checking and correcting (ECC) module further comprises a register for storing the error result to indicate the number of errors since being deployed in a system.

7. The random access memory (RAM) device of claim 1, wherein the error threshold comprises a number of errors configured for the random access memory (RAM) device during a manufacturing process.

8. The random access memory (RAM) device of claim 1, wherein the random access memory (RAM) device comprises a volatile dynamic random access memory (DRAM) device.

9. The random access memory (RAM) device of claim 1, wherein the random access memory (RAM) device comprises a non-volatile random access memory (RAM) device.

10. A system comprising: Memory controller; as well as A plurality of random access memory RAM devices coupled in parallel, wherein the random access memory RAM device comprises: Memory array; an error checking and correcting ECC module for performing internal error checking and correcting ECC operations to check and correct errors for a plurality of rows of the memory array, wherein the error checking and correcting ECC module is for internally generating address information to address the plurality of rows for the internal error checking and correcting ECC operations, the error checking and correcting ECC module including a counter for accumulating an error count, the error count to be incremented in response to detecting an error in any of the plurality of rows, wherein the error checking and correcting ECC module is for generating an error result as a difference between the accumulated error count and a non-zero error threshold, wherein the error threshold represents a preset number of errors to be excluded from the error result; and a register for storing the error result for access by an associated memory controller; Wherein the random access memory RAM device provides internal error correction for data independently of error correction based on parity bits provided by the memory controller.

11. The system of claim 10, wherein the ECC module is configured to perform the ECC operation in response to an error detection test initiated by the random access memory (RAM) device.

12. The system of claim 10, wherein the error checking and correcting (ECC) module is to automatically reset the accumulated error count in response to detecting an address rollover to a previously tested address.

13. The system of claim 10, wherein the random access memory (RAM) device comprises a volatile dynamic random access memory (DRAM) device.

14. The system of claim 10, wherein the random access memory (RAM) device comprises a non-volatile random access memory (RAM) device.

15. The system of claim 10, wherein the memory controller is to apply error results from the plurality of random access memory RAM devices for a system level error checking and correcting (ECC) across the plurality of random access memory RAM devices.

16. The system of claim 10, further comprising one or more of the following: at least one processor communicatively coupled to the memory controller; a display communicatively coupled to the at least one processor; or A network interface is communicatively coupled to the at least one processor.

17. A memory controller comprising: a hardware interface for receiving data from a plurality of memory devices, wherein the memory devices include on-die error checking and correcting ECC circuitry for performing internal error checking and correcting ECC operations to check and correct errors for a plurality of rows of the memory devices, wherein the error checking and correcting ECC circuitry is for internally generating address information to address the plurality of rows for the internal error checking and correcting ECC operations, the error checking and correcting ECC circuitry having a counter for accumulating an error count, the error count to be incremented in response to detecting the error in any of the plurality of rows of the memory devices, wherein the on-die error checking and correcting ECC circuitry is for generating an error result for storage in an error count register of the memory devices as a difference between the accumulated error count and a non-zero error threshold, wherein the error threshold represents a preset number of errors to be excluded from the error result; as well as A system-level error checking and correcting ECC circuit is configured to perform error checking and correcting ECC operations for the plurality of memory devices, the system-level error checking and correcting ECC circuit performing error correction based on parity bits provided by the memory controller to the plurality of memory devices and error counts from the plurality of memory devices.

18. The memory controller of claim 17, wherein the hardware interface is used to send a command to a mode register of the memory device to cause the memory device to perform error checking and scrubbing with the memory device to generate address information for the error checking and scrubbing.

19. The memory controller of claim 18, wherein the memory device is to automatically reset the accumulated error count in response to detecting an address rollover to a previously tested address.

20. The memory controller of claim 17, wherein the baseline number of errors comprises a number of errors detected during manufacturing testing of the memory device.

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