Integrated circuit device, integrated system, and method for testing bonding pads

Abstract

The present invention discloses an integrated circuit device, an integrated system, and a method for testing bonding pads on an integrated circuit device. The integrated circuit device includes an integrated circuit, a plurality of first-type bonding pads, and a plurality of second-type bonding pads. Each of the plurality of first-type bonding pads is electrically connected to the integrated circuit and is configured to be electrically connected to a corresponding external integrated circuit device. Each of the plurality of second-type bonding pads is configured not to be electrically connected to the corresponding external integrated circuit device. Each of the plurality of first-type bonding pads is configured to be electrically connected to a corresponding one of the plurality of second-type bonding pads. The number of the plurality of first-type bonding pads may be greater than the number of the plurality of second-type bonding pads. Each of the plurality of second-type bonding pads may have a larger pad area for detection than each of the plurality of first-type bonding pads.

Description

Technical Field

[0001] The present invention relates to a technology for testing bonding pads, and more particularly to an integrated circuit device, an integrated system, and a method for testing bonding pads on the integrated circuit device. Background Art

[0002] Devices based on multi-die packaging or stacked die packaging can encapsulate multiple integrated circuits (ICs) in a chip carrier package to maximize capacity and performance. However, monolithic system-on-chip (SoC) integration has some disadvantages, such as high initial prototype costs and the requirement for alternative material sets.

[0003] In order to enhance overall system flexibility and reduce product design time, chiplet systems have been developed for heterogeneous integration and system-level assembly, which allows low cost and short electrical signal routing to achieve high performance. Before packaging, the IC devices on the wafer need to undergo wafer-level testing. After wafer-level testing, the wafer is cut into multiple dies, which are selected to be packaged into chiplet systems. There may be a large number of connecting wires between these selected dies. The bonding pads on the dies must be small enough to support a large number of connections. However, small bonding pads cannot be detected during wafer-level testing and the signals on the bonding pads may be unmeasurable. Therefore, it would be desirable to develop an IC device that can test the bonding pads at the wafer level before packaging to ensure that the functions work correctly. Summary of the Invention

[0004] This disclosure describes systems and techniques for testing bond pads, such as those connecting different integrated circuit devices (or dies) in a chiplet system.

[0005] One aspect of the present invention provides an integrated circuit device, comprising: an integrated circuit; a plurality of first-type bonding pads electrically connected to the integrated circuit, each of the plurality of first-type bonding pads being configured to be electrically connected to a corresponding external integrated circuit device; and a second-type bonding pad configured not to be electrically connected to the corresponding external integrated circuit device, each of the plurality of first-type bonding pads being configured to be electrically connected to the second-type bonding pad.

[0006] The second type bond pad may have a pad area greater than a pad area of ​​each of the plurality of first type bond pads.The integrated circuit may be electrically connected to each of the plurality of first type bond pads via a respective buffer.

[0007] In some embodiments, the integrated circuit device further includes a multiplexer configured to select one of the plurality of first-type bond pads based on a selection signal, such that the selected one of the plurality of first-type bond pads is electrically connected to the second-type bond pad. The integrated circuit can be configured to provide the selection signal to the multiplexer. The multiplexer can be electrically connected to corresponding electrical contacts between the integrated circuit and the respective buffers.

[0008] In some implementations, each of the plurality of first type bond pads is electrically connected to the multiplexer via a respective buffer, and the second type bond pad is electrically connected to the multiplexer via a second buffer different from the respective buffers for the plurality of first type bond pads.

[0009] The integrated circuit device may further include a plurality of latch circuits. Each of the plurality of first-type bond pads may be electrically connected to the multiplexer via a respective latch circuit among the plurality of latch circuits. The plurality of latch circuits may be configured to receive a control signal and may be configured to simultaneously latch the signals on the plurality of first-type bond pads when the control signal is in a first state, and to individually update the signals on the plurality of first-type bond pads when the control signal is in a second state different from the first state.

[0010] In some embodiments, the multiplexer is configured to: when the control signal remains in the first state, sequentially select the multiple first type bonding pads to be electrically connected to the second type bonding pads, so that the signals latched simultaneously in the multiple latch circuits are provided to the second type bonding pads in sequence.

[0011] In some embodiments, the integrated circuit device further includes a plurality of latch circuits, and each of the plurality of first-type bond pads may be configured to be electrically connected to the second-type bond pad via a respective latch circuit of the plurality of latch circuits.

[0012] Each of the multiple latch circuits can be configured to receive a switching signal and can be configured to: when the switching signal is an off signal, electrically isolate the second type bonding pad from the corresponding first type bonding pad electrically connected to the latch circuit; and when the switching signal is an on signal, use the latch circuit to electrically connect the second type bonding pad to the corresponding first type bonding pad.

[0013] In some embodiments, each of the plurality of latch circuits is configured to receive a respective control signal and is configured to: update the signal from the second-type bonding pad to the corresponding first-type bonding pad when the switching signal is the on signal and the respective control signal is in a first state, and latch the signal from the second-type bonding pad to the corresponding first-type bonding pad when the switching signal is the on signal and the respective control signal is in a second state different from the first state. The integrated circuit may be configured to provide the switching signal and the respective control signal to the plurality of latch circuits.

[0014] In some embodiments, the integrated circuit includes an input configured to be electrically connected to the second-type bond pad via a first buffer, and an output configured to be electrically connected to the second-type bond pad via a second buffer different from the first buffer.

[0015] In some embodiments, the plurality of first type bonding pads include: a plurality of output type bonding pads, each of the plurality of output type bonding pads being configured to transmit internal data from the integrated circuit to the corresponding external integrated circuit device; and a plurality of input type bonding pads, each of the input type bonding pads being configured to receive external data from the corresponding external integrated circuit device.

[0016] In some embodiments, the integrated circuit device further includes: a multiplexer, which is electrically connected to each of the multiple output type bonding pads via a corresponding electrical connection and electrically connected to the second type bonding pad via a buffer, and is configured to select one of the multiple output type bonding pads based on a selection signal, so that the selected one of the multiple output type bonding pads is electrically connected to the second type bonding pad; and a plurality of latch circuits, wherein each of the multiple input type bonding pads is configured to be electrically connected to the second type bonding pad via a respective latch circuit among the multiple latch circuits.

[0017] Each of the multiple latch circuits can be configured to: receive a respective control signal and a respective switching signal, and when the respective switching signal is an off signal, electrically isolate the second type bonding pad from the corresponding input type bonding pad electrically connected to the latch circuit; and when the respective switching signal is an on signal, use the latch circuit to electrically connect the second type bonding pad to the corresponding input type bonding pad, so that when the respective control signal is in a first state, the signal from the second type bonding pad to the corresponding input type bonding pad is updated, and when the respective control signal is in a second state different from the first state, the signal from the second type bonding pad to the input type bonding pad is latched.

[0018] The integrated circuit device may further include a plurality of second latch circuits, each of the plurality of output-type bonding pads being electrically connected to the multiplexer via a respective second latch circuit in the plurality of second latch circuits. The plurality of second latch circuits may be configured to receive a second control signal and may be configured to: simultaneously latch the signals on the plurality of first-type bonding pads when the second control signal is in the first state, and individually update the signals on the plurality of first-type bonding pads when the second control signal is in the second state. The integrated circuit may be configured to: provide the selection signal to the multiplexer; provide the respective switching signals and the respective control signals to the plurality of latch circuits; and provide the second control signal to the plurality of second latch circuits.

[0019] Another aspect of the present disclosure provides an integrated system comprising: a plurality of integrated circuit devices electrically connected together, each of the plurality of integrated circuit devices comprising: an integrated circuit; a plurality of first-type bond pads electrically connected to the integrated circuit and electrically connected to at least one other of the plurality of integrated circuit devices; and a plurality of second-type bond pads electrically not connected to the at least one other of the plurality of integrated circuit devices, wherein each of the plurality of first-type bond pads is configured to be electrically connected to a corresponding one of the plurality of second-type bond pads.

[0020] The integrated system may further include a carrier on which the integrated circuit devices are arranged. The carrier may include a wiring layer electrically contacting the first-type bond pads of the plurality of integrated circuit devices, and the carrier may include one or more pins electrically connected to one or more of the first-type bond pads of the plurality of integrated circuit devices. On each of the plurality of integrated circuit devices, the number of the plurality of first-type bond pads may be greater than the number of the plurality of second-type bond pads, and each of the plurality of first-type bond pads may have a smaller pad area than each of the plurality of second-type bond pads.

[0021] Another aspect of the present invention provides a method for testing bonding pads on an integrated circuit device, comprising: transmitting a signal from an integrated circuit to a selected first-type bonding pad among a plurality of first-type bonding pads, the selected first-type bonding pad being configured to be electrically connected to an external integrated circuit device and to transmit internal data from the integrated circuit to the external integrated circuit device; receiving a signal on a second-type bonding pad electrically connected to the selected first-type bonding pad, the second-type bonding pad being configured not to be electrically connected to the external integrated circuit device and to be electrically connected to each of the plurality of first-type bonding pads, the second-type bonding pad having a larger pad area than each of the plurality of first-type bonding pads; measuring the signal on the second-type bonding pad; and determining the condition of the selected first-type bonding pad based on the result of the measurement.

[0022] In some embodiments, the method further includes: receiving an external signal at the second type bond pad; controlling a plurality of latch circuits electrically connected to a plurality of third type bond pads to transmit the external signal from the second type bond pad to a selected third type bond pad among the plurality of third type bond pads; receiving the external signal from the selected third type bond pad via the integrated circuit; outputting an output signal corresponding to the external signal via the integrated circuit; and determining a condition of the selected third type bond pad based on a result of measuring the output signal from the integrated circuit. The selected third type bond pad can be configured to be electrically connectable to a second external integrated circuit device and to receive external data from the second external integrated circuit device. The second type bond pad can be configured not to be electrically connected to the second external integrated circuit device and to be electrically connected to each of the plurality of third type bond pads, and each of the plurality of third type bond pads has a smaller pad area than the second type bond pad.

[0023] Another aspect of the present invention provides an integrated circuit device, comprising: an integrated circuit; a first type bonding pad electrically connected to the integrated circuit, the first type bonding pad being configured to be electrically connected to an external integrated circuit device; and a second type bonding pad configured to be electrically connected to the first type bonding pad and not electrically connected to the external integrated circuit device.

[0024] The second-type bond pads may be configured to have a larger size than the first-type bond pads. The integrated circuit may be electrically connected to the first-type bond pads via a first buffer and to the second-type bond pads via a second buffer, and the second buffer may be electrically connected to an electrical connection between the integrated circuit and the first buffer.

[0025] The integrated circuit may be configured to be electrically connected to the first type bond pad via a first buffer, and the first type bond pad may be configured to be electrically connected to the second type bond pad via a second buffer. The integrated circuit device may include a latch circuit electrically connected to an electrical connection between the first type bond pad and the second buffer, the latch circuit configured to receive a control signal. The integrated circuit may be configured to provide the control signal to the latch circuit.

[0026] In some embodiments, the integrated circuit is configured to provide a signal to the first type bonding pad, and the latch circuit is configured to: update the signal from the first type bonding pad to the second type bonding pad when the control signal is in a first state, and latch the signal from the first type bonding pad to the second type bonding pad when the control signal is in a second state different from the first state.

[0027] In some embodiments, the latch circuit is configured to receive a switching signal. The latch circuit can be configured to: electrically isolate the second type bonding pad from the first type bonding pad when the switching signal is an off signal, and electrically connect the second type bonding pad to the first type bonding pad when the switching signal is an on signal, so that when the control signal is in a first state, the signal from the second type bonding pad to the first type bonding pad is updated, and when the control signal is in a second state different from the first state, the signal from the second type bonding pad to the first type bonding pad is latched.

[0028] Implementations of the above-described technology include methods, systems, circuits, computer program products, and computer-readable media. In one example, a method may be performed in non-volatile memory and the method may include the above-described actions, such as actions for testing bond pads of a chiplet system. In another example, one such computer program product is suitably embodied in a non-transitory machine-readable medium storing instructions executable by one or more processors. The instructions are configured to cause the one or more processors to perform the above-described actions. One such computer-readable medium stores instructions that, when executed by one or more processors, are configured to cause the one or more processors to perform the above-described actions.

[0029] The technology can be implemented for any type of circuit, device, or system that requires testing smaller area bonding pads for electrical connections between different integrated circuit (IC) devices or smaller area bonding pads that are tested at the wafer level and packaged into a multi-die package. For example, the signal on the bonding pad must be correct. Before entering the package, the bonding pads on the IC device must be tested at the wafer level. The technology herein provides an integrated circuit (IC) device (die or chip) that can include two different types of bonding pads: system pads and test pads. The system pads are used to connect signal lines among the dies inside the package, and the pad area (or layout size) of the system pads can be smaller to support a large number of system connections. The test pads are mainly used for wafer-level testing (or probing) before packaging. The test pads can remain unconnected after packaging. The pad area of ​​the test pads can be larger so that they can be probed during wafer-level testing. The number of system pads can be greater than the number of test pads. For example, there may be hundreds of system pads on an IC device, while there may be only a few test pads on the IC device. Through pad type separation, a large number of wire connections can exist between dies or chips via small-area system pads, while only a few large-area test pads can be probed during wafer-level testing. Each system pad is electrically connected to a corresponding test pad on the IC device, making it possible to test the system pad without probing it, but by internally sending the signal on the system pad to the test pad or providing the signal from the system pad to the internal integrated circuit on the IC device via the test pad. Each test pad can be electrically connected to multiple system pads and these multiple system pads can be tested, for example, via multiplexing or latching techniques. In this way, the system pads (bonding pads between dies) on the IC device can be fully tested at the wafer level before packaging to ensure that the functions are working correctly. By using latching technology, multiple signals on multiple system pads can be sampled simultaneously at a specific point in time, which can be used to measure high-speed signals.

[0030] Compared to conventional IC devices that test all signals on bond pads (or system pads) to be bonded out at the wafer level, where the bond pads may be too small to support a large number of connections and cannot be probed for accurate signal measurement, the technology implemented herein can greatly simplify wafer-level testing and improve detection accuracy and efficiency. Furthermore, the technology can develop chiplet systems with a large number of wire connections between different ICs, which can form complex heterogeneous IC integration or system-level assemblies for enhancing overall system flexibility and reducing design time, and can allow low-cost and short electrical signal routing to achieve high performance.

[0031] The technology can be applied to form various types of non-volatile memory devices, such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase-change random-access memory (PCRAM), etc. Additionally or alternatively, the technology can be applied to form various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSD), embedded systems, etc.

[0032] The details of one or more disclosed embodiments are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a schematic diagram of an example chiplet system that packages multiple integrated circuit devices (or dies) according to one or more implementations.

[0034] Figure 2A is a schematic diagram of an example integrated circuit device for testing output-type system pads using a test pad according to one or more implementations.

[0035] Figure 2B is a schematic diagram of another example integrated circuit device for testing output-type system pads using a test pad according to one or more implementations.

[0036] Figure 2C is a schematic diagram of yet another example integrated circuit device for testing output-type system pads using a test pad according to one or more implementations.

[0037] Figure 2D is a schematic diagram of an example integrated circuit device for testing an input-type system pad using a test pad according to one or more implementations.

[0038] Figure 3 A circuit diagram of an example latch (LAT) circuit is shown according to one or more implementations.

[0039] Figure 4 A circuit diagram of an example controlled latch (LATZ) circuit is shown in accordance with one or more implementations.

[0040] Figure 5Ais a schematic diagram of an example integrated circuit device for testing multiple output type system pads using test pads according to one or more implementations.

[0041] Figure 5B is a schematic diagram of another example integrated circuit device for testing multiple output type system pads using test pads according to one or more implementations.

[0042] Figure 5C 2 is a schematic diagram of yet another example integrated circuit device for testing signals on multiple output-type system pads at a specific point in time using test pads according to one or more implementations.

[0043] Figure 6A is a schematic diagram of an example integrated circuit device for testing multiple input-type system pads using a test pad according to one or more implementations.

[0044] Figure 6B is a schematic diagram of an example integrated circuit device for testing a plurality of input-type system pads and a plurality of output-type system pads using test pads according to one or more implementations.

[0045] Figure 6C is a schematic diagram of another example integrated circuit device for testing a plurality of input-type system pads and a plurality of output-type system pads using test pads according to one or more implementations.

[0046] Figure 7A A flow chart illustrating an example process for testing output-type bond pads in an integrated circuit device according to one or more implementations.

[0047] Figure 7B A flow chart illustrating an example process for testing input-type bond pads in an integrated circuit device, according to one or more implementations.

[0048]

Explanation of symbols

[0049] 100: Small chip system

[0050] 101: Connecting Lines

[0051] 102: Encapsulation

[0052] 104: Silicon board

[0053] 110: Grain A

[0054] 112, 122, 132, 204, 234, 254, 274, 504, 604, 634: System pads

[0055] 114, 124, 134, 206, 236, 256, 276, 506, 606: test pads

[0056] 120: Grain B

[0057] 130: Grain C

[0058] 200, 230, 250, 270, 500, 530, 550, 600, 630, 650: integrated circuit devices

[0059] 202, 232, 252, 272, 502, 602, 632: Internal circuit

[0060] 208, 210, 238, 240, 258, 260: Buffer

[0061] 262, 300, 562-1, 562-N, 652-1, 652-N: Latch circuit

[0062] 278, 280, 514, 608-1, 608-M, 610: Into the buffer

[0063] 282, 400, 612-1, 612-M: Controlled latch circuits

[0064] 302, 402, 412: switch

[0065] 304, 310, 404, 410, 414: Reversers

[0066] 306, 406: Large inverter

[0067] 308, 408: Smaller inverters

[0068] 501, 631: selection line

[0069] 503-1, 503-N, 533-1, 533-N, 633: Electrical connection

[0070] 504-1, 504-N, 634-1, 634-N: Output type system pad

[0071] 505: Signal line

[0072] 508-1, 508-N, 510, 636: Outbound buffer

[0073] 512, 636: Multiplexer

[0074] 604-1, 604-M: Input type system pad

[0075] 614: Output buffer

[0076] 635. Y: Wire

[0077] 700, 750: Process

[0078] 702, 704, 706, 708, 752, 754, 756, 758, 760: Operation

[0079] D, S, T, U, U1, U2, U3, UM: Input

[0080] Q: Output DETAILED DESCRIPTION

[0081] Figure 1 FIG. 1 is a schematic diagram of an example chiplet system 100 for packaging multiple integrated circuit devices (or dies) according to one or more embodiments. Figure 1 As shown in FIG, the chiplet system 100 is a system-level assembly that packages multiple integrated circuit devices, such as those described in other details and in FIG. Figures 2A to 2D 、 Figures 5A to 5C as well as Figures 6A to 6C The integrated circuit device shown in .

[0082] like Figure 1 As shown in FIG, a chiplet system 100 includes a package 102 that packages three dies (die A 110, die B 120, and die C 130) integrated on a silicon-based substrate 104. The chiplet system 100 may include, for example, a plurality of pins on the silicon-based substrate 104, which may be configured to receive external signals from an external device or system or transmit signals to an external device or system.

[0083] Each die can be an integrated circuit device including an internal integrated circuit (or internal circuit) and bonding pads. During integration and packaging, the three dies 110, 120, and 130 are flipped (or face downward) relative to the silicon-based board 104 so that the bonding pads of the three dies are electrically connected to the wiring layer (or interposer) on the silicon-based board 104, for example, via microbump technology.

[0084] The bonding pads on each die may include two types of bonding pads: a first type of bonding pad (referred to as a system pad) and a second type of bonding pad (referred to as a test pad). For purposes of illustration only in the present invention, the first type of bonding pad and the second type of bonding pad are referred to as a system pad and a test pad, respectively. The system pads are configured for signal line connection among the die inside the package, and the system pads are configured not to be used for probing during wafer-level testing prior to packaging. Some of the system pads are externally connected to the pins of the chiplet system, while some others of the system pads are not externally connected to the pins. The test pads are configured primarily for probing during wafer-level testing prior to packaging, and the test pads are configured not to be connected to any other die in the package and may remain unconnected after packaging.

[0085] The system pad can be electrically connected to a corresponding test pad on the same die so that the system pad can be inspected or tested without probing during wafer-level testing. The system pad can be an output-type system pad or an input-type system pad. In some cases, the system pad is a hybrid pad that acts as an output-type system pad in some cases and as an input-type system pad in other cases. The output-type system pad is configured to transmit a signal or internal data from an internal circuit in a die to an external die, and can be tested during wafer-level testing by sending the signal from the internal circuit internally to the system pad and the test pad. The input-type system pad is configured to receive a signal or external data from an external die to an internal circuit in the die, and can be tested during wafer-level testing by providing an external signal from the test pad to the internal circuit via the system pad. The test pad can be, for example, connected via a Figures 5A to 5C as well as Figures 6A to 6C The multiplexing or latching techniques discussed in further detail in are electrically connected to multiple system pads and used to test the number of system pads during wafer level testing.

[0086] Since the system pads on the die are not used for probing during wafer-level testing, the system pads can have a smaller size (bonding area or pad area) so that the die can include a larger number of system pads for external connection to external dies. The test pads on the same die can have a larger size than the system pads so that the test pads can be probed at wafer-level testing. In the chiplet system 100, the test pads used for probing can have one or more probing scratches, while the system pads remain smooth and scratch-free. On the same die, the number of system pads on the die can be greater than the number of test pads. For example, in the same die, there may be hundreds of system pads, while there may be only one or a few test pads. In some instances, all system pads are electrically connected to the test pads on the same die. In some other instances, some of the system pads are electrically connected to the test pads on the same die, while others of the system pads are not connected to any of the test pads.

[0087] like Figure 1As shown in FIG, die A 110 includes a plurality of system pads 112 and a plurality of test pads 114. Each of the system pads 112 can be electrically connected to a corresponding one of the test pads 114 and can be tested by using the corresponding test pad 114 during wafer-level testing before die A 110 is packaged into package 102. Die B 120 includes a plurality of system pads 122 and a plurality of test pads 124. Each of the system pads 122 can be electrically connected to a corresponding one of the test pads 124 and can be tested by using the corresponding test pad 124 during wafer-level testing before die B 120 is packaged into package 102. Die C 130 includes a plurality of system pads 132 and a plurality of test pads 134. Each of the system pads 132 can be electrically connected to a corresponding one of the test pads 134 and can be tested by using the corresponding test pad 134 during wafer-level testing before die C 130 is packaged into package 102.

[0088] After packaging, the system pad 112 on die A 110 is electrically connected to the system pad 122 on die B 120 and to the system pad 132 on die C 130 via the connection line 101, while the test pad 114 on die A 110 remains unconnected to die B 120 and die C 130. After packaging, the system pad 122 on die B 120 is electrically connected to the system pad 112 on die A 110 and to the system pad 132 on die C 130 via the connection line 101, while the test pad 124 on die B 120 remains unconnected to die A 110 and die C 130. After packaging, the system pad 132 on die C 130 is electrically connected to the system pad 112 on die A 110 and to the system pad 122 on die B 120 through the connection line 101 , while the test pad 134 on die C 130 remains unconnected to die A 110 and die B 120 .

[0089] Figure 2A FIG. 2 is a schematic diagram of an example integrated circuit (IC) device 200 for testing an output type system pad using a test pad according to one or more implementations. The IC device 200 may be Figure 1 The IC device 200 includes an internal circuit (or internal integrated circuit) 202, a system pad 204, and a test pad 206. The system pad 204 can be Figure 1 The system pad 112, the system pad 122 or the system pad 132, and the test pad 206 can be Figure 1The system pad 204 is an output type system pad configured to transmit a signal from the internal circuit 202 to an external integrated circuit device or die. The IC device 200 can be configured to inspect the system pad 204 during wafer-level testing by using the test pad 206 (e.g., by internally sending a signal on the system pad 204 from the internal circuit 202 to the test pad 206).

[0090] like Figure 2A As shown in FIG, the internal circuit 202 is electrically connected to the system pad 204 via a buffer 208 and is electrically connected to the test pad 206 via a buffer 210.

[0091] During wafer-level testing, when the internal circuit 202 sends a signal to the system pad 204 via the buffer 208, the signal is also sent or transferred to the test pad 206 via the buffer 210. The test pad 206 can be probed and the signal on the test pad 206 can be measured, for example, by an external measurement device, and the signal on the system pad 204 can be determined based on the measurement result of the signal on the test pad 206. That is, the measurement result can be used to determine whether the signal on the system pad 204 is correct or whether the system pad 204 and / or the circuit path from the internal circuit 202 to the system pad 204 is functioning correctly.

[0092] The buffer 208 can be configured to amplify signals from the internal circuit 202 and convert the logic type of the internal circuit 202 to the logic type of the system pad 204. The buffer 210 can be configured to convert the logic type of the internal circuit 202 to the logic type of the test pad 206. The buffer 210 can also be configured to be disconnected from the internal circuit 202 so that the test pad 206 is blocked or isolated from the internal circuit 202 and the system pad 204 during normal operation after wafer-level testing.

[0093] Figure 2B FIG. 2 is a schematic diagram of another example integrated circuit (IC) device 230 for testing an output type system pad 234 using a test pad 236 according to one or more implementations. The IC device 230 includes an internal circuit 232 electrically connected to the system pad 234 via a buffer 238. The internal circuit 232, the system pad 234, and the buffer 238 may be similar to Figure 2A The internal circuit 202, system pad 204 and buffer 208 are shown in FIG.

[0094] Different from the test pad 206 being electrically connected to the internal circuit 202 via the buffer 210 Figure 2A In the IC device 200, the IC device 230 instead includes a test pad 236 electrically connected to the system pad 234 via a buffer 240. The test pad 236 and the buffer 240 may be similar to Figure 2A206 and buffer 210. During wafer-level testing, a signal is sent from the internal circuit 232 to the system pad 234 via the buffer 238, and then from the system pad 234 to the test pad 236 via the buffer 240. The signal on the test pad 236 can be measured, and the signal on the system pad 234 can be determined based on the measurement result of the signal on the test pad 236. In this way, the system pad 234, the path from the buffer 238 to the system pad 234, and / or the path from the internal circuit 232 to the system pad 234 can also be inspected or tested during wafer-level testing.

[0095] Figure 2C FIG. 2 is a schematic diagram of yet another example integrated circuit (IC) device 250 for testing an output type system pad 254 using a test pad 256 according to one or more implementations. The IC device 250 is similar to FIG. Figure 2B The IC device 230 includes an internal circuit 252 electrically connected to a system pad 254 via a buffer 258, and the system pad 254 is electrically connected to a test pad 256 via a buffer 260. Figure 2B , the IC device 230 includes a latch circuit 262 disposed between a system pad 254 and a buffer 260. The latch circuit 262 is configured to latch a signal on the system pad 254 (e.g., a signal from the internal circuit 252 to the system pad 254) to a test pad 256 via a control signal input from an input S. In this manner, the signal on the system pad can be sampled at a specific time point controlled by the control signal from the input S, and the sampled signal can be transferred to the test pad 256 for testing.

[0096] Figure 3 A circuit diagram of an example latch (LAT) circuit 300 is shown according to one or more implementations. The latch circuit 300 may be used as Figure 2C 3. Latch circuit 300 includes a switching element having a switch 302 and an inverter 304, a latch element having a larger inverter 306 and a smaller inverter 308, and an inverter 310. Latch circuit 300 includes a first input S for receiving a control signal, a second input D for receiving an input signal (e.g., a signal on a system pad), and an output Q for outputting a signal latched in the latch element.

[0097] Switch 302 and inverter 304 are coupled together and configured to each receive a control signal from a first input S. When the control signal remains high at "1," the switching element turns on and the input signal from input D is transferred to the latch element. Because the smaller inverter 308 has a weaker drive capability than the larger inverter 306, the input signal from input D can overwrite the previously stored signal and be output at output Q. When the control signal transitions from "1" to "0" at a specific point in time, the switching element turns off and input D is disconnected from the latch element, and output Q continues to output the signal stored in the latch element. In other words, the input signal is sampled at a specific point in time.

[0098] Return Reference Figure 2C During wafer-level testing, internal circuit 252 transmits a signal to system pad 254 via buffer 258. The signal on system pad 254 is then passed to test pad 256 via latch circuit 262 and buffer 260. A control signal can be sent to input S of latch circuit 262, for example, via internal circuit 272. The control signal remains high at "1," allowing the signal on system pad 254 to be measured in real time at test pad 256. When the control signal transitions from "1" to "0" at a specific point in time, the signal on system pad 254 is latched in latch circuit 262 and sampled at that specific point in time. The sampled signal is then continuously passed to test pad 256 for measurement. In this way, the signal on system pad 254 at a specific point in time can be tested.

[0099] Figure 2D is a schematic diagram of an example integrated circuit (IC) device 270 for testing an input type system pad 274 using a test pad 276 according to one or more implementations. The IC device 270 may be Figure 1 The IC device 270 includes an internal circuit (or internal integrated circuit) 272, a system pad 274, and a test pad 276. The system pad 274 can be Figure 1 The system pad 112, the system pad 122 or the system pad 132, and the test pad 276 can be Figure 1 The system pad 274 is an input type system pad configured to receive a signal from an external integrated circuit device or die and transmit the signal to the internal circuit 272. The IC device 270 is configured to be inspected or tested during wafer-level testing by using the test pad 276 (e.g., by providing an external signal from the test pad 276 to the internal circuit 272 via the system pad 274).

[0100] like Figure 2DAs shown in FIG, the system pad 274 is electrically connected to the internal circuit 272 via an in buffer 278. The in buffer 278 can be configured to convert the logic type of the system pad 274 to the logic type of the internal circuit 272. The test pad 276 is electrically coupled to the system pad 274 via an in buffer 280. The in buffer 280 can also be configured to convert the logic type of the test pad 276 to the logic type of the system pad 274.

[0101] During wafer-level testing, when a signal on a test pad 276, for example, from an external source, is sent to a system pad 274 via an inbound buffer 280, the signal on the system pad 274 is then sent to the internal circuit 272 via an inbound buffer 278. The signal received through the internal circuit 272 can be output to another test pad on the IC device 270 for measurement. The measurement result can be used to determine whether the signal on the system pad 274 is correct or whether the system pad 274 and / or the path from the system pad 274 to the internal circuit 272 is functioning correctly, for example, whether the difference between the measurement result and the reference result is within a predetermined threshold.

[0102] In some embodiments, as Figure 2D As shown in FIG, the IC device 270 includes a controlled latch (LATZ) circuit 282 disposed between the feed buffer 280 and the system pad 274. Figure 4 A circuit diagram of an example LATZ circuit 400 is shown according to one or more implementations. The LATZ circuit 400 may be used as Figure 2D The LATZ circuit 282. The LATZ circuit 400 includes a latch circuit (e.g., Figure 3 latch circuit 300) and additional switching elements.

[0103] like Figure 4 As shown in FIG, LATZ circuit 400 includes a first switching element having a switch 402 and an inverter 404, a latch element having a larger inverter 406 and a smaller inverter 408, an inverter 410, and a second switching element having a switch 412 and an inverter 414. Latch circuit 400 includes a first input U for receiving a first control signal, a second input T for receiving a second control signal (or switching signal), a third input D for receiving an input signal (e.g., a signal on a system pad), and an output Q for outputting a signal latched in the latch element.

[0104] The first switching element of the LATZ circuit 400 may be similar to Figure 3 The switching element of the LAT circuit 300. The latch element of the LATZ circuit 400 may be similar to Figure 3The latch element of the LAT circuit 300 is shown in FIG. The smaller inverter 408 has a weaker driving capability than the larger inverter 406. A first control signal on the first input U determines whether to update the signal stored in the latch element. When the first control signal on the first input U remains high at "1," the latch element of the LATZ 400 updates the stored signal; when the first control signal transitions from "1" to "0," the latch element retains the signal. When the second control signal on the second input T is "0," the output Q is isolated from downstream components, such as a system pad; when the second control signal on the second input T is set to "1," the second switching element turns on, and the output Q passes the signal stored in the latch element.

[0105] Return Reference Figure 2D During normal operation, signals are sent externally (e.g., from an external IC device) to the internal circuit 272 via the system pad 274. The control signal on input T of the LATZ circuit 282 can be set to "0" to isolate the circuit from the system pad 274, eliminating power or energy consumption and interference from the test pad 276. During wafer-level testing, the system pad 274 is disconnected from the external IC device. Setting the control signal on input T of the LATZ circuit 282 to "1" allows signals sent externally (e.g., from an external source) via the test pad 276 to be passed to the system pad 274 for simulating the external signal. While the control signal on input U remains high at "1," the LATZ circuit 282 continuously updates the simulated signal on the system pad 274. When the control signal on input U transitions from "1" to "0" at a specific time, the LATZ circuit 282 samples the simulated signal on the system pad 274 at that specific time. The control signals on input U and input T of the LATZ circuit 282 may be provided and controlled by the internal circuit 272 .

[0106] In an integrated circuit (IC) device, a test pad can be electrically connected to multiple system pads and used to test signals on each of the system pads, for example, using multiplexing or latching techniques. The system pad can be an output-type system pad, an input-type system pad, or a combination of both. Figures 5A to 5C Different examples of IC devices for testing multiple output type system pads using test pads are shown. Figures 5A to 5C The same reference numerals are used for the same components. Figure 6A An example IC device for testing multiple input type system pads using a test pad is shown, and Figures 6B to 6C An example IC device for testing a plurality of output type system pads and a plurality of input type system pads using a test pad is shown. Figures 6A to 6C The same reference numerals are used for the same components.

[0107] Figure 5A FIG. 5 is a diagram of an example integrated circuit (IC) device 500 for testing a plurality of output type system pads 504-1 ... 504-N (collectively referred to as output type system pads 504 and individually as output type system pads 504) using a test pad 506 according to one or more implementations. The IC device 500 corresponds to Figure 2A The IC device 200 has multi-tasking capabilities.

[0108] IC device 500 includes an internal integrated circuit (or internal circuit) 502 electrically connected to each of system pads 504 via respective out buffers 508-1...508-N (collectively referred to as out buffers 508 or individually as out buffers 508). Internal circuit 502 may be similar to Figure 2A The internal circuit 202, Figure 2B The internal circuit 232 or Figure 2C The internal circuit 252. The output type system pad 504 can be Figure 2A System pad 204, Figure 2B System Pad 234 or Figure 2C The system pad 254. The output buffer 508 can be Figure 2A The output buffer 208, Figure 2B The output buffer 238 or Figure 2C The test pad 506 can be Figure 2A Test pad 206, Figure 2B Test pad 236 or Figure 2C Test pad 256.

[0109] IC device 500 includes a multiplexer (MUX) 512 electrically connected to electrical connections between internal circuit 502 and each of output buffers 508, such that a signal sent from internal circuit 502 to any of output-type system pads 504 can also be sent to multiplexer 512 via corresponding electrical connections, such as wires 503-1 ... 503-N (collectively, electrical connections 503 and individually, electrical connections 503). Internal circuit 502 is configured to send a select signal to multiplexer 512 via select (SEL) line 501. Multiplexer 512 is electrically connected to test pad 506 via output buffer 510. Multiplexer 512 is controlled by a select signal to select one of the signals on electrical connection 503 for output to test pad 506. Internal circuit 502 is configured to control the select signal.

[0110] During wafer level testing, by controlling the select signals to the multiplexer 512 for selecting the corresponding electrical connections 503, the multiplexer 512 can be configured to sequentially select the system pads 504 for testing. Figure 2A 506 is used to test the selected system pad 504. For example, the test signal sent from the internal circuit 502 to the selected system pad 504 via the corresponding output buffer 508 can also be sent to the test pad 506 via the corresponding electrical connection 503, the multiplexer 512 and the output buffer 510.

[0111] In some embodiments, the internal circuit 502 is electrically connected to a multiplexer 512 using an additional signal line 505. The multiplexer 512 can be controlled by a selection signal to select a signal from the internal circuit 502 via the signal line 505 for output to the test pad 506. A signal on the test pad 506, for example, from an external device, can be sent to the internal circuit 502 via the in-put buffer 514. For example, during wafer-level testing, a signal for probing the internal circuit 502 can be provided to the test pad 506 and passed to the internal circuit 502 via the in-put buffer 514. The internal circuit 502 can also output an output signal to the test pad 506 via the electrical connection 505 by selecting the electrical connection 505 via the multiplexer 512.

[0112] Figure 5B FIG. 5 is a schematic diagram of another example integrated circuit device 530 for testing multiple output type system pads 504 using a test pad 506 according to one or more implementations. The IC device 530 corresponds to Figure 2B The IC device 230 has multi-tasking capabilities.

[0113] Each of the electrical connections 503 is electrically connected to an electrical connection between the internal circuit 502 and the corresponding output buffer 508. Figure 5A In the IC device 500 of FIG. 5 , each of the system pads 504 in the IC device 530 is electrically connected to a multiplexer 512 using corresponding electrical connections 533-1 ... 533-N (collectively, electrical connections 533 and individually, electrical connections 533). The multiplexer 512 is configured to select one of the electrical connections 533 based on a selection signal from the internal circuit 502. In this manner, during wafer-level testing, each of the system pads 504 can be selected for testing by selecting the multiplexer 512 such that the corresponding electrical connection 533 is connected to the test pad 506 via the buffer 510.

[0114] Figure 5C Schematic diagram of yet another example integrated circuit device 550 for testing signals on multiple output type system pads 504 at a specific point in time using test pads 506 according to one or more implementations. The IC device 550 corresponds to Figure 2C The IC device 250 has multi-tasking capabilities.

[0115] Different from Figure 5B The IC device 530 includes a plurality of latch circuits 562-1, 562-N (collectively referred to as latch circuits 562 and individually as latch circuits 562). The latch circuit 562 may be Figure 2C The latch circuit 262 or Figure 3 50. Each of the latch circuits 562 is arranged downstream of a respective system pad 504 and upstream of the multiplexer 512 via a corresponding electrical connection 533. The latch circuits 562 can be controlled by the same control signal provided on the input (S) of the latch circuit 562. In this way, the signal on the system pad 504 from the internal circuit 502 can be sampled at a specific point in time immediately when the control signal goes low to "0". That is, the signal on the system pad 504 at a specific point in time is sampled and latched in the latch circuit 562. The control signal can be controlled by the internal circuit 502.

[0116] After latching, the control signal can be kept low to hold the sampled signal latched in the latch circuit 562, and the sampled signal on the test pad 506 can then be checked at a slower speed. The latched sampled signals can be sequentially sent to the test pad 506 for testing by selecting or switching the multiplexer 512 of the latch circuit based on the selection signal. After all latched signals are checked by probing the test pad 506, the control signal input to the latch circuit 562 can be turned high again to receive the signal on the system pad 504, and then turned low at another specific time point to sample the signal on the system pad 504 at that specific time point.

[0117] Figure 6A Schematic diagram of an example integrated circuit device 600 for testing a plurality of input type system pads 604-1 ... 604-M (collectively referred to as input type system pads 604 and individually as input type system pad 604) using a test pad 606 according to one or more implementations. The IC device 600 corresponds to Figure 2D The IC device 270 has multi-tasking capabilities.

[0118] IC device 600 includes an internal integrated circuit (or internal circuit) 602 electrically connected to each of system pads 604 via respective in buffers 608-1...608-M (collectively referred to as in buffers 608 or individually as in buffers 608). Internal circuit 602 may be similar to Figure 2D The internal circuit 272. Input type system pad 604 can be Figure 2D The system pad 274. The buffer 608 can be Figure 2D into buffer 278.

[0119] Test pads 606 may correspond to Figure 2D Test pad 276. Different from Figure 2D The test pad 276 is electrically connected to a system pad 274 via a LATZ circuit 282. The test pads 606 are electrically connected to multiple system pads 604 via a buffer 610 and respective LATZ circuits 612-1...LATZ circuits 612-M (collectively referred to as LATZ circuits 612 or individually referred to as LATZ circuits 612). The LATZ circuit 612 can be Figure 2D LATZ circuit 282 or Figure 4LATZ circuit 400 is shown. Each LATZ circuit 612 has a U input (U1...UM) for receiving a first control signal and a T input for receiving a second control signal. The T inputs of LATZ circuits 612 are configured to be connected together to receive the same second control signal. The U inputs of LATZ circuits 612-1...LATZ circuits 612-M are configured to receive respective first control signals, thereby selecting system pads 604 to receive test signals from test pads 606. The respective first control signals to the U inputs of LATZ circuits 612 and the second control signals to the T inputs of LATZ circuits 612 can be controlled by internal circuit 602.

[0120] During normal operation, signals are sent externally (e.g., from one or more external IC devices) to the internal circuit 602 via the system pad 604. A control signal at input T of the LATZ circuit 612 can be set to "0" to isolate the test pad 606 (as well as the LATZ circuit 612 and the feed buffer 610) from the system pad 604, eliminating power or energy consumption and interference from the test pad 606. During wafer-level testing, the system pad 604 is disconnected from the external IC devices. Setting the control signal at input T of the LATZ circuit 612 to "1" allows signals sent externally (e.g., from an external source) via the test pad 606 to be passed to the system pad 604 for emulation of the external signal. When the control signal at input U of the LATZ circuit 612 remains high at "1," the LATZ circuit 612 continuously updates the simulation signal on the corresponding system pad 604. When the control signal at input U transitions from "1" to "0" at a specific time point, the LATZ circuit 612 samples the simulation signal on the corresponding system pad 604 at that specific time point. Whenever updating a signal to be sent to the corresponding system pad 604 for testing, the internal circuit 602 may set one of the control signals at input U of the LATZ circuit 612 to "1."

[0121] In some implementations, the IC device 600 includes an output buffer 614 coupled between the output of the internal circuit 602 and the test pad 606. A signal on the test pad 606, such as from an external device, can be sent to the internal circuit 602 via the input buffer 610. The internal circuit 602 can also output an output signal to the test pad 606 via the output buffer 614. For example, during wafer-level testing, a signal for probing the internal circuit 602 can be provided to the test pad 606 and transmitted to the internal circuit 602 via the input buffer 610. The internal circuit 602 then outputs an output signal to the test pad 606 via the output buffer 614 based on the received signal. The output signal can then be detected or measured at the test pad 606.

[0122] Figure 6BFIG. 6 is a diagram of an example integrated circuit (IC) device 630 for testing a plurality of input type system pads 604 and a plurality of output type system pads 634-1 ... 634-N (collectively referred to as output type system pads 634 and individually as output type system pads 634) using the same test pad 606 according to one or more implementations. Figure 6A The same IC device configuration of the IC device 600 is tested, and multiple output type system pads 634 can be tested by corresponding Figure 5B The IC device 530 is configured to be tested.

[0123] IC device 630 includes internal circuitry 632 electrically connected to each of the input-type system pads 604 via respective input buffers 608 and to each of the output-type system pads 634 via respective output buffers 636. Internal circuitry 632 is configured to control testing of input-type system pads 604 and output-type system pads 634. Each output-type system pad 634 is coupled to a multiplexer 636 via respective electrical connections 633. Multiplexer 636 is configured to receive a select signal from internal circuitry 632 via select line 631 and, based on the select signal, select one of the output-type system pads 634 for testing. Multiplexer 636 is also configured to receive a dedicated signal from internal circuitry 632 via line Y 635. The dedicated signal can be a signal that samples an internal signal from an internal logic block to check the correctness of the internal signal, or a signal that indicates other test status of internal circuitry 632 (e.g., test in progress, test pass / fail). Dedicated signals may be selected by multiplexer 636 to be sent to test pad 606 .

[0124] Figure 6C FIG. 6 is a diagram of another example integrated circuit (IC) device 650 for testing multiple input type system pads 604 and multiple output type system pads 634 using the same test pad 606 according to one or more implementations. Figure 6A The same IC device configuration of the IC device 600 is tested, and multiple output type system pads 634 can be tested by corresponding Figure 5C The IC device 550 is configured to be tested.

[0125] Compared to Figure 6BIC device 630, IC device 650 further includes a plurality of latch circuits 652-1 ... latch circuits 652-N (collectively referred to as latch circuits 652 and individually as latch circuits 652). Latch circuit 652 can be Figure 2C The latch circuit 262, Figure 3 The latch circuit 300, Figure 5C Latch circuits 562 are provided. Each latch circuit 652 is configured between a respective system pad 634 and a multiplexer 636 via a corresponding electrical connection 633. The latch circuits 652 can be controlled by the same control signal provided to the input (S) of the latch circuit 652. In this way, the signal on the system pad 634 from the internal circuit 632 can be sampled at a specific point in time immediately when the control signal goes low to "0." That is, the signal on the system pad 634 at a specific point in time is sampled and latched in the latch circuit 652. The control signal can be controlled by the internal circuit 632. After latching, the control signal can remain low to maintain the sampled signal latched in the latch circuit 652, and the sampled signal on the test pad 606 can then be checked at a slower speed. The latched sampled signal can be sequentially sent to the test pad 606 for testing by selecting or switching the multiplexer 636 of the latch circuit based on the selection signal. After checking all latched signals by probing the test pad 606, the control signal input to the latch circuit 652 can go high again to receive the signal on the system pad 634, and select another specific time point to go low to sample the signal on the system pad 634 at the other specific time point.

[0126] Figure 7A A flow chart illustrating an example process 700 for testing output type bond pads in an integrated circuit (IC) device according to one or more implementations. The IC device may be Figure 1 of grain A 110, grain B 120 or grain C 130, Figure 2A IC device 200, Figure 2B IC device 230 or Figure 2C IC device 250, Figure 5A IC device 500, Figure 5B IC device 530 or Figure 5C IC device 550, or Figure 6B IC device 630 or Figure 6C IC device 650. Output type bonding pads can be Figure 1 System pad 112, system pad 122 or system pad 132, Figure 2A System pad 204, Figure 2B System Pad 234 or Figure 2C System pad 254, Figures 5A to 5C System Pad 504, or Figures 6B to 6C The IC device includes at least one second type bonding pad, such as Figure 1 The test pad 114, the test pad 124 or the test pad 134, Figure 2A Test pad 206, Figure 2B Test pad 236, Figure 2C Test pad 256, Figures 5A to 5C Test pad 506, or Figures 6B to 6C The IC device includes an internal integrated circuit, such as Figure 2A The internal circuit 202, Figure 2B The internal circuit 232 or Figure 2C Internal circuit 252, Figures 5A to 5C The internal circuit 502, or Figures 6B to 6C The process 700 may be performed during wafer-level testing (e.g., before integrating or packaging an IC device with one or more other IC devices to form, for example, Figure 1 The system 100 chiplet system (previously) is performed by an IC device.

[0127] A signal is transmitted from an internal circuit to an output-type bonding pad (operation 702), and a signal is received at a second-type bonding pad electrically connected to the output-type bonding pad (operation 704). The output-type bonding pad is configured to be electrically connected to an external IC device and is configured to transmit internal data from the IC device to the external IC device. The second-type bonding pad is configured not to be electrically connected to the external IC device. The second-type bonding pad has a larger pad area than the output-type bonding pad.

[0128] In some embodiments, the IC device includes a plurality of output-type bonding pads. The integrated circuit is electrically connected to each of the output-type bonding pads via a respective buffer. The IC device may include a multiplexer, such as Figures 5A to 5C The multiplexer 512, or Figures 6B to 6C The multiplexer 636 is configured to select one of the output type bonding pads based on the selection signal, so that the selected output type bonding pad is electrically connected to the second type bonding pad. The integrated circuit can be configured to provide the selection signal to the multiplexer.

[0129] In some embodiments, the multiplexer is electrically connected to corresponding electrical contacts between the integrated circuit and the respective buffers. In some embodiments, each of the output-type bonding pads is electrically connected to the multiplexer via a respective buffer, and the second-type bonding pads are electrically connected to the multiplexer via a second buffer different from the respective buffers for the output-type bonding pads. In some examples, the IC device further includes a plurality of latch circuits, such as Figure 2C LAT circuit 262, Figure 3 LAT circuit 300, Figure 5C LAT circuit 562, or Figure 6C LAT circuit 652. Each of the output type bonding pads can be electrically connected to the multiplexer via a respective latch circuit. The multiple latch circuits can be configured to receive a control signal and to simultaneously latch the signals on the multiple first type bonding pads when the control signal is in a first state, and to individually update the signals on the multiple first type bonding pads when the control signal is in a second state different from the first state. The multiplexer can be configured to sequentially select the first type bonding pads to be electrically connected to the second type bonding pads when the control signal remains in the first state, so that the signals latched simultaneously in the multiple latch circuits are sequentially provided to the second type bonding pads.

[0130] The signal on the second type bond pad is measured (operation 706). For example, an external measurement device such as an ammeter or a voltmeter can probe the second type bond pad and obtain a measurement of the signal on the second type bond pad.

[0131] The condition of the output-type bond pad is determined based on the measurement result of the signal on the second-type bond pad (operation 708). Since the signal on the second-type bond pad corresponds to the signal on the output-type bond pad, the condition of the output-type bond pad and / or the condition of the circuit path from the internal circuit to the output-type bond pad and to the second-type bond pad can be determined (for example, to see whether it is operating correctly).

[0132] Figure 7B A flow chart illustrating an example process 750 for testing input type bond pads in an integrated circuit (IC) device according to one or more implementations. The IC device may be Figure 1 of grain A 110, grain B 120 or grain C 130, Figure 2D IC device 270, or Figure 6A IC device 600, Figure 6B IC device 630 or Figure 6C IC device 650. Input type bonding pads can be Figure 1 System pad 112, system pad 122 or system pad 132, Figure 2D System Pad 274, or Figures 6A to 6C The IC device includes at least one second type bonding pad, such as Figure 1 The test pad 114, the test pad 124 or the test pad 134, Figure 2D Test pad 276, or Figures 6A to 6C The IC device includes an internal integrated circuit, such as Figure 2D Internal circuit 272, Figure 6A The internal circuit 602 or Figures 6B to 6C The internal circuit 632 of the device. Process 750 may be performed during wafer-level testing (e.g., before integrating or packaging the IC device with one or more other IC devices to form, for example, Figure 1 The system 100 chiplet system (previously) is performed by an IC device.

[0133] A test signal is received at the second type bonding pad (operation 752). An external signal source can provide the test signal to the second type bonding pad. Each of the input type bonding pads is configured to be electrically connected to a corresponding external IC device and to receive external data from the corresponding IC device to the integrated circuit. The second type bonding pad is configured not to be electrically connected to the corresponding external IC device. The second type bonding pad has a larger pad area than the input type bonding pad.

[0134] The latch circuit is controlled to pass the test signal from the second type bonding pad to the input type bonding pad (operation 754). The latch circuit may be Figure 2D LATZ circuit 282, Figure 4 LATZ circuit 400, or Figures 6A to 6C LATZ circuit 612.

[0135] In some embodiments, the IC device includes a plurality of latch circuits, wherein the plurality of latch circuits include latch circuits. Each of the input type bonding pads is configured to be electrically connected to the second type bonding pad via a respective latch circuit in the plurality of latch circuits. Each of the plurality of latch circuits is configured to receive a switching signal and is configured to: when the switching signal is an off signal, electrically isolate the second type bonding pad from the corresponding input type bonding pad electrically connected to the latch circuit, and when the switching signal is an on signal, electrically connect the second type bonding pad to the corresponding input type bonding pad using the latch circuit. Each of the plurality of latch circuits may be configured to receive a respective control signal and be configured to: when the switching signal is an on signal and the respective control signal is in a first state, update the signal from the second type bonding pad to the corresponding input type bonding pad, and when the switching signal is an on signal and the respective control signal is in a second state different from the first state, latch the signal from the second type bonding pad to the corresponding input type bonding pad. The integrated circuit may be configured to provide the switching signal and the respective control signal to the plurality of latch circuits.

[0136] A test signal is received from the input type bonding pads by the integrated circuit (operation 756). Each of the input type bonding pads may be electrically connected to the integrated circuit via a respective input buffer. The input buffer may be Figure 2D into the buffer 280 or Figures 6A to 6C into buffer 608.

[0137] The integrated circuit may output an output signal corresponding to the test signal from the input type bonding pad (operation 758). For example, the integrated circuit is electrically connected to another second type bonding pad via an output buffer. The other second type bonding pad may be Figure 1 The test pad 114, the test pad 124 or the test pad 134, Figure 2A Test pad 206, Figure 2B Test pad 236, Figure 2C Test pad 256, Figures 5A to 5C Test pad 506, or Figures 6B to 6C The test pad 606. The output buffer can be Figure 2A Buffer 210, Figure 2B Buffer 240, Figure 2C Buffer 260, or Figures 5A to 5C The buffer 510, or Figures 6A to 6C The other second type bonding pad can be probed by an external measurement device, and the output signal can be measured.

[0138] The condition of the input-type bonding pad is determined based on the measurement result of the output signal on the other second-type bonding pad (operation 760). Since the output signal on the other second-type bonding pad corresponds to the test signal passing through the input-type bonding pad, the condition of the input-type bonding pad and / or the condition of the circuit path from the second-type bonding pad to the input-type bonding pad and then to the internal circuit can be determined (for example, to check whether it is operating correctly).

[0139] In some embodiments, the IC device includes: a plurality of output-type bonding pads, each of the output-type bonding pads being configured to transmit internal data from the integrated circuit to a corresponding external integrated circuit device; and a plurality of input-type bonding pads, each of the input-type bonding pads being configured to receive external data from a corresponding external integrated circuit device. Each of the output-type bonding pads can be connected to a corresponding external integrated circuit device by using Figure 7A Each of the input type bonding pads can be tested by using Figure 7B The process 750 is tested.

[0140] The IC device may further include a multiplexer, which is electrically connected to each of the output type bonding pads via a corresponding electrical connection and electrically connected to the second type bonding pad via a buffer, and is configured to select one of the output type bonding pads based on a selection signal so that the selected one of the output type bonding pads is electrically connected to the second type bonding pad.

[0141] The IC device may further include a plurality of latch circuits, such as LATZ circuits. Each of the input-type bonding pads is configured to be electrically connected to the second-type bonding pad via a respective latch circuit in the plurality of latch circuits. Each of the plurality of latch circuits is configured to receive a respective control signal and a respective switching signal, electrically isolate the second-type bonding pad from the corresponding input-type bonding pad electrically connected to the latch circuit when the respective switching signal is an off signal, and electrically connect the second-type bonding pad to the corresponding input-type bonding pad using the latch circuit when the respective switching signal is an on signal, so that when the respective control signal is in a first state, the signal from the second-type bonding pad to the corresponding input-type bonding pad is updated, and when the respective control signal is in a second state different from the first state, the signal from the second-type bonding pad to the input-type bonding pad is latched.

[0142] The IC device may further include a plurality of second latch circuits (e.g., LAT circuits), wherein each of the output-type bonding pads is electrically connected to the multiplexer via a respective second latch circuit of the plurality of second latch circuits. The plurality of second latch circuits are configured to receive a second control signal and are configured to simultaneously latch the signals on the plurality of first-type bonding pads when the second control signal is in a first state, and to individually update the signals on the plurality of first-type bonding pads when the second control signal is in a second state.

[0143] The integrated circuit may be configured to: provide a selection signal to the multiplexer; provide respective switching signals and respective control signals to the plurality of latch circuits; and provide a second control signal to the plurality of second latch circuits.

[0144] The disclosed and other examples may be implemented as one or more computer program products, such as one or more modules of computer program instructions encoded on a computer-readable medium, which are executed by a data processing apparatus or control the operation of the data processing apparatus. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or a combination of one or more thereof. The term "data processing apparatus" covers all apparatus, devices, and machines for processing data, including (by way of example) a programmable processor, a computer, or multiple processors or computers. In addition to hardware, the apparatus may also include program code that creates an execution environment for the computer program in question, such as program code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more thereof.

[0145] A system may encompass all devices, apparatuses, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, a system may also include program code that creates an execution environment for the computer program in question, such as program code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more thereof.

[0146] A computer program (also referred to as a program, software, software application, script, or program code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to an archive in a file system. A program may be stored as part of an archive that holds other programs or data (e.g., one or more scripts stored in a markup language file), in a single archive dedicated to the program in question, or in multiple coordinated archives (e.g., archives that store one or more modules, subroutines, or portions of program code). A computer program may be deployed to be executed on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0147] The processes and logic flows described herein can be performed by one or more programmable processors executing one or more computer programs to perform the functions described herein. The processes and logic flows can also be performed by, and the apparatus can be implemented as, special purpose logic circuitry, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0148] Processors suitable for executing a computer program include, by way of example, both general-purpose and special-purpose microprocessors, and any one or more processors of any kind of digital computer. Typically, a processor will receive instructions and data from a read-only memory or a random-access memory, or both. The essential elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer may also include, or be operatively coupled to, receive data from or transfer data to, one or more mass storage devices, or both, for storing data. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data may include all forms of nonvolatile memory, media, and storage devices, including, by way of example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; and magnetic disks. The processor and memory may be supplemented by, or incorporated in, special-purpose logic circuitry.

[0149] Although many features may be described herein, these features should not be viewed as limitations on the claimed or claimable scope of the invention, but rather as describing features specific to a particular embodiment. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed as such, one or more features from the claimed combination may in some cases be deleted from the combination, and the claimed combination may be directed to a subcombination or variation of the subcombination. Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring such operations to be performed in the particular order shown or in a sequential order, or requiring all illustrated operations to be performed in order to achieve the desired result.

[0150] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An integrated circuit device for use in a non-volatile memory, wherein: include: integrated circuit; a plurality of first-type bonding pads electrically connected to the integrated circuit, each of the plurality of first-type bonding pads being configured to be electrically connected to a corresponding external integrated circuit device; as well as The second-type bonding pad is configured to not be electrically connected to the corresponding external integrated circuit device, each of the multiple first-type bonding pads is configured to be electrically connected to the second-type bonding pad, the integrated circuit, the multiple first-type bonding pads and the second-type bonding pad are arranged on the same die, and the area of ​​the second-type bonding pad is larger than the area of ​​the first-type bonding pad, and the integrated circuit, the first-type bonding pad and the second-type bonding pad are electrically connected in series in sequence.

2. The integrated circuit device according to claim 1, wherein: The integrated circuit is electrically connected to each of the plurality of first-type bond pads via a respective buffer.

3. The integrated circuit device according to claim 2, wherein: Also included is a multiplexer configured to select one of the plurality of first-type bonding pads based on a selection signal so that the selected one of the plurality of first-type bonding pads is electrically connected to the second-type bonding pad.

4. The integrated circuit device according to claim 3, wherein: Each of the plurality of first type bonding pads is electrically connected to the multiplexer, and The second-type bonding pads are electrically connected to the multiplexer via a second buffer that is different from the respective buffers for the plurality of first-type bonding pads.

5. The integrated circuit device according to claim 4, wherein: It also includes multiple latch circuits, wherein each of the plurality of first type bonding pads is electrically connected to the multiplexer via a respective latch circuit among the plurality of latch circuits, The plurality of latch circuits are configured to receive a control signal and are configured to: When the control signal is in a first state, the signals on the plurality of first type bonding pads are latched simultaneously, and When the control signal is in a second state different from the first state, the signals on the plurality of first-type bond pads are individually updated.

6. The integrated circuit device according to claim 5, wherein: The multiplexer is configured to: When the control signal is maintained in the first state, the plurality of first type bonding pads to be electrically connected to the second type bonding pads are sequentially selected so that the signals latched simultaneously in the plurality of latch circuits are sequentially provided to the second type bonding pads.

7. The integrated circuit device according to claim 1, wherein: It also includes multiple latch circuits, Each of the plurality of first-type bond pads is configured to be electrically connected to the second-type bond pad via a respective latch circuit of the plurality of latch circuits.

8. The integrated circuit device according to claim 7, wherein: Each of the plurality of latch circuits is configured to receive a switching signal and is configured to: When the switching signal is an off signal, the second type bonding pad is electrically isolated from the corresponding first type bonding pad electrically connected to the latch circuit, and When the switching signal is an on signal, the latch circuit is used to electrically connect the second-type bonding pad to the corresponding first-type bonding pad.

9. The integrated circuit device according to claim 8, wherein: Each of the plurality of latch circuits is configured to receive a respective control signal and is configured to: When the switching signal is the on signal and the respective control signal is in the first state, updating the signal from the second type bonding pad to the corresponding first type bonding pad, and When the switching signal is the on signal and the respective control signal is in a second state different from the first state, the signal from the second-type bonding pad to the corresponding first-type bonding pad is latched.

10. The integrated circuit device according to claim 1, wherein: The integrated circuit comprises: input, configured to be electrically connected to the second type bonding pad via a first buffer, and The output is configured to be electrically connected to the second-type bonding pad via a second buffer different from the first buffer.

11. The integrated circuit device according to claim 1, wherein: The plurality of first type bonding pads include: a plurality of output-type bonding pads, each of the plurality of output-type bonding pads being configured to transmit internal data from the integrated circuit to the corresponding external integrated circuit device; and A plurality of input-type bonding pads are provided, each of the plurality of input-type bonding pads being configured to receive external data from the corresponding external integrated circuit device.

12. The integrated circuit device according to claim 11, wherein: Also includes: a multiplexer electrically connected to each of the plurality of output type bonding pads via a corresponding electrical connection and to the second type bonding pad via a buffer, and configured to select one of the plurality of output type bonding pads based on a selection signal so that the selected one of the plurality of output type bonding pads is electrically connected to the second type bonding pad; as well as A plurality of latch circuits, wherein each of the plurality of input type bond pads is configured to be electrically connected to the second type bond pad via a respective latch circuit of the plurality of latch circuits.

13. The integrated circuit device according to claim 12, wherein: A plurality of second latch circuits is also included, each of the plurality of output type bonding pads being electrically connected to the multiplexer via a respective second latch circuit of the plurality of second latch circuits.

14. An integrated system, applied to a non-volatile memory, wherein: include: A plurality of integrated circuit devices electrically connected together, each of the plurality of integrated circuit devices comprising: integrated circuit; a plurality of first type bond pads electrically connected to the integrated circuit and electrically connected to at least one other of the plurality of integrated circuit devices; and a plurality of second type bonding pads not electrically connected to the at least one other of the plurality of integrated circuit devices, Each of the plurality of first-type bonding pads is configured to be electrically connected to a corresponding one of the plurality of second-type bonding pads, the integrated circuit, the plurality of first-type bonding pads and the corresponding second-type bonding pads are arranged on the same die, and the area of ​​the second-type bonding pad is larger than the area of ​​the first-type bonding pad, and the integrated circuit, the first-type bonding pad and the corresponding second-type bonding pad are electrically connected in series in sequence.

15. The integrated system according to claim 14, wherein: Also included is a carrier board on which the plurality of integrated circuit devices are arranged, wherein the carrier comprises a wiring layer electrically contacting the plurality of first type bonding pads of the plurality of integrated circuit devices, and The carrier includes one or more pins electrically connected to one or more of the first-type bonding pads of the integrated circuit devices.

16. The integrated system according to claim 14, wherein: On each of the plurality of integrated circuit devices, the number of the plurality of first-type bonding pads is greater than the number of the plurality of second-type bonding pads.

17. A method for testing bonding pads on an integrated circuit device, applied to a non-volatile memory, wherein: include: transmitting a signal from the integrated circuit to a selected first type bond pad of a plurality of first type bond pads, the selected first type bond pad being configured to be electrically connected to an external integrated circuit device and to transmit internal data from the integrated circuit to the external integrated circuit device; receiving the signal on a second-type bond pad electrically connected to the selected first-type bond pad, the second-type bond pad being configured not to be electrically connected to the external integrated circuit device and being configured to be electrically connected to each of the plurality of first-type bond pads, the second-type bond pad having a larger pad area than each of the plurality of first-type bond pads, the integrated circuit, the selected first-type bond pad, and the second-type bond pad being disposed on a same die, and the integrated circuit, the selected first-type bond pad, and the second-type bond pad being electrically connected in series in sequence; measuring the signal on the second-type bonding pad; as well as The condition of the selected first-type bonding pad is determined based on the measurement result.

18. The method according to claim 17, wherein Also includes: receiving an external signal at the second-type bonding pad; controlling a plurality of latch circuits electrically connected to a plurality of third-type bonding pads to transmit the external signal from the second-type bonding pad to a selected third-type bonding pad among the plurality of third-type bonding pads, wherein the selected third-type bonding pad is configured to be electrically connectable to a second external integrated circuit device and configured to receive external data from the second external integrated circuit device, wherein the second type bonding pad is configured not to be electrically connected to the second external integrated circuit device and is configured to be electrically connected to each of the plurality of third type bonding pads, and wherein each of the plurality of third type bonding pads has a smaller pad area than the second type bonding pad; receiving the external signal from the selected third-type bonding pad via the integrated circuit; outputting an output signal corresponding to the external signal through the integrated circuit; as well as A condition of the selected third-type bond pad is determined based on a result of measuring the output signal from the integrated circuit.

19. An integrated circuit device for use in a non-volatile memory, wherein: include: integrated circuit; a first type bond pad electrically connected to the integrated circuit, wherein the first type bond pad is configured to be electrically connected to an external integrated circuit device; as well as The second type bonding pad is configured to be electrically connected to the first type bonding pad and not electrically connected to the external integrated circuit device, the integrated circuit, the first type bonding pad and the second type bonding pad are arranged on the same die, the area of ​​the second type bonding pad is larger than the area of ​​the first type bonding pad, and the integrated circuit, the first type bonding pad and the second type bonding pad are electrically connected in series in sequence.

20. The integrated circuit device according to claim 19, wherein The integrated circuit is configured to be electrically connected to the first type bonding pad via a first buffer, and The first-type bonding pads are configured to be electrically connected to the second-type bonding pads via a second buffer.

21. The integrated circuit device according to claim 20, wherein: Also included is a latch circuit electrically connected to an electrical connection between the first type bonding pad and the second buffer, The latch circuit is configured to receive a control signal.

22. The integrated circuit device according to claim 21, wherein: The integrated circuit is configured to provide the control signal to the latch circuit.

23. The integrated circuit device according to claim 21, wherein: The integrated circuit is configured to provide a signal to the first type bond pad, and The latch circuit is configured as follows: When the control signal is in a first state, updating the signal from the first type bonding pad to the second type bonding pad, and When the control signal is in a second state different from the first state, the signal from the first-type bonding pad to the second-type bonding pad is latched.

24. The integrated circuit device according to claim 21, wherein: The latch circuit is configured to receive a switching signal, The latch circuit is configured as follows: When the switching signal is an off signal, the second type bonding pad is electrically isolated from the first type bonding pad, and When the switching signal is an on signal, the second type bonding pad is electrically connected to the first type bonding pad, so that when the control signal is in a first state, the signal from the second type bonding pad to the first type bonding pad is updated, and when the control signal is in a second state different from the first state, the signal from the second type bonding pad to the first type bonding pad is latched.

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