Semiconductor Devices

Abstract

The semiconductor device of the present invention comprises a first electrode, a second electrode and a multilayer stack located between the first electrode and the second electrode, wherein the multilayer stack comprises at least one antiferroelectric layer and at least one high-k dielectric layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0059056, filed on May 18, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to semiconductor devices, and more particularly, to semiconductor devices including capacitors. Background Art

[0004] The recent trend of high integration of semiconductor memory devices has reduced the unit cell area, resulting in low operating voltage, which requires a high-k material with high capacitance and low leakage current.

[0005] To date, zirconium oxide (ZrO2) has been used as a high-k material for the dielectric layer of a capacitor, however, zirconium oxide has limited effect in improving capacitance. Therefore, new techniques, materials and / or structures are needed to further improve the characteristics of capacitors in highly integrated semiconductor memories. Summary of the invention

[0006] Embodiments of the present invention are directed to a semiconductor device including a capacitor having a high dielectric constant, a low leakage current, and a high capacitance.

[0007] According to one embodiment of the present invention, a semiconductor device includes: a first electrode; a second electrode; and a multilayer stack located between the first electrode and the second electrode, the multilayer stack including at least one antiferroelectric layer and at least one high-k dielectric layer.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a first electrode; a second electrode; and a multilayer stack located between the first electrode and the second electrode, the multilayer stack including a negative capacitance ferroelectric material layer and at least one high-k dielectric layer.

[0009] These and other features and advantages will become apparent to those of ordinary skill in the art to which the present invention pertains from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0011] Figure 2 It shows that according to Figure 1 A cross-sectional view of a capacitor of a modified example.

[0012] Figure 3is a cross-sectional view showing a capacitor according to another embodiment of the present invention.

[0013] FIG. 4A to FIG. 4E It shows that according to Figure 3 A cross-sectional view of a capacitor of a modified example.

[0014] Figure 5 is a cross-sectional view showing a capacitor according to another embodiment of the present invention.

[0015] FIG. 6A to FIG. 6E It is shown Figure 5 A sectional view of a modified example of .

[0016] Figures 7 to 15 is a cross-sectional view showing a capacitor according to another embodiment of the present invention.

[0017] Fig.16A is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0018] FIG. 16A to FIG. 17C is a cross-sectional view showing a capacitor according to another embodiment of the present invention.

[0019] Fig.18 is a flow chart describing an example of a method for depositing a hafnium zirconium oxide layer rich in hafnium oxide.

[0020] Fig.19 is a flow chart describing another example of a method of depositing a hafnium zirconium oxide layer rich in hafnium oxide.

[0021] Fig. 20 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0022] Figures 21 to 22B is a cross-sectional view showing a storage unit.

[0023] FIG. 23A to FIG. 23F is a cross-sectional view showing application of a capacitor 600 to a memory cell.

[0024] Fig.24 is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0025] Figure 25 to Figure 27 is a cross-sectional view showing a capacitor according to another embodiment of the present invention. DETAILED DESCRIPTION

[0026] Various embodiments of the present invention may be described in more detail below with reference to the accompanying drawings. However, the present invention may be embodied in different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention thorough and complete, and to enable those skilled in the art to fully understand the scope of the present invention. Throughout this disclosure, the same reference numerals in the various figures and embodiments of the present invention will refer to the same components.

[0027] The drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0028] It is further understood that when an element is referred to as being "connected" or "coupled to" another element, it may be directly on the other element, directly connected to or coupled to the other element, or there may be one or more intervening elements. In addition, the connection / coupling may not be limited to a physical connection, and may further include a non-physical connection, for example, a wireless connection.

[0029] In addition, it will also be understood that when an element is referred to as being “between” two elements, it can be the only element between the two elements, or one or more intervening elements may also be present.

[0030] It should be understood that the drawings are simplified schematic representations of the devices described and that well-known details have not been included in order to avoid obscuring aspects of the present invention.

[0031] It should also be noted that features present in one embodiment may be used with one or more features of another embodiment without departing from the scope of the present invention.

[0032] Hafnium oxide may exhibit ferroelectric FE. Hafnium zirconium oxide (HfZrO) in which hafnium oxide and zirconium oxide are mixed together may exhibit antiferroelectric AFE or ferroelectric FE by adjusting the content of hafnium oxide in the mixture. Hafnium zirconium oxide (HfZrO) may be hereinafter referred to as 'HZO'.

[0033] Table 1

[0034]

[0035] Table 1 describes the hafnium oxide content (x), zirconium oxide content (y), and thickness (t) of HZO for obtaining an antiferroelectric AFE or a ferroelectric FE.

[0036] Referring to Table 1, it can be seen that no matter what the ratio of hafnium oxide content (x) to zirconium oxide content (y) is, the first thickness In other words, when the hafnium oxide content (x) and the zirconium oxide content (y) are the same (x=y), when the hafnium oxide content (x) is greater than the zirconium oxide content (y) (x>y), and when the zirconium oxide content (y) is greater than the hafnium oxide content (x), HZO can exhibit an antiferroelectric AFE.

[0037] When the HZO is formed to satisfy the inequality When the layer of the second thickness t is formed, when the hafnium oxide content (x) and the zirconium oxide content (y) are the same and when the zirconium oxide content (y) is greater than the hafnium oxide content (x), an antiferroelectric AFE can be exhibited. However, when the hafnium oxide content (x) is greater than the zirconium oxide content (y), HZO can exhibit a ferroelectric FE.

[0038] When HZO is formed to have the inequality satisfying When the third thickness t of the layer is formed, when the zirconium oxide content (y) is greater than the hafnium oxide content (x), HZO can exhibit antiferroelectric AFE. However, when the hafnium oxide content (x) and the zirconium oxide content (y) are the same and when the hafnium oxide content (x) is greater than the zirconium oxide content (y), HZO can exhibit ferroelectric FE.

[0039] As described above, when the hafnium oxide content and the zirconium oxide content are the same, or when the hafnium oxide content is greater than the zirconium oxide content, the antiferroelectric AFE and ferroelectric FE of HZO can be selectively controlled by adjusting its thickness. When the zirconium oxide content is greater than the hafnium oxide content, the antiferroelectric AFE can be exhibited regardless of the thickness of HZO.

[0040] Hereinafter, a hafnium zirconium oxide in which the hafnium oxide content and the zirconium oxide content are the same may be referred to as a 'base hafnium zirconium oxide (base-HZO, B-HZO)'. A hafnium zirconium oxide in which the hafnium oxide content is greater than the zirconium oxide content may be referred to as a 'hafnium oxide-rich hafnium zirconium oxide (hafnium oxide-rich HZO, HR-HZO)'. A hafnium zirconium oxide in which the zirconium oxide content is greater than the hafnium oxide content may be referred to as a 'zirconium oxide-rich hafnium zirconium oxide (zirconium oxide-rich HZO, ZR-HZO)'. A hafnium zirconium oxide having ferroelectricity may be referred to as a 'ferroelectric hafnium zirconium oxide (ferroelectric HZO, FE-HZO)', and a hafnium zirconium oxide having antiferroelectricity may be referred to as an 'antiferroelectric hafnium zirconium oxide (antiferroelectric HZO, AFE-HZO)'.

[0041] Antiferroelectric hafnium zirconium oxide AFE-HZO can have a higher dielectric constant than the base hafnium zirconium oxide B-HZO and ferroelectric hafnium zirconium oxide FE-HZO, and can induce the property that the amount of charge increases in the voltage region where switching occurs, that is, the ultra-high k property.

[0042] Hereinafter, in the embodiments of the present invention, Hf x Zr y O can refer to hafnium zirconium oxide in which hafnium oxide and zirconium oxide are mixed with each other. In Hf x Zr y O, 'x' can refer to the hafnium oxide content or hafnium content, and 'y' can refer to the zirconium oxide content or zirconium content. Hafnium-rich hafnium zirconium oxide HR-HZO can also be referred to as hafnium-rich hafnium zirconium oxide. Zirconium-rich hafnium zirconium oxide HR-HZO can also be referred to as zirconium-rich hafnium zirconium oxide. Hf x Zr y O can also be represented by (HfO) x (ZrO) y where HfO represents hafnium oxide and ZrO represents zirconium oxide.

[0043] The base hafnium zirconium oxide B-HZO can include Hf x Zr y O (x = y = 0.5). Hf x Zr y O (x = y = 0.5) can refer to a material with the same hafnium oxide content (x) and zirconium oxide content (y). Hf x Zr y O (x = y = 0.5) can exhibit antiferroelectricity AFE when the thickness is about or less. When the thickness of Hf x Zr y O (x = y = 0.5) is greater than , it can exhibit ferroelectricity FE.

[0044] The hafnium-rich hafnium zirconium oxide HR-HZO can include Hf x Zr y O (x > y, 0.5 < x < 0.9). Hf x Zr y O (x > y, 0.5 < x < 0.9) can refer to a material with a hafnium oxide content (x) greater than the zirconium oxide content (y). When Hf x Zr y O (x > y, 0.5 < x < 0.9) is less than , it can exhibit antiferroelectricity AFE. When Hf x Zr y O (x > y, 0.5 < x < 0.9) has about When the thickness is equal to or greater than a certain value, it can exhibit ferroelectricity FE.

[0045] Zirconium-rich hafnium zirconium oxide (Zr-HfO) can include Hf x Zr y O (x < y, 0.5 < y < 0.7). Hf x Zr y O (x < y, 0.5 < y < 0.7) can refer to a material in which the zirconia content (y) is greater than the hafnia content (x). Hf x Zr y O (x < y, 0.5 < y < 0.7) can exhibit antiferroelectricity AFE not only when the thickness is about or greater, but also when the thickness is about or less. Hf x Zr y O (x < y, y ≥ 0.7) can exhibit antiferroelectricity AFE even when the zirconia content (z) is significantly greater than the hafnia content (x), that is, regardless of the thickness, it can exhibit antiferroelectricity AFE.

[0046] According to the above description, by controlling at least one parameter among the hafnia content (or hafnium content), zirconia content (or zirconium content), and thickness, HZO can exhibit ferroelectricity FE or antiferroelectricity AFE.

[0047] Figure 1 FIG. is a cross-sectional view showing a semiconductor device 100 according to an embodiment of the present invention.

[0048] Refer to Figure 1 , the semiconductor device 100 can include a capacitor C11. The capacitor C11 can include a first electrode BE, a second electrode TE, and a multilayer stack ML11 between the first electrode BE and the second electrode TE. The multilayer stack ML11 can include at least one antiferroelectric layer AFE1 and AFE2 and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML11 can further include at least one high bandgap layer HBG.

[0049] The multilayer stack ML11 may include a stack of a first high-k dielectric layer HK1, a first antiferroelectric layer AFE1, a high bandgap layer HBG, a second antiferroelectric layer AFE2, and a second high-k dielectric layer HK2 in the order described. The first high-k dielectric layer HK1 may be formed over the first electrode BE, and the first antiferroelectric layer AFE1 may be formed over the first high-k dielectric layer HK1. The high bandgap layer HBG may be formed over the first antiferroelectric layer AFE1, and the second antiferroelectric layer AFE2 may be formed over the high bandgap layer HBG. The second high-k dielectric layer HK2 may be formed over the second antiferroelectric layer AFE2, and the second electrode TE may be formed over the second high-k dielectric layer HK2. The multilayer stack ML11 may include at least one direct contact interface, including at least one direct contact interface where at least one antiferroelectric layer AFE1 and AFE2 is in direct contact with at least one high-k dielectric layer HK1 and HK2. For example, the first high-k dielectric layer HK1 and the first antiferroelectric layer AFE1 may be in direct contact, or the second antiferroelectric layer AFE2 and the second high-k dielectric layer HK2 may be in direct contact. In another example, the first high-k dielectric layer HK1 and the first antiferroelectric layer AFE1 may be in direct contact, and the second antiferroelectric layer AFE2 and the second high-k dielectric layer HK2 may be in direct contact.

[0050] The first antiferroelectric layer AFE1 may be made of or include hafnium (Hf), zirconium (Zr), and oxygen (O). The first antiferroelectric layer AFE1 may include an antiferroelectric hafnium zirconium oxide AFE-HZO. As the first antiferroelectric layer AFE1, the antiferroelectric hafnium zirconium oxide AFE-HZO may include at least one of a basic hafnium zirconium oxide B-HZO, a hafnium oxide-rich hafnium zirconium oxide HR-HZO, or a zirconium oxide-rich hafnium zirconium oxide (ZR-HZO). According to an embodiment of the present invention, the first antiferroelectric layer AFE1 may include a layer having about or smaller ( to ) of an antiferroelectric hafnium zirconium oxide AFE-HZO having a thickness of . For example, the first antiferroelectric layer AFE1 may include Hf in which the hafnium oxide content (x) and the zirconium oxide content (y) are the same. x Zr y O(x=y). In this case, the thickness can be about According to another embodiment of the present invention, the first antiferroelectric layer AFE1 may include Hf in which the hafnium oxide content (x) is greater than the zirconium oxide content (y). x Zr y O(x>y). In this case, the thickness can be less than about According to another embodiment of the present invention, the first antiferroelectric layer AFE1 may include Hf in which the zirconium oxide content (y) is greater than the hafnium oxide content (x). x Zr y O(y>x). In this case, the thickness can be about or smaller.

[0051] The second antiferroelectric layer AFE2 may be made of or include hafnium (Hf), zirconium (Zr) and oxygen (O). The second antiferroelectric layer AFE2 may include an antiferroelectric hafnium zirconium oxide AFE-HZO. As the second antiferroelectric layer AFE2, the antiferroelectric hafnium zirconium oxide AFE-HZO may include a basic hafnium zirconium oxide B-HZO, a hafnium zirconium oxide rich in hafnium oxide HR-HZO or a hafnium zirconium oxide rich in zirconium oxide (ZR-HZO). According to an embodiment of the present invention, the second antiferroelectric layer AFE2 may include a layer having about or smaller ( to ) of antiferroelectric hafnium zirconium oxide AFE-HZO. For example, the second antiferroelectric layer AFE2 may include Hf in which the hafnium oxide content (x) and the zirconium oxide content (y) are the same. x Zr y O(x=y). In this case, the thickness can be about According to another embodiment of the present invention, the second antiferroelectric layer AFE2 may include Hf in which the hafnium oxide content (x) is greater than the zirconium oxide content (y). x Zr y O(x>y). In this case, the thickness can be less than about According to another embodiment of the present invention, the second antiferroelectric layer AFE2 may include Hf in which the zirconium oxide content (y) is greater than the hafnium oxide content (x). x Zr y O(y>x). In this case, the thickness can be about or smaller.

[0052] The first and second antiferroelectric layers AFE1 and AFE2 may each be an antiferroelectric hafnium zirconium oxide AFE-HZO of the same type or the same material. For example, the first and second antiferroelectric layers AFE1 and AFE2 may each be about or less of the base hafnium zirconium oxide B-HZO. In addition, the first and second antiferroelectric layers AFE1 and AFE2 may each be less than about Hafnium oxide-rich hafnium zirconium oxide HR-HZO.

[0053] According to another embodiment of the present invention, the first and second antiferroelectric layers AFE1 and AFE2 may each be antiferroelectric hafnium zirconium oxide AFE-HZO of different materials. For example, the first antiferroelectric layer AFE1 may be approximately or less of the base hafnium zirconium oxide B-HZO, while the second antiferroelectric layer AFE2 may be less than about In addition, the first antiferroelectric layer AFE1 may be less than about The hafnium oxide-rich hafnium zirconium oxide HR-HZO, and the second antiferroelectric layer AFE2 may be about Or smaller base hafnium zirconium oxide B-HZO.

[0054] According to another embodiment of the present invention, the first and second antiferroelectric layers AFE1 and AFE2 may each include different antiferroelectric hafnium zirconium oxides and may have the same thickness or different thicknesses.

[0055] According to another embodiment of the present invention, the first and second antiferroelectric layers AFE1 and AFE2 may both include the same antiferroelectric hafnium zirconium oxide AFE-HZO. Here, the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2 may have the same thickness or different thicknesses. For example, the first and second antiferroelectric layers AFE1 and AFE2 may both be less than about The first antiferroelectric layer AFE1 may be about or less of the base hafnium zirconium oxide B-HZO, while the second antiferroelectric layer AFE2 may be less than about The basis of hafnium zirconium oxide B-HZO.

[0056] According to another embodiment of the present invention, the first and second antiferroelectric layers AFE1 and AFE2 may both be antiferroelectric hafnium zirconium oxides having the same hafnium oxide content. For example, the first antiferroelectric layer AFE1 may include a first hafnium oxide-rich hafnium zirconium oxide HR-HZO, and the second antiferroelectric layer AFE2 may include a second hafnium oxide-rich hafnium zirconium oxide HR-HZO. Here, the first hafnium oxide-rich hafnium zirconium oxide HR-HZO and the second hafnium oxide-rich hafnium zirconium oxide HR-HZO may have the same hafnium oxide content.

[0057] According to another embodiment of the present invention, the first and second antiferroelectric layers AFE1 and AFE2 may each be an antiferroelectric hafnium zirconium oxide having different hafnium oxide contents. For example, the first antiferroelectric layer AFE1 may include a first hafnium oxide-rich hafnium zirconium oxide HR-HZO, and the second antiferroelectric layer AFE2 may include a second hafnium oxide-rich hafnium zirconium oxide HR-HZO. Here, the first hafnium oxide-rich hafnium zirconium oxide HR-HZO and the second hafnium oxide-rich hafnium zirconium oxide HR-HZO may have different hafnium oxide contents. The hafnium oxide content of the first hafnium oxide-rich hafnium zirconium oxide HR-HZO may be greater than the hafnium oxide content of the second hafnium oxide-rich hafnium zirconium oxide HR-HZO. The hafnium oxide content of the second hafnium oxide-rich hafnium zirconium oxide HR-HZO may be greater than the hafnium oxide content of the first hafnium oxide-rich hafnium zirconium oxide HR-HZO.

[0058] The high bandgap layer HBG can be used to suppress the leakage current of the multilayer stack ML11. The high bandgap layer HBG can be made of or include a high energy bandgap material. The high bandgap layer HBG can include a material having a larger energy bandgap (hereinafter referred to as "bandgap") than the first and second antiferroelectric layers AFE1 and AFE2. The high bandgap layer HBG can be made of a material different from the first and second antiferroelectric layers AFE1 and AFE2. The high bandgap layer HBG can be made of or include a high-k material, and can have a lower dielectric constant than the first and second antiferroelectric layers AFE1 and AFE2. The high bandgap layer HBG can have a higher dielectric constant than silicon oxide and silicon nitride. The high bandgap layer HBG can be made of or include an aluminum-containing material or a beryllium-containing material. The high bandgap layer HBG can be made of or include aluminum oxide or beryllium oxide. The high bandgap layer HBG may be thinner than each of the first and second antiferroelectric layers AFE1 and AFE2. According to another embodiment of the present invention, the high bandgap layer HBG may be made of or include aluminum-doped zirconium oxide, aluminum-doped hafnium oxide, beryllium-doped zirconium oxide, or beryllium-doped hafnium oxide.

[0059] The first and second antiferroelectric layers AFE1 and AFE2 may have a higher dielectric constant than the first and second high-k dielectric layers HK1 and HK2. The first high-k dielectric layer HK1 may improve the crystallinity of the first antiferroelectric layer AFE1, and the first high-k dielectric layer HK1 may be used to control the incomplete switching region of the interface between the first antiferroelectric layer AFE1 and the first electrode BE. The second high-k dielectric layer HK2 may improve the crystallinity of the second antiferroelectric layer AFE2, and may also be used to control the incomplete switching region of the interface between the second antiferroelectric layer AFE2 and the second electrode TE.

[0060] The first high-k dielectric layer HK1 may include at least one of hafnium and zirconium. The first high-k dielectric layer HK1 may be made of or include hafnium oxide or zirconium oxide. The first high-k dielectric layer HK1 may be made of a single layer of hafnium oxide or a single layer of zirconium oxide. The bottom of the first high-k dielectric layer HK1 may directly contact the first electrode BE, and the top of the first high-k dielectric layer HK1 may directly contact the first antiferroelectric layer AFE1. According to another embodiment of the present invention, an additional material may be further formed between the first high-k dielectric layer HK1 and the first electrode BE.

[0061] The second high-k dielectric layer HK2 may include at least one of hafnium and zirconium. The second high-k dielectric layer HK2 may be made of or include hafnium oxide or zirconium oxide. The second high-k dielectric layer HK2 may be made of a single layer of hafnium oxide or a single layer of zirconium oxide. The bottom of the second high-k dielectric layer HK2 may directly contact the second antiferroelectric layer AFE2, and the top of the second high-k dielectric layer HK2 may directly contact the second electrode TE. According to another embodiment of the present invention, an additional material may be further formed between the second high-k dielectric layer HK2 and the second electrode TE.

[0062] The first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 may be the same material. For example, each of the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 may be made of a single layer of hafnium oxide. Additionally, both the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 may be a single layer of zirconium oxide.

[0063] The first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 may be different materials. For example, the first high-k dielectric layer HK1 may be made of a single layer of hafnium oxide, while the second high-k dielectric layer HK2 may be made of a single layer of zirconium oxide. Similarly, the first high-k dielectric layer HK1 may be made of a single layer of zirconium oxide, while the second high-k dielectric layer HK2 may be made of a single layer of hafnium oxide.

[0064] The first high-k dielectric layer HK1 or the second high-k dielectric layer HK2 may be an antiferroelectric material. For example, the first high-k dielectric layer HK1 may include zirconium-rich hafnium zirconium oxide (ZR-HZO), while the second high-k dielectric layer HK2 may be hafnium oxide or zirconium oxide. According to another embodiment of the present invention, the first high-k dielectric layer HK1 may be hafnium oxide or zirconium oxide, while the second high-k dielectric layer HK2 may include zirconium-rich hafnium zirconium oxide (ZR-HZO). Zirconium-rich hafnium zirconium oxide (ZR-HZO) may include Hf x Zr y O(x<y), such as Hf 0.3 Zr 0.7 O.

[0065] The first and second high-k dielectric layers HK1 and HK2 may be thicker than the first and second antiferroelectric layers AFE1 and AFE2. The first and second high-k dielectric layers HK1 and HK2 may have the same thickness as the first and second antiferroelectric layers AFE1 and AFE2.

[0066] As described above, the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2 may be made of or include a high-k material, and the high bandgap layer HBG may include a material having a higher bandgap than the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2. The dielectric constants of the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2 may be higher than those of the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2.

[0067] The first and second high-k dielectric layers HK1 and HK2 may both include hafnium or zirconium, and the first and second antiferroelectric layers AFE1 and AFE2 may both include hafnium and zirconium. The first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 may be hafnium oxide or zirconium oxide, and the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2 may be antiferroelectric hafnium zirconium oxide. The first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 may be ferroelectric hafnium oxide, and the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2 may both be antiferroelectric hafnium zirconium oxide.

[0068] According to some embodiments of the present invention, the multilayer stack ML11 may include a HfO2 / AFE-HZO / Al2O3 / AFE-HZO / HfO2 stack. The HfO2 / AFE-HZO / Al2O3 / AFE-HZO / HfO2 stack may include a first hafnium oxide layer (HfO2), a first antiferroelectric hafnium zirconium oxide layer AFE-HZO, an aluminum oxide layer (Al2O3), a second antiferroelectric hafnium zirconium oxide layer AFE-HZO, and a second hafnium oxide layer (HfO2) stacked in the following order. The first hafnium oxide layer (HfO2) may correspond to the first high-k dielectric layer HK1, and the second hafnium oxide layer (HfO2) may correspond to the second high-k dielectric layer HK2. The aluminum oxide layer (Al2O3) may correspond to the high bandgap layer HBG. The first antiferroelectric hafnium zirconium oxide layer AFE-HZO may correspond to the first antiferroelectric layer AFE1 , and the second antiferroelectric hafnium zirconium oxide layer AFE-HZO may be the second antiferroelectric layer AFE2 .

[0069] According to some embodiments of the present invention, the multilayer stack ML11 may include a ZrO2 / AFE-HZO / Al2O3 / AFE-HZO / ZrO2 stack. The ZrO2 / AFE-HZO / Al2O3 / AFE-HZO / ZrO2 stack may include a first zirconium oxide layer (ZrO2), a first antiferroelectric hafnium zirconium oxide layer AFE-HZO, an aluminum oxide layer (Al2O3), a second antiferroelectric hafnium zirconium oxide layer AFE-HZO, and a second zirconium oxide layer (ZrO2) stacked in the following order. The first zirconium oxide layer (ZrO2) may correspond to the first high-k dielectric layer HK1, and the second zirconium oxide layer (ZrO2) may correspond to the second high-k dielectric layer HK2. The aluminum oxide layer (Al2O3) may correspond to the high bandgap layer HBG. The first antiferroelectric hafnium zirconium oxide layer AFE-HZO may correspond to the first antiferroelectric layer AFE1 , and the second antiferroelectric hafnium zirconium oxide layer AFE-HZO may correspond to the second antiferroelectric layer AFE2 .

[0070] According to some embodiments of the present invention, the multilayer stack ML11 may include a ZrO2 / AFE-HZO / Al-doped ZrO2 / AFE-HZO / ZrO2 stack, a HfO2 / AFE-HZO / Al-doped HfO2 / AFE-HZO / HfO2 stack, a ZrO2 / AFE-HZO / Al2O3 / AFE-HZO / HfO2 stack, or a HfO2 / AFE-HZO / Al2O3 / AFE-HZO / ZrO2 stack.

[0071] The first high-k dielectric layer HK1 , the first antiferroelectric layer AFE1 , the high bandgap layer HBG, the second antiferroelectric layer AFE2 , and the second high-k dielectric layer HK2 may be formed by atomic layer deposition (ALD).

[0072] The high bandgap layer HBG may have a or smaller ( to ), and the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2 may have a thickness of about or smaller ( to ). The first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 may have a thickness of about or smaller ( to The first and second high-k dielectric layers HK1 and HK2 and the first and second antiferroelectric layers AFE1 and AFE2 may have the same thickness or different thicknesses.

[0073] Figure 2 It shows that according to Figure 1 sectional view of a capacitor C12 of a modified example.

[0074] refer to Figure 2 , capacitor C12 can be similar to Figure 1 The capacitor C11 of the capacitor C11 can be omitted in the following text. Figure 1 Detailed description of the constituent elements in .

[0075] The capacitor C12 may include a first electrode BE, a second electrode TE, and a multilayer stack ML12 located between the first electrode BE and the second electrode TE. The multilayer stack ML12 may include at least one antiferroelectric layer AFE1 and AFE2 and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML12 may further include at least one high bandgap layer HBG. The multilayer stack ML12 may further include a leakage barrier layer LBL and an interface control layer ICL.

[0076] The multilayer stack ML12 may include a first high-k dielectric layer HK1, a first antiferroelectric layer AFE1, a high bandgap layer HBG, a second antiferroelectric layer AFE2, a second high-k dielectric layer HK2, a leakage barrier layer LBL, and an interface control layer ICL stacked in this order.

[0077] The leakage barrier layer LBL and the interface control layer ICL may be located between the second high-k dielectric layer HK2 and the second electrode TE. The leakage barrier layer LBL may be located between the second high-k dielectric layer HK2 and the interface control layer ICL. The interface control layer ICL may be located between the leakage barrier layer LBL and the second electrode TE.

[0078] Suitable materials for the leakage barrier layer LBL may include high bandgap materials with high energy bandgap. The leakage barrier layer LBL may include a material having a larger energy bandgap than the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2. The leakage barrier layer LBL may include a high-k material whose dielectric constant may be lower than the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2. The leakage barrier layer LBL may have a higher dielectric constant than silicon oxide and silicon nitride. The leakage barrier layer LBL may be made of or include aluminum oxide or beryllium oxide. The leakage barrier layer LBL may be formed by atomic layer deposition (ALD). The leakage barrier layer LBL may be thinner than each of the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2. Since the dielectric constants of the leakage barrier layer LBL and the high bandgap layer HBG are relatively lower than those of the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2, in order to increase the capacitance of the capacitor C12, the leakage barrier layer LBL and the high bandgap layer HBG may be thinner than each of the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2. The leakage barrier layer LBL and the high bandgap layer HBG may each have a dielectric constant of about or less. The leakage barrier layer LBL and the high bandgap layer HBG may have the same thickness. The leakage barrier layer LBL and the high bandgap layer HBG may have different thicknesses. The leakage barrier layer LBL may be thicker than the high bandgap layer HBG.

[0079] According to another embodiment of the present invention, the leakage barrier layer LBL and the high bandgap layer HBG may be formed of the same type of material or the same material. For example, the leakage barrier layer LBL may be made of or include aluminum-doped zirconium oxide or beryllium-doped zirconium oxide.

[0080] The interface control layer ICL can be used to protect the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the high bandgap layer HBG, the second antiferroelectric layer AFE2 and the second high-k dielectric layer HK2 when forming the second electrode TE. In addition, the interface control layer ICL can reduce the leakage current of the multilayer stack ML12.

[0081] The interface control layer ICL may be made of a material that is reduced prior to the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2 when the second electrode TE is deposited. The interface control layer ICL may be used as a leakage current blocking layer having a large effective work function (eWF) and a large conduction band offset (CBO). In addition, the interface control layer ICL may not increase the equivalent oxide film thickness T of the multilayer stack ML12. ox .

[0082] The interface control layer ICL may be made of a material having a high electronegativity. The interface control layer ICL may have a higher Pauling electronegativity than the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2. The interface control layer ICL may include a material having a high Pauling electronegativity (hereinafter referred to as electronegativity) compared to the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2. When the electronegativity is high, it is difficult to be oxidized and is easily reduced. Therefore, the interface control layer ICL may replace the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2 for deoxidation. The interface control layer ICL may prevent the first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the second high-k dielectric layer HK2 from losing oxygen.

[0083] The interface control layer ICL may include atoms with high electronegativity, for example, metal atoms, silicon atoms or germanium atoms. The interface control layer ICL may be made of titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni) or a combination thereof, or include titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), nickel (Ni) or a combination thereof. The interface control layer ICL may include a stack of molybdenum and molybdenum nitride (Mo / MoN) or a stack of tungsten and tungsten nitride (W / WN). The interface control layer ICL may include a conductive material containing highly electronegative atoms, and thus the interface control layer ICL may be used as a part of the second electrode TE.

[0084] The interface control layer ICL can be made of titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO2), tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide or a combination thereof, or include titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO2), tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, nickel oxide or a combination thereof.

[0085] According to some embodiments of the present invention, the multilayer stack ML12 may include a HfO2 / AFE-HZO / Al2O3 / AFE-HZO / HfO2 / Al2O3 / TiO2 stack. The HfO2 / AFE-HZO / Al2O3 / AFE-HZO / HfO2 / Al2O3 / TiO2 stack may include a first hafnium oxide layer (HfO2), a first antiferroelectric hafnium zirconium oxide layer AFE-HZ O, a first aluminum oxide layer (Al2O3), a second antiferroelectric hafnium zirconium oxide layer AFE-HZO, a second hafnium oxide layer (H fO2), a second aluminum oxide layer (Al2O3), and a titanium oxide layer (TiO2) stacked in the following order. The first hafnium oxide layer (HfO2) may correspond to the first high-k dielectric layer HK1, and the second hafnium oxide layer (HfO2) may correspond to the second high-k dielectric layer HK2. The aluminum oxide layer (Al2O3) may correspond to the high bandgap layer HBG. The first antiferroelectric hafnium zirconium oxide layer AFE-HZO may correspond to the first antiferroelectric layer AFE1, and the second antiferroelectric hafnium zirconium oxide layer AFE-HZO may correspond to the second antiferroelectric layer AFE2. The second aluminum oxide layer (Al2O3) may correspond to the leakage barrier layer LBL, and the titanium oxide layer (TiO2) may correspond to the interface control layer ICL.

[0086] According to some embodiments of the present invention, the multilayer stack ML12 may include a ZrO2 / AFE-HZO / Al2O3 / AFE-HZO / ZrO2 / Al2O3 / TiO2 stack. The ZrO2 / AFE-HZO / Al2O3 / AFE-HZO / ZrO2 / Al2O3 / TiO2 stack may include a first zirconium oxide layer (ZrO2), a first antiferroelectric hafnium zirconium oxide AFE-HZO, an aluminum oxide layer (Al2O3), a second antiferroelectric hafnium zirconium oxide AFE-HZO, a second zirconium oxide layer (ZrO2), a second aluminum oxide layer (Al2O3), and a titanium oxide layer (TiO2) stacked in the following order. The first zirconium oxide layer (ZrO2) may correspond to the first high-k dielectric layer HK1, and the second zirconium oxide layer (ZrO2) may correspond to the second high-k dielectric layer HK2. The aluminum oxide layer (Al2O3) may correspond to the high bandgap layer HBG. The first antiferroelectric hafnium zirconium oxide layer AFE-HZO may correspond to the first antiferroelectric layer AFE1, the second antiferroelectric hafnium zirconium oxide layer AFE-HZO may correspond to the second antiferroelectric layer AFE2. The second aluminum oxide layer (Al2O3) may correspond to the leakage barrier layer LBL, and the titanium oxide layer (TiO2) may correspond to the interface control layer ICL.

[0087] According to some embodiments of the present invention, the multilayer stack ML12 may include a ZrO2 / AFE-HZO / Al-doped ZrO2 / AFE-HZO / ZrO2 / Al2O3 / TiO2 stack, a HfO2 / AFE-HZO / Al-doped HfO2 / AFE-HZO / HfO2 / Al2O3 / TiO2 stack, a ZrO2 / AFE-HZO / Al2O3 / AFE-HZO / HfO2 / Al2O3 / TiO2 stack, or a HfO2 / AFE-HZO / Al2O3 / AFE-HZO / ZrO2 / Al2O3 / TiO2 stack. The aluminum oxide layer (Al2O3), the aluminum-doped zirconium oxide layer (Al-doped ZrO2), and the aluminum-doped hafnium oxide layer (Al-doped HfO2) may correspond to the high bandgap layer HBG.

[0088] Figure 3 is a cross-sectional view showing a capacitor C13 according to another embodiment of the present invention.

[0089] refer to Figure 3 , capacitor C13 can be similar to Figure 1 The capacitor C11 of the capacitor C11 can be omitted in the following text. Figure 1 Detailed description of the constituent elements in .

[0090] The capacitor C13 may include a first electrode BE, a second electrode TE, and a multilayer stack ML13 located between the first electrode BE and the second electrode TE. The multilayer stack ML13 may include at least one antiferroelectric layer AFE1 and AFE2 and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML13 may further include at least one high bandgap layer HBG.

[0091] The multilayer stack ML13 may include a first antiferroelectric layer AFE1 , a first high-k dielectric layer HK1 , a high bandgap layer HBG, a second high-k dielectric layer HK2 , and a second antiferroelectric layer AFE2 stacked in this order.

[0092] The first antiferroelectric layer AFE1 may directly contact the first electrode BE and the first high-k dielectric layer HK1. The first antiferroelectric layer AFE1 may be located between the first electrode BE and the first high-k dielectric layer HK1. The second antiferroelectric layer AFE2 may directly contact the second electrode TE and the second high-k dielectric layer HK2. The second antiferroelectric layer AFE2 may be located between the second electrode TE and the second high-k dielectric layer HK2.

[0093] The high bandgap layer HBG may be located between the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2. The high bandgap layer HBG may directly contact the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2. Return to Reference Figure 1 , the high bandgap layer HBG of the capacitor C11 may be located between the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2.

[0094] The high bandgap layer HBG may be made of or include a high bandgap material having a large energy bandgap. The high bandgap layer HBG may include a material having a larger energy bandgap than the first and second high-k dielectric layers HK1 and HK2. The high bandgap layer HBG may be made of a material different from the first and second high-k dielectric layers HK1 and HK2. The high bandgap layer HBG may be made of or include a high-k material, but may have a smaller dielectric constant than the first and second high-k dielectric layers HK1 and HK2. The high bandgap layer HBG may have a dielectric constant greater than silicon oxide and silicon nitride. The high bandgap layer HBG may be made of or include an aluminum-containing material or a beryllium-containing material. The high bandgap layer HBG may be made of or include aluminum oxide or beryllium oxide. The high bandgap layer HBG may be thinner than each of the first and second high-k dielectric layers HK1 and HK2.

[0095] According to another embodiment of the present invention, the high bandgap layer HBG may not isolate the grains of the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2. For example, the grains of the first high-k dielectric layer HK1, the high bandgap layer HBG, and the second high-k dielectric layer HK2 may be in a continuous state without being spaced apart. The high bandgap layer HBG may have a thin thickness that does not space the grains of the first high-k dielectric layer HK1 and the grains of the second high-k dielectric layer HK2 apart. Therefore, the grains of the first high-k dielectric layer HK1 and the grains of the second high-k dielectric layer HK2 may be continuous in the vertical direction.

[0096] When the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 include zirconium oxide, the high bandgap layer HBG may be aluminum-doped zirconium oxide or beryllium-doped zirconium oxide. When the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 include hafnium oxide, the high bandgap layer HBG may be aluminum-doped hafnium oxide or beryllium-doped hafnium oxide. The high bandgap layer HBG, the first high-k dielectric layer HK1, and the second high-k dielectric layer HK2 may all have a tetragonal crystal structure.

[0097] Figures 4A to 4E It shows that according to Figure 3 A cross-sectional view of a capacitor of a modified example.

[0098] refer to Figure 4A , capacitor C14 can be similar to Figure 3 The capacitor C13 that also appears in the Figure 3 Detailed description of the constituent elements in .

[0099] The capacitor C14 may include a first electrode BE, a second electrode TE, and a multilayer stack ML14 located between the first electrode BE and the second electrode TE. The multilayer stack ML14 may include at least one antiferroelectric layer AFE1 and AFE2 and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML14 may further include at least one high bandgap layer HBG. The multilayer stack ML14 may further include a leakage barrier layer LBL and an interface control layer ICL.

[0100] The multilayer stack ML14 may include a first antiferroelectric layer AFE1 , a first high-k dielectric layer HK1 , a high bandgap layer HBG, a second high-k dielectric layer HK2 , a second antiferroelectric layer AFE2 , a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order.

[0101] The leakage barrier layer LBL and the interface control layer ICL may be located between the second antiferroelectric layer AFE2 and the second electrode TE. The leakage barrier layer LBL may be located between the second antiferroelectric layer AFE and the interface control layer ICL. The interface control layer ICL may be located between the leakage barrier layer LBL and the second electrode TE. For a detailed description of the leakage barrier layer LBL and the interface control layer ICL, reference may be made to Figure 2 and accompanying instructions.

[0102] An application example of the multilayer stack ML14 can be described as follows.

[0103] refer to Figure 4B , the multilayer stack ML14A may include an AFE-HZO / ZrO2 / Al2O3 / ZrO2 / AFE-HZO / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may each include antiferroelectric hafnium zirconium oxide AFE-HZO. The first and second high-k dielectric layers HK1 and HK2 may both include zirconium oxide (ZrO2). The high bandgap layer HBG may be made of or include aluminum oxide (Al2O3). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2).

[0104] Therefore, the multilayer stack ML14A can be made of antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order, or include antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order.

[0105] refer to Figure 4C, the multilayer stack ML14B may include an AFE-HZO / ZrO2 / Al-doped ZrO2 / ZrO2 / AFE-HZO / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may both include antiferroelectric hafnium zirconium oxide AFE-HZO. The first and second high-k dielectric layers HK1 and HK2 may both include zirconium oxide (ZrO2). The high bandgap layer HBG may be made of aluminum-doped zirconium oxide (Al-doped ZrO2) or include aluminum-doped zirconium oxide (Al-doped ZrO2). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2). In ZrO 2 / Al-doped ZrO 2 / ZrO 2 , the aluminum-doped zirconium oxide (Al-doped ZrO 2 ) may not separate the grains of zirconium oxide (ZrO 2 ).

[0106] Therefore, the multilayer stack ML14B can be made of antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum-doped zirconium oxide (Al-doped ZrO2), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order, or include antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum-doped zirconium oxide (Al-doped ZrO2), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order.

[0107] In the multilayer stack ML14B, aluminum-doped zirconium oxide (Al-doped ZrO2) may be thinner than zirconium oxide (ZrO2). Zirconium oxide (ZrO2) and aluminum-doped zirconium oxide (Al-doped ZrO2) may both have a tetragonal crystal structure. ZrO2 / Al-doped ZrO2 / ZrO2 may also be referred to as aluminum-embedded zirconium oxide (Al-embedded ZrO2).

[0108] Aluminum-doped zirconium oxide (Al-doped ZrO2) can be a high bandgap layer HBG, which is similar to Figure 4B The high bandgap layer HBG in the MOSFET is different from aluminum oxide (Al2O3). Figure 4B The thickness of the aluminum oxide (Al2O3) may separate the grains of the lower zirconium oxide (ZrO2) from the grains of the upper zirconium oxide (ZrO2). The aluminum oxide (Al2O3) may be thicker than the aluminum-doped zirconium oxide (AZ). The grains of the lower zirconium oxide (ZrO2) and the grains of the upper zirconium oxide (ZrO2) may be continuous without being separated. Figure 4CThe grains of the lower zirconia (ZrO2) and the grains of the upper zirconia (ZrO2) can be separated by Figure 4B separated by alumina (Al2O3).

[0109] refer to Figure 4D , the multilayer stack ML14C may include an AFE-HZO / HfO2 / Al2O3 / HfO2 / AFE-HZO / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may both include antiferroelectric hafnium zirconium oxide AFE-HZO. The first and second high-k dielectric layers HK1 and HK2 may both include hafnium oxide (HfO2). The high bandgap layer HBG may be made of or include aluminum oxide (Al2O3). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2).

[0110] Therefore, the multilayer stack ML14C can be made of antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order, or include antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order.

[0111] refer to Figure 4E , the multilayer stack ML14D may include an AFE-HZO / HfO2 / Al-doped HfO2 / HfO2 / AFE-HZO / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may both include antiferroelectric hafnium zirconium oxide AFE-HZO. The first and second high-k dielectric layers HK1 and HK2 may both include hafnium oxide (HfO2). The high bandgap layer HBG may be made of or include aluminum-doped hafnium oxide (Al-doped HfO2). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2). In HfO2 / Al-doped HfO2 / HfO2, aluminum-doped hafnium oxide (Al-doped HfO2) may not isolate grains of hafnium oxide (HfO2).

[0112] Therefore, the multilayer stack ML14D can be made of antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum-doped hafnium oxide (Al-doped HfO2), hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order, or include antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum-doped hafnium oxide (Al-doped HfO2), hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order.

[0113] Figure 5 is a cross-sectional view showing a capacitor C15 according to another embodiment of the present invention.

[0114] refer to Figure 5 , the capacitor C15 may include a first electrode BE, a second electrode TE, and a multilayer stack ML15 located between the first electrode BE and the second electrode TE. The multilayer stack ML15 may include at least one antiferroelectric layer AFE1 and AFE2 and at least one high-k dielectric layer HK1, HK2, and HK3. The multilayer stack ML15 may further include a leakage barrier layer LBL and an interface control layer ICL. According to another embodiment of the present invention, the leakage barrier layer LBL and the interface control layer ICL in the multilayer stack ML15 may be omitted.

[0115] The multilayer stack ML15 may include a first high-k dielectric layer HK1, a first antiferroelectric layer AFE1, a second high-k dielectric layer HK2, a high bandgap layer HBG, a third high-k dielectric layer HK3, a second antiferroelectric layer AFE2, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order. The first antiferroelectric layer AFE1 may be located between the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2. The second antiferroelectric layer AFE2 may be located between the third high-k dielectric layer HK3 and the leakage barrier layer LBL. The high bandgap layer HBG may be located between the second high-k dielectric layer HK2 and the third high-k dielectric layer HK3.

[0116] The first high-k dielectric layer HK1 , the second high-k dielectric layer HK2 , and the third high-k dielectric layer HK3 may be made of the same material or different materials.

[0117] The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, and the third high-k dielectric layer HK3 may be made of or include hafnium or zirconium. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, and the third high-k dielectric layer HK3 may be made of or include hafnium oxide or zirconium oxide. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, and the third high-k dielectric layer HK3 may be made of a single layer of hafnium oxide or a single layer of zirconium oxide. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, and the third high-k dielectric layer HK3 may have a tetragonal crystal structure.

[0118] The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, and the third high-k dielectric layer HK3 may be different materials. For example, the first high-k dielectric layer HK1 may be made of a single layer of hafnium oxide, and the second high-k dielectric layer HK2 and the third high-k dielectric layer HK3 may be made of a single layer of zirconium oxide. In addition, the first high-k dielectric layer HK1 may be made of a single layer of zirconium oxide, and the second high-k dielectric layer HK2 and the third high-k dielectric layer HK3 may be made of a single layer of hafnium oxide. In addition, the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 may be made of a single layer of hafnium oxide, and the third high-k dielectric layer HK3 may be made of a single layer of zirconium oxide. The first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 may be made of a single layer of zirconium oxide, and the third high-k dielectric layer HK3 may be made of a single layer of hafnium oxide.

[0119] At least one of the first high-k dielectric layer HK1, the second high-k dielectric layer HK2, and the third high-k dielectric layer HK3 may be an antiferroelectric material. For example, the first high-k dielectric layer HK1 may be zirconium oxide-rich hafnium zirconium oxide (ZR-HZO), and the second high-k dielectric layer HK2 and the third high-k dielectric layer HK3 may be hafnium oxide or zirconium oxide. In addition, the first high-k dielectric layer HK1 may be hafnium oxide or zirconium oxide, and the second high-k dielectric layer HK2 and the third high-k dielectric layer HK3 may be zirconium oxide-rich hafnium zirconium oxide (ZR-HZO).

[0120] The multilayer stack ML15 may include a ZrO2 / AFE-HZO / ZrO2 / Al2O3 / ZrO2 / AFE-HZO / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may each include antiferroelectric hafnium zirconium oxide AFE-HZO. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, and the third high-k dielectric layer HK3 may include zirconium oxide (ZrO2). The high bandgap layer HBG may be made of or include aluminum oxide (Al2O3). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2).

[0121] Therefore, the multilayer stack ML15 may include zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order.

[0122] According to another embodiment of the present invention, the multilayer stack ML15 may include a ZrO2 / AFE-HZO / ZrO2 / Al-doped ZrO2 / ZrO2 / AFE-HZO / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may each include antiferroelectric hafnium zirconium oxide AFE-HZO. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, and the third high-k dielectric layer HK3 may include zirconium oxide (ZrO2). The high bandgap layer HBG may be made of aluminum-doped zirconium oxide (Al-doped ZrO2) or include aluminum-doped zirconium oxide (Al-doped ZrO2). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2). Therefore, the multilayer stack ML15 may include zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum-doped zirconium oxide (Al-doped ZrO2), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order.

[0123] According to another embodiment of the present invention, the multilayer stack ML15 may include a HfO2 / AFE-HZO / HfO2 / Al-doped HfO2 / HfO2 / AFE-HZO / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may each include antiferroelectric hafnium zirconium oxide AFE-HZO. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, and the third high-k dielectric layer HK3 may be made of or include hafnium oxide (HfO2), respectively. The high bandgap layer HBG may be made of or include aluminum-doped hafnium oxide (Al-doped HfO2). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2). Therefore, the multilayer stack ML15 can be made of hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum-doped hafnium oxide (Al-doped HfO2), hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order, or include hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum-doped hafnium oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order.

[0124] According to another embodiment of the present invention, the multilayer stack ML15 may include a HfO2 / AFE-HZO / HfO2 / Al2O3 / HfO2 / AFE-HZO / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may each include antiferroelectric hafnium zirconium oxide AFE-HZO. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, and the third high-k dielectric layer HK3 may be made of or include hafnium oxide (HfO2), respectively. The high bandgap layer HBG may be made of or include aluminum oxide (Al2O3). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2). Therefore, the multilayer stack ML15 can be made of hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2), or include hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, aluminum oxide (Al2O3) and titanium oxide (TiO2).

[0125] Figures 6A to 6E It is shown Figure 5 A sectional view of a modified example of .

[0126] refer to Fig. 6A , the capacitor C16 may include a first electrode BE, a second electrode TE, and a multilayer stack ML16 located between the first electrode BE and the second electrode TE. The multilayer stack ML16 may include at least one antiferroelectric layer AFE1 and AFE2 and at least one high-k dielectric layer HK1, HK2, HK3, and HK4. The multilayer stack ML16 may further include a leakage barrier layer LBL and an interface control layer ICL. According to another embodiment of the present invention, the leakage barrier layer LBL and the interface control layer ICL of the multilayer stack ML16 may be omitted.

[0127] The multilayer stack ML16 may include a first high-k dielectric layer HK1, a first antiferroelectric layer AFE1, a second high-k dielectric layer HK2, a high bandgap layer HBG, a third high-k dielectric layer HK3, a second antiferroelectric layer AFE2, a fourth high-k dielectric layer HK4, a leakage barrier layer LBL, and an interface control layer ICL. The first antiferroelectric layer AFE1 may be located between the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2. The second antiferroelectric layer AFE2 may be located between the third high-k dielectric layer HK3 and the fourth high-k dielectric layer HK4. The high bandgap layer HBG may be located between the second high-k dielectric layer HK2 and the third high-k dielectric layer HK3.

[0128] The first high-k dielectric layer HK1 , the second high-k dielectric layer HK2 , the third high-k dielectric layer HK3 , and the fourth high-k dielectric layer HK4 may be made of the same material or different materials.

[0129] The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, and the fourth high-k dielectric layer HK4 may be made of or include hafnium or zirconium. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, and the fourth high-k dielectric layer HK4 may be made of or include hafnium oxide or zirconium oxide. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, and the fourth high-k dielectric layer HK4 may be made of a single layer of hafnium oxide or a single layer of zirconium oxide.

[0130] At least one of the first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, and the fourth high-k dielectric layer HK4 may be an antiferroelectric material. At least one of the first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, and the fourth high-k dielectric layer HK4 may be hafnium zirconium oxide rich in zirconium oxide.

[0131] refer to Figure 6B, the multilayer stack ML16A may include a ZrO2 / AFE-HZO / ZrO2 / Al2O3 / ZrO2 / AFE-HZO / ZrO2 / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may each include antiferroelectric hafnium zirconium oxide AFE-HZO. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, and the fourth high-k dielectric layer HK4 may include zirconium oxide (ZrO2). The high bandgap layer HBG may be made of or include aluminum oxide (Al2O3). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2).

[0132] Therefore, the multilayer stack ML20 may include zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum oxide (Al2O3) and titanium oxide (ZrO2).

[0133] refer to Figure 6C , the multilayer stack ML16B may include a ZrO2 / AFE-HZO / ZrO2 / Al-doped ZrO2 / ZrO2 / AFE-HZO / ZrO2 / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may both include antiferroelectric hafnium zirconium oxide AFE-HZO. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, and the fourth high-k dielectric layer HK4 may include zirconium oxide (ZrO2). The high bandgap layer HBG may be made of or include aluminum-doped zirconium oxide (Al-doped ZrO2). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2).

[0134] Therefore, the multilayer stack ML16B may include zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum-doped zirconium oxide (Al-doped ZrO2), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order.

[0135] refer to Fig.6D, the multilayer stack ML16C may include a HfO2 / AFE-HZO / ZrO2 / Al2O3 / ZrO2 / AFE-HZO / HfO2 / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may both include antiferroelectric hafnium zirconium oxide AFE-HZO. The second high-k dielectric layer HK2 and the third high-k dielectric layer HK3 may include zirconium oxide (ZrO2), while the first high-k dielectric layer HK1 and the fourth high-k dielectric layer HK4 may be made of or include hafnium oxide (HfO2), respectively. The high bandgap layer HBG may be made of or include aluminum oxide (Al2O3). The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2).

[0136] Therefore, the multilayer stack ML16D can be made of hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order, or include hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order.

[0137] refer to Fig. 6E , the multilayer stack ML16E may include a HfO2 / AFE-HZO / ZrO2 / Al-doped ZrO2 / ZrO2 / AFE-HZO / HfO2 / Al2O3 / TiO2 stack. The first and second antiferroelectric layers AFE1 and AFE2 may both include antiferroelectric hafnium zirconium oxide AFE-HZO. The second high-k dielectric layer HK2 and the third high-k dielectric layer HK3 may include zirconium oxide (ZrO2), while the first high-k dielectric layer HK1 and the fourth high-k dielectric layer HK4 may be made of or include hafnium oxide (HfO2), respectively. The high bandgap layer HBG may be made of or include aluminum-doped zirconium oxide (Al-doped ZrO2). The leakage blocking layer LBL may be made of or include aluminum oxide (Al 2 O 3 ), and the interface control layer ICL may be made of or include titanium oxide (TiO 2 ).

[0138] Therefore, the multilayer stack ML16E can be made of hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum-doped zirconium oxide (Al-doped ZrO2), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order, or include hafnium oxide (HfO2), antiferroelectric hafnium zirconium oxide AFE-HZO, zirconium oxide (ZrO2), aluminum-doped zirconium oxide (Al-doped ZrO2), zirconium oxide (ZrO2), antiferroelectric hafnium zirconium oxide AFE-HZO, hafnium oxide (HfO2), aluminum oxide (Al2O3) and titanium oxide (TiO2) stacked in the following order.

[0139] Figure 7 is a cross-sectional view showing a capacitor according to another embodiment of the present invention.

[0140] refer to Figure 7 , the capacitor C17 may include a first electrode BE, a second electrode TE, and a multilayer stack ML17 between the first electrode BE and the second electrode TE. The multilayer stack ML17 may include at least one antiferroelectric layer AFE1 and AFE2 and one high-k dielectric layer HK.

[0141] The multilayer stack ML17 may include a first antiferroelectric layer AFE1, a high-k dielectric layer HK, and a second antiferroelectric layer AFE2 stacked in the following order. The high-k dielectric layer HK may be located between the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2. The high-k dielectric layer HK may be larger than Figures 1 to 6E The high-k dielectric layers HK1, HK2, HK3 and HK4 in the embodiment of the present invention are thicker than the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2. The high-k dielectric layer HK may have a thickness of about to The first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2 may each have a thickness of about or less thickness.

[0142] The high-k dielectric layer HK may be made of or include hafnium or zirconium. The high-k dielectric layer HK may be made of or include hafnium oxide or zirconium oxide. The high-k dielectric layer HK may be made of a single layer of hafnium oxide. The high-k dielectric layer HK may be made of a single layer of zirconium oxide. According to another embodiment of the present invention, the high-k dielectric layer HK may be an antiferroelectric material. For example, the high-k dielectric layer HK may include hafnium zirconium oxide rich in zirconium oxide.

[0143] Figure 8 is a cross-sectional view showing a capacitor according to another embodiment of the present invention.

[0144] refer to Figure 8 , capacitor C18 can be similar to Figure 7 Here, the capacitor C17 that also appears in Figure 7 Detailed description of the constituent elements in .

[0145] The capacitor C18 may include a first electrode BE, a second electrode TE, and a multilayer stack ML18 between the first electrode BE and the second electrode TE. The multilayer stack ML18 may include at least one antiferroelectric layer AFE1 and AFE2 and a high-k dielectric layer HK. The multilayer stack ML18 may further include a leakage barrier layer LBL and an interface control layer ICL.

[0146] The multilayer stack ML18 may include a first antiferroelectric layer AFE1, a high-k dielectric layer HK, a second antiferroelectric layer AFE2, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order. The high-k dielectric layer HK may be located between the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2. The high-k dielectric layer HK may be thicker than the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2. The high-k dielectric layer HK may have a thickness of about to The first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2 may each have a thickness of about or less thickness.

[0147] The leakage barrier layer LBL and the interface control layer ICL may be located between the second antiferroelectric layer AFE2 and the second electrode TE. The leakage barrier layer LBL may be located between the second antiferroelectric layer AFE2 and the interface control layer ICL. The interface control layer ICL may be located between the leakage barrier layer LBL and the second electrode TE. For the description of the leakage barrier layer LBL and the interface control layer ICL, please refer to Figure 2 and accompanying instructions.

[0148] Figures 9 to 17C Capacitors according to other embodiments of the present invention are shown. Figures 9 to 17C The capacitors according to other embodiments of the present invention may have the same Figures 1 to 8 The following is a similar component to the capacitor. Figures 1 to 8 For a detailed description of the components in Figures 1 to 8 and accompanying instructions.

[0149] refer to Fig. 9, the capacitor C19 may include a first electrode BE, a second electrode TE, and a multilayer stack ML19 located between the first electrode BE and the second electrode TE. The multilayer stack ML19 may include at least one antiferroelectric layer AFE1 and AFE2 and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML19 may further include a leakage barrier layer LBL and an interface control layer ICL. According to another embodiment of the present invention, the leakage barrier layer LBL and the interface control layer ICL of the multilayer stack ML19 may be omitted.

[0150] The multilayer stack ML19 may include a first antiferroelectric layer AFE1, a first high-k dielectric layer HK1, a high bandgap layer HBG, a second antiferroelectric layer AFE2, a second high-k dielectric layer HK2, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order. The first antiferroelectric layer AFE1 may be in direct contact with the first electrode BE and the first high-k dielectric layer HK1. The first antiferroelectric layer AFE1 may be located between the first electrode BE and the first high-k dielectric layer HK1. The second antiferroelectric layer AFE2 may be in direct contact with the second high-k dielectric layer HK2 and the high bandgap layer HBG. The second antiferroelectric layer AFE2 may be located between the high bandgap layer HGB and the second high-k dielectric layer HK2.

[0151] Different from the above-mentioned embodiments of the present invention, the high bandgap layer HBG of the multilayer stack ML19 may be located between the first high-k dielectric layer HK1 and the second antiferroelectric layer AFE2. Return to Reference Figure 1 and Figure 2 , the high bandgap layer HBG may be located between the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2. Return to Reference Figure 3 , the high band gap layer HBG may be located between the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2 .

[0152] The multilayer stack ML19 may include a first stack including a first antiferroelectric layer AFE1 and a first high-k dielectric layer HK1 over the first antiferroelectric layer AFE1, and a second stack including a second antiferroelectric layer AFE2 and a second high-k dielectric layer HK2 over the second antiferroelectric layer AFE2. A high bandgap layer HBG may be located between the first stack and the second stack.

[0153] refer to Fig.10, the capacitor C20 may include a first electrode BE, a second electrode TE, and a multilayer stack ML20 located between the first electrode BE and the second electrode TE. The multilayer stack ML20 may include at least one antiferroelectric layer AFE1 and AFE2 and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML20 may further include a leakage barrier layer LBL and an interface control layer ICL. According to another embodiment of the present invention, the leakage barrier layer LBL and the interface control layer ICL of the multilayer stack ML20 may be omitted.

[0154] The multilayer stack ML20 may include a first high-k dielectric layer HK1, a first antiferroelectric layer AFE1, a high bandgap layer HBG, a second high-k dielectric layer HK2, a second antiferroelectric layer AFE2, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order. The first antiferroelectric layer AFE1 may be in direct contact with the first high-k dielectric layer HK1 and the high bandgap layer HBG, and may be located between the first high-k dielectric layer HK1 and the high bandgap layer HBG. The second antiferroelectric layer AFE2 may be in direct contact with the second high-k dielectric layer HK2 and the leakage barrier layer LBL, and may be located between the second high-k dielectric layer HK2 and the leakage barrier layer LBL.

[0155] The high bandgap layer HBG of the multilayer stack ML20 may be located between the first antiferroelectric layer AFE1 and the second high-k dielectric layer HK2 .

[0156] The multilayer stack ML20 may include a first stack including a first high-k dielectric layer HK1 and a first antiferroelectric layer AFE1 over the first high-k dielectric layer HK1, and a second stack including a second high-k dielectric layer HK2 and a second antiferroelectric layer AFE2 over the second high-k dielectric layer HK2. The high bandgap layer HBG may be located between the first stack and the second stack.

[0157] refer to Fig.11 , the capacitor C21 may include a first electrode BE, a second electrode TE, and a multilayer stack ML21 located between the first electrode BE and the second electrode TE. The multilayer stack ML21 may include at least one antiferroelectric layer AFE1, AFE2 and AFE3 and at least one high-k dielectric layer HK1, HK2 and HK3. The multilayer stack ML21 may further include a leakage barrier layer LBL and an interface control layer ICL. According to another embodiment of the present invention, the leakage barrier layer LBL and the interface control layer ICL of the multilayer stack ML21 may be omitted.

[0158] The multilayer stack ML21 may include a first high-k dielectric layer HK1, a first antiferroelectric layer AFE1, a second high-k dielectric layer HK2, a high bandgap layer HBG, a second antiferroelectric layer AFE2, a third high-k dielectric layer HK3, a third antiferroelectric layer AFE3, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order.

[0159] The first antiferroelectric layer AFE1 may be located between the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2. The second antiferroelectric layer AFE2 may be located between the high bandgap layer HBG and the third high-k dielectric layer HK3. The third antiferroelectric layer AFE3 may be located between the third high-k dielectric layer HK3 and the leakage barrier layer LBL. The high bandgap layer HBG may be located between the second high-k dielectric layer HK2 and the second antiferroelectric layer AFE2.

[0160] The first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be made of hafnium (Hf) and zirconium (Zr), or include hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be made of antiferroelectric hafnium zirconium oxide or include antiferroelectric hafnium zirconium oxide. As the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3, the antiferroelectric hafnium zirconium oxide may include basic hafnium zirconium oxide, hafnium oxide-rich hafnium zirconium oxide or zirconium oxide-rich hafnium zirconium oxide.

[0161] According to an embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be formed of a layer having a thickness of about 100 mm. or smaller ( to ) of an antiferroelectric hafnium zirconium oxide, or comprising a thickness of about or smaller ( to For example, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the third antiferroelectric layer AFE3 may contain Hf2O3 in which the hafnium oxide content (x) and the zirconium oxide content (y) are the same. x Zr y O(x=y). In this case, the thickness can be about According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be made of Hf in which the hafnium oxide content (x) is greater than the zirconium oxide content (y). x Zr y O(x>y), or comprising Hf having a hafnium oxide content (x) greater than a zirconium oxide content (y) x Zr yO(x>y). In this case, the thickness can be less than about According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be made of Hf in which the zirconium oxide content (y) is greater than the hafnium oxide content (x). x Zr y O (y>x), or includes Hf having a zirconium oxide content (y) greater than a hafnium oxide content (x) x Zr y O(y>x). In this case, the thickness can be about or smaller.

[0162] The first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be antiferroelectric hafnium zirconium oxide of the same type or the same material.

[0163] According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be antiferroelectric hafnium zirconium oxides made of different materials.

[0164] According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be made of or include the same antiferroelectric material, and they may have the same thickness or different thicknesses.

[0165] According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be made of or include different antiferroelectric materials, and they may have the same thickness or different thicknesses.

[0166] According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be antiferroelectric hafnium zirconium oxide having the same hafnium oxide content.

[0167] According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3 may be antiferroelectric hafnium zirconium oxides having different hafnium oxide contents.

[0168] refer to Fig.12, the capacitor C22 may include a first electrode BE, a second electrode TE, and a multilayer stack ML22 located between the first electrode BE and the second electrode TE. The multilayer stack ML22 may include at least one antiferroelectric layer AFE1, AFE2 and AFE3 and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML22 may further include a leakage barrier layer LBL and an interface control layer ICL. According to another embodiment of the present invention, the leakage barrier layer LBL and the interface control layer ICL of the multilayer stack ML22 may be omitted.

[0169] The multilayer stack ML22 may include a first antiferroelectric layer AFE1, a first high-k dielectric layer HK1, a second antiferroelectric layer AFE2, a high bandgap layer HBG, a second high-k dielectric layer HK2, a third antiferroelectric layer AFE3, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order.

[0170] The first antiferroelectric layer AFE1 may be located between the first electrode BE and the first high-k dielectric layer HK1. The second antiferroelectric layer AFE2 may be located between the first high-k dielectric layer HK1 and the high bandgap layer HBG. The third antiferroelectric layer AFE3 may be located between the second high-k dielectric layer HK2 and the leakage barrier layer LBL. The high bandgap layer HBG may be located between the second antiferroelectric layer AFE2 and the second high-k dielectric layer HK2.

[0171] refer to Fig.13 , the capacitor C23 may include a first electrode BE, a second electrode TE, and a multilayer stack ML23 located between the first electrode BE and the second electrode TE. The multilayer stack ML23 may include at least one antiferroelectric layer AFE1, AFE2 and AFE3 and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML23 may further include a leakage barrier layer LBL and an interface control layer ICL. According to another embodiment of the present invention, the leakage barrier layer LBL and the interface control layer ICL of the multilayer stack ML23 may be omitted.

[0172] The multilayer stack ML23 may include a first antiferroelectric layer AFE1, a high-k dielectric layer HK1, a second antiferroelectric layer AFE2, a high bandgap layer HBG, a third antiferroelectric layer AFE3, a second high-k dielectric layer HK2, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order.

[0173] The first antiferroelectric layer AFE1 may be located between the first electrode BE and the first high-k dielectric layer HK1. The second antiferroelectric layer AFE2 may be located between the first high-k dielectric layer HK1 and the high bandgap layer HBG. The third antiferroelectric layer AFE3 may be located between the high bandgap layer HBG and the second high-k dielectric layer HK2. The high bandgap layer HBG may be located between the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3.

[0174] refer to Fig.14 , the capacitor C24 may include a first electrode BE, a second electrode TE, and a multilayer stack ML24 between the first electrode BE and the second electrode TE. The multilayer stack ML24 may include at least one antiferroelectric layer AFE1, AFE2, AFE3 and AFE4 and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML24 may further include a leakage barrier layer LBL and an interface control layer ICL. According to another embodiment of the present invention, the leakage barrier layer LBL and the interface control layer ICL of the multilayer stack ML24 may be omitted.

[0175] The multilayer stack ML24 may include a first antiferroelectric layer AFE1, a first high-k dielectric layer HK1, a second antiferroelectric layer AFE2, a high bandgap layer HBG, a third antiferroelectric layer AFE3, a second high-k dielectric layer HK2, a fourth antiferroelectric layer AFE4, a leakage barrier layer LBL and an interface control layer ICL stacked in the following order.

[0176] The first antiferroelectric layer AFE1 may be located between the first electrode BE and the first high-k dielectric layer HK1. The second antiferroelectric layer AFE2 may be located between the first high-k dielectric layer HK1 and the high bandgap layer HBG. The third antiferroelectric layer AFE3 may be located between the high bandgap layer HBG and the second high-k dielectric layer HK2. The fourth antiferroelectric layer AFE4 may be located between the second high-k dielectric layer HK2 and the leakage barrier layer LBL. The high bandgap layer HBG may be located between the second antiferroelectric layer AFE2 and the third antiferroelectric layer AFE3.

[0177] The first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, the third antiferroelectric layer AFE3 and the fourth antiferroelectric layer AFE4 may be made of or include hafnium (Hf) and zirconium (Zr). The first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, the third antiferroelectric layer AFE3 and the fourth antiferroelectric layer AFE4 may be made of or include antiferroelectric hafnium zirconium oxide.

[0178] The first antiferroelectric layer AFE1 , the second antiferroelectric layer AFE2 , the third antiferroelectric layer AFE3 , and the fourth antiferroelectric layer AFE4 may be antiferroelectric hafnium zirconium oxides made of different materials.

[0179] According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, the third antiferroelectric layer AFE3 and the fourth antiferroelectric layer AFE4 may include the same antiferroelectric material, and they may have the same thickness or different thicknesses.

[0180] According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, the third antiferroelectric layer AFE3 and the fourth antiferroelectric layer AFE4 may include different antiferroelectric materials, and they may have the same thickness or different thicknesses.

[0181] According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, the third antiferroelectric layer AFE3 and the fourth antiferroelectric layer AFE4 may be antiferroelectric hafnium zirconium oxides having the same hafnium oxide content.

[0182] According to another embodiment of the present invention, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, the third antiferroelectric layer AFE3 and the fourth antiferroelectric layer AFE4 may be antiferroelectric hafnium zirconium oxides having different hafnium oxide contents.

[0183] refer to Fig.15 , the capacitor C25 may include a first electrode BE, a second electrode TE, and a multilayer stack ML25 located between the first electrode BE and the second electrode TE. The multilayer stack ML25 may include at least one antiferroelectric layer AFE1, AFE2 and AFE3 and at least one high-k dielectric layer HK1, HK2 and HK3. The multilayer stack ML25 may further include a leakage barrier layer LBL and an interface control layer ICL. According to another embodiment of the present invention, the leakage barrier layer LBL and the interface control layer ICL of the multilayer stack ML25 may be omitted.

[0184] The multilayer stack ML25 may include a first antiferroelectric layer AFE1, a first high-k dielectric layer HK1, a second antiferroelectric layer AFE2, a high bandgap layer HBG, a second high-k dielectric layer HK2, a third antiferroelectric layer AFE3, a third high-k dielectric layer HK3, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order.

[0185] The first antiferroelectric layer AFE1 may be located between the first electrode BE and the first high-k dielectric layer HK1. The second antiferroelectric layer AFE2 may be located between the first high-k dielectric layer HK1 and the high bandgap layer HBG. The third antiferroelectric layer AFE3 may be located between the second high-k dielectric layer HK2 and the third high-k dielectric layer HK3. The high bandgap layer HBG may be located between the second antiferroelectric layer AFE2 and the second high-k dielectric layer HK2.

[0186] refer to Figures 1 to 15, the antiferroelectric layers AFE1, AFE2, AFE3, and AFE4 may include a material exposed to a subsequent annealing process to improve crystallinity. The antiferroelectric layers AFE1, AFE2, AFE3, and AFE4 may have a tetragonal crystal structure through the annealing process. The tetragonal crystal structure may have a larger dielectric constant than other crystal structures (e.g., amorphous or monoclinic).

[0187] refer to Figures 1 to 10 , all the antiferroelectric layers AFE1 and AFE2 may be formed of hafnium zirconium oxide rich in hafnium oxide. Figures 11 to 13 and Fig.15 , the antiferroelectric layers AFE1, AFE2 and AFE3 may all be formed of hafnium zirconium oxide rich in hafnium oxide. Fig.14 In the embodiment, the antiferroelectric layers AFE1, AFE2, AFE3 and AFE4 may all be formed of hafnium zirconium oxide rich in hafnium tetrahydrate.

[0188] Fig.16A A semiconductor device according to another embodiment of the present invention is shown.

[0189] refer to Fig.16A , the semiconductor device 200 may include a capacitor C26. The capacitor C26 may include a first electrode BE, a second electrode TE, and a multilayer stack ML26 located between the first electrode BE and the second electrode TE. The multilayer stack ML26 may include a hafnium zirconium oxide layer HR-HZO rich in hafnium oxide and at least one high-k dielectric layer HK1 and HK2.

[0190] The multilayer stack ML26 may include a first high-k dielectric layer HK1, a hafnium-rich zirconium oxide layer HR-HZO, and a second high-k dielectric layer HK2 stacked in the following order. The hafnium-rich zirconium oxide layer HR-HZO may be located between the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2. The hafnium-rich zirconium oxide layer HR-HZO may be larger than Figures 1 to 15 The hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may be thicker than the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2. The hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may have a thickness of about to thickness, and it can exhibit ferroelectricity.

[0191] Please refer to Table 1. When the thickness of the hafnium-rich zirconium oxide layer HR-HZO is about When the thickness is 0.0447 W or greater, the hafnium zirconium oxide layer HR-HZO rich in hafnium oxide can exhibit ferroelectricity. The ferroelectric hafnium zirconium oxide layer HR-HZO rich in hafnium tetrahydrate can exert a negative capacitance effect.

[0192] When conventional dielectric materials and ferroelectric materials are stacked, a negative capacitance effect can be obtained, which can refer to the effect of obtaining a capacitance greater than the capacitance of the dielectric material alone. The negative capacitance effect can be achieved in both antiferroelectric materials and ferroelectric materials, but may be easier to achieve in ferroelectric materials than in antiferroelectric materials. Therefore, in order to ensure the ferroelectric properties of hafnium zirconium oxide, it is advantageous to make the content of hafnium oxide greater than the content of zirconium oxide.

[0193] According to an embodiment of the present invention, the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO can advantageously achieve a negative capacitance effect, and therefore, the capacitance of the capacitor C26 can be further increased by combining the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO with the first and second high-k dielectric layers HK1 and HK2. The hafnium oxide-rich hafnium zirconium oxide layer HR-HZO can be referred to as a negative capacitance material layer or a negative capacitance ferroelectric material layer.

[0194] In order to obtain the negative capacitance effect, according to another embodiment of the present invention, the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO can be replaced by a basic hafnium zirconium oxide B-HZO. Referring again to Table 1, the basic hafnium zirconium oxide with the same hafnium oxide content and zirconium oxide content has a thickness greater than When , ferroelectricity can be exhibited. Therefore, a negative capacitance effect can be obtained.

[0195] Fig. 16B and 16C A capacitor according to another embodiment of the present invention is shown. Fig. 16B and 16C yes Fig.16A The improvement of capacitor C26 shown in FIG. 1 may be omitted in the following. Fig.16A Detailed description of the constituent elements.

[0196] refer to Fig. 16B The capacitor C26A may include a first electrode BE, a second electrode TE, and a multilayer stack ML26A between the first electrode BE and the second electrode TE. The multilayer stack ML26A may include a hafnium-rich zirconium oxide layer HR-HZO and a high-k dielectric layer HK1.

[0197] The multilayer stack ML26A may include a first high-k dielectric layer HK1 and a hafnium oxide-rich hafnium zirconium oxide layer HR-HZO stacked in the following order. The first high-k dielectric layer HK1 may directly contact the first electrode BE, and the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may directly contact the second electrode TE. The hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may be thicker than the first high-k dielectric layer HK1. The hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may have a thickness of about to thickness and can exhibit ferroelectricity.

[0198] refer to Fig. 16C The capacitor C26B may include a first electrode BE, a second electrode TE, and a multilayer stack ML26B between the first electrode BE and the second electrode TE. The multilayer stack ML26B may include a hafnium-rich zirconium oxide layer HR-HZO and a high-k dielectric layer HK2.

[0199] The multilayer stack ML26B may include a hafnium oxide-rich hafnium zirconium oxide layer HR-HZO and a second high-k dielectric layer HK2 stacked in the following order. The second high-k dielectric layer HK2 may directly contact the second electrode TE, and the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may directly contact the first electrode BE. The hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may have a thickness of about to thickness and can exhibit ferroelectricity.

[0200] Fig.17A A capacitor according to another embodiment of the present invention is shown. Fig.17A The capacitor C27 shown in FIG. 1 can be similar to Fig.16A In the following, the capacitor C26 which also appears in Fig.16A Detailed description of the constituent elements in .

[0201] The capacitor C27 may include a first electrode BE, a second electrode TE, and a multilayer stack ML27 between the first electrode BE and the second electrode TE. The multilayer stack ML27 may include a hafnium-rich zirconium oxide layer HR-HZO and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML27 may further include a leakage barrier layer LBL and an interface control layer ICL.

[0202] The multilayer stack ML27 may include a first high-k dielectric layer HK1, a hafnium oxide-rich hafnium zirconium oxide layer HR-HZO, a second high-k dielectric layer HK2, a leakage barrier layer LBL, and an interface control layer ICL. The hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may be located between the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2. A negative capacitance effect may be obtained by the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO.

[0203] The leakage barrier layer LBL and the interface control layer ICL may be located between the second high-k dielectric layer HK2 and the second electrode TE. The leakage barrier layer LBL may be located between the second high-k dielectric layer HK2 and the interface control layer ICL. The interface control layer ICL may be located between the leakage barrier layer LBL and the second electrode TE. For the description of the leakage barrier layer LBL and the interface control layer ICL, reference may be made to Figure 2 and accompanying instructions.

[0204] Fig. 17B and 17C shows a capacitor according to another embodiment of the present invention, Fig. 17B and 17C yes Fig.17A The improvement of capacitor C27 shown in FIG. 1 may be omitted in the following. Fig.17A A detailed description of the constituent elements in .

[0205] refer to Fig. 17B The capacitor C27A may include a first electrode BE, a second electrode TE, and a multilayer stack ML27A between the first electrode BE and the second electrode TE. The multilayer stack ML27A may include a hafnium-rich zirconium oxide layer HR-HZO and a high-k dielectric layer HK1. The multilayer stack ML27A may further include a leakage barrier layer LBL and an interface control layer ICL.

[0206] The multilayer stack ML27A may be sequentially stacked with a first high-k dielectric layer HK1, a hafnium-rich zirconium oxide layer HR-HZO, a leakage barrier layer LBL, and an interface control layer ICL. The hafnium-rich zirconium oxide layer HR-HZO may be located between the first high-k dielectric layer HK1 and the leakage barrier layer LBL.

[0207] refer to Fig. 17C The capacitor C27B may include a first electrode BE, a second electrode TE, and a multilayer stack ML27B located between the first electrode BE and the second electrode TE. The multilayer stack ML27B may include a hafnium zirconium oxide layer HR-HZO rich in hafnium oxide and a high-k dielectric layer HK2. The multilayer stack ML27B may further include a leakage barrier layer LBL and an interface control layer ICL.

[0208] The multilayer stack ML27B may include a hafnium oxide rich hafnium zirconium oxide layer HR-HZO and a second high-k dielectric layer HK2, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order: The hafnium oxide rich hafnium zirconium oxide layer HR-HZO may be located between the first electrode BE and the second high-k dielectric layer HK2.

[0209] According to another embodiment of the present invention, the multilayer stacks ML26, ML26A, ML26B, ML27, ML27A, and ML27B may be formed by alternately stacking a plurality of negative capacitance material layers (e.g., hafnium zirconium oxide layers rich in hafnium oxide) and a plurality of high-k dielectric layers. In this case, the negative capacitance material layer may be thicker than the high-k dielectric layer.

[0210] FIG. 16A to FIG. 17C The thickness of the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO and Figures 1 to 15 The thicknesses of the antiferroelectric layers AFE1, AFE2, AFE3 and AFE4 may be different from each other. Figures 1 to 15 The thickness of the antiferroelectric layers AFE1, AFE2, AFE3 and AFE4 may be about or smaller, and FIG. 16A to FIG. 17C The thickness of the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO can be about to FIG. 16A to FIG. 17C The thickness of the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO can be Figures 1 to 15 The antiferroelectric layers AFE1, AFE2, AFE3 and AFE4 are thick.

[0211] According to another embodiment of the present invention, when Figures 1 to 15 When the antiferroelectric layers AFE1, AFE2, AFE3 and AFE4 include hafnium zirconium oxide layers rich in hafnium oxide, a negative capacitance effect can be obtained.

[0212] refer to Figures 1 to 17C , the multilayer stacks ML11 to ML27B may have the same height (or thickness).

[0213] Fig.18 is a flow chart describing an example of a method for depositing a hafnium zirconium oxide layer HR-HZO rich in hafnium oxide.

[0214] The hafnium zirconium oxide layer HR-HZO rich in hafnium oxide can be deposited by atomic layer deposition (ALD). The atomic layer deposition (ALD) of the hafnium zirconium oxide layer HR-HZO rich in hafnium oxide can be performed by repeating multiple cycles at a temperature of about 250°C to 380°C. Here, the cycle may include a first cycle Z1 for depositing a zirconium oxide layer (ZrO2) and a second cycle H1 for depositing a hafnium oxide layer (HfO2). The zirconium oxide layer can be deposited by repeating the first cycle Z1 A times, and the hafnium oxide layer can be deposited by repeating the second cycle H1 B times. Here, A and B can be different natural numbers. B can be greater than A. For example, A can be 1 to 10, and B can be greater than 10. By making B greater than A, the hafnium oxide layer can be deposited thicker than the zirconium oxide layer, and accordingly, the hafnium zirconium oxide layer HR-HZO rich in hafnium oxide can be deposited.

[0215] The first cycle Z1 may include a Zr source adsorption operation (S1), a purging operation (S2), a reaction gas supply operation (S3), and an operation of purging unreacted gas (S4). The first cycle (Z1) may be repeated A times. A zirconium oxide layer may be deposited in the first cycle Z1.

[0216] The second cycle H1 may include a hafnium (Hf) source adsorption operation (S11), a purging operation (S12), a reaction gas supply operation (S13), and an operation of purging unreacted gas (S14). The second cycle H1 may be repeated B times. A hafnium oxide layer may be deposited in the second cycle H1.

[0217] The zirconium (Zr) source may include TEMAZ (tetrakis(ethylmethylamino)zirconium), TDMAZ (tetrakis(dimethylamino)zirconium), and the like.

[0218] The hafnium (Hf) source may include TEMAH (tetrakis(ethylmethylamino)hafnium), TDEAH (tetrakis(diethylamino)hafnium), TDMAH (tetrakis(dimethylamino)hafnium), or the like.

[0219] The reaction gas may include an oxidant, and the oxidant may include O3, O2, H2O, H2O2, O2 plasma, or a combination thereof. When ozone (O3) is used as an oxidant, the concentration and flow rate of ozone may be optimized and supplied. For example, the concentration of ozone may be about 50 g / m 3 Up to 310g / m 3 The flow rate of ozone may be in the range of about 100 sccm to 5000 sccm. The purge operation may be performed sufficiently long in the range of about 1 second to 100 seconds.

[0220] According to another embodiment of the present invention, a hafnium zirconium oxide layer HR-HZO rich in hafnium oxide may be deposited by making A and B the same and making the flow rate of the hafnium (Hf) source greater than the flow rate of the zirconium (Zr) source.

[0221] According to another embodiment of the present invention, a hafnium zirconium oxide layer HR-HZO rich in hafnium oxide may be deposited by making A and B the same and making the supply time of the hafnium (Hf) source longer than the supply time of the zirconium (Zr) source.

[0222] To obtain antiferroelectricity, one can use less than about A hafnium zirconium oxide layer HR-HZO rich in hafnium oxide is deposited with a thickness of .

[0223] To obtain ferroelectricity, a hafnium-zirconium oxide layer HR-HZO rich in hafnium oxide can be deposited to about or greater thickness.

[0224] After the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO is subjected to atomic layer deposition, the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may be exposed to a subsequent annealing process. The subsequent annealing process may improve the crystallinity of the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO, thereby increasing the dielectric constant.

[0225] Fig.19 is a flow chart describing another example of a method of depositing a hafnium zirconium oxide layer HR-HZO rich in hafnium oxide.

[0226] The hafnium zirconium oxide layer HR-HZO rich in hafnium oxide may be deposited by atomic layer deposition (ALD), and the atomic layer deposition (ALD) of the hafnium zirconium oxide layer HR-HZO rich in hafnium oxide may be performed by repeating a unit cycle HZ at about 250° C. to 380° C. Here, the unit cycle HZ may include a zirconium (Zr) source adsorption operation (S21), a purge operation (S22), a hafnium (Hf) source adsorption operation (S23), a purge operation (S24), a reaction gas supply operation (S25), and an operation of purging unreacted gas (S26), and the unit cycle HZ may be repeated C times.

[0227] The zirconium (Zr) source may include TEMAZ (tetrakis(ethylmethylamino)zirconium), TDMAZ (tetrakis(dimethylamino)zirconium), and the like.

[0228] The hafnium (Hf) source may include TEMAH (tetrakis(ethylmethylamino)hafnium), TDEAH (tetrakis(diethylamino)hafnium), TDMAH (tetrakis(dimethylamino)hafnium), or the like.

[0229] The reaction gas may include an oxidant, and the oxidant may include O3, O2, H2O, H2O2, O2 plasma, or a combination thereof. When ozone (O3) is used as an oxidant, the concentration and flow rate of ozone may be optimized and supplied. For example, the concentration of ozone may be about 50 g / m 3 Up to 310g / m 3The flow rate of ozone may be in the range of about 100 sccm to 5000 sccm. The purge operation of any unreacted gas may be sufficiently long, and may be, for example, in the range of about 1 second to 100 seconds.

[0230] In the unit cycle HZ, the hafnium zirconium oxide layer HR-HZO rich in hafnium oxide can be deposited by making the flow rate of the hafnium (Hf) source greater than the flow rate of the zirconium (Zr) source. According to another embodiment of the present invention, the hafnium zirconium oxide layer HR-HZO rich in hafnium oxide can be deposited by making the supply time of the hafnium (Hf) source longer than the supply time of the zirconium (Zr) source.

[0231] After performing the atomic layer deposition of the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO, the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may be exposed to a subsequent annealing process. Through the subsequent annealing process, the crystallinity of the hafnium oxide-rich hafnium zirconium oxide layer HR-HZO may be improved.

[0232] Fig. 20 is a cross-sectional view showing a semiconductor device 300 according to another embodiment of the present invention.

[0233] refer to Fig. 20 , the semiconductor device 300 may include a capacitor C28. The capacitor C28 may include a first electrode BE, a second electrode TE, and a multilayer stack ML28 located between the first electrode BE and the second electrode TE. The multilayer stack ML28 may include at least one antiferroelectric layer AFE1 and AFE2 and at least one high-k dielectric layer HK1 and HK2. The multilayer stack ML28 may further include a leakage barrier layer LBL and an interface control layer ICL. According to another embodiment of the present invention, the leakage barrier layer LBL and the interface control layer ICL of the multilayer stack ML28 may be omitted. The capacitor C28 may be similar to Figure 2 The capacitor C12 is also shown in FIG. 1. Figure 2 Detailed description of the constituent elements in .

[0234] The multilayer stack ML28 may further include a booster layer KBL. The booster layer KBL may directly contact the first antiferroelectric layer AFE1. The booster layer KBL may be formed below the first antiferroelectric layer AFE1. The booster layer KBL may be located between the first high-k dielectric layer HK1 and the first antiferroelectric layer AFE1. The booster layer KBL may directly contact the first high-k dielectric layer HK1.

[0235] The enhancement layer KBL can improve the dielectric constant of the first antiferroelectric layer AFE1. In other words, the enhancement layer KBL can be used as a dielectric constant enhancement member (which can be called a k booster member). The enhancement layer KBL can increase the dielectric constant of the first antiferroelectric layer AFE1. The enhancement layer KBL can also be used as a polarization enhancement layer, which enhances the polarization of the first antiferroelectric layer AFE1. The enhanced polarization can further improve the dielectric constant of the first antiferroelectric layer AFE1.

[0236] The reinforcement layer KBL may be made of or include a metal. The metal of the reinforcement layer KBL may include a divalent metal, a trivalent metal, or a pentavalent metal. The divalent metal and the trivalent metal may have a high electron affinity.

[0237] The reinforcement layer KBL may contain a metal. The reinforcement layer KBL may include at least one selected from niobium, tantalum, and vanadium. The reinforcement layer KBL may be made of or include a metal oxide. According to another embodiment of the present invention, the reinforcement layer KBL may be a metal oxynitride. The reinforcement layer KBL may include niobium oxide, niobium oxynitride, tantalum oxide, tantalum oxynitride, vanadium oxide, or vanadium oxynitride.

[0238] As described above, the enhancement layer KBL may contain metal and oxygen. In addition, the enhancement layer KBL may contain metal, oxygen and nitrogen. In order to improve the dielectric constant of the first antiferroelectric layer AFE1, the oxygen content and nitrogen content of the enhancement layer KBL may be adjusted. For example, when the enhancement layer KBL contains metal oxide, the oxygen content may be adjusted in the range of about 1at% to 50at%. When the enhancement layer KBL contains metal oxynitride, the oxygen content may be greater than the nitrogen content, and the total content of oxygen and nitrogen may be in the range of about 60at% to 70at%. By controlling the oxygen content of the enhancement layer KBL, it is beneficial to improve the dielectric constant of the first antiferroelectric layer AFE1.

[0239] The enhancement layer KBL may have a to Thickness.

[0240] According to another embodiment of the present invention, the enhancement layer KBL may also be located below the second antiferroelectric layer AFE2.

[0241] According to another embodiment of the present invention, the enhancement layer KBL may be located below one of the first antiferroelectric layer AFE1 and the second antiferroelectric layer AFE2.

[0242] refer to Figures 1 to 17C The multilayer stack may include at least one reinforcement layer KBL. The reinforcement layer KBL may be located below the antiferroelectric layers AFE1, AFE2, AFE3 and AFE4 or the hafnium-rich hafnium zirconium oxide layer HR-HZO.

[0243] Figures 21 to 22Bis a cross-sectional view showing a storage unit. Fig.22A is along Fig.21 A cross-sectional view taken along line AA'. Fig. 22B is along Fig.21 A cross-sectional view taken along line BB'.

[0244] The memory cell 400 may include a cell transistor including a buried word line 508, a bit line 514, and a capacitor 600. The capacitor 600 may include a multilayer stack, which may include one of the multilayer stacks ML11 to ML28 in the above-described embodiments of the present invention.

[0245] The storage unit 400 may be described in detail.

[0246] The isolation layer 503 and the active area 504 may be formed in the substrate 501. A plurality of active areas 504 may be defined by the isolation layer 503. The substrate 501 may be made of a material suitable for semiconductor processing. The substrate 501 may include a semiconductor substrate. The substrate 501 may be formed of a silicon-containing material. The substrate 501 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof or a multilayer thereof. The substrate 501 may also include other semiconductor materials such as germanium. The substrate 501 may include a III / V semiconductor substrate, such as a composite semiconductor substrate, such as GaAs. The substrate 501 may include a silicon on insulator (SOI) substrate. The isolation layer 503 may be formed in the isolation trench 502 by a shallow trench isolation (STI) process.

[0247] A word line trench 506 may be formed in the substrate 501. The word line trench 506 may be referred to as a gate trench. A gate dielectric layer 507 may be formed on the surface of the word line trench 506. A buried word line 508 partially filling the word line trench 506 may be formed above the gate dielectric layer 507. The buried word line 508 may be referred to as a buried gate electrode. A word line capping layer 509 may be formed above the buried word line 508. The upper surface of the buried word line 508 may be located at a level lower than the surface of the substrate 501. The buried word line 508 may be a low resistance metal material. The buried word line 508 may be formed by sequentially stacking titanium nitride and tungsten. According to another embodiment of the present invention, the buried word line 508 may be formed only of titanium nitride (only TiN).

[0248] The first and second impurity regions 510 and 511 may be formed in the substrate 501. The first and second impurity regions 510 and 511 may be spaced apart from each other by the word line trench 506. The first and second impurity regions 510 and 511 may be referred to as first and second source / drain regions. The first and second impurity regions 510 and 511 may include N-type impurities such as arsenic (As) or phosphorus (P). Therefore, the buried word line 508 and the first and second impurity regions 510 and 511 may become a cell transistor. The buried word line 508 may improve the short channel effect of the cell transistor.

[0249] The bit line contact plug 513 may be formed over the substrate 501. The bit line contact plug 513 may be coupled to the first impurity region 510. The bit line contact plug 513 may be located in the bit line contact hole 512. The bit line contact hole 512 may be formed in the hard mask layer 505. The hard mask layer 505 may be formed over the substrate 501. The bit line contact hole 512 may expose the first impurity region 510. The lower surface of the bit line contact plug 513 may be lower than the upper surface of the substrate 501. The bit line contact plug 513 may be formed of polysilicon or a metal material. A portion of the bit line contact plug 513 may have a line width smaller than the diameter of the bit line contact hole 512. The bit line 514 may be formed over the bit line contact plug 513. The bit line hard mask 515 may be formed over the bit line 514. The stacked structure of the bit line 514 and the bit line hard mask 515 may be referred to as a bit line structure BL. The bit line 514 may have a line shape extending in a direction crossing the buried word line 508. A portion of the bit line 514 may be coupled to the bit line contact plug 513. The bit line 514 may be made of or include a metal material. The bit line hard mask 515 may include a dielectric material.

[0250] The bit line spacer 516 may be formed on the sidewall of the bit line structure BL. The bottom of the bit line spacer 516 may extend to both sides formed on the bit line contact plug 513. The bit line spacer 516 may include silicon oxide, silicon nitride, or a combination thereof. According to another embodiment of the present invention, the bit line spacer 516 may include an air gap. For example, it may be a NAN (nitride-air gap-nitride) structure in which an air gap is located between silicon nitrides.

[0251] The storage node contact plug SNC may be formed between adjacent bit line structures BL. The storage node contact plug SNC may be formed in the storage node contact hole 518. The storage node contact plug SNC may be coupled to the second impurity region 511. The storage node contact plug SNC may include a lower plug 519 and an upper plug 521. The storage node contact plug SNC may further include an ohmic contact layer 520 between the lower plug 519 and the upper plug 521. The ohmic contact layer 520 may be made of or include a metal silicide. The upper plug 521 may be made of or include a metal material, and the lower plug 519 may include a silicon-containing material.

[0252] From the direction parallel to the bit line structure BL ( Fig.21 From the perspective of the center line CC', a plug isolation layer 517 may be formed between adjacent storage node contact plugs SNC. The plug isolation layer 517 may be formed between adjacent bit line structures BL and may provide a storage node contact hole 518 together with the hard mask layer 505.

[0253] The capacitor 600 may be coupled to the storage node contact plug SNC.

[0254] Figures 23A to 23F is a cross-sectional view showing application of a capacitor 600 to a memory cell.

[0255] refer to Fig.23A , the capacitor 611 may include a bottom electrode 601, a top electrode 602, and a multilayer stack 603 between the bottom electrode 601 and the top electrode 602. The bottom electrode 601 may have a cylindrical shape. The multilayer stack 603 may be formed above the bottom electrode 601, and the top electrode 602 may be formed above the multilayer stack 603. The multilayer stack 603 may correspond to one of the multilayer stacks ML11 to ML28 in the above-mentioned embodiment of the present invention. Therefore, the multilayer stack 603 may include at least one antiferroelectric layer.

[0256] In the following, FIG. 23B to FIG. 23F can be omitted for the Fig.23A Detailed description of the constituent elements in .

[0257] refer to Fig. 23B , the capacitor 612 may include a cylindrical bottom electrode 601, a multilayer stack 603, and a top electrode 602. The capacitor 612 may further include a support member 600S. The support member 600S may be a structure supporting the outer wall of the bottom electrode 601. The support member 600S may include silicon nitride.

[0258] refer to Fig.23C and Fig.23D, capacitors 613 and 614 may include a pillar-shaped bottom electrode 601P, a multilayer stack 603 , and a top electrode 602 . Fig.23D The capacitor 614 may further include a support member 600S.

[0259] refer to Fig.23E and Fig.23F , capacitors 615 and 616 may include a bottom electrode 601L, a multilayer stack 603 , and a top electrode 602 . Fig.23F The capacitor 616 may further include a support member 600S. The bottom electrode 601L may have a hybrid structure in which a column shape and a cylinder shape are fused. As described above, the hybrid structure of the column shape and the cylinder shape may be referred to as a pylinder shape or a hybrid shape.

[0260] As described above, by forming the multilayer stack 603 to include at least one antiferroelectric layer, a multilayer stack 603 having a high dielectric constant and low leakage current can be obtained. Therefore, a highly integrated DRAM memory cell with improved refresh characteristics and reliability can be manufactured.

[0261] The dielectric layer stack according to the above-described embodiment of the present invention can be applied to the peripheral circuit of a DRAM. For example, a DRAM may include a memory cell (see Fig.22A The memory cell region 400 of the present invention and the peripheral circuit region including the peripheral transistors may include at least one of the capacitor 600 and the peripheral transistors of the memory cell 400. The memory cell region 400 of the present invention may include at least one of the multilayer stacks ML11 to ML28 of the above-described embodiments of the present invention.

[0262] The multilayer stacks ML11 to ML28 according to the above-described embodiments of the present invention may be applied to a metal-insulator-metal (MIM) capacitor. For example, the MIM capacitor may include a multilayer stack including a first metal electrode, a second metal electrode, and at least one antiferroelectric layer formed between the first metal electrode and the second metal electrode.

[0263] The multilayer stack according to the above-described embodiment of the present invention may be applied to an embedded DRAM. For example, the embedded DRAM may include a logic circuit and an embedded DRAM, and a capacitor of the embedded DRAM may include a multilayer stack including at least one antiferroelectric layer.

[0264] The multilayer stack according to the above-described embodiments of the present invention can be applied to a three-dimensional (3D) NAND. For example, a 3D NAND may include a pillar channel layer, a word line surrounding the pillar channel layer, and a multilayer stack including at least one antiferroelectric layer between the pillar channel layer and the word line.

[0265] Fig.24is a cross-sectional view showing a semiconductor device according to another embodiment of the present invention.

[0266] refer to Fig.24 , the semiconductor device 700 may include a transistor. The semiconductor device 700 may include a semiconductor substrate 701, a gate dielectric layer 710, a gate electrode 720, a source region 740, and a drain region 750. The gate dielectric layer 710 may be formed over the semiconductor substrate 701, and the gate electrode 720 may be formed over the gate dielectric layer 710. The source region 740 and the drain region 750 may be formed in the semiconductor substrate 701.

[0267] The gate dielectric layer 710 may include one of the multilayer stacks according to the above-described embodiments. The gate dielectric layer 710 may include at least one antiferroelectric layer and at least one high-k dielectric layer. Fig.24 In an embodiment of the present invention, the gate dielectric layer 710 may include a first high-k dielectric layer HK1, an antiferroelectric layer AFE, and a second high-k dielectric layer HK2 stacked in the following order: The antiferroelectric layer AFE may be located between the first high-k dielectric layer HK1 and the second high-k dielectric layer HK2.

[0268] The gate electrode 720 may be a metal gate electrode including a metal-based material, for example, the gate electrode 720 may be made of tungsten, aluminum, tungsten nitride, titanium nitride, titanium, or a combination thereof, or may include tungsten, aluminum, tungsten nitride, titanium nitride, titanium, or a combination thereof.

[0269] The source region 740 and the drain region 750 may include impurities of the same conductivity type. The source region 740 and the drain region 750 may include N-type impurities or P-type impurities. The N-type impurities may include phosphorus or arsenic, and the P-type impurities may include boron or indium.

[0270] According to another embodiment of the present invention, a thin interface layer may be further formed between the gate dielectric layer 710 and the semiconductor substrate 701. Here, the thin interface layer may include silicon oxide or silicon oxynitride.

[0271] According to another embodiment of the present invention, the gate dielectric layer 710 may be applied to a gate dielectric layer of a FinFET.

[0272] According to another embodiment of the present invention, the gate dielectric layer 710 may include hafnium zirconium oxide rich in hafnium oxide to obtain a negative capacitance effect. For example, the antiferroelectric layer AFE may be replaced by hafnium zirconium oxide rich in hafnium oxide.

[0273] Figures 25 to 27 is a cross-sectional view showing a capacitor according to another embodiment of the present invention.

[0274] refer to Fig.25, the capacitor C29 may include a first electrode BE, a second electrode TE, and a multilayer stack ML29 between the first electrode BE and the second electrode TE. The multilayer stack ML29 may include at least one antiferroelectric layer AFE1, AFE2, and AFE3 and at least one high-k dielectric layer HK1, HK2, HK3, and HK4. The multilayer stack ML29 may further include a leakage barrier layer LBL and an interface control layer ICL.

[0275] The multilayer stack ML29 may include a first high-k dielectric layer HK1, a first antiferroelectric layer AFE1, a second high-k dielectric layer HK2, a second antiferroelectric layer AFE2, a third high-k dielectric layer HK3, a third antiferroelectric layer AFE3, a fourth high-k dielectric layer HK4, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order.

[0276] The first high-k dielectric layer HK1 , the second high-k dielectric layer HK2 , the third high-k dielectric layer HK3 , and the fourth high-k dielectric layer HK4 may be made of the same material or different materials.

[0277] The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, and the fourth high-k dielectric layer HK4 may be made of, or include, hafnium oxide or zirconium oxide. The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, and the fourth high-k dielectric layer HK4 may be made of a single layer of hafnium oxide or a single layer of zirconium oxide. The first high-k dielectric layer HK1 and the fourth high-k dielectric layer HK4 may be thinner than each of the second high-k dielectric layer HK2 and the third high-k dielectric layer HK3. The first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the third antiferroelectric layer AFE3 may be thinner than each of the first and second high-k dielectric layers HK1 and HK2.

[0278] The first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the third antiferroelectric layer AFE3 may be made of or include antiferroelectric hafnium zirconium oxide AFE-HZO. The first high-k dielectric layer HK1 and the fourth high-k dielectric layer HK4 may include thin zirconium oxide, while the second high-k dielectric layer HK2 and the third high-k dielectric layer HK3 may include thick zirconium oxide. The leakage blocking layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2).

[0279] refer to Fig.26, the capacitor C30 may include a first electrode BE, a second electrode TE, and a multilayer stack ML30 located between the first electrode BE and the second electrode TE. The multilayer stack ML30 may include at least one antiferroelectric layer AFE1, AFE2, AFE3, and AFE4 and at least one high-k dielectric layer HK1, HK2, HK3, HK4, and HK5. The multilayer stack ML30 may further include a leakage barrier layer LBL and an interface control layer ICL.

[0280] The multilayer stack ML30 may include a first high-k dielectric layer HK1, a first antiferroelectric layer AFE1, a second high-k dielectric layer HK2, a second antiferroelectric layer AFE2, a third high-k dielectric layer HK3, a third antiferroelectric layer AFE3, a fourth high-k dielectric layer HK4, a fourth antiferroelectric layer AFE4, a fifth high-k dielectric layer HK5, a leakage barrier layer LBL, and an interface control layer ICL stacked in the following order.

[0281] The first high-k dielectric layer HK1 , the second high-k dielectric layer HK2 , the third high-k dielectric layer HK3 , the fourth high-k dielectric layer HK4 , and the fifth high-k dielectric layer HK5 may be made of the same material or different materials.

[0282] The first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, the fourth high-k dielectric layer HK4, and the fifth high-k dielectric layer HK5 may be made of hafnium oxide or zirconium oxide, or include zirconium oxide or zirconium oxide. Each of the first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, the fourth high-k dielectric layer HK4, and the fifth high-k dielectric layer HK5 may be made of a single layer of hafnium oxide or a single layer of zirconium oxide. The thickness of the first high-k dielectric layer HK1, the second high-k dielectric layer HK2, the third high-k dielectric layer HK3, the fourth high-k dielectric layer HK4, and the fifth high-k dielectric layer HK5 may be the same. The first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, the third antiferroelectric layer AFE3, and the fourth antiferroelectric layer AFE4 may be thinner than each of the first to fifth high-k dielectric layers HK1 to HK5.

[0283] The first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, the third antiferroelectric layer AFE3 and the fourth antiferroelectric layer AFE4 may include antiferroelectric hafnium zirconium oxide AFE-HZO. The first to fifth high-k dielectric layers HK1 to HK5 may include thin zirconium oxide. The leakage barrier layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2).

[0284] refer to Fig. 27, the capacitor C31 may include a first electrode BE, a second electrode TE, and a multilayer stack ML31 between the first electrode BE and the second electrode TE. The multilayer stack ML31 may include at least one antiferroelectric layer AFE1, AFE2, AFE3, and AFE4 and at least one high-k dielectric layer HK1, HK2, HK3, HK4, HK5, and HK6. The multilayer stack ML31 may further include a leakage barrier layer LBL and an interface control layer ICL.

[0285] The multilayer stack ML31 may include a first multilayer stack ML31A, a second multilayer stack ML31B, and a high bandgap layer HBG located between the first multilayer stack ML31A and the second multilayer stack ML31B. The first multilayer stack ML31A may include a first high-k dielectric layer HK1, a first antiferroelectric layer AFE1, a second high-k dielectric layer HK2, a second antiferroelectric layer AFE2, and a third high-k dielectric layer HK3 stacked in the following order. The second multilayer stack ML31B may include a fourth high-k dielectric layer HK4, a third antiferroelectric layer AFE3, a fifth high-k dielectric layer HK5, a fourth antiferroelectric layer AFE4, and a sixth high-k dielectric layer HK6 stacked in the following order.

[0286] In the first multilayer stack ML31A, the second high-k dielectric layer HK2 may be thicker than each of the first and third high-k dielectric layers HK1 and HK3. The first high-k dielectric layer HK1, the first antiferroelectric layer AFE1, the second antiferroelectric layer AFE2, and the third high-k dielectric layer HK3 may have the same thickness.

[0287] In the second multilayer stack ML31B, the fifth high-k dielectric layer HK5 may be thicker than the fourth and sixth high-k dielectric layers HK4 and HK6. The fourth high-k dielectric layer HK4, the third antiferroelectric layer AFE3, the fourth antiferroelectric layer AFE4, and the sixth high-k dielectric layer HK6 may have the same thickness.

[0288] The first to sixth high-k dielectric layers HK1 to HK6 may be made of the same material, or may be made of different materials. The first to sixth high-k dielectric layers HK1 to HK6 may be made of, or include, hafnium oxide or zirconium oxide. The first to sixth high-k dielectric layers HK1 to HK6 may be made of a single layer of hafnium oxide or a single layer of zirconium oxide.

[0289] The first antiferroelectric layer AFE1 , the second antiferroelectric layer AFE2 , the third antiferroelectric layer AFE3 , and the fourth antiferroelectric layer AFE4 may be made of or include antiferroelectric hafnium zirconium oxide AFE-HZO.

[0290] The leakage blocking layer LBL may be made of or include aluminum oxide (Al2O3), and the interface control layer ICL may be made of or include titanium oxide (TiO2). The high bandgap layer HBG may be made of or include aluminum oxide (Al2O3) or aluminum-doped zirconium oxide (Al-doped ZrO2).

[0291] FIG. 23A to FIG. 23F The multilayer stack 603 may include Figure 25 to Figure 27 One of the multilayer stacks ML29 to ML31.

[0292] According to the embodiment of the present invention, since the dielectric layer of the capacitor includes at least one antiferroelectric layer and at least one high-k dielectric layer, the capacitance of the capacitor can be increased.

[0293] Since the reinforcement layer enhances the dielectric constant, the capacitance of the capacitor can be further increased.

[0294] While the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor device, comprising: a first electrode; a second electrode; and a multilayer stack located between the first electrode and the second electrode, the multilayer stack comprising at least one antiferroelectric layer and at least one high-k dielectric layer, wherein the multilayer stack comprises: a first antiferroelectric layer overlying the first electrode; a first high-k dielectric layer overlying the first antiferroelectric layer; a high bandgap layer overlying the first high-k dielectric layer; a second high-k dielectric layer over the high bandgap layer; a second antiferroelectric layer overlying the second high-k dielectric layer; wherein the first high-k dielectric layer and the second high-k dielectric layer comprise zirconium oxide, wherein the high bandgap layer comprises an aluminum-containing material, The first antiferroelectric layer and the second antiferroelectric layer include hafnium zirconium oxide.

2. The semiconductor device according to claim 1, wherein The multilayer stack includes at least one direct contact interface between the at least one antiferroelectric layer and the at least one high-k dielectric layer.

3. The semiconductor device according to claim 1, wherein The at least one antiferroelectric layer of the first and second antiferroelectric layers includes antiferroelectric hafnium zirconium oxide.

4. The semiconductor device according to claim 1, wherein: The thickness of at least one of the first antiferroelectric layer and the second antiferroelectric layer is less than 5. The semiconductor device according to claim 1, wherein At least one of the first antiferroelectric layer and the second antiferroelectric layer comprises a hafnium zirconium oxide in which the hafnium oxide content is the same as the zirconium oxide content, and the thickness of the hafnium zirconium oxide is less than 6. The semiconductor device according to claim 1, wherein At least one of the first antiferroelectric layer and the second antiferroelectric layer comprises a hafnium-zirconium oxide rich in hafnium oxide in which the hafnium oxide content is greater than the zirconium oxide content, and the thickness of the hafnium-zirconium oxide rich in hafnium oxide is less than 7. The semiconductor device according to claim 1, wherein At least one of the first and second antiferroelectric layers includes a zirconium oxide-rich hafnium zirconium oxide in which the zirconium oxide content is greater than the hafnium oxide content.

8. The semiconductor device according to claim 1, wherein The at least one high-k dielectric layer of the first and second high-k dielectric layers includes hafnium oxide or zirconium oxide.

9. The semiconductor device according to claim 1, wherein: The high bandgap layer has an energy bandgap greater than the first and second antiferroelectric layers and the first and second high-k dielectric layers.

10. The semiconductor device according to claim 1, wherein The multilayer stack further comprises: a leakage barrier layer between the second high-k dielectric layer and the second electrode; and An interface control layer is above the leakage barrier layer.

11. The semiconductor device according to claim 10, wherein: The leakage barrier layer includes a material having a lower dielectric constant and a higher energy bandgap than the first and second antiferroelectric layers and the first and second high-k dielectric layers.

12. The semiconductor device according to claim 10, wherein: The interface control layer includes a material having a greater electronegativity than the first and second antiferroelectric layers and the first and second high-k dielectric layers.

13. The semiconductor device according to claim 1, wherein The multilayer stack further comprises: a leakage barrier layer overlying the second antiferroelectric layer; and An interface control layer is above the leakage barrier layer.

14. The semiconductor device according to claim 1, wherein The multilayer stack further comprises: An enhancement layer improves the dielectric constant of at least one of the first antiferroelectric layer and the second antiferroelectric layer, wherein the enhancement layer is located below the at least one antiferroelectric layer and the enhancement layer is in direct contact with the at least one antiferroelectric layer.

15. The semiconductor device according to claim 14, wherein: The enhancement layer includes niobium oxide, niobium oxynitride, tantalum oxide, tantalum oxynitride, vanadium oxide or vanadium oxynitride.

16. The semiconductor device according to claim 1, further comprising: Semiconductor substrate; a transistor comprising a buried word line structure formed in the semiconductor substrate and a first source / drain region and a second source / drain region on both sides of the buried word line structure; as well as a bit line coupled to the first source / drain region of the transistor, The first electrode is coupled to the second source / drain region of the transistor.

17. The semiconductor device according to claim 1, wherein The first antiferroelectric layer and the second antiferroelectric layer have a tetragonal crystal structure.

18. The semiconductor device according to claim 1, wherein The at least one antiferroelectric layer of the first and second antiferroelectric layers includes a hafnium oxide-rich antiferroelectric hafnium zirconium oxide layer, and the high-k dielectric layer includes a hafnium oxide layer or a zirconium oxide layer.

19. A semiconductor device comprising: a first electrode; a second electrode; as well as a multilayer stack located between the first electrode and the second electrode, the multilayer stack comprising a negative capacitance ferroelectric material layer and at least one high-k dielectric layer, Wherein, the multi-layer stack comprises: a first negative capacitance ferroelectric material layer, which is above the first electrode; a first high-k dielectric layer above the negative capacitance ferroelectric material layer; a high bandgap layer overlying the first high-k dielectric layer; a second high-k dielectric layer over the high bandgap layer; a second negative capacitance ferroelectric material layer overlying the second high-k dielectric layer; wherein the first high-k dielectric layer and the second high-k dielectric layer comprise zirconium oxide, wherein the high bandgap layer comprises an aluminum-containing material, The first negative capacitance ferroelectric material layer and the second negative capacitance ferroelectric material layer include hafnium zirconium oxide.

20. The semiconductor device according to claim 19, wherein The first negative capacitance ferroelectric material layer and the second negative capacitance ferroelectric material layer include hafnium zirconium oxide layers rich in hafnium oxide in which the content of hafnium oxide is greater than that of zirconium oxide.

21. The semiconductor device according to claim 19, wherein The first negative capacitance ferroelectric material layer and the second negative capacitance ferroelectric material layer are thicker than the first high-k dielectric layer and the second high-k dielectric layer.

22. The semiconductor device according to claim 19, wherein The thickness of the first negative capacitance ferroelectric material layer and the second negative capacitance ferroelectric material layer is to 23. The semiconductor device according to claim 19, wherein: The multilayer stack further comprises: a leakage blocking layer in contact with the first negative capacitance ferroelectric material layer and the second negative capacitance material layer or the first high-k dielectric layer and the second high-k dielectric layer; and An interface control layer is located between the leakage barrier layer and the second electrode.

24. The semiconductor device according to claim 19, wherein The first negative capacitance ferroelectric material layer and the second negative capacitance ferroelectric material layer have a tetragonal crystal structure.

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