Switched mode dc / dc converter with bootstrap high-side driver

Abstract

A gate driver (103) for a high-side NMOS power transistor (Mhs) in a DC / DC boost converter (100) includes a first switch (102) and a second switch (104) coupled in series between an output pin (Pl) and a gate of the high-side transistor. A third switch (106) is coupled between the gate and a switch node (SW) between the high-side transistor (Mhs) and a low-side transistor (Mls), the switch node also coupled to an input pin (P3). A fourth switch (108) and a fifth switch (110) are coupled in series between the output pin and a clamp pin (P4). A sixth switch (112) and a seventh switch (114) are coupled in series between the output pin and a ground pin (P2). A first bootstrap capacitor (Cl) and a second bootstrap capacitor (C2) have respective first terminals coupled to a first node (105) between the first switch and the second switch. The first capacitor has a second terminal coupled to a node (107) between the fourth switch and the fifth switch; the second capacitor has a second terminal coupled to a node (109) between the sixth switch and the seventh switch.

Description

Technical Field

[0001] The described embodiments relate generally to the field of voltage conversion circuits. More particularly, and without limitation, the present description is directed to a switch-mode DC / DC converter with a bootstrapped high-side driver. Background Art

[0002] In the power stage of a DC / DC boost converter, two N-type metal oxide silicon (NMOS) transistors can be used as low-side and high-side switches. This arrangement can utilize a bootstrap gate driver for the high-side switch. To generate a stable bootstrap voltage, a large capacitor may be required. Using a large capacitor can consume a large area and introduce additional switching losses, reducing converter efficiency. Improvements are desirable. Summary of the Invention

[0003] The described embodiments provide a switched-mode DC / DC boost converter using stacked bootstrap capacitors that can be charged to different bootstrap voltages. Stacking the bootstrap capacitors reduces the required area and can provide additional advantages to be described.

[0004] In one aspect, an embodiment of a gate driver for a high-side NMOS power transistor in a DC / DC boost converter implemented in an IC chip is disclosed. The gate driver includes: a first switch coupled in series with a second switch between an output pin for coupling to an output voltage and a gate of the high-side NMOS power transistor; a third switch coupled between the gate of the high-side NMOS power transistor and a switch node, the switch node being located between the high-side NMOS power transistor and the low-side NMOS power transistor and further coupled to an input terminal pin; a fourth switch coupled in series with a fifth switch between the output pin and a clamp pin for coupling to a clamp voltage; a sixth switch coupled in series with a seventh switch between the output pin and a ground pin for coupling to a lower rail; a first bootstrap capacitor having a first terminal coupled to a first node between the first and second switches and a second terminal coupled to a second node between the fourth and fifth switches; and a second bootstrap capacitor having a first terminal coupled to the first node and a second terminal coupled to a third node between the sixth and seventh switches.

[0005] In another aspect, an embodiment of a DC / DC boost converter implemented in an IC chip is described. The DC / DC boost converter includes: a high-side N-type metal oxide silicon (NMOS) power transistor coupled in series with a low-side NMOS power transistor between an output pin for coupling to an output voltage and a ground pin for coupling to a lower rail; a switch node located between the high-side NMOS power transistor and the low-side NMOS power transistor, the switch node coupled to an input pin, the input pin being coupled to an input voltage via an inductor; a first bootstrap capacitor having a first terminal coupled to selectively connect to one of the output voltage and a gate of the high-side NMOS power transistor and coupled to selectively connect to a clamp pin for coupling to a clamp voltage and one of the output pin; and a second bootstrap capacitor having a first terminal coupled to selectively connect to one of the output pin and the gate of the high-side NMOS power transistor and a second terminal coupled to selectively connect to the ground pin and one of the output pin.

[0006] In yet another aspect, an embodiment of a method of operating a DC / DC boost converter is described. The method includes providing the DC / DC boost converter on an integrated circuit (IC) chip, the DC / DC boost converter including stacked bootstrap capacitors; and coupling output pins of the IC chip to provide an output voltage, wherein the output pins are coupled to respective first terminals of the stacked bootstrap capacitors during a first phase and to respective second terminals of the stacked bootstrap capacitors during a second phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments of the specification are shown by way of example and not limitation, and in the figures of the accompanying drawings, like reference numerals indicate similar elements. It should be noted that different references to "an" or "one" embodiment in this specification do not necessarily refer to the same embodiment, and such references may mean at least one. In addition, when a particular feature, structure or characteristic is described in conjunction with an embodiment, it should be understood that such feature, structure or characteristic can be implemented in conjunction with other embodiments within the knowledge of those skilled in the art, whether or not explicitly described. As used herein, the term "couple" or "couples" is intended to mean an indirect or direct electrical connection, unless limited to a "communicative coupling" that may include a wireless connection portion. Thus, if a first device is coupled to a second device, the connection may be by a direct electrical connection, or by an indirect electrical connection via other devices and connections.

[0008] Figure 1 depicts an example of a switch-mode DC / DC boost converter implemented in an integrated circuit chip;

[0009] Figure 2A and Figure 2BDepicts the period during the two operating phases Figure 1 The position of the switch;

[0010] Figure 3A depicts the voltage across the first and second bootstrap capacitors as the output voltage increases;

[0011] Figure 3B The graph of Rds-on,hs as the output voltage increases is depicted;

[0012] Figure 4A Describes the basis Figure 9 The relative areas consumed by the implementation of the circuit of FIG. 1 when implementing the high-side NMOS power transistor, the high-side gate drive switch, and the bootstrap capacitor C1;

[0013] Figure 4B Depicts the relative area consumed in implementing the high-side NMOS power transistor, high-side gate drive switch, and bootstrap capacitors C1 / C2;

[0014] Figure 5 Depicts the Figure 4B A cross section of line A-A';

[0015] Figure 6 depicts a graph of the capacitance ratio of the bootstrap capacitor C2 to the bootstrap capacitor C1 versus how many times smaller the stacked capacitor implementation is than the single capacitor implementation;

[0016] Figure 7 depicts the overall boost converter efficiency for a single bootstrap capacitor implementation versus a stacked bootstrap capacitor implementation;

[0017] Figure 8 A flow chart depicting a method of operating a DC / DC boost converter; and

[0018] Figure 9 An example of a switch-mode DC / DC boost converter according to the prior art is depicted. DETAILED DESCRIPTION

[0019] Specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following detailed description of the embodiments of the present invention, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other cases, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0020] Figure 9FIGURE 9 illustrates a prior art DC / DC boost converter 900 with an output voltage Vout of up to 10V. DC / DC boost converter 900 is implemented on an integrated circuit (IC) chip 901, which can be coupled to a first terminal of an inductor L, with an input voltage Vin coupled to a second terminal of the inductor L. DC / DC boost converter 900 is also coupled to the output voltage Vout and a lower rail, which can be a ground plane. A bootstrap capacitor C1 is provided on the chip, and in the illustrated embodiment, the technology used to manufacture IC chip 901 can only handle a voltage across bootstrap capacitor C1 of 5V. Because the first terminal of bootstrap capacitor C1 is coupled to the output voltage Vout, which can have a value as high as 10V, a clamping voltage Vclamp can be coupled to the second terminal of bootstrap capacitor C1 to limit the voltage across bootstrap capacitor C1. Therefore, when the output voltage Vout is 10V, the clamping voltage Vclamp is 5V.

[0021] The DC / DC boost converter 900 includes a high-side NMOS power transistor Mhs coupled in series with a low-side NMOS power transistor Mls between the output voltage Vout and the lower rail. A switch node SW is located between the high-side NMOS power transistor Mhs and the low-side NMOS power transistor Mls and can be coupled to an inductor L to receive an input voltage Vin. Control of the low-side NMOS power transistor Mls is generally easier than control of the high-side NMOS power transistor Mhs and is simply shown as a driver circuit 920, which is coupled to the voltage Vdd and the lower rail and receives an activation signal ACTls.

[0022] The driver circuit for the high-side NMOS power transistor Mhs includes a bootstrap capacitor C1 and five switches 902-910. These switches are shown in their most general form, as the exact implementation of the switches is not relevant to this description. A first terminal of the bootstrap capacitor C1 is coupled to switch 902, which operates to couple that terminal to the output voltage Vout. The first terminal is also coupled to switch 904, which operates to couple the first terminal to the gate of the high-side NMOS power transistor Mhs. The gate of the high-side NMOS power transistor Mhs is also coupled to switch 906, which operates to couple the gate to a switching node SW. The second terminal of the bootstrap capacitor C1 is coupled to switch 908, which operates to couple the second terminal to the output voltage Vout, and to switch 910, which operates to couple the second terminal to the clamping voltage Vclamp.

[0023] The switches 902-910 operate in two phases, wherein the switches are coupled in phase as Figure 9As shown, the high-side NMOS power transistor Mhs is closed. In the first phase Φ1, which occurs when the low-side NMOS power transistor M1s is turned on, switches 902, 906, and 910 are closed, while switches 904 and 908 are open. The bootstrap capacitor C1 is charged to a bootstrap voltage Vboot1, which is equal to the output voltage Vout minus the clamping voltage Vclamp and is 5V in one embodiment. Simultaneously, the gate of the high-side NMOS power transistor Mhs is coupled to the switching node SW via switch 906. Since the gate and source terminals of the power transistors are at the same potential, the high-side NMOS power transistor Mhs remains in the off state.

[0024] In the second phase Φ2, the low-side power transistor M1s is turned off, switches 902, 906, and 910 are open, and switches 904 and 908 are closed. The second terminal of the bootstrap capacitor C1 now receives the output voltage Vout. The charge accumulated during the first phase Φ1 is shared with the gate capacitor of the high-side NMOS power transistor Mhs, generating a gate-source voltage and turning on the high-side NMOS power transistor Mhs. As previously mentioned, integrating the bootstrap capacitor C1 can occupy a large area on the IC chip 901 and introduce additional switching losses that reduce converter efficiency.

[0025] Figure 1 A DC / DC boost converter 100 implemented on an IC chip 101 and having an output voltage of up to 10V is depicted. The DC / DC boost converter 100 includes a high-side NMOS power transistor Mhs and a low-side NMOS power transistor Mls, and has a switch node SW located between the high-side NMOS power transistor Mhs and the low-side NMOS power transistor Mls. The high-side NMOS power transistor Mhs and the low-side NMOS power transistor Mls are coupled in series between an output pin P1 for coupling to an output voltage Vout and a ground pin P2 for coupling to a lower rail. The switch node SW is coupled to an input pin P3, which is coupled to an inductor L and, through the inductor L, to an input voltage Vin during operation of the DC / DC boost converter 100.

[0026] The high-side NMOS power transistor Mhs is controlled by a gate driver 103, which includes a first bootstrap capacitor C1, a second bootstrap capacitor C2, and seven switches 102-114; the low-side gate driver 120 is coupled between the voltage Vdd and the lower rail and receives an activation low-side signal ACTls. Figure 9 As shown, Figure 1The stage in which each of the switches 102-114 is coupled to be closed is shown. Although their structures are on different levels of the chip, the first bootstrap capacitor C1 and the second bootstrap capacitor C2 are both on-chip capacitors, as explained below. The first bootstrap capacitor C1 is again limited in the voltage it can handle and can be coupled to the clamping voltage Vclamp via the clamp pin P4, while the second bootstrap capacitor C2 can handle the full output voltage Vout across the plates and is coupled to the lower rail via the ground pin P2. It can be noted that Figure 1 Three ground pins P2 are shown. In a power supply circuit, the actual number of pins coupled to high-current pins may vary depending on the needs and circuit design, and these illustrations should not be considered limiting. In one embodiment, the clamping voltage Vclamp is 5V. A first terminal of each of the first and second bootstrap capacitors C1 and C2 is coupled to a first node 105.

[0027] Regarding the switching circuitry of gate driver 103, a first switch 102 and a second switch 104 are coupled in series between output pin P1 and the gate of high-side NMOS power transistor Mhs, with a first node 105 located between first switch 102 and second switch 104. A third switch 106 is coupled between the gate of high-side NMOS power transistor Mhs and switch node SW. A fourth switch 108 and a fifth switch 110 are coupled in series between output pin P1 and clamp voltage Vclamp, with a second terminal of a first bootstrap capacitor C1 coupled to a second node 107 between fourth and fifth switches 108, 110. A sixth switch 112 and a seventh switch 114 are coupled in series between output pin P1 and a lower rail, which in one embodiment is ground, with a second terminal of a second bootstrap capacitor C2 coupled to a third node 109 between sixth and seventh switches 112, 114.

[0028] The operation of switches 102-114 again occurs in two distinct phases, which are determined by reference to Figure 2A and Figure 2B Inactive transistors, switches, and paths are shown as dashed lines, while active transistors, switches, and paths are shown as solid lines. Figure 2ADuring the illustrated first phase Φ1, the first switch 102, the third switch 106, the fifth switch 110, and the seventh switch 114 are closed, while the second switch 104, the fourth switch 108, and the sixth switch 112 are open. During the first phase Φ1, a first bootstrap capacitor C1 is coupled between the output pin P1 and the clamp pin P4 to charge the first bootstrap capacitor C1 to a first bootstrap voltage Vboot1 equal to (Vout − Vclamp), and a second bootstrap capacitor C2 is coupled between the output pin P1 and the lower rail to charge the second bootstrap capacitor C2 to a second bootstrap voltage Vboot2 equal to the output voltage Vout. While the first and second bootstrap capacitors C1 and C2 are charging, the third switch 106 couples the gate of the high-side NMOS power transistor Mhs to the switching node SW. Closing the third switch 106 ensures that the gate and source terminals of the high-side NMOS power transistor Mhs are at the same potential and that the high-side NMOS power transistor Mhs is in the off state.

[0029] Then in Figure 2B In the illustrated second phase Φ2, the second switch 104, the fourth switch 108, and the sixth switch 112 are closed, while the first switch 102, the third switch 106, the fifth switch 110, and the seventh switch 114 are open. During the second phase Φ2, the low-side NMOS power transistor M1s is turned off. Current continues to flow through the inductor L and begins charging the switch node SW, which is now decoupled from the gate of the high-side NMOS power transistor Mhs. Simultaneously, the bottom plates of the first bootstrap capacitor C1 and the second bootstrap capacitor C2 (i.e., the plates with lower voltages) are coupled to the output pin P1 and the output voltage Vout via the fourth switch 108 and the sixth switch 112, respectively, causing the voltage on the top plates of the capacitors to increase accordingly. The total charge accumulated during the first phase Φ1 is shared with the gate capacitor of the high-side NMOS power transistor Mhs, generating a gate-source voltage that turns on the high-side NMOS power transistor Mhs.

[0030] Figure 3A The bootstrap voltages Vboot1 and Vboot2 are depicted as the value of the output voltage Vout increases. As the output voltage Vout increases, the clamping voltage Vclamp applied to the second terminal of the bootstrap capacitor C1 is adjusted to ensure that the first bootstrap voltage Vboot1 remains the same at all values ​​of the output voltage Vout. The second bootstrap capacitor C2 is supplied by the output voltage Vout and the lower rail (e.g., ground plane), so that the second bootstrap voltage Vboot2 rises proportionally to the output voltage Vout. At the same time, as Figure 3BAs shown in Figure 1, the high-side drain / source on-resistance Rds-on,hs is inversely proportional to the output voltage Vout and decreases as the output voltage increases. Therefore, for lower values ​​of the output voltage Vout, the operation of the high-side NMOS power transistor Mhs reduces switching losses due to the lower gate / source voltage Vgs, while at higher values ​​of the output voltage Vout, the operation of the high-side NMOS power transistor Mhs reduces conduction losses due to the higher overdrive that reduces the drain / source on-resistance Rds-on,hs.

[0031] As shown in the figure, the DC / DC boost converter 100 includes two independent bootstrap capacitors that can be charged to different voltages, wherein the first bootstrap voltage Vboot1 contributed by the first bootstrap capacitor C1 remains constant, while the second bootstrap voltage Vboot2 increases proportionally with the output voltage Vout. The charge shared between the first bootstrap capacitor C1 and the second bootstrap capacitor C2 can reduce the capacitance required for a single capacitor. In addition, the efficiency of the DC / DC boost converter is improved by making one of the voltages (e.g., the second bootstrap voltage Vboot2) depend on the operating point of the output voltage Vout. When the DC / DC boost converter 100 is implemented in the IC chip 101, the second bootstrap capacitor C2 can be stacked in the layout to achieve significant area reduction.

[0032] Figure 4A Depicted is the relative footprint on an IC chip of the components of the high-side circuit 400A for DC / DC boost converter 900. The high-side NMOS power transistor area, HS-NMOS 402A, consumes approximately half of the chip portion dedicated to the high-side circuit 400A. Of the remaining half of the high-side circuit 400A, the C1 capacitor area 404A consumes approximately two-thirds, and the gate drive switch area HS_GDRV 406A consumes the remaining third.

[0033] Figure 4BDepicted are the relative areas occupied by components of the high-side circuit 400B for the DC / DC boost converter 100. In the illustrated embodiment, the high-side NMOS power transistor area, HS-NMOS 402B, has been reduced by approximately 10%. This area reduction depends on the capacitance ratio between the first bootstrap capacitor C1 and the second bootstrap capacitor C2, which influences how much the gate / source voltage of the high-side switch varies over the voltage range of Vout and can vary. The reduction in on-chip capacitor area is even more significant. The C1 / C2 capacitor area 404B is less than half the size of the C1 capacitor area 404A. By stacking two capacitors with the same capacitance, the area consumed by the capacitors can be halved. Further area reductions can be achieved when a high-voltage capacitor (such as the second bootstrap capacitor C2) is stacked on top of an existing capacitor with a limited voltage. Again, the actual reduction in space used by the capacitors depends on the capacitance ratio, as described below. Because the area added for the new switches 112 , 114 is comparable to the possible reduction in switch size of the first bootstrap capacitor C1 due to current sharing with the second bootstrap capacitor C2 , the size of the high-side gate drive switch area HS-GDRV406B is substantially the same as in the prior art.

[0034] Figure 5 A portion of an IC chip 500 is depicted on which stacked bootstrap capacitors C1 and C2 are implemented and correspond to the Figure 4B , a cross section taken at line A-A' of FIG. As shown, the second bootstrap capacitor C2 overlies the first bootstrap capacitor C1 and has the same area as the first bootstrap capacitor C1. Although not required to have the same area in the described embodiment, fabricating the first bootstrap capacitor C1 and the second bootstrap capacitor C2 to have the same area provides minimal area usage. The epitaxial layer 502 of the IC chip 500 includes a thick oxide layer 504, a doped well in the substrate of the IC chip 500 that forms a lower plate 506 of the first capacitor C1, and a contact area 508 for the lower plate 506. The oxide layer overlies the lower plate 506 and forms a capacitor dielectric 510 for the first capacitor C1. In one embodiment, the capacitor dielectric 510 is formed simultaneously with the formation of the gate oxide for the logic transistors on the IC chip 500. The polysilicon layer forms the upper plate 512 of the first capacitor C1.

[0035] A dielectric layer 514 separates the upper plate 512 from the lower metal wiring stack 518, while vias 516 form connections between the lower metal wiring stack 518 and both the contact area 508 and the upper plate 512. A dielectric layer 520 separates the lower metal wiring stack 518 from the second capacitor C2, which is comprised of a lower plate 522 and an upper plate 524 separated by a C2 dielectric layer 526. An upper metal wiring stack 530 is coupled to both the upper plate 524 and the lower plate 522 through corresponding vias 532. The overlap between the first capacitor C1 and the second capacitor C2 is indicated by arrows 534. Arrows 534 also depict the overlap between the upper plate 524 and the lower plate 522 of the second capacitor C2, as well as the overlap between the upper plate 512 and the lower plate 506 of the first capacitor C1.

[0036] The mathematics of area reduction will now be demonstrated. Figure 9 The bootstrap capacitor C1 is implemented similarly to Figure 5 The first capacitor C1 is manufactured in this way, Figure 5 In this embodiment, the first plate is a heavily doped polysilicon layer separated from the second plate formed in the substrate of the wafer by a gate oxide layer. For such a single 5V bootstrap capacitor embodiment, the total charge in the 5V gate oxide capacitor C1 is expressed as:

[0037] Q1=5V·C1 Equation 1

[0038] Where Q is the charge and C is the capacitance.

[0039] The gate-source voltage Vgs generated by charge redistribution between the bootstrap capacitor C1 and the gate of the high-side NMOS power transistor Mhs is expressed by the following equation:

[0040]

[0041] Where Cgg is the effective gate capacitance of the high-side NMOS power transistor Mhs. Rearranging this equation to determine the bootstrap capacitance yields:

[0042]

[0043] Looking next at the described stacked bootstrap capacitor implementation, the total charge in the 5V gate oxide capacitor and the high voltage capacitor charged to 10V is expressed as:

[0044] Q1,2 = 5V·C1 + 10V·C2 Equation 4

[0045] The gate-source voltage Vgs of the high-side NMOS power transistor generated by charge redistribution between the first bootstrap capacitor C1, the second bootstrap capacitor C2 and the gate of the high-side NMOS power transistor Mhs is:

[0046]

[0047] Assuming the capacitance of the high voltage capacitor is 1 / r of the capacitance of the 5V gate oxide capacitor, the following results are obtained:

[0048]

[0049] Solving the equation for the bootstrap capacitor yields:

[0050]

[0051] Comparing the 5V gate oxide bootstrap capacitance values ​​using a single capacitor versus the proposed stacked capacitor implementation yields:

[0052]

[0053] Since the second bootstrap capacitor C2 is stacked on top of the first bootstrap capacitor C1 , the reduction of the 5V gate oxide capacitor C1 directly translates into area reduction.

[0054] Figure 6 A graph 600 is depicted where the Y axis provides the ratio of capacitor area when using a single bootstrap capacitor to the capacitor area when using stacked bootstrap capacitors, and the X axis depicts the capacitance ratio r. It can be seen that as the capacitance ratio becomes larger, the area reduction becomes smaller. Figure 1 The embodiment of is implemented at point 602 along the curve, where the capacitance ratio plotted on the X-axis is 3 and the area reduction plotted on the Y-axis is 2.444 times.

[0055] Figure 7 Depicted is a graph comparing the overall boost converter efficiency of a single capacitor embodiment shown by curve 702 and the overall boost converter efficiency shown by curve 704. Figure 1 Graph 700 shows the overall boost converter efficiency for a stacked capacitor embodiment. The efficiency loss of the bootstrap capacitor includes the high-side gate charge that needs to be replenished during each switching cycle, as well as the capacitor isolation well associated with the dynamically moving high-voltage node. The proposed capacitor stacking embodiment reduces the capacitor isolation well. The estimated efficiency curve shows approximately a 4% improvement in the light-load region, where switching losses dominate.

[0056] Figure 8A flow chart depicts a method 800 of operating a DC / DC boost converter according to an embodiment of the specification. The method 800 begins by providing (805) a DC / DC boost converter on an IC chip, wherein the DC / DC boost converter has stacked bootstrap capacitors. The method continues by coupling (810) an output pin of the IC chip to provide an output voltage such that the output voltage is coupled to a corresponding first terminal of the stacked bootstrap capacitor during a first phase and to a corresponding second terminal of the stacked bootstrap capacitor during a second phase. Further elements include coupling (815) a ground pin of the IC chip to a ground plane; coupling (820) an input pin of the IC chip to an inductor and an input voltage; and coupling (825) a clamp pin of the IC chip to a clamp voltage.

[0057] Applicants have described a DC / DC boost converter having a high-side NMOS power transistor and stacked bootstrap capacitor implementation that can exhibit one or more of the following advantages: reduced die area for the high-side switch, reduced die area for the stacked capacitors, lower switching losses, and lower dynamic on-resistance, the latter two of which are attributed to the dynamic bootstrap voltage of the second bootstrap capacitor. Applicants have also described a method of operating the DC / DC boost converter.

[0058] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. None of the above detailed descriptions should be understood to imply that any particular component, element, step, action or function is essential so that it must be included within the scope of the claims. Unless expressly stated, elements in the singular form are not intended to mean "one and only one", but "one or more". All structural and functional equivalents of the elements of the above-described embodiments known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the present claims. Therefore, those skilled in the art will recognize that, within the spirit and scope of the appended claims, the exemplary embodiments described herein can be practiced by various modifications and changes.

Claims

1. A DC / DC boost converter implemented in an integrated circuit chip (IC chip), the DC / DC boost converter comprising: a high-side N-type metal oxide silicon power transistor, namely a high-side NMOS power transistor, coupled in series with the low-side NMOS power transistor between an output pin for coupling to an output voltage and a ground pin for coupling to a lower rail; a switch node between the high-side NMOS power transistor and the low-side NMOS power transistor, the switch node coupled to an input pin for coupling to an input voltage through an inductor; a first bootstrap capacitor having a first terminal coupled to be selectively connected to one of an output voltage and a gate of the high-side NMOS power transistor and a second terminal coupled to be selectively connected to one of the output pin and a clamp pin for coupling to a clamp voltage; as well as A second bootstrap capacitor has a first terminal coupled to be selectively connected to one of the output pin and the gate of the high-side NMOS power transistor and a second terminal coupled to be selectively connected to one of the ground pin and the output pin. 2 . The DC / DC boost converter according to claim 1 , wherein the second terminal of the first bootstrap capacitor is formed in a substrate of the IC chip. 3 . The DC / DC boost converter according to claim 2 , wherein the second bootstrap capacitor overlies the first bootstrap capacitor. 4 . The DC / DC boost converter according to claim 2 , wherein an area of ​​the second bootstrap capacitor is the same as an area of ​​the first bootstrap capacitor.

5. The DC / DC boost converter of claim 1 , wherein the gate of the high-side NMOS power transistor is coupled to be connected to the switch node during a first phase of operation of the DC / DC boost converter and to be connected to respective first terminals of the first and second bootstrap capacitors during a second phase of operation. 6 . The DC / DC boost converter of claim 5 , wherein the respective first terminals of the first and second bootstrap capacitors are further coupled to be connected to the output pin during the first phase of operation. 7 . The DC / DC boost converter of claim 6 , wherein the second terminal of the first bootstrap capacitor is further coupled to connect to the clamp pin during the first phase of operation.

8. The DC / DC boost converter of claim 7, wherein the second terminal of the second bootstrap capacitor is further coupled to be connected to the lower rail during the first phase of operation. 9 . The DC / DC boost converter of claim 8 , wherein respective second terminals of the first and second bootstrap capacitors are coupled to be connected to the output pin during the second phase of operation.

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