Active X-ray attack prevention device

Abstract

The present invention relates to an active X-ray attack prevention device. The present disclosure relates to a metal layer of an active X-ray attack prevention device for protecting an integrated circuit. Specifically, the present disclosure relates to a structure comprising: a semiconductor material; one or more devices located on the front side of the semiconductor material; a back patterned metal layer located below the one or more devices, which is positioned and constructed to protect the one or more devices from active intrusion; and at least one contact that provides an electrical connection through the semiconductor material to the front side of the back patterned metal layer. The back patterned metal layer is located between one of the semiconductor material and the insulator layer and the wafer.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits, and more particularly to active x-ray attack prevention devices and operating methods for protecting integrated circuits. Background Art

[0002] When using active x-ray spectroscopy, a party can observe the integrated circuit under power and voltage contrast and determine the functional state of the design. In addition, once the decryption step of the private key occurs, it is possible to unlock the private key of the device and use the registers of the integrated circuit for the first time. Known techniques to prevent such unlocking may include package shielding, but package shielding is still susceptible to tampering. Therefore, known techniques have not been able to prevent the discovery of key technologies and intellectual property in the integrated circuit. Summary of the invention

[0003] In one aspect of the present disclosure, a structure includes: semiconductor material; one or more devices located on a front side of the semiconductor material; a back side patterned metal layer located below the one or more devices and positioned and configured to protect the one or more devices from active intrusion; and at least one contact providing an electrical connection through the semiconductor material to a front side of the back side patterned metal layer. The back side patterned metal layer is located between one of the semiconductor material and an insulator layer and a wafer.

[0004] In another aspect of the present disclosure, a structure includes: a semiconductor material; at least one device located on the front side of the semiconductor material; a back side patterned metal layer buried on the back side of the semiconductor material; at least one contact connected to the front side of the back side patterned metal layer, the at least one contact extending through the semiconductor material; and a logic circuit connected to the back side patterned metal layer via the at least one contact and configured to detect a resistance change in the back side patterned metal layer.

[0005] In another aspect of the present disclosure, a method includes: forming an insulator layer; forming a semiconductor layer on the insulator layer; forming a back-end-of-line (BEOL) layer on the semiconductor layer; forming a back-side patterned metal layer on a back side of the insulator layer; and forming a handle wafer on the back-side patterned metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following detailed description, the disclosure is described by way of non-limiting examples of exemplary embodiments of the disclosure with reference to the various figures mentioned.

[0007] Figure 1 Shown are body contacts and corresponding manufacturing processes, among other features, in accordance with aspects of the present disclosure.

[0008] Figure 2 A handle wafer and corresponding manufacturing process are shown, among other features, in accordance with aspects of the present disclosure.

[0009] Figure 3 A backside patterned metal layer and a corresponding manufacturing process are shown, among other features, in accordance with aspects of the present disclosure.

[0010] Figure 4 Removal of a handle wafer and a corresponding manufacturing process are shown, among other features, in accordance with aspects of the present disclosure.

[0011] Figure 5 A representative diagram of a backside metal pattern according to aspects of the present disclosure is shown.

[0012] Figure 6 A bulk silicon wafer having a silicon germanium (SiGe) stack and a corresponding manufacturing process are shown, among other features, in accordance with aspects of the present disclosure.

[0013] Figure 7 Back-end of the line (BEOL) layers and corresponding manufacturing processes are shown, among other features, in accordance with aspects of the present disclosure.

[0014] Figure 8 A thinned wafer and corresponding manufacturing process are shown, among other features, in accordance with aspects of the present disclosure.

[0015] Fig. 9 A backside patterned metal layer on a backside of a semiconductor material and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0016] The present disclosure relates to integrated circuits, and more specifically to an active x-ray attack prevention device and operating method for protecting integrated circuits. More specifically, the present disclosure provides a buried patterned metal layer to prevent a scanning electron microscope (SEM) from invading a chip using a backside attack. By implementing the device disclosed herein, when there is a backside attack from a scanning electron microscope (SEM), the circuit can detect a resistance change in the buried patterned metal layer and generate a tampering signal to change the circuit operation. Therefore and advantageously, by implementing the device disclosed herein, the device can prevent active x-ray attacks from determining the functional state of the circuit design and prevent the theft of key technologies and intellectual property.

[0017] In known circuits, attacks and / or analysis of the circuit occur by scanning the back side of the chip across the die. The attack and / or analysis can capture the functionality of the device, which can then be reconstructed. For example, the analysis can be accomplished by performing active and passive optical probing using photoemission (PE), electro-optical frequency modulation, or laser voltage techniques. To avoid attacks and / or analysis of the circuit, a charge trap logic structure can be used; however, in this type of circuit, the attack and / or analysis may occur after bypassing the charge trap device. In addition, package shielding can prevent attacks and / or analysis of the circuit; however, the package shielding is susceptible to tampering. In contrast, the present invention provides a buried metal layer that is used to generate a tampering signal to change the circuit operation when there is a backside attack from a SEM. In particular, the present disclosure includes a buried metal layer that prevents x-rays from passing through to reach functional circuits.

[0018] In an embodiment of the present disclosure, an integrated circuit includes active and passive devices formed on the front side of a wafer. In addition, patterned metal is buried between a buried oxide layer (BOX) and the wafer. Contacts in the integrated circuit provide electrical connections from the patterned metal to the front side of the wafer. In addition, the integrated circuit includes a logic circuit that detects resistance changes in the patterned metal and generates a tamper signal to change circuit operation. Advantageously, the present disclosure prevents x-rays from penetrating into the chip while using body contacts to the buried patterned metal or the back patterned metal. The integrated circuit detects any resistance changes in the buried patterned metal or the back patterned metal, which indicates tampering for removing the buried metal.

[0019] The devices of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the devices of the present disclosure have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a film of material patterned by a photolithographic process on top of the wafer. Specifically, the manufacture of the device uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film to the mask.

[0020] Figure 1 Shown are body contacts and corresponding manufacturing processes, among other features. Figure 1 The structure 100 may represent a semiconductor-on-insulator (SOI) technology. More specifically, in Figure 1In the embodiment, the structure 100 includes a substrate 115, which includes a silicon-on-insulator (SOI) technology. In the SOI technology, the substrate 115 includes a semiconductor material 120 bonded or attached to an insulating layer 130, and the insulating layer 130 is bonded to a processing wafer 140. The semiconductor material 120 can be bonded to the insulating layer 130 using wafer bonding technology and / or other suitable methods. In an embodiment, the processing wafer 140 and the semiconductor material 120 can be composed of any suitable material, including but not limited to Si, SiGe, SiGeC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. The insulating layer 130 can also be formed by any suitable process, such as isolation by implantation of oxygen (SIMOX), oxidation, deposition and / or other suitable processes. The insulator layer 130 includes any suitable material, including silicon oxide, sapphire or other suitable insulating materials and / or combinations thereof. An exemplary insulator layer 130 can be a buried oxide layer (BOX). In an embodiment, the depth of semiconductor material 120 and insulator layer 130 is approximately 100 nanometers; however, other dimensions are also contemplated herein.

[0021] Still reference Figure 1 , device 160 is formed in or on semiconductor material 120. Device 160 can be an active or passive device. For example, device 160 can be a transistor, a resistor, a capacitor, a combination thereof, etc. Back-end of line (BEOL) layers 110 are deposited on semiconductor material 120 by conventional deposition processes, such as chemical vapor deposition (CVD) processes. In an embodiment, BEOL layers 110 are the entire back-end stack, which includes a stack of metals and vias for wiring including inductors, resistors, and capacitors.

[0022] Figure 1Also shown are a plurality of contacts 150 formed by conventional photolithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed over the BEOL layer 110 is exposed to energy (light) to form a pattern (opening). Using an etching process with selective chemistry (e.g., reactive ion etching (RIE)), one or more trenches extending into the handle wafer 140 are formed in the BEOL layer 110, the semiconductor material 120, and the insulating layer 130 through the openings in the resist. In another embodiment, one or more trenches extending into the handle wafer 140 through the openings in the resist are formed in the front end of line (FEOL) using an etching process with selective chemistry (e.g., reactive ion etching (RIE)). After the resist is removed by a conventional oxygen ashing process or other known strippers, a metal material may be deposited in these trenches to form a plurality of contacts 150, such as body contacts. In an embodiment, the metal material may be aluminum or tungsten (e.g., WSi) or copper and other materials deposited by any conventional deposition process (e.g., CVD process), among other materials. Any residual material on the surface of BEOL layer 110 may be removed by conventional chemical mechanical polishing (CMP) processes.

[0023] exist Figure 2 In the embodiment, the temporary handling wafer 170 is attached to the BEOL layer 110 by a conventional bonding process. For example, the temporary handling wafer 170 can be bonded to the BEOL layer 110 by contact bonding or thermocompression bonding. Contact bonding uses a liquid curable adhesive layer coated on a carrier wafer; while the thermocompression process involves heating and applying heat and mechanical pressure to two connections.

[0024] exist Figure 3 middle, Figure 2 The structure of the back side patterned metal layer 180 is turned over, for example, inverted, and the handle wafer 140 is removed by conventional processes including mechanical polishing, debonding or other known processes. The removal of the handle wafer 140 will expose the insulator layer 130 (i.e., BOX layer) and the body contact 150. A back side patterned metal layer 180 (i.e., buried patterned metal layer 180) is formed on the exposed back side of the insulator layer 130 (i.e., BOX layer), and the back side patterned metal layer 180 contacts the body contact 150. In particular, the pattern of the back side patterned metal layer 180 has a size that prevents the SEM from detecting the device above the pattern.

[0025] In an embodiment, the metal material of the back patterned metal layer 180 can be deposited by conventional deposition methods, and then a patterning process (such as photolithography and etching) is performed to form different patterns. The handling wafer 190 is attached or deposited on the back patterned metal layer 180 by conventional techniques, which are as described herein and are well known to those skilled in the art, and therefore do not require further explanation.

[0026] exist Figure 4 In the embodiment, temporary handling wafer 170 is removed by conventional debonding techniques. For example, debonding can be provided by mechanical forces, such as cleaving, or by other debonding techniques, which are well known to those skilled in the art and therefore do not require further explanation to fully understand the present disclosure.

[0027] By implementing the processes described herein, a backside patterned metal layer 180 is provided between the insulator layer 130 (ie, the BOX layer 130 ) and the handle wafer 190 . Figure 4 The integrated circuit 100 does not require through silicon vias (TSVs). Figure 4 In the embodiment of the present invention, the buried pattern metallization layer (i.e., back patterned metal layer 180) with body contact 150 can be connected to a logic circuit (which can be represented by any device 160). The logic circuit 160 can be used to detect any tampering of the back patterned metal layer 180. For example, any attempt to remove the handle wafer 190 and the back patterned metal layer 180 will cause the logic circuit to measure a higher resistance, which will trigger a tamper signal. The logic circuit 160 for detecting resistance changes can be any known circuit design.

[0028] Figure 5 A representative diagram of the backside metal pattern is shown. Figure 5 In FIG. 1 , the back metal pattern 180 includes a body contact 150, which is placed at different distances and positions of the back metal pattern 180 to measure the resistance of the back patterned metal layer 180. Figure 5 In the pattern, the back patterned metal layer 180 is a serpentine pattern. However, other patterns are also contemplated herein. The pattern should preferably shield the device and its functions from attack. For example, the pattern can be a spiral structure of concentric shapes (e.g., circular, rectangular, octagonal, etc.), different shapes (e.g., circular, rectangular, octagonal, etc.), and the size of the spacing or interval between adjacent lines can be set to prevent back monitoring. In this way, the back patterned metal layer 180 will prevent X-rays from penetrating the back of the processing wafer 190, and any tampering with the patterning will change the resistance of the back patterned metal layer 180. The change in resistance will be an alarm of tampering, and the device can be disabled at this time.

[0029] In other embodiments, the serpentine shape may have multiple sensing taps (e.g., body contacts 150) along the length of the serpentine structure. In this way, external resistors cannot be used to bypass the integrated circuit (i.e., integrated circuit 100). In addition, a series of these serpentine (or other shaped) patterned metal structures can be added to the chip to prevent localized attacks. In some other embodiments, in order to compensate for resistance changes as a function of temperature (i.e., relative to hacking attempts), several resistors can be used for comparison. For example, if all of the resistances of these resistors increase (within a known tolerance), it is most likely due to thermal changes rather than hacking / tampering attempts. However, if at least one of these resistors increases beyond a known tolerance, while the other resistors remain stable or only increase within a known tolerance, it is most likely due to a hacking / tampering attempt, rather than thermal changes.

[0030] Figures 6 to 9 A through silicon via (TSV) method with backside metallization according to aspects of the present disclosure is shown. Figure 6 , structure 100a includes a bulk silicon wafer 305 having a silicon germanium (SiGe) stack 320 grown thereon. Specifically, the SiGe material 320 may be 10-20% Ge and 80-90% Si. The SiGe material 320 may be 100 nanometers or thicker to serve as a marking layer (e.g., an etch stop layer), and the bulk wafer 310 may be approximately 100 microns; however, other dimensions are contemplated herein. In an embodiment, semiconductor material 310 is deposited (e.g., grown) on the SiGe material 320. In an embodiment, the semiconductor material 310 may be a single crystal Si material; however, other semiconductor materials described herein are also contemplated. In further embodiments, the SiGe stack 320 may be removed by performing an etch based on the final wafer thickness.

[0031] exist Figure 7 In the embodiment, the back-end of line (BEOL) layer 110 is deposited on the semiconductor material 310 by a conventional deposition process (e.g., a CVD process). In an embodiment, the BEOL layer 110 is the entire back-end stack, which includes a stack of metals and vias for wiring including inductors, resistors, and capacitors. In addition, the device 160 is formed on the semiconductor material 310 surrounded by the BEOL layer 110. The device 160 can be an active or passive device as described herein.

[0032] Figure 7Also shown are a plurality of through silicon via (TSV) contacts 330 formed by conventional photolithography, etching, and deposition methods, which are well known to those skilled in the art and therefore require no further explanation to understand the present disclosure. The TSV contacts 330 may extend through the BEOL layer 110, the semiconductor material 310, the SiGe material 320, and into the wafer 305. As an example, the TSV 330 may have a depth of approximately 100 microns; however, other dimensions are contemplated herein.

[0033] exist Figure 8 In the embodiment, the wafer 305 is thinned to the depth of the SiGe material 320. Due to the material selectivity between the wafer 305 and the SiGe material 320, the SiGe material 320 can be used as an etch stop layer. Fig. 9 In the embodiment, after the SiGe material 320 is removed, the TSV 330 is exposed, and a backside patterned metal layer 180 (and the wafer 190 ) is formed on the backside of the semiconductor material 310 , wherein the backside patterned metal layer 180 is in electrical contact with the TSV contact 330 .

[0034] In alternative embodiments, SiGe material 320 may remain on semiconductor material 310, such as Fig. 9 In this embodiment, a backside patterned metal layer 180 (i.e., a buried patterned metal layer 180) is formed on the backside of the SiGe material 320, in electrical contact with the TSV contacts 330. In any embodiment and as previously described, the metallization on the backside of the wafer will prevent scanning electron microscope / transmission electron microscope (SEM / TEM) electrons from reaching the device 160.

[0035] The metal layer of the active x-ray attack prevention device can be utilized in system-on-chip (SoC) technology. It should be understood by those skilled in the art that a SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, the SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0036] The above-described structures and methods are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0037] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: Semiconductor materials; one or more devices located on the front side of the semiconductor material; a backside patterned metal layer, located beneath the one or more devices, positioned and configured to protect the one or more devices from active intrusion; at least one contact providing an electrical connection through the semiconductor material to the front side of the back side patterned metal layer; as well as a logic circuit connected to the back side patterned metal layer and configured to detect a resistance change in the back side patterned metal layer, wherein the back patterned metal layer is located between one of the semiconductor material and the insulator layer and the wafer, and Therein, the logic circuit detects when at least one of the contacts has a change in resistance above a threshold resistance while the other contacts have a change in resistance below the threshold resistance.

2. The semiconductor structure according to claim 1, wherein: The insulator layer is located below the semiconductor material, The wafer is located below the insulator layer, The backside patterned metal layer is located between the insulator layer and the wafer, and The at least one contact is provided through the insulator layer.

3. The semiconductor structure according to claim 1, wherein: The logic circuit is configured to generate a tamper signal to alter circuit operation in response to the detected change in resistance.

4. The semiconductor structure according to claim 1, wherein: The logic circuit is configured to indicate that a thermal change has occurred.

5. The semiconductor structure according to claim 1, wherein: The at least one contact includes a plurality of contacts along the backside patterned metal layer.

6. The semiconductor structure according to claim 1, wherein: The back patterned metal layer is in a serpentine shape.

7. The semiconductor structure of claim 1, wherein: The wafer comprises a handle wafer, The semiconductor material is bulk Si, and The backside patterned metal layer is located between the handle wafer and the bulk Si.

8. The semiconductor structure of claim 7, further comprising a marking layer different from the bulk Si, wherein: The marking layer is located on the lower side of the Si body, The back patterned metal layer is located at the lower side of the marking layer, and The at least one contact is a plurality of through silicon vias extending through the marking layer and contacting the back side patterned metal layer along a length of the back side patterned metal layer.

9. A semiconductor structure comprising: Semiconductor materials; at least one device located on the front side of the semiconductor material; a backside patterned metal layer buried on the backside of the semiconductor material; at least one contact connected to the front side of the back side patterned metal layer, the at least one contact extending through the semiconductor material; as well as a logic circuit connected to the back side patterned metal layer via the at least one contact and configured to detect a resistance change in the back side patterned metal layer, Therein, the logic circuit detects when at least one of the contacts has a change in resistance above a threshold resistance while the other contacts have a change in resistance below the threshold resistance.

10. The semiconductor structure of claim 9, further comprising an insulator material beneath the semiconductor material and a wafer beneath the backside patterned metal layer.

11. The semiconductor structure according to claim 10, wherein: The backside patterned metal layer is buried between the wafer and the insulator material.

12. The semiconductor structure according to claim 11, wherein: The at least one contact is a plurality of contacts along a length of the back side patterned metal layer.

13. The semiconductor structure of claim 9, further comprising a wafer below the semiconductor material, wherein: The semiconductor material is a bulk semiconductor material, and the backside patterned metal layer is buried between the wafer and the bulk semiconductor material.

14. The semiconductor structure according to claim 12, wherein: The at least one contact is a plurality of through silicon vias (TSVs).

15. The semiconductor structure of claim 12, further comprising a silicon germanium (SiGe) material between the semiconductor material and the backside patterned metal layer.

16. The semiconductor structure according to claim 9, wherein: The backside patterned metal layer prevents a scanning electron microscope (SEM) or a transmission electron microscope (TEM) from reaching the at least one device.

17. The semiconductor structure according to claim 9, wherein: The logic circuit is configured to generate a tamper signal to alter circuit operation in response to a detected change in resistance of the backside patterned metal layer.

18. A method of forming a semiconductor structure, comprising: forming an insulator layer; forming a semiconductor layer on the insulator layer; forming a back-end-of-line (BEOL) layer on the semiconductor layer; forming a back patterned metal layer on a back side of the insulator layer; forming a handle wafer on the backside patterned metal layer; as well as forming a logic circuit connected to the backside patterned metal layer via at least one contact, the logic circuit being configured to detect a resistance change in the backside patterned metal layer, Therein, the logic circuit detects when at least one of the contacts has a change in resistance above a threshold resistance while the other contacts have a change in resistance below the threshold resistance.

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