Method and apparatus for managing data scrambling seed values in a NAND memory

Abstract

Embodiments of the present disclosure disclose a method and apparatus for managing data scrambling seed values in a NAND memory. The method includes: detecting, by a NAND controller, a first scrambling of data of a word line in the NAND memory. The method further includes: caching, by the NAND controller for each open block, the last written data of the word line that has undergone the first scrambling in a dynamic random access memory (DRAM) for programming the word line, and / or caching a super page of the last written data of the word line in the DRAM for programming the super page. The method can be used to manage seed values for NAND page scrambling, which can reduce the retention impact. As a result, the retention recovery for NAND cells can be reduced, which can improve durability.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Indian Patent Application No. 202041022041, filed on May 26, 2020, with the Indian Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to a memory system, and more particularly to a method and apparatus for managing a seed value (hereinafter also referred to as a seed) for data scrambling in a NAND memory to improve data retention. Background art

[0004] Data retention is an important phenomenon in NAND memories, which causes a change in the threshold voltage of NAND cells. In existing methods, the flash translation layer (FTL) performs a periodic patrol read to identify NAND cells that are on the verge of having irrecoverable errors due to retention and recycle them. The FTL accumulates data for a complete word line before programming. Typically, due to the stronger electric field between adjacent cells of different word lines, three - dimensional (3D) NAND has a unique charge loss mechanism of lateral charge migration. When adjacent cells of different word lines are storing the limit NAND cell threshold, a strong electric field is generated. If the electric field is high, the data retention rate may increase.

[0005] Figure 1 is an example illustration depicting the distribution of page data in NAND cells according to conventional techniques. To achieve a uniform distribution of the number of cells in different NAND states within a word line, NAND page data is scrambled using a random seed for scrambling. The FTL stores the seed in a spare area of the NAND page, and after reading the page from the NAND, the seed from the spare area is used to descramble the NAND page. In a triple - level cell (TLC) NAND, there are eight states, and a word line consists of three pages. The three pages in a TLC NAND are the lower page, the middle page, and the upper page. The data from each page is combined bit - by - bit and encoded into a specific state. The data encoding in a TLC NAND is NAND - specific and is related to how sensing is done.

[0006] Many conventional methods have been proposed to recover NAND cells on the verge of having irrecoverable errors to improve data retention. This is achieved by scrambling the data in the NAND page using a random seed. The random seed scrambles the data in the NAND page to achieve a uniform distribution of the number of cells in different NAND states within a word line, thereby reducing the data retention impact. However, the disadvantage of conventional methods and apparatuses that use a random seed for data scrambling to achieve an improved retention impact is that due to the voltage difference between adjacent cells in a word line, the random seed used to scramble the data in the NAND page may be inappropriate in some cases.

[0007] Accordingly, the above disadvantages or other deficiencies can be advantageously solved by providing the following method and apparatus: The method and apparatus manage seed values for data scrambling in a NAND memory to improve data retention and / or provide useful alternatives. Summary of the Invention

[0008] Embodiments provide a method and a NAND memory for managing seed values for data scrambling to improve data retention.

[0009] Embodiments manage seed values for NAND page scrambling, which can reduce the retention impact.

[0010] Accordingly, embodiments herein disclose a method for managing seed values for data scrambling in a NAND memory. The method includes: detecting, by a NAND controller, a first scrambling of data of a word line in the NAND memory; and caching, by the NAND controller for each open block, the last written data of the word line that has undergone the first scrambling in a dynamic random access memory (DRAM) for programming the word line, and / or caching a super page of the last written data of the word line in the DRAM for programming the super page.

[0011] Accordingly, embodiments herein disclose an apparatus for managing seed values for data scrambling. The apparatus includes: an array of NAND storage cells; a dynamic random access memory (DRAM); and a NAND controller configured to cause the apparatus to: detect a first scrambling of data of a word line in the NAND storage cell array; and cache, for each open block, the last written data of the word line that has undergone the first scrambling in the DRAM for programming the word line, and / or cache a super page of the last written data of the word line in the DRAM for programming the super page.

[0012] These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. However, it should be understood that the following description, although indicating embodiments and numerous specific details thereof, is given by way of illustration and not limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit of the embodiments herein, and the embodiments herein include all such modifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The inventive concept is illustrated in the accompanying drawings, and like reference numerals throughout the drawings indicate corresponding parts. Embodiments herein will be better understood from the following description with reference to the drawings, in which:

[0014] Figure 1 is an example illustration depicting the distribution of page data in NAND cells according to a conventional technique;

[0015] Figure 2A is an example illustration of a device for managing a seed value for data scrambling in a NAND memory according to an embodiment disclosed herein;

[0016] Figure 2B shows various hardware components of a device for managing a seed value for data scrambling in a NAND memory according to an embodiment disclosed herein;

[0017] Figure 2C is a schematic representation of a NAND memory cell according to an embodiment disclosed herein;

[0018] Figure 3A is a flowchart showing a method for managing a seed value for data scrambling in a NAND memory according to an embodiment disclosed herein;

[0019] Figure 3B is a flowchart showing various operations for programming a word line according to an embodiment disclosed herein;

[0020] Figure 3C is a flowchart showing various operations for programming a super page according to an embodiment disclosed herein;

[0021] Figure 3D is a flowchart showing various operations for selecting a seed for programming a word line based on the last written data of the word line cached in DRAM according to an embodiment disclosed herein;

[0022] Figure 3E is another flowchart showing various operations for selecting a seed for programming a word line based on the last written data of the word line cached in DRAM according to an embodiment disclosed herein;

[0023] Figure 4 is an example flowchart showing various operations for programming word lines according to embodiments disclosed herein;

[0024] Figure 5 is an example illustration of a device selecting a die for writing data received from a host according to embodiments disclosed herein. DETAILED DESCRIPTION

[0025] Embodiments herein and their various features and advantageous details are more fully illustrated with reference to the non - limiting embodiments shown in the accompanying drawings and described in detail below. Descriptions of well - known components and processing techniques are omitted so as not to unnecessarily obscure the embodiments herein. Further, the various embodiments described herein need not be mutually exclusive, since some embodiments can be combined with one or more other embodiments to form new embodiments. Unless otherwise stated, the term "or" as used herein refers to a non - exclusive "or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When an expression such as "at least one" follows a list of elements, it modifies the entire list of elements rather than individual elements of the list. Examples used herein are only intended to facilitate understanding of the manner in which embodiments herein can be practiced and further enable those skilled in the art to practice embodiments herein. Thus, the examples should not be construed as limiting the scope of embodiments herein.

[0026] As is traditional in the art, embodiments can be described and illustrated from the perspective of blocks that perform one or more of the described functions. These blocks, which may be referred to herein as units or modules, etc., are physically implemented by electronic devices such as mobile devices, laptop computers, small tablets, etc., and optionally can be driven by firmware and software. For example, a module can be implemented in one or more electronic devices, or on any other communication device, etc. The modules that make up the blocks can be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block. Without departing from the scope of the present invention, each block of an embodiment can be physically divided into two or more interacting and discrete blocks. Similarly, without departing from the scope of the present invention, the blocks of an embodiment can be physically combined into more complex blocks.

[0027] The accompanying drawings are used to help easily understand various technical features, and it should be understood that the embodiments presented herein are not limited by the accompanying drawings. Thus, the present disclosure should be construed as extending to any alterations, equivalents, and alternatives other than those specifically listed in the accompanying drawings. The same reference numerals always denote the same elements. Therefore, even if the same or similar reference numerals are not mentioned or described in the corresponding accompanying drawings, they can be described with reference to other accompanying drawings. In addition, elements not denoted by reference numerals can be described with reference to other accompanying drawings. Although terms such as first and second can be used herein to describe various elements, these elements should not be limited by these terms. These terms are generally only used to distinguish one element from another element.

[0028] Accordingly, embodiments herein disclose a method of managing a seed value for data scrambling in a NAND memory. The method includes detecting a first scrambling of data of a word line in the NAND memory by a NAND controller (110a). The NAND controller (110a) can include: processing circuitry, such as hardware including logic circuitry; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, the processing circuitry can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, and an application specific integrated circuit (ASIC), etc.

[0029] The method further includes: by the NAND controller, for each open block, caching the last written data of the word line that has undergone the first scrambling (hereinafter also referred to as the last written word line or the last programmed word line) in the DRAM (104) of the storage device for programming the word line, and / or caching the super page of the last written data of the word line in the DRAM (104) for programming the super page.

[0030] Different from conventional methods and systems, the method can be used to manage the seed value for NAND page scrambling, which can reduce the hold impact. As a result, the retention recycle of NAND cells can be reduced, which can improve durability.

[0031] The proposed method utilizes a selected optimal seed to scramble the data of a word line during word line programming. The seed can be stored in a spare area of the word line. The spare area of the word line is updated with the selected optimal seed, and the programming of the word line is completed. To select the optimal seed for data scrambling, multiple iterations are performed. The number of iterations for selecting the optimal seed value for data scrambling depends on the desired system performance. The proposed method can be used both when writing host data and when reclaiming data. Implementing this method can result in a solid state drive (SSD) with high durability. This method can be used to reduce the number of bit-flips caused by retention.

[0032] Now referring to the drawings, and more specifically, referring to Figures 2A to 5 , embodiments of the inventive concept are shown.

[0033] Figure 2A is an exemplary illustration of a device (100a) managing seed values for data scrambling in a NAND memory (110) in a storage device according to embodiments disclosed herein. The storage device can be, for example but not limited to, a solid state drive (SSD) device, an embedded multimedia card (eMMC), a secure digital (SD) card, etc. The device (100a) includes input data (102) of a word line in a DRAM (104) to be programmed. The DRAM (104) includes a plurality of open FTL blocks for accumulating the input data (102) of the word line and performing a write operation on the input data (102) of the word line. The NAND controller (110a) is configured to: perform a first scrambling of the input data (102) using a random seed (106), and cache the previous write data of the word line with the first scrambled input data (102) into the DRAM (104) of the storage device for programming the word line, cache the super page of the previous write data of the word line into the DRAM (104) for programming the super page. Calculate a cell differential voltage, where the cell differential voltage is an average of threshold voltage differences between the previously programmed word line and all adjacent cells of the new word line. Calculate the cell differential voltage between the scrambled data (108b) of the adjacent word line and the scrambled data (108a) of the new word line. The scrambled data (108b) of the adjacent word line and the scrambled data (108a) of the new word line are stored in at least one page of the NAND memory (110).

[0034] Figure 2C is a schematic diagram of a NAND storage cell according to embodiments disclosed herein. As Figure 2C shown, a super block can be formed by a set of erase blocks from all dies (e.g., Figure 2CThe superblock therein is formed by the erase blocks from die 0 to die 3). A superpage can be formed by a set of word lines at the same horizontal height from the erase blocks (e.g., Figure 2C The superpage therein is formed by word lines at the same horizontal height from the erase blocks of dies 0 to 3). In Figure 2C The last programmed word line, the new word line (i.e., the currently programmed word line), the superblock, and the superpage are shown. Each word line has three pages in TLC NAND.

[0035] As shown, in Figure 2A NAND controller (110a) is configured to select a seed for programming data of a word line based on the last written data of the word line cached in DRAM (104). In addition, NAND controller (110a) uses the selected seed to initiate programming of the word line.

[0036] Figure 2B Shows various hardware components of an apparatus (100a) for managing seed values for data scrambling in a NAND memory (110) according to an embodiment disclosed herein. In an embodiment, the apparatus (100a) includes a host (not shown) and a NAND memory (110). The host sends input data (102) of a word line, and the input data (102) can be scrambled to improve retention due to a large threshold voltage difference between cells of adjacent word lines and cells of the new word line. The host may include a memory (not shown), a processor (not shown), and a communicator (not shown). In this embodiment, the NAND memory (110) includes a NAND controller (110a) and a NAND storage cell array (110b). The NAND controller (110a) is coupled to the NAND storage cell array (110b). DRAM (104) is connected to the NAND controller (110a).

[0037] In an embodiment, the NAND controller (110a) is configured to receive input data (102) of a word line from the host. The NAND controller (110a) is configured to cache the input data (102) of the new word line in DRAM (104). In addition, the NAND controller (110a) is configured to randomly initialize a seed for second scrambling of the input data (102) of the word line from the host by using the last written word line cached in DRAM (104). In addition, the NAND controller (110a) is configured to perform second scrambling of the input data (102) of the word line from the host by using the new word line. In addition, the NAND controller (110a) is configured to determine the threshold cell difference voltage of each open FTL block based on the last written word line cached in DRAM (104).

[0038] In addition, the NAND controller (110a) is configured to determine a cell differential voltage between adjacent NAND cells associated with the last written data of the first-scrambled word line and adjacent NAND cells associated with the second-scrambled input data (102). In addition, the NAND controller (110a) is configured to determine whether the cell differential voltage satisfies an allowable threshold cell differential voltage. In addition, the NAND controller (110a) is configured to perform a selection of a random initialization seed for programming the word line, update the spare area of the word line with the selected seed in response to determining that the cell differential voltage satisfies the threshold cell differential voltage, and randomly generate another seed in response to determining that the cell differential voltage does not satisfy the threshold cell differential voltage.

[0039] In an embodiment, the NAND controller (110a) is further configured to determine whether an iteration count for selecting a seed is satisfied. In addition, the NAND controller (110a) is configured to randomly generate another seed in response to determining that the iteration count for selecting a seed is not satisfied. In addition, the NAND controller (110a) is configured to perform a selection of a seed to update the spare area of the word line and initiate programming of the word line in response to determining that the iteration count for selecting a seed is satisfied.

[0040] Figure 2A and Figure 2B FIG. shows various hardware components of the apparatus 100a, but it should be understood that other embodiments are not limited thereto. In other embodiments, the apparatus (100a) may include fewer or more components. In addition, the labels or names of the components are for illustrative purposes only and do not limit the scope of the present disclosure. One or more components may be combined together to perform the same or substantially similar functions to manage seed values for scrambling data in the NAND memory, thereby programming word lines in the NAND memory (110).

[0041] Figure 3A is a flowchart (300a) showing a method of managing seed values for data scrambling in a NAND memory (110) according to embodiments disclosed herein. Operations (302a - 304b) are performed by the NAND controller (110a). The method includes: at (302a), detecting a first scrambling of data of a word line in the NAND memory (110). The method includes: at (304a), caching, for each open FTL block, the last written data of the first-scrambled word line in the DRAM (104) of the storage device for programming the word line. The method includes: at (304b), caching a superpage of the last written data of the word line in the DRAM (104) for programming the superpage.

[0042] Figure 3B is a flowchart (304a) showing various operations for programming word lines according to embodiments disclosed herein. Operations (304aa and 304ab) are performed by the NAND controller (110a). The method includes: at (304aa), selecting a seed for programming the word line based on the last written data of the word line cached in the DRAM (104). The method includes: at (304ab), programming the word line using the selected seed.

[0043] Figure 3C is a flowchart (304b) showing various operations for programming superpages according to embodiments disclosed herein. Operations (304ba - 304bc) are performed by the flash translation layer (FTL) module. The FTL module runs in the storage device to map user pages to physical NAND pages. The FTL module may be implemented by the NAND controller (110a). The method includes: at (304ba), caching the superpage of the last written data of the word line in the DRAM (104). The method includes: at (304bb), creating multiple superpages in the host write buffer. The method includes: at (304bc), reordering the multiple superpages in the host write buffer to determine the best or desired cell differential voltage of the complete superpage relative to the superpage of the last written data of the word line in the DRAM (104).

[0044] Figure 3DIt is a flowchart (304aa) showing various operations of selecting a seed for programming a word line based on the last-written data of the word line cached in DRAM (104) according to an embodiment disclosed herein. Operations (304da - 304dj) are performed by the NAND controller (110a). The method includes: at (304da), receiving input data (102) of the word line from a host. The method includes: at (304db), randomly initializing a seed from a NAND page using the last-written word line cached in DRAM (104), the seed being used for second scrambling of the input data (102) of the word line from the host. The method includes: at (304dc), performing second scrambling of the input data (102) of the word line from the host using a new word line. The method includes: at (304dd), determining the threshold cell difference voltage of each open FTL block based on the last-written word line. The method includes: at (304de), determining the cell difference voltage between adjacent NAND cells associated with the last-written data of the word line after first scrambling and adjacent NAND cells associated with the input data (102) after second scrambling. At (304df), the method includes determining whether the cell difference voltage satisfies the threshold cell difference voltage. If the cell difference voltage satisfies the threshold cell difference voltage, the method includes: at (304dg), performing selection of a randomly initialized seed for programming the word line and updating the spare area of the word line using the selected seed. If the cell difference voltage does not satisfy the threshold cell difference voltage, the method includes: at (304dh), determining whether the iteration count for selecting a seed is satisfied. If the iteration count for selecting a seed is not satisfied, the method includes: at (304di), performing random generation of another seed. If the iteration count for selecting a seed is satisfied, the method includes: at (304dj), selecting a seed to update the spare area of the word line and initiating programming of the word line.

[0045] Figure 3E It is another flowchart (304aa) showing various operations of selecting a seed for programming a word line based on the last-written data of the word line cached in DRAM (104) according to an embodiment disclosed herein. Operations (304ea - 304ef) are performed by the NAND controller (110a).

[0046] The method includes: at (304ea), randomly initializing a seed from a NAND page using a word line written last time cached in DRAM (104), where the seed is used for second scrambling of the input data (102) of the word line. The method includes: at (304eb), performing second scrambling on the input data of the word line using a new word line. The method includes: at (304ec), determining a cell differential voltage between each adjacent NAND cell associated with the last written data of the word line after first scrambling and each adjacent NAND cell associated with the input data after second scrambling. The method includes: at (304ed), selecting a seed corresponding to the minimum cell differential voltage for programming the word line. The method includes: at (304ee), updating a spare area of the word line using the selected seed.

[0047] Figure 4 FIG. (400) is an example flowchart showing various operations for programming a word line according to an embodiment disclosed herein. Operations (402 - 418) are performed by a NAND controller (110a). The method includes: at (402), randomly initializing a seed from a NAND page using a word line written last time cached in DRAM (104), where the seed is used for second scrambling of the input data (102) of the word line. The method includes: at (404), performing second scrambling on the input data (102) of the word line using a new word line. The method includes: at (406), determining a threshold cell differential voltage of all adjacent NAND cells in the word line. The method includes: at (408), the NAND controller (110a) determining a cell differential voltage between each NAND cell in the adjacent NAND cells associated with the last written data of the word line after first scrambling and each cell in the adjacent NAND cells associated with the input data (102) after second scrambling.

[0048] The method includes: at (410), determining whether the cell differential voltage is lower than the threshold cell differential voltage, or determining whether the allowed number of iterations is exceeded. If the cell differential voltage is lower than the threshold cell differential voltage or the allowed number of iterations is exceeded, then the method includes: at (412), the NAND controller (110a) selecting a seed corresponding to the minimum cell differential voltage for programming the word line. The method includes: at (414), updating a spare area of the word line using the selected seed. The method includes: at (416), performing programming of the word line. If the cell differential voltage is not lower than the threshold cell differential voltage or the allowed number of iterations is not exceeded, then the method includes: at (418), randomly generating a next seed for scrambling the data of the word line.

[0049] Figure 5An example illustration of a die selected for writing data received from a host by a device (100) according to an embodiment disclosed herein. As Figure 5 shown, the FTL module receives input host data during a host write operation for forming a complete superpage in a host write buffer among a plurality of host write buffers (502a1 - 502xn). Further, the FTL module compares the input host data with the last written data of word lines of a plurality of dies (804a - 804n) in the last written superpage. Further, the FTL module selects at least one die from the plurality of dies (804a - 804n) to locate a superpage satisfying a minimum cell difference voltage among a plurality of superpages from the host write buffer within a stripe of a superblock, and writes the input host data in the selected die. Further, the FTL module indicates the location of the superpage after programming of the superblock.

[0050] In an embodiment, the FTL holds one open block as a superpage or a superblock for writing host data. In an embodiment, the superpage or superblock includes a plurality of host write buffers (502a1 - 502xn) as blocks from a plurality of dies (804a - 804n). In an example, 64 blocks from 64 dies constitute a superblock. The FTL remembers the superpage of the last written word line. Once a superpage is formed in the host write buffer, the pages within the host write buffer are reordered to satisfy the best or desired cell difference voltage of the complete superpage relative to the last written superpage.

[0051] The various actions, acts, blocks, steps, etc. in the flowcharts (300a, 304a, 304b, 304aa and 400) may be performed in the order presented, a different order, or simultaneously. Further, in some embodiments, some actions, acts, blocks, steps, etc. may be omitted, added, modified, skipped, etc. without departing from the scope of the present invention.

[0052] Embodiments disclosed herein may be implemented using at least one software program running on at least one hardware device and performing network management functions to control elements.

[0053] The foregoing description of the specific embodiments will fully disclose the general nature of the embodiments herein, so that others can, by applying the existing knowledge, readily modify and / or adapt these specific embodiments for various applications without departing from the concept of the invention, and therefore, these adaptations and modifications should and are intended to be understood as being within the meaning and scope of the equivalents of the disclosed embodiments. It should be understood that the terminology or phraseology used herein is for the purpose of description and not of limitation. Thus, although the embodiments herein have been described in terms of embodiments, those skilled in the art will recognize that embodiments herein can be practiced with modifications within the spirit and scope of the embodiments as described herein.

Claims

1. A method for managing a seed value for data scrambling in a NAND memory, the method comprising: detecting, by a NAND controller, scrambled data of a word line in the NAND memory, the scrambled data being a result of a first scrambling of input data; and after the first scrambling, caching, by the NAND controller, at least one of the following in a dynamic random access memory (DRAM): the last written data of a previous word line in the NAND memory for programming the word line for each open block in the DRAM, or a previous superpage of the last written data for programming a superpage.

2. The method according to claim 1, wherein the programming of the word line comprises: selecting, by the NAND controller, a selected seed value based on the last written data of the previous word line cached in the DRAM; and programming, by the NAND controller, the word line using the selected seed value.

3. The method according to claim 2, wherein the selecting, by the NAND controller, of the selected seed value comprises: randomly generating, by the NAND controller, a first seed value from a NAND page; performing, by the NAND controller, a second scrambling of the input data using the first seed value; determining, by the NAND controller, a cell threshold of each open block; determining, by the NAND controller, a cell differential voltage between adjacent NAND cells associated with the last written data of the previous word line and adjacent NAND cells associated with the scrambled data after the second scrambling; determining, by the NAND controller, whether the cell differential voltage meets the cell threshold; randomly generating, by the NAND controller, a second seed value in response to determining that the cell differential voltage does not meet the cell threshold; and selecting, by the NAND controller, the randomly generated seed value as the selected seed value in response to determining that the cell differential voltage meets the cell threshold, and updating a spare area of the word line using the selected seed value.

4. The method according to claim 3, wherein the randomly generating of the second seed value comprises: determining, by the NAND controller, whether an iteration count for selecting a seed value is met; randomly generating, by the NAND controller, the second seed value in response to determining that the iteration count for selecting a seed value is not met; and selecting, by the NAND controller, the first seed value as the selected seed value in response to determining that the iteration count for selecting a seed value is met.

5. The method according to claim 4, wherein the iteration count depends on the performance of the NAND controller.

6. The method according to claim 3, wherein the selecting, by the NAND controller, of the randomly generated seed value comprises: The NAND controller determines a cell differential voltage between each adjacent NAND cell associated with the last written data of the previous word line and each adjacent NAND cell associated with the scrambled data after the second scrambling; The NAND controller selects a randomly generated seed value corresponding to the minimum cell differential voltage as the selected seed value; and The NAND controller updates the spare area of the word line using the selected seed value.

7. The method according to claim 1, wherein, the programming of the super page includes: The NAND controller caches the previous super page of the last written data in the DRAM; The NAND controller creates a plurality of super pages in the host write buffer; and The NAND controller reorders the plurality of super pages in the host write buffer to determine a desired cell differential voltage of the complete super page relative to the previous super page of the last written data cached in the DRAM.

8. The method according to claim 7, further including: The NAND controller receives the input data as input host data during a host write operation for forming the complete super page in the host write buffer among a plurality of host write buffers; The NAND controller compares the scrambled data with the last written data, wherein the previous super page has a plurality of dies; The NAND controller selects at least one die from the plurality of dies to locate, in a stripe area of a super block, the super page among the plurality of super pages from the host write buffer that satisfies the minimum cell differential voltage; and The NAND controller writes the scrambled data in the selected die.

9. The method according to claim 8, further including: After programming of the super block, indicating the location of the super page.

10. An apparatus for managing a seed value for data scrambling in a NAND memory, the apparatus comprising: A NAND storage cell array; A dynamic random access memory DRAM; and A NAND controller configured to cause the apparatus to: Detect scrambled data of a word line in the NAND storage cell array, the scrambled data being a result of a first scrambling of input data; and After the first scrambling, cache at least one of the following in the DRAM: The last written data of the previous word line in the NAND memory for programming the word line for each open block in the DRAM, or The previous super page of the last written data for programming a super page.

11. The apparatus according to claim 10, wherein, The NAND controller is further configured to cause the apparatus: Select a selected seed value for programming the word line based on the last written data of the previous word line cached in the DRAM; and Initiate programming of the word line using the selected seed value.

12. The apparatus according to claim 11, wherein the NAND controller is further configured to cause the apparatus to: Randomly generate a first seed value from a NAND page; Perform a second scrambling of the input data using the first seed value; Determine the cell thresholds of each open block; Determine the cell differential voltage between the adjacent NAND cells associated with the last written data of the previous word line and the adjacent NAND cells associated with the scrambled data after the second scrambling; Determine whether the cell differential voltage satisfies the cell threshold; In response to determining that the cell differential voltage does not satisfy the cell threshold, randomly generate a second seed value; and In response to determining that the cell differential voltage satisfies the cell threshold, select the randomly generated seed value as the selected seed value and update the spare area of the word line using the selected seed value.

13. The apparatus according to claim 12, wherein the NAND controller is further configured to cause the apparatus to: Determine whether the iteration count for selecting a seed value is satisfied; In response to determining that the iteration count for selecting a seed value is not satisfied, randomly generate the second seed value; and In response to determining that the iteration count for selecting a seed value is satisfied, select the first seed value as the selected seed value.

14. The apparatus according to claim 13, wherein the iteration count depends on the performance of the NAND controller.

15. The apparatus according to claim 12, wherein the NAND controller is further configured to cause the apparatus to: Determine the cell differential voltage between each adjacent NAND cell associated with the last written data of the previous word line and each adjacent NAND cell associated with the scrambled data after the second scrambling; Select the randomly generated seed value corresponding to the minimum cell differential voltage as the selected seed value; and Update the spare area of the word line using the selected seed value.

16. The apparatus according to claim 10, wherein the NAND controller is further configured to cause the apparatus to: Cache the superpage of the last written data in the DRAM; Create multiple superpages in the host write buffer; and Reorder the multiple superpages in the host write buffer to determine the desired cell differential voltage of the complete superpage relative to the previous superpage of the last written data cached in the DRAM.

17. The apparatus according to claim 16, wherein the NAND controller is further configured to cause the apparatus to: Receive the input data as input host data during a host write operation for forming the complete superpage in the host write buffer among multiple host write buffers; Compare the scrambled data with the last written data, wherein the previous superpage has a plurality of dies; Select at least one die from the plurality of dies to locate, in a stripe of the superblock, the superpages from the plurality of superpages in the host write buffer that satisfy the minimum unit differential voltage; and Write the scrambled data in the selected die.

18. The apparatus according to claim 17, wherein, the NAND controller is further configured to cause the apparatus to: after programming of the superblock, indicate the location of the superpage.

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