Display device

Abstract

A display device is provided. The display device includes a substrate. The substrate has a groove portion that is recessed inward at one side, and includes: a display area including a first display area, a second display area, and a third display area, the second display area and the third display area protrude from a first side of the first display area, and the groove portion is placed between the second display area and the third display area; and a peripheral area surrounding the display area. A first gate line, a second gate line, and a third gate line are respectively located on the first display area, the second display area, and the third display area, and are respectively coupled to a first pixel, a second pixel, and a third pixel. The first, second, and third gate drivers are respectively used to sequentially provide a first gate signal, a second gate signal, and a third gate signal to the first gate line, the second gate line, and the third gate line. The third gate driver is located on the peripheral area between the third display area and the second display area.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0060556, filed on May 20, 2020, which is hereby incorporated by reference herein in its entirety. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] The display device can be divided into a display area where pixels are set and a non-display area where pixels are not set. When the display area is larger, the display device can display a larger image and improve the aesthetics. Therefore, a narrow frame design in which the non-display area is reduced and a frameless design in which the non-display area is removed have become the focus.

[0004] A load matching capacitor for overcoming the difference in RC delay (e.g., resistance-capacitance delay) of a signal depending on the load difference at each location and a driver for controlling pixels are installed in the non-display area, but since the non-display area is reduced, it becomes difficult to install the driver and the load matching capacitor. Summary of the invention

[0005] Example embodiments of the present disclosure provide a display device capable of sufficiently securing an installation space of a load matching capacitor (eg, capable of providing a sufficient installation space).

[0006] A display device according to an exemplary embodiment of the present disclosure includes: a substrate having a groove portion recessed inward at one side, and including a display area and a peripheral area surrounding the display area, the display area including a first display area, a second display area, and a third display area, the second display area and the third display area protrude from a first side of the first display area, and the groove portion is placed between the second display area and the third display area; a first pixel located on the first display area; a second pixel located on the second display area; a third pixel located on the third display area; a first gate line located on the first display area and coupled to the first pixel; a second gate line located on the second display area and coupled to the second pixel; a third gate line located on the third display area and coupled to the third pixel; a first gate driver for sequentially providing a first gate signal to the first gate line; a second gate driver for sequentially providing a second gate signal to the second gate line; and a third gate driver for sequentially providing a third gate signal to the third gate line, wherein the third gate driver is located on the peripheral area between the second display area and the third display area.

[0007] In example embodiments, the first gate line, the second gate line, and the third gate line extend in a first direction, and the second display area and the third display area may be spaced apart from each other in the first direction.

[0008] In example embodiments, the display device may further include a first control line extending through a peripheral area between the second display area and the third display area and coupled to the second gate driver and the third gate driver.

[0009] In an example embodiment, the second gate driver may be used to generate a second gate signal corresponding to the first start pulse in the second gate signal using the first clock signal provided via the first control line, and the third gate driver may be used to generate a third gate signal corresponding to the second start pulse in the third gate signal using the first clock signal provided via the first control line.

[0010] In example embodiments, the second start pulse may be the same as the first start pulse, and the second start pulse may be provided to the third gate driver through one of the first control lines.

[0011] In example embodiments, the second gate line and the third gate line may be separated from each other with the trench portion interposed between the second gate line and the third gate line.

[0012] In an example embodiment, the display device may further include: a fourth gate line located on the first display area and coupled to the first pixel; a fifth gate line located on the second display area and coupled to the second pixel; a sixth gate line located on the third display area and coupled to the third pixel; a connecting line located on a peripheral area between the second display area and the third display area and coupling the fifth gate line and the sixth gate line to each other; and a fourth gate driver for sequentially providing a fourth gate signal to the fifth gate line and the fourth gate line.

[0013] In example embodiments, the display device may further include a dummy pattern overlapping the connection line to form a capacitor.

[0014] In example embodiments, the display device may further include a power supply line commonly coupled to the first pixel, the second pixel, and the third pixel, and the dummy pattern may be coupled to the power supply line.

[0015] In example embodiments, the display device may further include a fifth gate driver for sequentially supplying a fifth gate signal to the sixth gate line and the fourth gate line.

[0016] In example embodiments, the fourth gate driver may be adjacent to the second side of the first display area and the second side of the second display area, and the fifth gate driver may be adjacent to the third side of the first display area and the third side of the third display area.

[0017] In an example embodiment, the display device may further include: a seventh gate line located on the first display area and coupled to the first pixel; an eighth gate line located on the second display area and coupled to the second pixel; a ninth gate line located on the third display area and coupled to the third pixel; a sixth gate driver for sequentially providing a sixth gate signal to the seventh gate line; a seventh gate driver for sequentially providing the seventh gate signal to the ninth gate line; and an eighth gate driver for sequentially providing the eighth gate signal to the eighth gate line, and the eighth gate driver may be located on a peripheral area between the second display area and the third display area.

[0018] In example embodiments, the second gate driver may be adjacent to the second side of the second display area, the third gate driver may be adjacent to the second side of the third display area, the seventh gate driver may be adjacent to the third side of the third display area, and the eighth gate driver may be adjacent to the third side of the second display area.

[0019] In example embodiments, the display device may further include a second control line extending through a peripheral area between the second display area and the third display area and coupled to the seventh gate driver and the eighth gate driver.

[0020] In an example embodiment, the seventh gate driver can be used to generate a seventh gate signal corresponding to the third start pulse among the seventh gate signals using the second clock signal provided through the second control line, and the eighth gate driver can be used to generate an eighth gate signal corresponding to the fourth start pulse among the eighth gate signals using the second clock signal provided through the second control line.

[0021] In example embodiments, the fourth start pulse may be the same as the third start pulse, and the fourth start pulse may be provided to the eighth gate driver through one of the second control lines.

[0022] In an example embodiment, the display device may further include a first data line, a first power line, a second power line, and a first initialization line, and one of the first pixels may include: a light emitting element coupled to both the first power line and the second power line and located between the first power line and the second power line; a driving transistor for transmitting a driving current to the light emitting element and including a first electrode, a second electrode, and a gate electrode; a switching transistor including a first electrode coupled to the first data line, a second electrode coupled to the first electrode of the driving transistor, and a gate electrode coupled to one of the fourth gate lines; a compensation transistor including a first electrode coupled to the second electrode of the driving transistor, a second electrode coupled to the gate electrode of the driving transistor, and a gate electrode coupled to one of the first gate lines; and an initialization transistor including a first electrode coupled to the gate electrode of the driving transistor, a second electrode coupled to the first initialization line, and a gate electrode coupled to one of the seventh gate lines.

[0023] In an example embodiment, the display device may further include a third power line, and the first pixel may further include: a first bypass transistor including a first electrode coupled to the third power line, a second electrode coupled to the first electrode of the driving transistor, and a gate electrode coupled to a first gate line among the first gate lines; and a first light emitting transistor including a first electrode coupled to the first power line, a second electrode coupled to the first electrode of the driving transistor, and a gate electrode coupled to a seventh gate line among the seventh gate lines.

[0024] In an example embodiment, the display device may further include a second initialization line, and the first pixel may further include: a second light emitting transistor including a first electrode coupled to a second electrode of the driving transistor, a second electrode coupled to an anode electrode of the light emitting element, and a gate electrode coupled to one of the seventh gate lines; and a second bypass transistor including a first electrode coupled to the anode electrode of the light emitting element, a second electrode coupled to the second initialization line, and a gate electrode coupled to one of the first gate lines.

[0025] A display device according to an exemplary embodiment of the present disclosure includes: a substrate including a first display area, a second display area, and a third display area and a peripheral area located between the second display area and the third display area, the second display area and the third display area protruding from a first side of the first display area and spaced apart from each other; a first pixel located on the first display area; a second pixel located on the second display area; a third pixel located on the third display area; a first gate line located on the first display area and coupled to the first pixel; a second gate line located on the second display area and coupled to the second pixel; a third gate line located on the third display area and coupled to the third pixel; a first gate driver for sequentially providing a first gate signal to the first gate line; a second gate driver for sequentially providing a second gate signal to the second gate line; and a third gate driver for sequentially providing a third gate signal to the third gate line. The third gate driver may be located on the peripheral area between the second display area and the third display area.

[0026] The display device according to the exemplary embodiment of the present disclosure may include a peripheral area between the second display area and the third display area spaced apart from each other at one side of the first display area, and may include a gate driver that supplies a gate signal to the second display area or the third display area. Therefore, a line on the peripheral area for transmitting the gate signal from the outside of the second display area and the third display area to the second display area or the third display area becomes unnecessary, and a mounting space for a load matching capacitor for compensating for a load difference between signal lines can be sufficiently ensured in the peripheral area between the second pixel area and the third pixel area.

[0027] In addition, since the installation space is ensured, the lines arranged on the peripheral area between the second display area and the third display area may not overlap each other and may be spaced apart from each other by a sufficient distance, thereby reducing the interference effect between the lines and the probability of defect occurrence.

[0028] Aspects and features of example embodiments of the present disclosure are not limited to what has been shown and described above, and other aspects and features are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0030] Figure 2 It is shown Figure 1 A plan view of an example embodiment of a display device.

[0031] Figure 3 It is shown Figure 1 A circuit diagram of an exemplary embodiment of a pixel included in a display device of FIG.

[0032] Figure 4 Is a description Figure 3 Waveform diagram of the pixel operation.

[0033] Figure 5 It is shown Figure 2 FIG. 1 is a diagram of an example embodiment of a display device.

[0034] Figure 6 It is shown Figure 5 FIG. 1 is a diagram of an example embodiment of a display device.

[0035] Figure 7 It is shown Figure 5 FIG. 1 is a diagram of an example embodiment of a display device.

[0036] Figure 8 is shown along Figure 7 A cross-sectional view of an exemplary embodiment of a display device taken along line II'.

[0037] Fig. 9 It is shown Figure 5 FIG. 1 is a diagram of an example embodiment of a display device.

[0038] Fig.10 It is shown Figure 2 FIG. 1 is a diagram of another example embodiment of a display device.

[0039] Fig.11 It is shown Figure 2 FIG. 1 is a diagram of another example embodiment of a display device. DETAILED DESCRIPTION

[0040] Hereinafter, with reference to the accompanying drawings, various example embodiments of the present disclosure will be described in more detail so that a person of ordinary skill in the art can easily perform (e.g., practice) the present disclosure. The present disclosure can be embodied in many different and suitable forms, without being limited to the example embodiments described herein. As used herein, when describing embodiments of the present disclosure, the use of the term "may (may)" refers to "one or more embodiments of the present disclosure". As used herein, unless the context clearly indicates otherwise, the singular forms "a", "one (kind / person)", and "the (said)" are also intended to include plural forms.

[0041] In order to clearly illustrate the present disclosure, parts not related to the description may be omitted, and the same or similar constituent elements are given the same reference numerals throughout the specification. Therefore, the aforementioned reference numerals may be used in other drawings.

[0042] In addition, because the size and thickness of each structure shown in the drawings may be exaggerated for better understanding and ease of description, the present disclosure is not limited by the structures shown. In the drawings, the sizes of layers and regions may be exaggerated for clarity. As used herein, the terms "substantially (roughly)", "approximately (about)", "roughly" and similar terms are used as approximate terms rather than terms of degree, and are intended to account for the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art.

[0043] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0044] Reference Figure 1 , the display device DD includes a timing controller TC, a data driver DDV, a first scan driver SDV1, a second scan driver SDV2 and a display unit DP (or a display panel).

[0045] The timing controller TC may receive an external input signal from an external processor. Here, the external input signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, RGB data, and a clock signal.

[0046] The vertical synchronization signal may include a plurality of pulses, and may indicate the end of the previous frame period and the beginning of the current frame period relative to the time point at which each pulse is generated. The interval between adjacent pulses of the vertical synchronization signal may correspond to a frame period. The horizontal synchronization signal may include a plurality of pulses, and may indicate the end of the previous horizontal period and the beginning of a new horizontal period relative to the time point at which each pulse is generated. The interval between adjacent pulses of the horizontal synchronization signal may correspond to a horizontal period. The data enable signal may indicate that RGB data is supplied in a horizontal period. For example, in response to the data enable signal, RGB data may be supplied in units of pixel rows (e.g., pixels combined (e.g., connected) to the same write scan line) in a horizontal period.

[0047] The timing controller TC may generate a gray value based on the RGB data to correspond to the specification of the display device DD. For example, the gray value may refer to the RGB data rearranged to correspond to the resolution of the display unit DP.

[0048] In addition, the timing controller TC may generate control signals for the data driver DDV, the first scan driver SDV1 , and the second scan driver SDV2 based on an external input signal to correspond to the specifications of the display device DD.

[0049] The data driver DDV may generate a data voltage (or data signal) using the grayscale value and the control signal received from the timing controller TC, and may provide the data voltage to the data lines DL1, DL2 to DLm. Here, m may be a natural number. For example, the data driver DDV may sample the grayscale value using the clock signal, may generate a data voltage corresponding to the grayscale value, and may supply the data voltage to the data lines DL1, DL2 to DLm in units of pixel rows.

[0050] The first scan driver SDV1 may receive a control signal from the timing controller TC, may generate a scan signal (or gate signal) based on the control signal, and may provide the scan signal to the scan lines GWL1, GCL1, GBL1, . . . GWLn, GCLn, GBLn. Here, n may be a natural number.

[0051] In an embodiment, the first scan driver SDV1 may include a first write scan driver, a compensation scan driver, and a bypass scan driver.

[0052] The first write scan driver may be in the form of a shift register and may include a plurality of write stages coupled (e.g., connected) to a write carry line. In response to a write start signal received from a timing controller TC, the write stage may sequentially generate a write carry signal. According to the write start signal and the write carry signal, the write stage may sequentially generate a write scan signal of a conduction level. The write scan signal of the conduction level may be provided to the corresponding write scan lines GWL1 to GWLn. The compensation scan driver may be in the form of a shift register and may include a plurality of compensation stages coupled (e.g., connected) to a compensation carry line. In response to a compensation start signal received from a timing controller TC, the compensation stage may sequentially generate a compensation carry signal. According to the compensation start signal and the compensation carry signal, the compensation stage may sequentially generate a compensation scan signal of a conduction level. The compensation scan signal of the conduction level may be provided to the corresponding compensation scan lines GCL1 to GCLn.

[0053] The bypass scan driver may be in the form of a shift register and may include a plurality of bypass stages coupled (e.g., connected) to the bypass carry lines. In response to a bypass start signal received from a timing controller TC, the bypass stages may sequentially generate bypass carry signals. According to the bypass start signal and the bypass carry signal, the bypass stages may sequentially generate bypass scan signals of a conduction level. The bypass scan signals of the conduction level may be provided to the corresponding bypass scan lines GBL1 to GBLn.

[0054] Will refer to later Figure 6 Example configurations of a first write scan driver, a compensation scan driver, and a bypass scan driver are described.

[0055] The second scan driver SDV2 may receive a control signal from the timing controller TC, may generate a scan signal based on the control signal, and may provide the scan signal to the scan lines GWL1 , GIL1 , EML1 , . . . , GWLn, GILn, and EMLn.

[0056] In an embodiment, the second scan driver SDV2 may include a second write scan driver, an initialization scan driver, and a light emission scan driver.

[0057] The second write scan driver may be substantially the same as or similar to the first write scan driver. The second write scan driver may sequentially generate write scan signals of an on level and may provide the write scan signals of the on level to the corresponding write scan lines GWL1 to GWLn.

[0058] The initialization scan driver may be in the form of a shift register and may include a plurality of initialization stages coupled (e.g., connected) to the initialization carry line. In response to an initialization start signal received from the timing controller TC, the initialization stage may sequentially generate an initialization carry signal. According to the initialization start signal and the initialization carry signal, the initialization stage may sequentially generate an initialization scan signal of a conduction level. The initialization scan signal of the conduction level may be provided to the corresponding initialization scan lines GIL1 to GILn.

[0059] The light emission scan driver may be in the form of a shift register and may include a plurality of light emission stages coupled (e.g., connected) to the light emission carry line. In response to a light emission stop signal received from the timing controller TC, the light emission stage may sequentially generate a light emission carry signal. According to the light emission stop signal and the light emission carry signal, the light emission stage may sequentially generate a light emission scan signal of an off level. The light emission scan signal of the off level may be provided to the corresponding light emission scan lines EML1 to EMLn.

[0060] Will refer to later Fig. 9 Example configurations of the second write scan driver, the initialization scan driver, and the light emission scan driver are described.

[0061] The display unit DP includes pixels. For example, a pixel PXLnm includes a data line DLm, a writing scan line GWLn, a compensation scan line GCLn, a bypass scan line GBLn, an initialization scan line GILn, and a light emission scan line EMLn corresponding thereto.

[0062] In example embodiments, the write scan lines GWL1 to GWLn may be coupled (e.g., connected) to the write stage of the first scan driver SDV1 and the write stage of the second scan driver SDV2, and the write scan signals may be applied to the scan lines GWL1 to GWLn from both sides of the display unit DP (e.g., from both the first scan driver SDV1 and the second scan driver SDV2). Therefore, the RC delay of the write scan signal may be minimized or may be reduced.

[0063] The first scan driver SDV1 may include a compensation stage and a bypass stage, and the second scan driver SDV2 may include an initialization stage and a light emission stage. Therefore, the stages required to control the pixels may be dispersedly arranged on both sides of the display unit DP, and the frame may be minimized or reduced.

[0064] Figure 2 It is shown Figure 1 A plan view of an example embodiment of a display device.

[0065] Reference Figure 2 The display device DD may include a substrate SUB, pixels PXL1, PXL2, and PXL3 (hereinafter, referred to as PXL) disposed on the substrate SUB, a driver disposed on the substrate SUB and driving the pixels PXL, and a line unit combining (e.g., connecting) the pixels PXL and the driver. In addition, the display device DD may further include a power supply unit to supply power to the pixels PXL.

[0066] The substrate SUB may include a groove portion recessed inwardly at one side. Figure 2 As shown in , the substrate SUB may include a groove portion recessed inwardly at an upper side.

[0067] The substrate SUB may include regions A1, A2, and A3, and at least two of the regions A1, A2, and A3 may have different areas (e.g., plane areas). The regions A1, A2, and A3 may be divided by the arrangement and length of corresponding lines. The second region A2 and the third region A3 may be arranged to protrude from one side of the first region A1, and may be spaced apart from each other with a groove portion therebetween.

[0068] exist Figure 2 , the substrate SUB is shown to include a first area A1, a second area A2, and a third area A3, but this is an example, and the substrate SUB is not limited thereto. For example, the substrate SUB may have two areas, or four or more areas, and at least two areas may have different areas.

[0069] Each of the first area A1, the second area A2, and the third area A3 may have various suitable shapes. For example, each of the first area A1, the second area A2, and the third area A3 may have various suitable shapes, such as a closed polygon having sides composed of straight lines, a circle or an ellipse having sides composed of curved lines, and a semicircle or a semiellipse having sides composed of straight lines and curved lines (e.g., sides partially composed of straight lines and partially composed of curved lines).

[0070] In an example embodiment, each of the first area A1, the second area A2, and the third area A3 may have a substantially quadrilateral shape, and may have a shape in which an area adjacent to at least one vertex selected from among the vertices of the quadrilateral is removed. The shape of the area adjacent to at least one vertex selected from among the vertices of the quadrilateral and removed may have a triangular shape, a quadrilateral shape, a diagonal shape inclined about one side of the quadrilateral shape, a curved shape, or a rounded shape. For example, one or more of the first area A1, the second area A2, and the third area A3 may have a shape corresponding to a quadrilateral shape with a portion removed, wherein the removed portion is located at a corner of the quadrilateral shape, and wherein the shape of the removed portion may be a triangular shape, a quadrilateral shape, or a shape having a curved side.

[0071] The first, second, and third areas A1, A2, and A3 may include pixel areas PXA1, PXA2, PXA3 (hereinafter, PXA) (or display areas) and peripheral areas PPA1, PPA2, PPA3 (hereinafter, PPA) (or non-display areas), respectively.

[0072] The pixel area PXA may be an area where the pixels PXL displaying an image are disposed, and may correspond to Figure 1 The first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3 may have shapes corresponding to the first area A1, the second area A2, and the third area A3, respectively.

[0073] The peripheral area PPA may be an area in which the pixels PXL are not disposed, and may be an area in which an image is not displayed. A driver, a power supply unit, and a portion of a line (or wiring) for controlling the pixels PXL may be disposed on the peripheral area PPA. The peripheral area PPA may correspond to a frame (or an invalid space) in the final display device DD, and the width of the frame may be determined according to the width of the peripheral area PPA.

[0074] The first area A1 may have the largest area among the first area A1, the second area A2, and the third area A3. The first area A1 may include a first pixel area PXA1 displaying an image and a first peripheral area PPA1 surrounding at least a portion of the first pixel area PXA1.

[0075] The first pixel region PXA1 may be provided in a shape corresponding to that of the first region A1. The first pixel region PXA1 may have a first width W1 in a first direction DR1, and may have a first length L1 in a second direction DR2 crossing the first direction DR1.

[0076] The first peripheral area PPA1 may be disposed at least one side of the first pixel area PXA1. The first peripheral area PPA1 may surround the edge of the first pixel area PXA1 and may be disposed on an area other than the second area A2 and the third area A3. The first peripheral area PPA1 may include a horizontal portion extending in a width direction (e.g., the first direction DR1) and a vertical portion extending in a length direction (e.g., the second direction DR2). A pair of vertical portions of the first peripheral area PPA1 may be spaced apart from each other in the width direction (or the first direction DR1) of the first pixel area PXA1. For example, a pair of vertical portions of the first peripheral area PPA1 may include two portions extending in the second direction DR2 and arranged with each other in the first direction DR1 with the first pixel area PXA1 therebetween.

[0077] The second area A2 may be disposed at one side (eg, upper side) of the first area A1 and may have a smaller area than the first area A1. The second area A2 may have a second pixel area PXA2 to display an image and a second peripheral area PPA2 surrounding at least a portion of the second pixel area PXA2.

[0078] The second pixel area PXA2 may be set to (e.g., may have) a shape corresponding to the shape of the second area A2. The second pixel area PXA2 may have a second width W2 that is smaller than the first width W1 of the first pixel area PXA1. The second pixel area PXA2 may have a second length L2 that is smaller than the first length L1 of the first pixel area PXA1. In some embodiments, the second width W2 and the second length L2 of the second pixel area PXA2 may be smaller than the width and the length of the first area A1, respectively. The second pixel area PXA2 may be set to a shape protruding from the first pixel area PXA1 and may be directly coupled to (e.g., connected to) the first pixel area PXA1. For example, in the second pixel area PXA2, the edge portion closest to the first pixel area PXA1 may coincide with the edge of the first pixel area PXA1.

[0079] The second peripheral area PPA2 may be disposed at at least one side of the second pixel area PXA2. The second peripheral area PPA2 may surround (e.g., partially surround) the second pixel area PXA2, but may not be disposed on a portion where the first pixel area PXA1 and the second pixel area PXA2 are combined (e.g., connected). The second peripheral area PPA2 may also include a horizontal portion extending in the first direction DR1 and a vertical portion extending in the second direction DR2. A pair of vertical portions of the second peripheral area PPA2 may be spaced apart from each other in the first direction DR1 of the second pixel area PXA2. For example, a pair of vertical portions of the second peripheral area PPA2 may include two portions of the second peripheral area PPA2, which extend along the second direction DR2 and are spaced apart from each other in the first direction DR1 with the second pixel area PXA2 therebetween.

[0080] The third area A3 may be disposed at one side (e.g., the upper side) of the first area A1, may be spaced apart from the second area A2, and may have a smaller area than the first area A1. For example, the third area A3 may be spaced apart from the second area A2 in the first direction DR1. For example, the third area A3 may have the same area as the second area A2. The third area A3 may have a third pixel area PXA3 to display an image and a third peripheral area PPA3 surrounding at least a portion of the third pixel area PXA3.

[0081] The third pixel area PXA3 may be set to (e.g., may have) a shape corresponding to the shape of the third area A3. The third pixel area PXA3 may have a third width W3 that is smaller than the first width W1 of the first pixel area PXA1. The third pixel area PXA3 may have a third length L3 that is smaller than the first length L1 of the first pixel area PXA1. In some embodiments, the third width W3 and the third length L3 of the third pixel area PXA3 may be smaller than the width and length of the first area A1, respectively. The second width W2 and the third width W3 may be the same as each other. In addition, the second length L2 and the third length L3 may be the same as each other.

[0082] The third pixel region PXA3 may be provided in a shape protruding from the first region A1 and may be directly coupled (eg, connected) to the first region A1. For example, in the third pixel region PXA3, an edge portion closest to the first pixel region PXA1 may coincide with an edge of the first pixel region PXA1.

[0083] The third peripheral area PPA3 may be disposed at at least one side of the third pixel area PXA3. The third peripheral area PPA3 may surround (e.g., partially surround) the third pixel area PXA3, but may not be disposed on a portion where the first pixel area PXA1 and the third pixel area PXA3 are combined (e.g., connected). The third peripheral area PPA3 may also include a horizontal portion extending in the width direction and a vertical portion extending in the length direction. A pair of vertical portions of the third peripheral area PPA3 may also be spaced apart from each other in the first direction DR1. For example, a pair of vertical portions of the third peripheral area PPA3 may include two portions of the third peripheral area PPA3, which extend along the second direction DR2 and are spaced apart from each other in the first direction DR1 and have the third pixel area PXA3 therebetween.

[0084] In example embodiments, the third area A3 may have a shape that is line-symmetrical (e.g., reflectively symmetrical) to the second area A2 relative to a center line of the first area A1 (e.g., an imaginary line extending along the second direction DR2 and extending through the center of the first area A1 or the first pixel area PXA1). In this case, the arrangement relationship of each component disposed on the third area A3 may be substantially the same as or similar to that of the second area A2, except for some lines.

[0085] Therefore, the substrate SUB may have a shape in which the second area A2 and the third area A3 protrude from the first area A1 in the second direction DR2. In addition, since the second area A2 and the third area A3 are spaced apart from each other, the substrate SUB may have a concave shape between the second area A2 and the third area A3. For example, the substrate SUB may have a notch between the second area A2 and the third area A3.

[0086] In an example embodiment, the vertical portions of the first peripheral area PPA1 may be respectively coupled (e.g., connected) to some of the vertical portions of the second peripheral area PPA2 and the third peripheral area PPA3. For example, the left vertical portion of the first peripheral area PPA1 and the left vertical portion of the second peripheral area PPA2 may be coupled (e.g., connected) to each other. The right vertical portion of the first peripheral area PPA1 and the right vertical portion of the third peripheral area PPA3 may be coupled (e.g., connected) to each other. In addition, the width W4 of the left vertical portion of the first peripheral area PPA1 and the width W4 of the left vertical portion of the second peripheral area PPA2 may be the same as each other. The width W5 of the right vertical portion of the first peripheral area PPA1 and the width W5 of the right vertical portion of the third peripheral area PPA3 may be the same as each other.

[0087] In some cases, the width W4 of the left vertical portion of the first and second peripheral areas PPA1 and PPA2 may be different from the width W5 of the right vertical portion of the first and third peripheral areas PPA1 and PPA3.

[0088] In example embodiments, the second peripheral area PPA2 and the third peripheral area PPA3 may be combined (e.g., connected) by the additional peripheral area APA. For example, the additional peripheral area APA may combine (e.g., connect) the right vertical portion of the second peripheral area PPA2 and the left vertical portion of the third peripheral area PPA3. For example, the additional peripheral area APA may be disposed at one side (e.g., the upper side) of the first pixel area PXA1 between the second area A2 and the third area A3.

[0089] The pixels PXL may be disposed on the pixel regions PXA on the substrate SUB, for example, on the first pixel region PXA1, the second pixel region PXA2, and the third pixel region PXA3. Each pixel PXL may include a light emitting element to emit color light.

[0090] Each pixel PXL may emit light of one of red, green, and blue, but is not limited thereto. For example, each pixel PXL may emit light of colors such as cyan, magenta, yellow, and white.

[0091] The pixel PXL may include a first pixel PXL1 disposed on a first pixel area PXA1, a second pixel PXL2 disposed on a second pixel area PXA2, and a third pixel PXL3 disposed on a third pixel area PXA3. In an example embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be arranged in a matrix form along rows extending in a first direction DR1 and columns extending in a second direction DR2. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be arranged in a pixel matrix, and each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be arranged along a corresponding row extending in the first direction DR1 and along a corresponding column extending in the second direction DR2. However, the arrangement form of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 is not particularly limited, and the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may be arranged in various suitable forms.

[0092] The driver may provide a signal to the pixel PXL through the line unit, thereby controlling the driving of the pixel PXL. The line unit may include a reference Figure 1For ease of description, the data lines DL1, DL2 to DLm and the scan lines GWL1, GCL1, GBL1, GIL1, EML1, . . . GWLn, GCLn, GBLn, GILn and EMLn are described. Figure 2 Line elements are omitted.

[0093] As reference Figure 1 As described, the driver may include a data driver DDV, a first scan driver SDV1, and a second scan driver SDV2.

[0094] The first scan driver SDV1 may include a first gate driver GDV1 , a second gate driver GDV2 , a third gate driver GDV3 , and a fourth gate driver GDV4 .

[0095] Each of the first gate driver GDV1, the second gate driver GDV2, and the third gate driver GDV3 may include a reference Figure 1 The fourth gate driver GDV4 may include a compensation scanning driver (or compensation stage) and a bypass scanning driver (or bypass stage) as described above. Figure 1 The first write scan driver (or write stage) described. Figure 6 An example configuration of each of the first to fourth gate drivers GDV1 to GDV4 is described.

[0096] The first gate driver GDV1 is disposed in a vertical portion of the first peripheral area PPA1 and may be coupled (e.g., connected) to the first pixel PXL1. For example, the first gate driver GDV1 may be disposed on a left vertical portion of the first peripheral area PPA1 disposed at the left side of the first pixel area PXA1. The first gate driver GDV1 may extend in the second direction DR2.

[0097] The second gate driver GDV2 may be disposed on a vertical portion of the second peripheral area PPA2 and may be coupled (e.g., connected) to the second pixel PXL2. For example, the second gate driver GDV2 may be disposed on a left vertical portion of the second peripheral area PPA2 disposed at the left side of the second pixel area PXA2. The second gate driver GDV2 may extend in the second direction DR2.

[0098] The third gate driver GDV3 may be disposed on a vertical portion of the third peripheral area PPA3 and may be coupled (e.g., connected) to the third pixel PXL3. For example, the third gate driver GDV3 may be disposed on a left vertical portion of the third peripheral area PPA3 disposed at the left side of the third pixel area PXA3. For example, the third gate driver GDV3 may be disposed on the third peripheral area PPA3 between the second pixel area PXA2 and the third pixel area PXA3. The third gate driver GDV3 may extend in the second direction DR2.

[0099] The fourth gate driver GDV4 may be disposed on the vertical portion of the first peripheral area PPA1 and the vertical portion of the second peripheral area PPA2, and may be coupled (e.g., connected) to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. For example, the fourth gate driver GDV4 may be coupled (e.g., connected) to the third pixel PXL3 via a connection line disposed on the additional peripheral area APA between the second pixel area PXA2 and the third pixel area PXA3. Figure 6 A connection structure between the fourth gate driver GDV4 and the third pixel PXL3 is described.

[0100] For example, the fourth gate driver GDV4 may be disposed on a left vertical portion of the first peripheral area PPA1 disposed at the left side of the first pixel area PXA1. For example, the fourth gate driver GDV4 may be disposed on a left vertical portion of the second peripheral area PPA2 disposed at the left side of the second pixel area PXA2. The fourth gate driver GDV4 may extend in the second direction DR2.

[0101] The second scan driver SDV2 may include a fifth gate driver GDV5 , a sixth gate driver GDV6 , a seventh gate driver GDV7 , and an eighth gate driver GDV8 .

[0102] The fifth gate driver GDV5 may include a reference Figure 1 Each of the sixth gate driver GDV6, the seventh gate driver GDV7, and the eighth gate driver GDV8 may include a reference Figure 1 The initialization scanning driver (or initialization stage) and the light emission scanning driver (or light emission stage) described above will be referred to later. Fig. 9 An example configuration of each of the fifth to eighth gate drivers GDV5 to GDV8 is described.

[0103] The fifth gate driver GDV5 may be disposed on a vertical portion of the first peripheral area PPA1 and a vertical portion of the third peripheral area PPA3, and may be coupled (e.g., connected) to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. For example, the fifth gate driver GDV5 may be coupled (e.g., connected) to the second pixel PXL2 via a connection line disposed on an additional peripheral area APA between the second pixel area PXA2 and the third pixel area PXA3. For example, the fifth gate driver GDV5 may be disposed on a right vertical portion of the first peripheral area PPA1 disposed at the right side of the first pixel area PXA1. For example, the fifth gate driver GDV5 may be disposed on a right vertical portion of the third peripheral area PPA3 disposed at the right side of the third pixel area PXA3. The fifth gate driver GDV5 may extend in the second direction DR2.

[0104] The sixth gate driver GDV6 may be disposed on a vertical portion of the first peripheral area PPA1 and may be coupled (e.g., connected) to the first pixel PXL1. For example, the sixth gate driver GDV6 may be disposed on a right vertical portion of the first peripheral area PPA1 disposed at the right side of the first pixel area PXA1. The sixth gate driver GDV6 may extend in the second direction DR2.

[0105] The seventh gate driver GDV7 may be disposed on a vertical portion of the third peripheral area PPA3 and may be coupled (e.g., connected) to the third pixel PXL3. For example, the seventh gate driver GDV7 may be disposed on a right vertical portion of the third peripheral area PPA3 disposed at the right side of the third pixel area PXA3. The seventh gate driver GDV7 may extend in the second direction DR2.

[0106] The eighth gate driver GDV8 is disposed on a vertical portion of the second peripheral area PPA2 and may be coupled (e.g., connected) to the second pixel PXL2. For example, the eighth gate driver GDV8 may be disposed on a right vertical portion of the second peripheral area PPA2 disposed at the right side of the second pixel area PXA2. For example, the eighth gate driver GDV8 may be disposed on the second peripheral area PPA2 between the second pixel area PXA2 and the third pixel area PXA3. The eighth gate driver GDV8 may extend in the second direction DR2.

[0107] In an exemplary embodiment, each of the first scan driver SDV1 and the second scan driver SDV2 may be directly mounted on the substrate SUB. When the first scan driver SDV1 and the second scan driver SDV2 are directly mounted on the substrate SUB, they may be formed together in the process of forming the pixel PXL. However, the location or method of setting is not limited thereto. For example, the first scan driver SDV1 and the second scan driver SDV2 may be formed on a plurality of separate chips and be disposed on the substrate SUB in the form of a chip on glass, or may be mounted on a printed circuit board and coupled (e.g., connected) to the substrate SUB by a connecting member.

[0108] The data driver DDV may be disposed on the first peripheral area PPA1. The data driver DDV may be disposed on a horizontal portion of the first peripheral area PPA1. The data driver DDV may extend in a width direction (eg, first direction DR1) of the first peripheral area PPA1.

[0109] Timing controller TC (refer to Figure 1 ) can be coupled (e.g., connected) to the first scan driver SDV1, the second scan driver SDV2, and the data driver DDV by wires (or wirings) in various suitable ways, and its position is not particularly limited. For example, the timing controller TC can be mounted on a printed circuit board and can be coupled (e.g., connected) to the first scan driver SDV1, the second scan driver SDV2, and the data driver DDV by a flexible printed circuit board, and the printed circuit board can be set at various suitable positions (such as, one side or back side of the substrate SUB).

[0110] The power supply unit may include at least one power line VDD and VSS. For example, the power supply unit may include a first power line VDD and a second power line VSS. The first power line VDD and the second power line VSS may supply power to the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0111] One of the first power line VDD and the second power line VSS (e.g., the first power line VDD) may be disposed corresponding to one side of the first pixel area PXA1. For example, the first power line VDD may be disposed on an area where the data driver DDV of the first peripheral area PPA1 is disposed. In addition, the first power line VDD may extend in a width direction of the first pixel area PXA1.

[0112] The other of the first power line VDD and the second power line VSS (e.g., the second power line VSS) may be disposed to surround (e.g., partially surround) the first pixel area PXA1 (except for an area of ​​the first pixel area PXA1 where the data driver DDV on the first peripheral area PPA1 is disposed), the second pixel area PXA2, and the third pixel area PXA3. For example, the second power line VSS may have a shape extending along the left vertical portion of the first peripheral area PPA1, the second peripheral area PPA2, the third peripheral area PPA3, the additional peripheral area APA, and the right vertical portion of the first peripheral area PPA1.

[0113] exist Figure 2 , an example embodiment is described in which the first power line VDD is disposed on a peripheral area of ​​the first peripheral area PPA1 corresponding to one side of the first pixel area PXA1, and the second power line VSS is disposed on the remaining peripheral area, but is not limited thereto. For example, the first power line VDD and the second power line VSS may be disposed to surround the first pixel area PXA1, the second pixel area PXA2, and the third pixel area PXA3.

[0114] A voltage applied to the first power line VDD may be higher than a voltage applied to the second power line VSS.

[0115] As reference Figure 2 As described, the third gate driver GDV3 (i.e., the third gate driver GDV3 including the compensation stage and the bypass stage and coupled (e.g., connected) to the third pixel PXL3) may be disposed on the third peripheral area PPA3 between the second pixel area PXA2 and the third pixel area PXA3. In addition, the eighth gate driver GDV8 (i.e., the eighth gate driver GDV8 including the initialization stage and the light emission stage and coupled (e.g., connected) to the second pixel PXL2) may be disposed on the second peripheral area PPA2 between the second pixel area PXA2 and the third pixel area PXA3.

[0116] Therefore, the line (eg, referring to FIG. 1 ) for transmitting the compensation scan signal and the bypass scan signal from the second pixel area PXA2 to the third pixel area PXA3 via the additional peripheral area APA may be removed. Figure 1 Some of the compensation scan lines GCL1 to GCLn and portions of the bypass scan lines GBL1 to GBLn passing through the additional peripheral area APA described above). In addition, a line for transmitting the initialization scan signal and the light emission scan signal from the third pixel area PXA3 to the second pixel area PXA2 via the additional peripheral area APA (e.g., referring to Figure 1Some of the initialization scan lines GIL1 to GILn and portions of the light emission scan lines EML1 to EMLn that pass through the additional peripheral area APA are described.

[0117] For example, the number of lines extending in the first direction DR1 between the second pixel area PXA2 and the third pixel area PXA3 may be reduced. Therefore, in the additional peripheral area APA having a width (or length) defined in the second direction DR2, a space in which other components may be disposed may be ensured in response to the reduced number of lines. In this space, a load matching capacitor may be disposed to compensate for the reference Figure 1 The load matching capacitor may have a larger capacitance than some of the write scan lines GWL1 to GWLn described above (e.g., the write scan lines coupled (e.g., connected) to the first pixel PXL1 and the second pixel PXL2 via the additional peripheral area APA), and thus, the load matching capacitor may have a larger capacitance. Therefore, the load difference between the write scan lines GWL1 to GWLn may be more fully compensated.

[0118] In addition, the lines extending in the first direction DR1 between the second pixel region PXA2 and the third pixel region PXA3 may not overlap each other and may be arranged to be spaced apart from each other by a sufficient distance (i.e., a distance in the second direction DR2) to reduce the influence of interference between adjacent lines and the possibility of defects (e.g., short circuits). For example, in some embodiments, the lines extending in the first direction DR1 between the second pixel region PXA2 and the third pixel region PXA3 do not overlap each other in a plan view, but are sufficiently spaced apart from each other in a plan view (e.g., spaced apart from each other in the second direction DR2) to reduce the influence of interference between the lines and also reduce the occurrence of defects.

[0119] At the same time, Figure 2 , the second gate driver GDV2 is described as being separated from the first gate driver GDV1 (e.g., spaced apart in a plan view, for example, along the second direction DR2), and the seventh gate driver GDV7 is described as being separated from the sixth gate driver GDV6 (e.g., spaced apart in a plan view, for example, along the second direction DR2), but the present disclosure is not limited thereto. For example, the second gate driver GDV2 and the first gate driver GDV1 may be implemented as one gate driver or integrated circuit, and / or the seventh gate driver GDV7 and the sixth gate driver GDV6 may also be implemented as one gate driver or integrated circuit.

[0120] Figure 3 It is shown Figure 1 A circuit diagram of an exemplary embodiment of a pixel included in a display device of FIG. Figure 1 The pixels shown in (and Figure 2The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 shown in FIG. 1 may be substantially the same or similar, so the pixel PXLnm will be described as a representative pixel.

[0121] Reference Figure 3 , the pixel PXLnm may include first to eighth transistors T1 to T8, a storage capacitor Cst, and a light emitting diode LD (or a light emitting element).

[0122] A first electrode of the first transistor T1 may be coupled (e.g., connected) to the second node N2, a second electrode of the first transistor T1 may be coupled (e.g., connected) to the third node N3, and a gate electrode of the first transistor T1 may be coupled (e.g., connected) to the first node N1. The first transistor T1 may be referred to as a driving transistor.

[0123] The first electrode of the second transistor T2 may be coupled (e.g., connected) to the data line DLm, the second electrode of the second transistor T2 may be coupled (e.g., connected) to the first electrode of the first transistor T1 (and / or the second node N2), and the gate electrode of the second transistor T2 may be coupled (e.g., connected) to the write scan line GWLn. In some embodiments, the second electrode of the second transistor T2 may be coupled (e.g., connected) to the second node N2 and the first electrode of the first transistor T1 (e.g., the second electrode of the second transistor T2 may be coupled (e.g., connected) to the first electrode of the first transistor T1 through the second node N2). The second transistor T2 may be referred to as a switching transistor.

[0124] A first electrode of the third transistor T3 may be coupled (e.g., connected) to the gate electrode of the first transistor T1 (and / or the first node N1), a second electrode of the third transistor T3 may be coupled (e.g., connected) to the second electrode of the first transistor T1 (and / or the third node N3), and a gate electrode of the third transistor T3 may be coupled (e.g., connected) to the compensation scan line GCLn. The third transistor T3 may be referred to as a compensation transistor.

[0125] A first electrode of the fourth transistor T4 may be coupled (e.g., connected) to the gate electrode of the first transistor T1 (and / or the first node N1), a second electrode of the fourth transistor T4 may be coupled (e.g., connected) to the first initialization line VINTL1, and a gate electrode of the fourth transistor T4 may be coupled (e.g., connected) to the initialization scan line GILn. The fourth transistor T4 may be referred to as an initialization transistor.

[0126] A first electrode of the fifth transistor T5 may be coupled (e.g., connected) to the first power line VDD, a second electrode of the fifth transistor T5 may be coupled (e.g., connected) to the first electrode of the first transistor T1 (and / or the second node N2), and a gate electrode of the fifth transistor T5 may be coupled (e.g., connected) to the light emission scanning line EMLn. The fifth transistor T5 may be referred to as a first light emitting transistor.

[0127] The first electrode of the sixth transistor T6 may be coupled (e.g., connected) to the second electrode (and / or the third node N3) of the first transistor T1, the second electrode of the sixth transistor T6 may be coupled (e.g., connected) to the anode (or anode electrode) of the light emitting diode LD, and the gate electrode of the sixth transistor T6 may be coupled (e.g., connected) to the light emission scanning line EMLn. The sixth transistor T6 may be referred to as a second light emitting transistor.

[0128] A first electrode of the seventh transistor T7 may be coupled (e.g., connected) to the anode of the light emitting diode LD, a second electrode of the seventh transistor T7 may be coupled (e.g., connected) to the second initialization line VINTL2, and a gate electrode of the seventh transistor T7 may be coupled (e.g., connected) to the bypass scan line GBLn. The seventh transistor T7 may be referred to as a second bypass transistor.

[0129] A first electrode of the eighth transistor T8 may be coupled (e.g., connected) to the third power line HVDD, a second electrode of the eighth transistor T8 may be coupled (e.g., connected) to the first electrode of the first transistor T1 (and / or the second node N2), and a gate electrode of the eighth transistor T8 may be coupled (e.g., connected) to the bypass scan line GBLn. The eighth transistor T8 may be referred to as a first bypass transistor.

[0130] The storage capacitor Cst may be formed and / or coupled (e.g., connected) between the first power line VDD and the gate electrode of the first transistor T1 (and / or the first node N1). For example, a first electrode of the storage capacitor Cst may be coupled (e.g., connected) to the first power line VDD, and a second electrode of the storage capacitor Cst may be coupled (e.g., connected) to the gate electrode of the first transistor T1.

[0131] The anode of the light emitting diode LD may be coupled (e.g., connected) to the second electrode of the sixth transistor T6, and the cathode (or cathode electrode) of the light emitting diode LD may be coupled (e.g., connected) to the second power supply line VSS. The light emitting diode LD may be composed of an organic light emitting diode or an inorganic light emitting diode (such as a micro light emitting diode (LED) or a quantum dot light emitting diode). In addition, the light emitting diode LD may be a light emitting element made of a combination of an organic material and an inorganic material (e.g., a composite material including an organic material and an inorganic material). Figure 3, the pixel PXLnm is shown as including a single light emitting diode LD, but is not limited thereto. For example, in another example embodiment, the pixel PXLnm may include a plurality of light emitting diodes, and the plurality of light emitting diodes may be connected in series, in parallel, or in series-parallel combination (eg, connected) with each other.

[0132] The voltage applied to the first power line VDD and the third power line HVDD may be set greater than the voltage applied to the first initialization line VINTL1, the second initialization line VINTL2, and the second power line VSS. The voltage applied to the third power line HVDD may be set greater than the voltage applied to the first power line VDD.

[0133] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be P-type transistors (e.g., P-type transistors). The channels of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be made of polysilicon. The polysilicon transistor may be a low temperature polysilicon (LTPS) transistor. The polysilicon transistor has high electron mobility and fast driving characteristics.

[0134] The third transistor T3 and the fourth transistor T4 may be N-type transistors (e.g., N-type transistors). In this case, the channels of the third transistor T3 and the fourth transistor T4 may be made of oxide semiconductors. The oxide semiconductor transistor may have an electron mobility lower than that of a polysilicon transistor. Therefore, the amount of leakage current generated in the off state of the oxide semiconductor transistor is less than the amount of leakage current of the polysilicon transistor.

[0135] Figure 4 Is a description Figure 3 Waveform diagram of the pixel operation.

[0136] Reference Figure 1 , Figure 3 and Figure 4 , Figure 1 The display device DD may display one image frame in a frame period. The image frame may sequentially include a data writing period WP and a light emitting period EP.

[0137] At the first time point t1a, the light emission scan signal EMn of the off level (or logic high level) may be supplied to the light emission scan line EMLn. In this case, the fifth transistor T5 and the sixth transistor T6 may be turned off, and the driving current flowing from the first power line VDD to the second power line VSS may be turned off.

[0138] At the second time point t2a, the bypass scan signal GBn of the conduction level (or logic low level) may be supplied to the bypass scan line GBLn. In this case, the seventh transistor T7 and the eighth transistor T8 may be turned on. The initialization voltage of the second initialization line VINTL2 may be applied to the anode of the light emitting diode LD by the seventh transistor T7 that is turned on, and the voltage of the anode of the light emitting diode LD may be initialized. In addition, the power supply voltage of the third power line HVDD may be applied to the first electrode (and / or the second node N2) of the first transistor T1 by the eighth transistor T8 that is turned on. Due to the voltage difference between the gate electrode and the first electrode of the first transistor T1, the first transistor T1 may be biased on. Therefore, the hysteresis phenomenon of the grayscale (or data voltage) depending on the previous frame period may be prevented or reduced. For example, because the power supply voltage of the third power line HVDD is used instead of the data voltage of the previous horizontal period as the bias on voltage of the first transistor T1, the first transistor T1 may be biased on in all frame periods.

[0139] At the third time point t3a, the initialization scan signal GIn of the on level (or logic high level) may be supplied to the initialization scan line GILn. In this case, the fourth transistor T4 may be turned on, the initialization voltage of the first initialization line VINTL1 may be applied to the gate electrode (and / or the first node N1) of the first transistor T1, and the voltage of the gate electrode of the first transistor T1 may be initialized.

[0140] At the fourth time point t4a, the compensation scan signal GCn of the on level (or logic high level) may be supplied to the compensation scan line GCLn. Thus, the third transistor T3 may be turned on, and the first transistor T1 may be coupled (eg, connected) in a diode form.

[0141] At the fifth time point t5a, a write scan signal GWn of the on level may be supplied to the write scan line GWLn. In this case, the second transistor T2 may be turned on. The data voltage corresponding to the pixel PXLnm may be applied to the data line DLm. The data voltage may be applied to the gate electrode (and / or the first node N1) of the first transistor T1 by sequentially passing through the second transistor T2, the first transistor T1, and the third transistor T3. Here, the voltage applied to the gate electrode of the first transistor T1 may correspond to the difference between the data voltage and the threshold voltage of the first transistor T1. The amount of current corresponding to the difference between the data voltage and the threshold voltage of the first transistor T1 may be accumulated in the storage capacitor Cst.

[0142] Thereafter, even if the write scan signal GWn of the cut-off level (or logic high level) is supplied, the first electrode of the first transistor T1 can maintain the data voltage through the parasitic capacitance. Therefore, the threshold voltage of the first transistor T1 can be compensated from the fifth time point t5a to the sixth time point t6a. At the sixth time point t6a, the compensation scan signal GCn at the cut-off level (or logic low level) can be supplied to the compensation scan line GCLn.

[0143] At the seventh time point t7a, a bypass scan signal GBn of a conduction level (or a logic low level) may be supplied to the bypass scan line GBLn. In this case, the seventh transistor T7 and the eighth transistor T8 may be turned on. The initialization voltage of the second initialization line VINTL2 may be applied to the anode of the light emitting diode LD through the turned-on seventh transistor T7, and the voltage of the anode of the light emitting diode LD may be initialized again. In addition, the power supply voltage of the third power supply line HVDD may be applied to the first electrode of the first transistor T1 through the turned-on eighth transistor T8, and the first transistor T1 may be biased and turned on by the voltage difference between the gate electrode and the first electrode of the first transistor T1. According to an example embodiment, the bypass scan signal GBn of the conduction level may be supplied only at one time point between the second time point t2a and the seventh time point t7a.

[0144] At the eighth time point t8a, the light emission scan signal EMn of the on level (or logic low level) may be supplied to the light emission scan line EMLn. In this case, the fifth transistor T5 and the sixth transistor T6 may be turned on, the driving current may flow from the first power line VDD to the second power line VSS, and the light emitting diode LD may emit light having a brightness corresponding to the driving current during the light emission period EP after the eighth time point t8a.

[0145] Figure 5 It is shown Figure 2 FIG. 1 is a diagram of an example embodiment of a display device.

[0146] Reference Figure 2 and Figure 5 , the bypass scan line GBL_1 (or the first bypass scan line), the compensation scan line GCL_1 (or the first compensation scan line), the initialization scan line GIL_1 (or the first initialization scan line), the light emission scan line EML_1 (or the first light emission scan line), and the write scan line GWL_1 (or the first write scan line) may be disposed on the first pixel region PXA1. Each of the bypass scan line GBL_1, the compensation scan line GCL_1, the initialization scan line GIL_1, the light emission scan line EML_1, and the write scan line GWL_1 in the first pixel region PXA1 may extend in the first direction DR1.

[0147] The first gate driver GDV1 may be coupled (e.g., connected) to the first pixel PXL1 through the bypass scan line GBL_1 and the compensation scan line GCL_1 in the first pixel area PXA1. The sixth gate driver GDV6 may be coupled (e.g., connected) to the first pixel PXL1 through the initialization scan line GIL_1 and the light emission scan line EML_1 in the first pixel area PXA1. The fourth gate driver GDV4 and the fifth gate driver GDV5 may be coupled (e.g., connected) to the write scan line GWL_1 in the first pixel area PXA1, and may be coupled (e.g., connected) to the first pixel PXL1 through the write scan line GWL_1 in the first pixel area PXA1.

[0148] The bypass scan line GBL_2 (or the second bypass scan line), the compensation scan line GCL_2 (or the second compensation scan line), the initialization scan line GIL_2 (or the second initialization scan line), the light emission scan line EML_2 (or the second light emission scan line), and the write scan line GWL_2 (or the second write scan line) may be disposed on the second pixel region PXA2. Each of the bypass scan line GBL_2, the compensation scan line GCL_2, the initialization scan line GIL_2, the light emission scan line EML_2, and the write scan line GWL_2 in the second pixel region PXA2 may extend in the first direction DR1.

[0149] The second gate driver GDV2 may be coupled (e.g., connected) to the bypass scan line GBL_2 and the compensation scan line GCL_2 in the second pixel area PXA2. In addition, the second gate driver GDV2 may be coupled (e.g., connected) to the second pixel PXL2 through the bypass scan line GBL_2 and the compensation scan line GCL_2 in the second pixel area PXA2. The eighth gate driver GDV8 may be coupled (e.g., connected) to the initialization scan line GIL_2 and the light emission scan line EML_2 in the second pixel area PXA2. In addition, the eighth gate driver GDV8 may be coupled (e.g., connected) to the second pixel PXL2 through the initialization scan line GIL_2 and the light emission scan line EML_2 in the second pixel area PXA2. The fourth gate driver GDV4 and the fifth gate driver GDV5 may be coupled (e.g., connected) to the write scan line GWL_2 in the second pixel area PXA2. In addition, the fourth gate driver GDV4 and the fifth gate driver GDV5 may be coupled (eg, connected) to the second pixel PXL2 through the write scan line GWL_2 in the second pixel area PXA2.

[0150] The bypass scan line GBL_3 (or the third bypass scan line), the compensation scan line GCL_3 (or the third compensation scan line), the initialization scan line GIL_3 (or the third initialization scan line), the light emission scan line EML_3 (or the third light emission scan line), and the write scan line GWL_3 (or the third write scan line) may be disposed on the third pixel area PXA3. Each of the bypass scan line GBL_3, the compensation scan line GCL_3, the initialization scan line GIL_3, the light emission scan line EML_3, and the write scan line GWL_3 in the third pixel area PXA3 may extend in the first direction DR1. In addition, the bypass scan line GBL_3, the compensation scan line GCL_3, the initialization scan line GIL_3, and the light emission scan line EML_3 in the third pixel area PXA3 may be spaced or separated from the bypass scan line GBL_2, the compensation scan line GCL_2, the initialization scan line GIL_2, and the light emission scan line EML_2 in the second pixel area PXA2, with an additional peripheral area APA therebetween. For example, the bypass scan line GBL_2, the compensation scan line GCL_2, the initialization scan line GIL_2, and the light emission scan line EML_2 may be only in the second pixel area PXA2, and the bypass scan line GBL_3, the compensation scan line GCL_3, the initialization scan line GIL_3, and the light emission scan line EML_3 may be only in the third pixel area PXA3. The write scan line GWL_3 in the third pixel area PXA3 may be coupled (e.g., connected) to the write scan line GWL_2 in the second pixel area PXA2 by a connection line CL provided on the additional peripheral area APA. The write scan line GWL_3 in the third pixel region PXA3 may be formed integrally with the connection line CL and the write scan line GWL_2 in the second pixel region PXA2. For example, in some embodiments, the write scan line GWL_3, the connection line CL, and the write scan line GWL_2 may be a single integrated line (eg, wiring).

[0151] The third gate driver GDV3 may be coupled (e.g., connected) to the bypass scan line GBL_3 and the compensation scan line GCL_3 in the third pixel area PXA3, and may be coupled (e.g., connected) to the third pixel PXL3 through the bypass scan line GBL_3 and the compensation scan line GCL_3 in the third pixel area PXA3. The seventh gate driver GDV7 may be coupled (e.g., connected) to the initialization scan line GIL_3 and the light emission scan line EML_3 in the third pixel area PXA3, and may be coupled (e.g., connected) to the third pixel PXL3 through the initialization scan line GIL_3 and the light emission scan line EML_3 in the third pixel area PXA3. The fourth gate driver GDV4 and the fifth gate driver GDV5 may be coupled (e.g., connected) to the write scan line GWL_3 in the third pixel area PXA3, and may be coupled (e.g., connected) to the third pixel PXL3 through the write scan line GWL_3 in the third pixel area PXA3.

[0152] The second gate driver GDV2 and the third gate driver GDV3 may be coupled (e.g., connected) to the first control signal line CSL1. The first control signal line CSL1 may extend from the second peripheral area PPA2 to the third peripheral area PPA3 via the additional peripheral area APA, and a clock signal and a start signal (e.g., a bypass start signal, a compensation start signal) may be applied to the first control signal line CSL1. In this case, the second gate driver GDV2 and the third gate driver GDV3 may generate a bypass scan signal and a compensation scan signal having the same waveform and the same phase using the same clock signal and the same start signal, respectively.

[0153] Similarly, the seventh gate driver GDV7 and the eighth gate driver GDV8 may be coupled (e.g., connected) to the second control signal line CSL2. The second control signal line CSL2 may extend from the third peripheral area PPA3 to the second peripheral area PPA2 via the additional peripheral area APA, and a clock signal and a start signal (e.g., an initialization start signal, a light emission stop signal) may be applied to the second control signal line CSL2. In this case, the seventh gate driver GDV7 and the eighth gate driver GDV8 may generate an initialization scan signal and a light emission scan signal having the same waveform and the same phase using the same clock signal and the same start signal, respectively.

[0154] Figure 6 It is shown Figure 5 FIG. 1 is a diagram of an example embodiment of a display device. Figure 6 In the embodiment, based on the first gate driver GDV1, the second gate driver GDV2, the third gate driver GDV3 and the fourth gate driver GDV4 (ie, the first scanning driver SDV1 (refer to Figure 1 )) briefly shows (eg, partially shows) a part of the display device DD.

[0155] Reference Figure 5 and Figure 6 , the second gate driver GDV2 may include bypass stages STB1_2, STB2_2, STB3_2 and STB4_2.

[0156] The bypass stages STB1_2, STB2_2, STB3_2, and STB4_2 may be coupled (e.g., connected) to the bypass clock signal lines GB_CLK1 and GB_CLK2, respectively, and may be coupled (e.g., connected) to the bypass scan lines GBL1_2, GBL2_2, GBL3_2, and GBL4_2, respectively. For example, each of the bypass stages STB1_2, STB2_2, STB3_2, and STB4_2 may be coupled (e.g., connected) to both the bypass clock signal lines GB_CLK1 and GB_CLK2.

[0157] The bypass clock signal lines GB_CLK1 and GB_CLK2 and the bypass start signal line GB_FLM which will be described later may be included in the reference Figure 5 The bypass clock signal may be applied to the bypass clock signal lines GB_CLK1 and GB_CLK2, and the bypass clock signals may have mutually inverted phases (e.g., phases offset by 180 degrees from each other). The bypass start signal (or the first bypass start signal, the first start pulse) may be applied to the bypass start signal line GB_FLM.

[0158] Each of the bypass stages STB1_2, STB2_2, STB3_2 and STB4_2 can receive a bypass start signal or a bypass scan signal (or a bypass carry signal) of a previous bypass stage, and can use the bypass clock signal to generate a bypass scan signal corresponding to (for example, according to, based on, etc.) the bypass start signal or the bypass scan signal of the previous bypass stage (i.e., the previous bypass scan signal).

[0159] For example, the first bypass stage STB1_2 may receive a bypass start signal through (e.g., from) the bypass start signal line GB_FLM, may generate a first bypass scan signal corresponding to the bypass start signal using the bypass clock signal, and may provide the first bypass scan signal to the first bypass scan line GBL1_2 in the second pixel area PXA2. For example, the first bypass stage STB1_2 may output a clock signal (e.g., a pulse of an on-level) as the first bypass scan signal in response to the bypass start signal. The first bypass scan signal may be provided to the 11th pixel PXL11_2 in the second pixel area PXA2.

[0160] The second bypass stage STB2_2 may receive the first bypass scan signal from the first bypass stage STB1_2, and may generate a second bypass scan signal corresponding to the first bypass scan signal to provide it to the second bypass scan line GBL2_2 in the second pixel area PXA2. Similarly, the third bypass stage STB3_2 may generate a third bypass scan signal corresponding to the second bypass scan signal to provide it to the third bypass scan line GBL3_2 in the second pixel area PXA2, and the fourth bypass stage STB4_2 may generate a fourth bypass scan signal corresponding to the third bypass scan signal to provide it to the fourth bypass scan line GBL4_2 in the second pixel area PXA2.

[0161] For example, the bypass stages STB1_2, STB2_2, STB3_2, and STB4_2 may sequentially provide the bypass scan signals to the bypass scan lines GBL1_2, GBL2_2, GBL3_2, and GBL4_2.

[0162] In addition, the second gate driver GDV2 may include compensation stages STC1_2, STC2_2, STC3_2, and STC4_2. The compensation stages STC1_2, STC2_2, STC3_2, and STC4_2 may be arranged to be adjacent to (e.g., close to) the second pixel region PXA2 than the bypass stages STB1_2, STB2_2, STB3_2, and STB4_2, but are not limited thereto. For example, in a plan view, the compensation stages STC1_2, STC2_2, STC3_2, and STC4_2 may be between the second pixel region PXA2 and the bypass stages STB1_2, STB2_2, STB3_2, and STB4_2.

[0163] The compensation stages STC1_2, STC2_2, STC3_2, and STC4_2 may be coupled (e.g., connected) to the compensation clock signal lines GC_CLK1 and GC_CLK2, and may be coupled (e.g., connected) to the compensation scan lines GCL1_2, GCL2_2, GCL3_2, and GCL4_2 in the second pixel area PXA2, respectively. For example, each of the compensation stages STC1_2, STC2_2, STC3_2, and STC4_2 may be coupled (e.g., connected) to both the compensation clock signal lines GC_CLK1 and GC_CLK2.

[0164] The compensation clock signal lines GC_CLK1 and GC_CLK2 and the compensation start signal line GC_FLM, which will be described later, may be included in the reference Figure 5 The first control signal line CSL1 described above may be extended from the second peripheral area PPA2 to the third peripheral area PPA3 via the additional peripheral area APA. The compensation clock signal may be applied to the compensation clock signal lines GC_CLK1 and GC_CLK2, and the compensation clock signals may have mutually inverted phases (e.g., phases offset by 180 degrees from each other). The compensation start signal (or the second start pulse) may be applied to the compensation start signal line GC_FLM.

[0165] Each of the compensation stages STC1_2, STC2_2, STC3_2 and STC4_2 can receive a compensation start signal or a compensation scan signal (or a compensation carry signal) of a previous compensation stage, and can use a compensation clock signal to generate a compensation scan signal corresponding to the compensation start signal or the compensation scan signal of the previous compensation stage (i.e., the previous compensation scan signal).

[0166] For example, the first compensation stage STC1_2 may receive a compensation start signal through the compensation start signal line GC_FLM, may generate a first compensation scan signal corresponding to the compensation start signal using the compensation clock signal, and may provide the first compensation scan signal to the first compensation scan line GCL1_2 in the second pixel area PXA2.

[0167] The second compensation stage STC2_2 may receive the first compensation scan signal from the first compensation stage STC1_2, and may generate a second compensation scan signal corresponding to the first compensation scan signal to provide it to the second compensation scan line GCL2_2 in the second pixel area PXA2. Similarly, the third compensation stage STC3_2 may generate a third compensation scan signal corresponding to the second compensation scan signal to provide it to the third compensation scan line GCL3_2 in the second pixel area PXA2, and the fourth compensation stage STC4_2 may generate a fourth compensation scan signal corresponding to the third compensation scan signal to provide it to the fourth compensation scan line GCL4_2 in the second pixel area PXA2.

[0168] For example, the compensation stages STC1_2, STC2_2, STC3_2, and STC4_2 may sequentially provide the compensation scan signals to the compensation scan lines GCL1_2, GCL2_2, GCL3_2, and GCL4_2.

[0169] Meanwhile, the first gate driver GDV1 may include bypass stages STB(k+1)_1 and STB(k+2)_1. Here, k may be a positive integer, and k may be about 100. However, the present disclosure is not limited thereto, and the integer k may be any suitable integer.

[0170] The bypass stages STB(k+1)_1 and STB(k+2)_1 may be coupled (e.g., connected) to the bypass clock signal lines GB_CLK1 and GB_CLK2, and may be coupled (e.g., connected) to the bypass scan lines GBLk+1 and GBLk+2, respectively. For example, each of the bypass stages STB(k+1)_1 and STB(k+2)_1 may be coupled (e.g., connected) to both the bypass clock signal lines GB_CLK1 and GB_CLK2. Here, the k+1th bypass scan line GBLk+1 may correspond to the reference Figure 5 The bypass scan line GBL_1 is described.

[0171] Each of the bypass stages STB(k+1)_1 and STB(k+2)_1 may receive a bypass scan signal (or a bypass carry signal) of a previous bypass stage, and may generate a bypass scan signal corresponding to the bypass scan signal of the previous bypass stage using a bypass clock signal.

[0172] For example, the k+1th bypass stage STB(k+1)_1 may receive a bypass scan signal (e.g., a kth bypass scan signal) from the last bypass stage of the second gate driver GVD2, may generate a k+1th bypass scan signal using a bypass clock signal, and may provide the k+1th bypass scan signal to the k+1th bypass scan line GBLk+1 in the first pixel area PXA1. The k+1th bypass scan signal may be provided to the (k+1)1th pixel PXL(k+1)1_1 in the first pixel area PXA1.

[0173] The k+1th bypass stage STB(k+1)_1 is described as receiving a bypass scan signal (e.g., a kth bypass scan signal) from the last bypass stage of the second gate driver GVD2, but is not limited thereto. For example, similar to the first bypass stage STB1_2 of the second gate driver GDV2, the k+1th bypass stage STB(k+1)_1 may receive a separate bypass start signal (e.g., a second bypass start signal), and may generate a k+1th bypass scan signal corresponding to the separate bypass start signal.

[0174] Similarly, the k+2th bypass stage STB(k+2)_1 can receive the k+1th bypass scan signal from the k+1th bypass stage STB(k+1)_1, and can generate a k+2th bypass scan signal corresponding to the k+1th bypass scan signal to provide it to the k+2th bypass scan line GBLk+2 in the first pixel area PXA1.

[0175] Furthermore, the first gate driver GDV1 may include compensation stages STC(k+1)_1 and STC(k+2)_1.

[0176] The compensation stages STC(k+1)_1 and STC(k+2)_1 may be coupled (e.g., connected) to the compensation clock signal lines GC_CLK1 and GC_CLK2, and may be coupled (e.g., connected) to the compensation scan lines GCLk+1 and GCLk+2, respectively. For example, each of the compensation stages STC(k+1)_1 and STC(k+2)_1 may be coupled (e.g., connected) to both the compensation clock signal lines GC_CLK1 and GC_CLK2, and the compensation stages STC(k+1)_1 and STC(k+2)_1 may be coupled (e.g., connected) to the compensation scan lines GCLk+1 and GCLk+2, respectively. Here, the k+1th compensation scan line GCLk+1 may correspond to the reference Figure 5 Described compensation scan line GCL_1.

[0177] Each of the compensation stages STC(k+1)_1 and STC(k+2)_1 can receive the compensation scan signal (or compensation carry signal) of the previous compensation stage, and can use the compensation clock signal to generate a compensation scan signal corresponding to the compensation scan signal of the previous compensation stage (i.e., the previous compensation scan signal).

[0178] For example, the k+1th compensation stage STC(k+1)_1 may receive a compensation scan signal (e.g., a kth compensation scan signal) from the last compensation stage of the second gate driver GVD2, may generate a k+1th compensation scan signal using the compensation clock signal, and may provide the k+1th compensation scan signal to the k+1th compensation scan line GCLk+1 in the first pixel area PXA1. In an embodiment, similar to the first compensation stage STC1_2 of the second gate driver GDV2, the k+1th compensation stage STC(k+1)_1 may receive a separate compensation start signal (e.g., a second compensation start signal), and may generate a k+1th compensation scan signal corresponding to the separate compensation start signal.

[0179] Similarly, the k+2th compensation stage STC(k+2)_1 can receive the k+1th compensation scan signal from the k+1th compensation stage STC(k+1)_1, and can generate a k+2th compensation scan signal corresponding to the k+1th compensation scan signal to provide it to the k+2th compensation scan line GCLk+2 in the first pixel area PXA1.

[0180] Meanwhile, the third gate driver GDV3 may include bypass stages STB1_3, STB2_3, STB3_3, and STB4_3.

[0181] The bypass stages STB1_3, STB2_3, STB3_3, and STB4_3 may be coupled (e.g., connected) to the bypass clock signal lines GB_CLK1 and GB_CLK2, and may be coupled (e.g., connected) to the bypass scan lines GBL1_3, GBL2_3, GBL3_3, and GBL4_3, respectively. For example, each of the bypass stages STB1_3, STB2_3, STB3_3, and STB4_3 may be coupled (e.g., connected) to both the bypass clock signal lines GB_CLK1 and GB_CLK2.

[0182] Each of the bypass stages STB1_3, STB2_3, STB3_3 and STB4_3 can receive a bypass start signal or a bypass scan signal (or a bypass carry signal) of a previous bypass stage, and can use a bypass clock signal to generate a bypass scan signal corresponding to the bypass start signal or the bypass scan signal of the previous bypass stage (i.e., the previous bypass scan signal).

[0183] For example, the first bypass stage STB1_3 may receive a bypass start signal through the bypass start signal line GB_FLM, may generate a first bypass scan signal corresponding to the bypass start signal using the bypass clock signal, and may provide the first bypass scan signal to the first bypass scan line GBL1_3 in the third pixel area PXA3. The first bypass scan signal may be provided to the 1m-th pixel PXL1m_3 in the third pixel area PXA3.

[0184] At the same time, because each of the first bypass stage STB1_3 of the third gate driver GDV3 and the first bypass stage STB1_2 of the second gate driver GDV2 generates a first bypass scan signal using the same bypass start signal (for example, the bypass start signal received by the bypass start signal line GB_FLM) and the same bypass clock signal (for example, the bypass clock signal received by the bypass clock signal lines GB_CLK1 and GB_CLK2), bypass scan signals of the same waveform can be provided at the same time point in the 11th pixel PXL11_2 in the second pixel area PXA2 and the 1mth pixel PXL1m_3 in the third pixel area PXA3.

[0185] The second bypass stage STB2_3 may receive the first bypass scan signal from the first bypass stage STB1_3, and may generate a second bypass scan signal corresponding to the first bypass scan signal to provide it to the second bypass scan line GBL2_3 in the third pixel area PXA3. Similarly, the third bypass stage STB3_3 may generate a third bypass scan signal corresponding to the second bypass scan signal to provide it to the third bypass scan line GBL3_3 in the third pixel area PXA3, and the fourth bypass stage STB4_3 may generate a fourth bypass scan signal corresponding to the third bypass scan signal to provide it to the fourth bypass scan line GBL4_3 in the third pixel area PXA3.

[0186] For example, the bypass stages STB1_3 , STB2_3 , STB3_3 , and STB4_3 of the third gate driver GDV3 may sequentially provide the bypass scan signals to the bypass scan lines GBL1_3 , GBL2_3 , GBL3_3 , and GBL4_3 in the third pixel area PXA3 , respectively.

[0187] In addition, the third gate driver GDV3 may include compensation stages STC1_3, STC2_3, STC3_3, and STC4_3. The compensation stages STC1_3, STC2_3, STC3_3, and STC4_3 may be arranged to be adjacent to the third pixel region PXA3 than the bypass stages STB1_3, STB2_3, STB3_3, and STB4_3, but are not limited thereto. For example, in some embodiments, the compensation stages STC1_3, STC2_3, STC3_3, and STC4_3 may be between the third pixel region PXA3 and the bypass stages STB1_3, STB2_3, STB3_3, and STB4_3.

[0188] The compensation stages STC1_3, STC2_3, STC3_3, and STC4_3 may be coupled (e.g., connected) to the compensation clock signal lines GC_CLK1 and GC_CLK2, and may be coupled (e.g., connected) to the compensation scan lines GCL1_3, GCL2_3, GCL3_3, and GCL4_3 in the third pixel area PXA3, respectively. For example, each of the compensation stages STC1_3, STC2_3, STC3_3, and STC4_3 may be coupled (e.g., connected) to both the compensation clock signal lines GC_CLK1 and GC_CLK2.

[0189] Each of the compensation stages STC1_3, STC2_3, STC3_3 and STC4_3 can receive a compensation start signal or a compensation scan signal (or a compensation carry signal) of a previous compensation stage, and can use a compensation clock signal to generate a compensation scan signal corresponding to the compensation start signal or the compensation scan signal of the previous compensation stage (i.e., the previous compensation scan signal).

[0190] For example, the first compensation stage STC1_3 may receive a compensation start signal via (e.g., from) the compensation start signal line GC_FLM, may generate a first compensation scan signal corresponding to the compensation start signal using the compensation clock signal, and may provide the first compensation scan signal to the first compensation scan line GCL1_3 in the third pixel area PXA3.

[0191] The second compensation stage STC2_3 may receive the first compensation scan signal from the first compensation stage STC1_3, and may generate a second compensation scan signal corresponding to the first compensation scan signal to provide it to the second compensation scan line GCL2_3 in the third pixel area PXA3. Similarly, the third compensation stage STC3_3 may generate a third compensation scan signal corresponding to the second compensation scan signal to provide it to the third compensation scan line GCL3_3 in the third pixel area PXA3, and the fourth compensation stage STC4_3 may generate a fourth compensation scan signal corresponding to the third compensation scan signal to provide it to the fourth compensation scan line GCL4_3 in the third pixel area PXA3.

[0192] For example, the compensation stages STC1_3 , STC2_3 , STC3_3 , and STC4_3 of the third gate driver GDV3 may sequentially provide compensation scan signals to the compensation scan lines GCL1_3 , GCL2_3 , GCL3_3 , and GCL4_3 in the third pixel area PXA3 .

[0193] Meanwhile, the fourth gate driver GDV4 may include write stages STW1, STW2, STW3, STW4, ..., STW(k+1), and STW(k+2). The write stages STW1, STW2, STW3, STW4, ..., STW(k+1), and STW(k+2) may be respectively disposed to be adjacent to the first pixel region PXA1 and the second pixel region PXA2 than the first gate driver GDV1 and the second gate driver GDV2. For example, the fourth gate driver GDV4 may be between the first pixel region PXA1 and the first gate driver GDV1, and the fourth gate driver GDV4 may be between the second pixel region PXA2 and the second gate driver GDV2. In this case, as Figure 4 As shown in , the RC delay of the write scan signal GWn having a relatively small pulse width can be relatively alleviated.

[0194] The write stages STW1, STW2, STW3, STW4, ..., STW(k+1) and STW(k+2) can be combined (e.g., connected) to corresponding two write clock signal lines among the write clock signal lines S_CLK1, S_CLK2, S_CLK3 and S_CLK4, and can be respectively combined (e.g., connected) to the write scan lines GWL1_2, GWL2_2, GWL3_2, GWL4_2, ..., GWLk+1, GWLk+2. For example, each of the write stages STW1, STW2, STW3, STW4, ..., STW(k+1) and STW(k+2) can be combined (e.g., connected) to two of the write clock signal lines S_CLK1, S_CLK2, S_CLK3 and S_CLK4. Here, the k+1th write scan line GWLk+1 can correspond to the reference Figure 5 Described writing scan line GWL_1.

[0195] In addition, the write stages STW1, STW2, STW3, STW4, ..., STW(k+1), and STW(k+2) coupled (e.g., connected) to the write scan lines GWL1_2, GWL2_2, GWL3_2, and GWL4_2 in the second pixel region PXA2 may be coupled (e.g., connected) to the write scan lines GWL1_3, GWL2_3, GWL3_3, and GWL4_3 in the third pixel region PXA3 through the connection lines CL1, CL2, CL3, and CL4, respectively. Here, the connection lines CL1, CL2, CL3, and CL4 may be included in the reference Figure 5 Described in the connecting line CL.

[0196] The write clock signal lines S_CLK1, S_CLK2, S_CLK3 and S_CLK4 may include a first write clock signal line S_CLK1, a second write clock signal line S_CLK2, a third write clock signal line S_CLK3 and a fourth write clock signal line S_CLK4, and four write clock signals having sequentially delayed phases (for example, sequentially delayed phases of 90 degrees) may be applied to the first write clock signal line S_CLK1, the second write clock signal line S_CLK2, the third write clock signal line S_CLK3 and the fourth write clock signal line S_CLK4, respectively.

[0197] When write stages STW1, STW2, STW3, STW4, ..., STW(k+1) and STW(k+2) utilize four write clock signals, a write scan signal having a relatively small pulse width can be easily generated compared to the case of utilizing two write clock signals. In some cases, considering the pulse width of the write scan signal, the write clock signal line may include two write clock signal lines, or six or more write clock signal lines.

[0198] Each of the write levels STW1, STW2, STW3 and STW4 can receive a write start signal or a write scan signal (or a write carry signal) of a previous write level, and can use a write clock signal to generate a write scan signal corresponding to the write start signal or the write scan signal of the previous write level (i.e., the previous write scan signal).

[0199] For example, the first write stage STW1 may receive a write start signal (or a third start pulse) through the write start signal line S_FLM, may generate a first write scan signal corresponding to the write start signal using the write clock signal, and may provide the first write scan signal to the first write scan line GWL1_2 in the second pixel region PXA2. The first write scan signal may be provided to the 11th pixel PXL11_2 in the second pixel region PXA2. In addition, because the first write scan line GWL1_2 is coupled (e.g., connected) to the first write scan line GWL1_3 in the third pixel region PXA3 through the first connection line CL1, the first write scan signal may be provided to the 1mth pixel PXL1m_3 in the third pixel region PXA3.

[0200] The second write stage STW2 may receive the first write scan signal from the first write stage STW1, and may generate a second write scan signal corresponding to the first write scan signal to provide it to the second write scan line GWL2_2 in the second pixel area PXA2. Because the second write scan line GWL2_2 is coupled (e.g., connected) to the second write scan line GWL2_3 in the third pixel area PXA3 through the second connection line CL2, the second write scan signal may also be provided to the second write scan line GWL2_3 in the third pixel area PXA3.

[0201] Similarly, the third write stage STW3 can generate a third write scan signal corresponding to the second write scan signal to provide it to the third write scan line GWL3_2 in the second pixel area PXA2, and can also provide the third write scan signal to the third write scan line GWL3_3 in the third pixel area PXA3 through the third connection line CL3. The fourth write stage STW4 can generate a fourth write scan signal corresponding to the third write scan signal to provide it to the fourth write scan line GWL4_2 in the second pixel area PXA2, and can also provide the fourth write scan signal to the fourth write scan line GWL4_3 in the third pixel area PXA3 through the fourth connection line CL4.

[0202] In addition, the k+1th write stage STW(k+1) may generate a k+1th write scan signal corresponding to the k+1th write scan signal to provide it to the k+1th write scan line GWLk+1 in the first pixel area PXA1, and the k+1th write scan signal may be provided to the (k+1)1th pixel PXL(k+1)1_1 in the first pixel area PXA1. The k+2th write stage STW(k+2) may generate a k+2th write scan signal corresponding to the k+1th write scan signal to provide it to the k+2th write scan line GWLk+2 in the first pixel area PXA1.

[0203] For example, the write levels STW1, STW2, STW3, STW4, ..., STW(k+1) and STW(k+2) can sequentially provide write scan signals to the write scan lines GWL1_2, GWL2_2, GWL3_2 and GWL4_2 in the second pixel area PXA2 and the write scan lines GWLk+1 and GWLk+2 in the first pixel area PXA1. In addition, the write levels STW1, STW2, STW3, STW4, ..., STW(k+1) and STW(k+2) combined (for example, connected) to the write scan lines GWL1_2, GWL2_2, GWL3_2 and GWL4_2 in the second pixel area PXA2 can sequentially provide write scan signals to the write scan lines GWL1_3, GWL2_3, GWL3_3 and GWL4_3 in the third pixel area PXA3 through the connecting lines CL1, CL2, CL3 and CL4.

[0204] As reference Figure 6As described, the bypass scan signal and the compensation scan signal may be provided to the third pixel area PXA3 through the third gate driver GDV3 disposed in the peripheral area (e.g., the third peripheral area PPA3) between the second pixel area PXA2 and the third pixel area PXA3. Therefore, compared with the case where the second gate driver GDV2 provides the bypass scan signal and the compensation scan signal to the third pixel area PXA3 through separate lines, the number of lines provided for the additional peripheral area APA may be reduced, and a space for a load matching capacitor to be described later may be sufficiently ensured. In addition, the lines (e.g., the connection lines CL1, CL2, CL3, and CL4) disposed on the additional peripheral area APA may not overlap each other (e.g., not overlap in a plan view), and may be spaced apart (e.g., spaced apart in a plan view) by a sufficient distance (or separation distance). Therefore, the phenomenon that the image (or the brightness of the image) displayed in the second pixel area PXA2 and the third pixel area PXA3 is different from the image displayed in the first pixel area PXA1 and defects (for example, interference, disconnection, etc.) occurring in the connecting lines CL1, CL2, CL3 and CL4 can be reduced or prevented.

[0205] In some embodiments, dummy cells (or dummy patterns or load matching capacitors) that are respectively coupled (e.g., connected) to or overlapped with connection lines CL1, CL2, CL3, and CL4 to form parasitic capacitors may be provided in the additional peripheral area APA.

[0206] For reference, the number of pixels coupled (e.g., connected) to the write scan lines GWL1_2, GWL2_2, GWL3_2, and GWL4_2 in the second pixel region PXA2 (and the write scan lines GWL1_3, GWL2_3, GWL3_3, and GWL4_3 in the third pixel region PXA3) may be less than the number of pixels coupled (e.g., connected) to the write scan lines GWLk+1 and GWLk+2 in the first pixel region PXA1. Therefore, the load values ​​of the write scan lines GWL1_2, GWL2_2, GWL3_2, and GWL4_2 in the second pixel region PXA2 (and the write scan lines GWL1_3, GWL2_3, GWL3_3, and GWL4_3 in the third pixel region PXA3) may be less than the load values ​​of the write scan lines GWLk+1 and GWLk+2 in the first pixel region PXA1. Therefore, the display device DD (reference Figure 2) The load values ​​of the write scan lines GWL1_2, GWL2_2, GWL3_2 and GWL4_2 in the second pixel area PXA2 (and the write scan lines GWL1_3, GWL2_3, GWL3_3 and GWL4_3 in the third pixel area PXA3) can be compensated to be the same as or similar to the load values ​​of the write scan lines GWLk+1 and GWLk+2 in the first pixel area PXA1 by using dummy units.

[0207] Figure 7 It is shown Figure 5 FIG. 1 is a diagram of an example embodiment of a display device. Figure 7 In the figure, a portion of the display device may be briefly shown (eg, partially shown) based on the additional peripheral area APA. Figure 8 is shown along Figure 7 A cross-sectional view of an exemplary embodiment of a display device taken along line II'.

[0208] Reference Figure 5 , Figure 6 and Figure 7 , respectively connected to the write scan lines GWL1_2, GWL2_2, GWL3_2 and GWL4_2 in the second pixel area PXA2 (see Figure 6 ) (or the second pixel PXL2) and the write scan lines GWL1_3, GWL2_3, GWL3_3 and GWL4_3 in the third pixel area PXA3 (see Figure 6 ) (or the third pixel PXL3) is combined with (eg, connected to) the connection line CL (or the connection lines CL1, CL2, CL3 and CL4, see Figure 6 ) can be set in the additional peripheral area APA.

[0209] In example embodiments, in the additional peripheral area APA, the dummy cell DPTN (or dummy pattern) may overlap with the connection line CL. According to example embodiments, the dummy cell DPTN may overlap with the connection line CL in the second peripheral area PPA2 and the third peripheral area PPA3. The dummy cell DPTN may be disposed via the second peripheral area PPA2, the third peripheral area PPA3, and the additional peripheral area APA (e.g., may overlap with the second peripheral area PPA2, the third peripheral area PPA3, and the additional peripheral area APA or may be disposed at the second peripheral area PPA2, the third peripheral area PPA3, and the additional peripheral area APA).

[0210] The dummy cell DPTN may be coupled (eg, connected) to the second power line VSS or the first power line VDD (see Figure 2 ), or may be one of the second power supply line VSS or the first power supply line VDD (see Figure 2). For example, the dummy cell DPTN may be the second power line VSS, and the second power voltage may be applied to the dummy cell DPTN.

[0211] The dummy cell DPTN may overlap the connection line CL to form a parasitic capacitor. The parasitic capacitance of the parasitic capacitor may increase the write scan lines GWL1_2, GWL2_2, GWL3_2, and GWL4_2 (see FIG. 1 ) in the second pixel region PXA2 connected to (eg, connected to) the connection line CL. Figure 6 ) and the write scan lines GWL1_3, GWL2_3, GWL3_3 and GWL4_3 in the third pixel area PXA3 (see Figure 6 )) and its load value can be compensated. As a result, the write scan lines GWL1_2, GWL2_2, GWL3_2 and GWL4_2 (see Figure 6 ) and the write scan lines GWL1_3, GWL2_3, GWL3_3 and GWL4_3 in the third pixel area PXA3 (see Figure 6 ) may be the same or similar to the load values ​​of the write scan lines GWLk+1 and GWLk+2 in the first pixel area PXA1. The parasitic capacitance of the parasitic capacitor formed by the dummy unit DPTN may be differently set according to the load value of the scan line to be compensated.

[0212] Reference Figure 8 , the display device DD may include a plurality of insulating layers GI, IL1, and IL2 (or insulating films), a passivation layer PSV, and an encapsulation layer SLM sequentially stacked on a substrate SUB.

[0213] The dummy cell DPTN (or the second power line VSS) may be disposed between the second interlayer insulating layer IL2 and the passivation layer PSV among the insulating layers GI, IL1, and IL2. The connection line CL may be disposed between the insulating layers GI, IL1, and IL2. For example, the connection line CL may be disposed between two insulating layers selected from the insulating layers GI, IL1, and IL2. For example, Figure 8 As shown in FIG. 1 , the connection line CL may be disposed between the first interlayer insulating layer IL1 and the second interlayer insulating layer IL2 .

[0214] In this case, a parasitic capacitor (or a load matching capacitor) may be formed at a portion where the dummy cell DPTN overlaps the connection line CL.

[0215] At the same time, Figure 8, the dummy cell DPTN is shown as being disposed between the second interlayer insulating layer IL2 and the passivation layer PSV, but is not limited thereto. For example, the display device DD may further include a conductive pattern disposed between the gate insulating layer GI and the first interlayer insulating layer IL1 among the insulating layers GI, IL1, and IL2, and the conductive pattern may be coupled (e.g., connected) to the dummy cell DPTN through a separate contact hole, and may be overlapped with the connection line CL to further form a parasitic capacitor. In addition, the portion (or region) overlapped with the connection line CL may be changed according to the shape of the conductive pattern (i.e., the shape on or in the top plan view), and therefore, the parasitic capacitance of the parasitic capacitor may be set differently and appropriately.

[0216] As reference Figure 7 and Figure 8 As described, the display device DD may include a parasitic capacitor formed by overlapping the dummy unit DPTN with the connection line CL in the additional peripheral area APA, and the parasitic capacitor may compensate for the load of the line (eg, write scan line) of the second pixel area PXA2 and the third pixel area PXA3.

[0217] Fig. 9 It is shown Figure 5 FIG. 1 is a diagram of an example embodiment of a display device. Fig. 9 In the embodiment, based on the fifth gate driver GDV5, the sixth gate driver GDV6, the seventh gate driver GDV7 and the eighth gate driver GDV8 (for example, the second scanning driver SDV2 (see Figure 1 )) briefly shows (eg, partially shows) a part of the display device DD.

[0218] Reference Figure 5 and Fig. 9 , the fifth gate driver GDV5 may include write stages STW1, STW2, STW3, STW4, ..., STW(k+1) and STW(k+2). Because the write stages STW1, STW2, STW3, STW4, ..., STW(k+1) and STW(k+2) are similar to the reference Figure 6 The write stages STW1, STW2, STW3, STW4, . . . , STW(k+1) and STW(k+2) of the described fourth gate driver GDV4 are substantially the same or similar, so repeated descriptions may not be repeated.

[0219] The fifth gate driver GDV5 may be disposed adjacent to the first pixel region PXA1 and the third pixel region PXA3, respectively, than the sixth gate driver GDV6 and the seventh gate driver GDV7. For example, the fifth gate driver GDV5 may be between the first pixel region PXA1 and the sixth gate driver GDV6, and the fifth gate driver GDV5 may be between the third pixel region PXA3 and the seventh gate driver GDV7. In this case, as Figure 4 As shown in , the RC delay of the write scan signal GWn having a relatively small pulse width can be relatively alleviated. In addition, the fifth gate driver GDV5 can apply the write scan signal to the write scan lines GWL1_3, GWL2_3, GWL3_3, GWL4_3, ..., GWLk+1 and GWLk+2 together with the fourth gate driver GDV4, so the RC delay of the write scan signal can be minimized or reduced.

[0220] The seventh gate driver GDV7 may include initialization stages STI1_3 , STI2_3 , STI3_3 , and STI4_3 .

[0221] The initialization stages STI1_3, STI2_3, STI3_3, and STI4_3 may be coupled (e.g., connected) to the initialization clock signal lines GI_CLK1 and GI_CLK2, and may be coupled (e.g., connected) to the initialization scan lines GIL1_3, GIL2_3, GIL3_3, and GIL4_3, respectively. For example, each of the initialization stages STI1_3, STI2_3, STI3_3, and STI4_3 may be coupled (e.g., connected) to both the initialization clock signal lines GI_CLK1 and GI_CLK2.

[0222] Initialization clock signal lines GI_CLK1 and GI_CLK2 and an initialization start signal line GI_FLM, which will be described later, may be included in the reference Figure 5 The first control signal line CSL2 is described, and can extend from the third peripheral area PPA3 to the second peripheral area PPA2 via (e.g., through) the additional peripheral area APA. The initialization clock signal can be applied to the initialization clock signal lines GI_CLK1 and GI_CLK2, and the initialization start signal (or the first initialization start signal or the fourth start pulse) can be applied to the initialization start signal line GI_FLM.

[0223] Each of the initialization stages STI1_3, STI2_3, STI3_3 and STI4_3 can receive an initialization start signal or an initialization scan signal (or an initialization carry signal) of a previous initialization stage, and can use the initialization clock signal to generate an initialization scan signal corresponding to the initialization start signal or the initialization scan signal of the previous initialization stage (i.e., the previous initialization scan signal).

[0224] For example, the first initialization stage STI1_3 can receive an initialization start signal through (e.g., from) the initialization start signal line GI_FLM, can use the initialization clock signal to generate a first initialization scan signal corresponding to the initialization start signal, and can provide the first initialization scan signal to the first initialization scan line GIL1_3 in the third pixel area PXA3.

[0225] The second initialization stage STI2_3 may receive the first initialization scan signal from the first initialization stage STI1_3, and may generate a second initialization scan signal corresponding to the first initialization scan signal to provide it to the second initialization scan line GIL2_3 in the third pixel area PXA3. Similarly, the third initialization stage STI3_3 may generate a third initialization scan signal corresponding to the second initialization scan signal to provide it to the third initialization scan line GIL3_3 in the third pixel area PXA3, and the fourth initialization stage STI4_2 may generate a fourth initialization scan signal corresponding to the third initialization scan signal to provide it to the fourth initialization scan line GIL4_3 in the third pixel area PXA3.

[0226] Furthermore, the seventh gate driver GDV7 may include light emitting stages STE1_3 , STE2_3 , STE3_3 , and STE4_3 .

[0227] The light emission stages STE1_3, STE2_3, STE3_3, and STE4_3 may be coupled (e.g., connected) to the light emission clock signal lines EM_CLK1 and EM_CLK2, and may be coupled (e.g., connected) to the light emission scan lines EML1_3, EML2_3, EML3_3, and EML4_3 in the third pixel area PXA3, respectively. For example, each of the light emission stages STE1_3, STE2_3, STE3_3, and STE4_3 may be coupled (e.g., connected) to both the light emission clock signal lines EM_CLK1 and EM_CLK2.

[0228] Light emission clock signal lines EM_CLK1 and EM_CLK2 and a light emission stop signal line EM_FLM, which will be described later, may be included in the reference Figure 5The second control signal line CSL2 is described, and can extend from the third peripheral area PPA3 to the second peripheral area PPA2 via (e.g., through) the additional peripheral area APA. The light emission clock signal can be applied to the light emission clock signal lines EM_CLK1 and EM_CLK2, and the light emission stop signal (or the fifth start pulse) can be applied to the light emission stop signal line EM_FLM.

[0229] Each of the light emission stages STE1_3, STE2_3, STE3_3 and STE4_3 can receive a light emission stop signal or a light emission scan signal (or a light emission carry signal) of a previous light emission level, and can use a light emission clock signal to generate a light emission scan signal corresponding to the light emission stop signal or the light emission scan signal of the previous light emission level (i.e., the previous light emission scan signal).

[0230] Since the operations of the light emission stages STE1_3, STE2_3, STE3_3, and STE4_3 are substantially the same as or similar to the operations of the initialization stages STI1_3, STI2_3, STI3_3, and STI4_3, a repeated description may not be repeated.

[0231] For example, the light emission stages STE1_1 , STE2_3 , STE3_3 , and STE4_3 may sequentially provide light emission scan signals to the light emission scan lines EML1_3 , EML2_3 , EML3_3 , and EML4_3 .

[0232] Meanwhile, the sixth gate driver GDV6 may include initialization stages STI(k+1)_1 and STI(k+2)_1.

[0233] Initialization stages STI(k+1)_1 and STI(k+2)_1 may be coupled (eg, connected) to initialization clock signal lines GI_CLK1 and GI_CLK2, and may be coupled (eg, connected) to initialization scan lines GILk+1 and GILk+2, respectively. Here, the k+1th initialization scan line GILk+1 may correspond to the reference Figure 5 Describes the initialization scan line GIL_1.

[0234] Each of the initialization stages STI(k+1)_1 and STI(k+2)_1 may receive an initialization scan signal (or an initialization carry signal) of a previous initialization stage, and may generate an initialization scan signal corresponding to the initialization scan signal of the previous initialization stage using an initialization clock signal.

[0235] Since the operation of each of the initialization stages STI(k+1)_1 and STI(k+2)_1 is substantially the same as or similar to the operation of the second initialization stage STI2_3 , a repeated description may not be repeated.

[0236] For example, the initialization stages STI(k+1)_1 and STI(k+2)_1 may sequentially supply the initialization scan signals to the initialization scan lines GILk+1 and GILk+2 in the first pixel area PXA1.

[0237] Furthermore, the sixth gate driver GDV6 may include light emitting stages STE(k+1)_1 and STE(k+2)_1.

[0238] The light emission stages STE(k+1)_1 and STE(k+2)_1 may be coupled (e.g., connected) to the light emission clock signal lines EM_CLK1 and EM_CLK2, and may be coupled (e.g., connected) to the light emission scan lines EMLk+1 and EMLk+2, respectively. For example, each of the light emission stages STE(k+1)_1 and STE(k+2)_1 may be coupled (e.g., connected) to both the light emission clock signal lines EM_CLK1 and EM_CLK2.

[0239] Each of the light emission stages STE(k+1)_1 and STE(k+2)_1 can receive a light emission scan signal (or a light emission carry signal) of a previous light emission stage, and can generate a light emission scan signal corresponding to the light emission scan signal of the previous light emission stage (i.e., the previous light emission scan signal) using a light emission clock signal.

[0240] Since the operation of each of the light emission levels STE(k+1)_1 and STE(k+2)_1 is substantially the same as or similar to the operation of each of the light emission levels STE1_3, STE2_3, STE3_3, and STE4_3 corresponding to the third pixel area PXA3, repeated description may not be repeated.

[0241] For example, the light emission stages STE(k+1)_1 and STE(k+2)_1 may sequentially provide light emission scan signals to the light emission scan lines EMLk+1 and EMLk+2 in the first pixel area PXA1.

[0242] The eighth gate driver GDV8 may include initialization stages STI1_2 , STI2_2 , STI3_2 , and STI4_2 .

[0243] The initialization stages STI1_2, STI2_2, STI3_2, and STI4_2 may be coupled (e.g., connected) to the initialization clock signal lines GI_CLK1 and GI_CLK2, and may be coupled (e.g., connected) to the initialization scan lines GIL1_2, GIL2_2, GIL3_2, and GIL4_2, respectively. For example, each of the initialization stages STI1_2, STI2_2, STI3_2, and STI4_2 may be coupled (e.g., connected) to both the initialization clock signal lines GI_CLK1 and GI_CLK2.

[0244] Since operations of the initialization stages STI1_2 , STI2_2 , STI3_2 , and STI4_2 are substantially the same as or similar to operations of the initialization stages STI1_3 , STI2_3 , STI3_3 , and STI4_3 corresponding to the third pixel area PXA3 , repeated descriptions may not be repeated.

[0245] For example, the initialization stages STI1_2, STI2_2, STI3_2, and STI4_2 of the eighth gate driver GDV8 may sequentially provide the initialization scan signals to the initialization scan lines GIL1_2, GIL2_2, GIL3_2, and GIL4_2 in the second pixel area PXA2.

[0246] Furthermore, the eighth gate driver GDV8 may include light emitting stages STE1_2 , STE2_2 , STE3_2 , and STE4_2 .

[0247] The light emission stages STE1_2, STE2_2, STE3_2, and STE4_2 may be coupled (e.g., connected) to the light emission clock signal lines EM_CLK1 and EM_CLK2, and may be coupled (e.g., connected) to the light emission scan lines EML1_2, EML2_2, EML3_2, and EML4_2 in the second pixel area PXA2. For example, each of the light emission stages STE1_2, STE2_2, STE3_2, and STE4_2 may be coupled (e.g., connected) to both the light emission clock signal lines EM_CLK1 and EM_CLK2.

[0248] Since operations of the light emission stages STE1_2, STE2_2, STE3_2, and STE4_2 are substantially the same as or similar to operations of the light emission stages STE1_3, STE2_3, STE3_3, and STE4_3 corresponding to the third pixel area PXA3, repeated descriptions may not be repeated.

[0249] For example, the light emission stages STE1_2, STE2_2, STE3_2, and STE4_2 of the eighth gate driver GDV8 may sequentially provide light emission scan signals to the light emission scan lines EML1_2, EML2_2, EML3_2, and EML4_2 in the second pixel area PXA2.

[0250] As reference Fig. 9 As described, the initialization scan signal and the light emission scan signal may be provided to the second pixel area PXA2 through the eighth gate driver GDV8 provided in the peripheral area (e.g., the second peripheral area PPA2) between the second pixel area PXA2 and the third pixel area PXA3. Therefore, compared with the case where the seventh gate driver GDV7 provides the initialization scan signal and the light emission scan signal to the second pixel area PXA2 through separate lines, the number of lines provided for the additional peripheral area APA (e.g., in the additional peripheral area APA) may be reduced, and the number of lines for reference may be sufficiently ensured. Figure 7 and Figure 8 The space of the dummy cell DPTN (or load matching capacitor) described above and the distances between the lines (eg, connection lines CL1, CL2, CL3, and CL4) provided for the additional peripheral area APA (eg, for reference Figure 7 and Figure 8 The space of the dummy unit DPTN (or the load matching capacitor) described above and the distance between the lines provided for the additional peripheral area APA (e.g., the connection lines CL1, CL2, CL3, and CL4) may be sufficiently large). Therefore, a phenomenon in which an image (or the brightness of an image) displayed in the second pixel area PXA2 and the third pixel area PXA3 is different from an image displayed in the first pixel area PXA1 and defects (e.g., interference, disconnection, etc.) occurring in the connection lines CL1, CL2, CL3, and CL4 may be mitigated or prevented.

[0251] Fig.10 It is shown Figure 2 FIG. 1 is a diagram of another example embodiment of a display device.

[0252] Reference Figure 2 , Figure 5 and Fig.10 , Fig.10 The display device DD_1 and Figure 5 The display device DD is different in that Fig.10 The display device DD_1 does not include the eighth gate driver GDV8, but further includes additional connection lines CL_A1 and CL_A2. Because in addition to the additional connection lines CL_A1 and CL_A2, Fig.10 The display device DD_1 and Figure 5The display devices DD are substantially the same or similar, so repeated descriptions are not necessary.

[0253] Similar to the connection line CL, the additional connection lines CL_A1 and CL_A2 may extend from the second pixel area PXA2 to the third pixel area PXA3 via (eg, through or across) the additional peripheral area APA.

[0254] The initialization scan line GIL_2 (or the second initialization scan line) and the light emission scan line EML_2 (or the second light emission scan line) set on the second pixel area PXA2 can be respectively combined (for example, connected) to the initialization scan line GIL_3 (or the third initialization scan line) and the light emission scan line EML_3 (or the third light emission scan line) set to the third pixel area PXA3 (for example, set on the third pixel area PXA3 or in the third pixel area PXA3) through external connecting lines CL_A1 and CL_A2.

[0255] For example, the initialization scan line GIL_2 in the second pixel region PXA2 may be coupled (e.g., connected) to the initialization scan line GIL_3 in the third pixel region PXA3 through the additional connection line CL_A1 and the first additional connection line CL_A1 of CL_A2. For example, the light emission scan line EML_2 in the second pixel region PXA2 may be coupled (e.g., connected) to the light emission scan line EML_3 (or the third light emission scan line) in the third pixel region PXA3 through the additional connection line CL_A1 and the second additional connection line CL_A2 of CL_A2.

[0256] In this case, the seventh gate driver GDV7 may be coupled (e.g., connected) to the initialization scan line GIL_2 in the second pixel area PXA2 through the initialization scan line GIL_3 in the third pixel area PXA3 and the first additional connection line CL_A1, and may provide the initialization scan signal to the second pixel PXL2. Similarly, the seventh gate driver GDV7 may be coupled (e.g., connected) to the light emission scan line EML_2 in the second pixel area PXA2 through the light emission scan line EML_3 in the third pixel area PXA3 and the second additional connection line CL_A2, and may provide the light emission scan signal to the second pixel PXL2.

[0257] When the width (or length) of the peripheral area (or the additional peripheral area APA) in the first direction DR1 is more limited (e.g., sufficiently small or relatively small) between the second pixel area PXA2 and the third pixel area PXA3, the display device DD_1 may use the seventh gate driver GDV7 instead of the eighth gate driver GDV8 (see Figure 5) provides an initialization scan signal and a light emission scan signal to the second pixel area PXA2.

[0258] Fig.11 It is shown Figure 2 FIG. 1 is a diagram of another example embodiment of a display device.

[0259] Reference Figure 2 , Figure 5 and Fig.11 , Fig.11 The display device DD_2 and Figure 5 The display device DD is different in that Fig.11 The display device DD_2 does not include the third gate driver GDV3, but further includes additional connection lines CL_A3 and CL_A4. Because in addition to the additional connection lines CL_A3 and CL_A4, Fig.11 The display device DD_2 and Figure 5 The display devices DD are substantially the same or similar, so repeated descriptions are not necessary.

[0260] Similar to the connection line CL, the additional connection lines CL_A3 and CL_A4 may extend from the second pixel area PXA2 to the third pixel area PXA3 via (eg, through or across) the additional peripheral area APA.

[0261] The bypass scan line GBL_3 (or the third bypass scan line) and the compensation scan line GCL_3 (or the third compensation scan line) set on the third pixel area PXA3 can be respectively combined (for example, connected) to the bypass scan line GBL_2 (or the second bypass scan line) and the compensation scan line GCL_2 (or the second compensation scan line) set to the second pixel area PXA2 (for example, set on the second pixel area PXA2 or in the second pixel area PXA2) through external connecting lines CL_A3 and CL_A4.

[0262] For example, the bypass scan line GBL_3 in the third pixel region PXA3 may be coupled (e.g., connected) to the bypass scan line GBL_2 in the second pixel region PXA2 through a third additional connection line CL_A3 of the additional connection lines CL_A3 and CL_A4. For example, the compensation scan line GCL_3 in the third pixel region PXA3 may be coupled (e.g., connected) to the compensation scan line GCL_2 in the second pixel region PXA2 through a fourth additional connection line CL_A4 of the additional connection lines CL_A3 and CL_A4.

[0263] In this case, the second gate driver GDV2 may be coupled (e.g., connected) to the bypass scan line GBL_3 in the third pixel area PXA3 through the bypass scan line GBL_2 in the second pixel area PXA2 and the third additional connection line CL_A3, and may provide the bypass scan signal to the third pixel PXL3. Similarly, the second gate driver GDV2 may be coupled (e.g., connected) to the compensation scan line GCL_3 in the third pixel area PXA3 through the compensation scan line GCL_2 in the second pixel area PXA2 and the fourth additional connection line CL_A4, and may provide the compensation scan signal to the third pixel PXL3.

[0264] When the width (or length) of the peripheral area (or the additional peripheral area APA) in the first direction DR1 is more limited (e.g., sufficiently small or relatively small) between the second pixel area PXA2 and the third pixel area PXA3, the display device DD_2 may use the second gate driver GDV2 instead of the third gate driver GDV3 (see Figure 5 ) provides the bypass scan signal and the compensation scan signal to the third pixel area PXA3.

[0265] While the present disclosure has been shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various suitable changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

[0266] Therefore, the technical scope of the present disclosure can be determined by the technical scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: a substrate having a groove portion recessed inwardly at one side and comprising a display area and a peripheral area surrounding the display area, the display area comprising a first display area, a second display area, and a third display area, the second display area and the third display area protruding from a first side of the first display area, and the groove portion being disposed between the second display area and the third display area; A first pixel, located on the first display area; A second pixel is located on the second display area; A third pixel is located on the third display area; a first gate line located on the first display area and coupled to the first pixel; a second gate line located on the second display area and coupled to the second pixel; a third gate line located on the third display area and coupled to the third pixel; a first gate driver, configured to sequentially provide a first gate signal to the first gate lines; a second gate driver, configured to sequentially provide a second gate signal to the second gate lines; A third gate driver, used for sequentially providing a third gate signal to the third gate lines; a fourth gate line located on the first display area and coupled to the first pixel; a fifth gate line located on the second display area and coupled to the second pixel; a sixth gate line, located on the third display area and coupled to the third pixel; a connecting line located on the peripheral area between the second display area and the third display area and connecting the fifth gate line and the sixth gate line to each other; as well as a fourth gate driver, configured to sequentially provide a fourth gate signal to the fifth gate line and the fourth gate line, The third gate driver is located on the peripheral area between the second display area and the third display area.

2. The display device according to claim 1, wherein: The first gate line, the second gate line and the third gate line extend in a first direction, and The second display area and the third display area are spaced apart from each other in the first direction. 3 . The display device according to claim 2 , further comprising a first control line extending through the peripheral area between the second display area and the third display area and coupled to the second gate driver and the third gate driver.

4. The display device according to claim 3, wherein: The second gate driver is used to generate a second gate signal corresponding to the first start pulse in the second gate signal by using the first clock signal provided through the first control line, and The third gate driver is used to generate a third gate signal corresponding to the second start pulse among the third gate signals by using the first clock signal provided through the first control line.

5. The display device according to claim 4, wherein: The second start pulse is the same as the first start pulse, and the second start pulse is provided to the third gate driver through one of the first control lines.

6. The display device according to claim 2, wherein: The second gate line and the third gate line are separated from each other, and the groove portion is interposed between the second gate line and the third gate line. 7 . The display device according to claim 1 , further comprising a dummy pattern overlapping the connection line to form a capacitor.

8. The display device according to claim 7, further comprising: a power supply line commonly coupled to the first pixel, the second pixel and the third pixel, Wherein, the dummy pattern is coupled to the power line. 9 . The display device according to claim 1 , further comprising a fifth gate driver for sequentially supplying a fifth gate signal to the sixth gate line and the fourth gate line.

10. The display device according to claim 9, wherein: The fourth gate driver is adjacent to the second side of the first display area and the second side of the second display area, and The fifth gate driver is adjacent to a third side of the first display area and a third side of the third display area.

11. The display device according to claim 1, further comprising: a seventh gate line located on the first display area and coupled to the first pixel; an eighth gate line located on the second display area and coupled to the second pixel; a ninth gate line, located on the third display area and coupled to the third pixel; a sixth gate driver, configured to sequentially provide a sixth gate signal to the seventh gate line; a seventh gate driver, configured to sequentially provide a seventh gate signal to the ninth gate line; as well as an eighth gate driver, configured to sequentially provide an eighth gate signal to the eighth gate line, The eighth gate driver is located on the peripheral area between the second display area and the third display area.

12. The display device according to claim 11, wherein: The second gate driver is adjacent to the second side of the second display area, The third gate driver is adjacent to the second side of the third display area. The seventh gate driver is adjacent to the third side of the third display area. Wherein, the eighth gate driver is adjacent to the third side of the second display area. 13 . The display device of claim 11 , further comprising a second control line extending through the peripheral area between the second display area and the third display area and coupled to the seventh gate driver and the eighth gate driver.

14. The display device according to claim 13, wherein: The seventh gate driver is used to generate a seventh gate signal corresponding to the third start pulse among the seventh gate signals by using the second clock signal provided through the second control line, and The eighth gate driver is used for generating an eighth gate signal corresponding to the fourth start pulse among the eighth gate signals by using the second clock signal provided through the second control line.

15. The display device according to claim 14, wherein: The fourth start pulse is the same as the third start pulse and is provided to the eighth gate driver through one of the second control lines.

16. The display device according to claim 11, further comprising a first data line, a first power line, a second power line and a first initialization line, in, One of the first pixels comprises: a light emitting element coupled to both the first power line and the second power line and located between the first power line and the second power line; a driving transistor for transmitting a driving current to the light emitting element and comprising a first electrode, a second electrode and a gate electrode; a switching transistor including a first electrode coupled to the first data line, a second electrode coupled to the first electrode of the driving transistor, and a gate electrode coupled to one of the fourth gate lines; a compensation transistor including a first electrode coupled to the second electrode of the driving transistor, a second electrode coupled to the gate electrode of the driving transistor, and a gate electrode coupled to one of the first gate lines; and An initialization transistor includes a first electrode coupled to the gate electrode of the driving transistor, a second electrode coupled to the first initialization line, and a gate electrode coupled to one of the seventh gate lines.

17. The display device according to claim 16, further comprising a third power line, in, The first pixel further includes: a first bypass transistor including a first electrode coupled to the third power line, a second electrode coupled to the first electrode of the driving transistor, and a gate electrode coupled to one of the first gate lines; and The first light emitting transistor includes a first electrode coupled to the first power line, a second electrode coupled to the first electrode of the driving transistor, and a gate electrode coupled to one of the seventh gate lines.

18. The display device according to claim 17, further comprising a second initialization line, in, The first pixel further includes: a second light emitting transistor including a first electrode coupled to the second electrode of the driving transistor, a second electrode coupled to an anode electrode of the light emitting element, and a gate electrode coupled to one of the seventh gate lines; and A second bypass transistor includes a first electrode coupled to the anode electrode of the light emitting element, a second electrode coupled to the second initialization line, and a gate electrode coupled to one of the first gate lines.

19. A display device, comprising: A substrate, comprising: a first display area, a second display area, and a third display area, wherein the second display area and the third display area protrude from a first side of the first display area and are spaced apart from each other; and a peripheral area located between the second display area and the third display area; A first pixel, located on the first display area; A second pixel is located on the second display area; A third pixel is located on the third display area; a first gate line located on the first display area and coupled to the first pixel; a second gate line located on the second display area and coupled to the second pixel; a third gate line located on the third display area and coupled to the third pixel; a first gate driver, configured to sequentially provide a first gate signal to the first gate lines; a second gate driver, configured to sequentially provide a second gate signal to the second gate lines; A third gate driver, used for sequentially providing a third gate signal to the third gate lines; a fourth gate line located on the first display area and coupled to the first pixel; a fifth gate line located on the second display area and coupled to the second pixel; a sixth gate line, located on the third display area and coupled to the third pixel; a connection line located on the peripheral area between the second display area and the third display area and connecting the fifth gate line and the sixth gate line to each other; and a fourth gate driver, configured to sequentially provide a fourth gate signal to the fifth gate line and the fourth gate line, The third gate driver is located on the peripheral area between the second display area and the third display area.

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