Semiconductor structure, packaging structure, and packaging method

Abstract

The present disclosure provides a semiconductor structure, including a first semiconductor device and a second semiconductor device, a first group of conductive connectors that mechanically and electrically connect the first semiconductor device to the second semiconductor device, a first bottom filler located between the first semiconductor device and the second semiconductor device and surrounding the first group of conductive connectors, a first sealant located at least on the sidewalls of the first semiconductor device, the second semiconductor device and the first bottom filler, and a second group of conductive connectors electrically coupled to the first semiconductor device, the second group of conductive connectors and the first group of conductive connectors being located on opposite sides of the first semiconductor device. The present disclosure also provides a packaging structure and a packaging method.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to a semiconductor manufacturing technology, and more particularly to a semiconductor structure, a packaging structure, and a packaging method. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials on a semiconductor substrate, and patterning the various material layers using lithography and etching processes to form circuit components and circuit elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise in each process used and these other problems should be solved. Summary of the invention

[0004] According to some embodiments of the present disclosure, a semiconductor structure is provided, comprising: a first semiconductor device, a second semiconductor device, a first group of conductive connectors, a first bottom filler, a first sealant, and a second group of conductive connectors. The first semiconductor device comprises: a plurality of first capacitors, and a first conductive through hole. The second semiconductor device comprises: a plurality of second capacitors, and a second conductive through hole. The first capacitor is formed on a first substrate. The first conductive through hole extends through the first substrate, and the first conductive through hole is electrically coupled to the first capacitor. The second capacitor is formed on a second substrate. The second conductive through hole extends through the second substrate, and the second conductive through hole is electrically coupled to the second capacitor. The first group of conductive connectors mechanically and electrically joins the first semiconductor device and the second semiconductor device, and at least one of the first group of conductive connectors electrically couples the first conductive through hole and the second conductive through hole. The first bottom filler is located between the first semiconductor device and the second semiconductor device, and surrounds the first group of conductive connectors. The first sealant is located on at least the sidewalls of the first semiconductor device and the second semiconductor device and the first bottom filler. The second group of conductive connectors is electrically coupled to the first semiconductor device, and the second group of conductive connectors and the first group of conductive connectors are located on opposite sides of the first semiconductor device.

[0005] According to other embodiments of the present disclosure, a packaging structure is provided, including: a first passive package, a first integrated circuit package, a first sealant, and a first redistribution structure. The first passive package includes a passive die stack. Each passive die in the passive die stack includes a plurality of passive components on a substrate and a conductive through hole extending through the substrate. The first integrated circuit package includes at least one integrated circuit die, and the at least one integrated circuit die includes a plurality of active components. The first sealant at least laterally encapsulates the first passive package and the first integrated circuit package. The first redistribution structure is located on the first sealant, the first integrated circuit package, and the first passive package, and the first redistribution structure includes a plurality of dielectric layers having metallization patterns therein, and the metallization patterns of the first redistribution structure are electrically coupled to the first integrated circuit package and the first passive package.

[0006] According to some other embodiments of the present disclosure, a packaging method is provided, including forming a first passive package; forming a first semiconductor device, including: forming a plurality of first capacitors in a first substrate; and forming a first conductive through hole extending through the first substrate, the first conductive through hole being electrically coupled to the first capacitor; forming a second semiconductor device, including: forming a plurality of second capacitors in a second substrate; and forming a second conductive through hole extending through the second substrate, the second conductive through hole being electrically coupled to the second capacitor; attaching the first semiconductor device to a first carrier substrate; forming a first bottom filler on the attached first semiconductor device; bonding the second semiconductor device to the first semiconductor device with a first set of conductive connectors, the first set of conductive connectors being located in the first bottom filler, at least one of the first set of conductive connectors being electrically coupled to the first conductive through hole and the second conductive through hole; encapsulating the first semiconductor device and the second semiconductor device and the first bottom filler with a first sealant; removing the first carrier substrate; and forming a second set of conductive connectors on the first semiconductor device, the second set of conductive connectors being electrically coupled to the first semiconductor device, the second set of conductive connectors being located on opposite sides of the first semiconductor device as the first set of conductive connectors. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not necessarily drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity.

[0008] Figures 1 to 6 Cross-sectional views of various intermediate stages in the fabrication of a semiconductor device are shown in accordance with some embodiments.

[0009] Figures 7 to 16Cross-sectional views of various intermediate stages in the fabrication of a semiconductor package are shown in accordance with some embodiments.

[0010] Figures 17 to 20 Cross-sectional views of various intermediate stages in the fabrication of a semiconductor package are shown in accordance with some embodiments.

[0011] Figure 21 to Figure 29 Cross-sectional views are shown of various intermediate stages in the fabrication of a package in accordance with some embodiments.

[0012] The reference numerals are described as follows:

[0013] 100: Semiconductor devices

[0014] 101: Sidewall

[0015] 102: Substrate

[0016] 104: Concave

[0017] 110: Padding layer

[0018] 112A: Conductive layer

[0019] 112B: Conductive layer

[0020] 112C: Conductive layer

[0021] 112D: Conductive layer

[0022] 114A: Dielectric layer

[0023] 114B: Dielectric layer

[0024] 114C: Dielectric layer

[0025] 114D: Dielectric layer

[0026] 116A: Spacer

[0027] 116B: Spacer

[0028] 116C: Spacer

[0029] 116D: Spacer

[0030] 118: Dielectric Materials

[0031] 120: Etch stop layer

[0032] 121: Deep trench capacitor

[0033] 122: Dielectric layer

[0034] 124A: Conductive vias

[0035] 124B: Conductive vias

[0036] 124C: Conductive vias

[0037] 124D: Conductive vias

[0038] 124E: Conductive vias

[0039] 126: Etch stop layer

[0040] 128: Dielectric layer

[0041] 130A: Conductive circuit

[0042] 130B: Conductive circuit

[0043] 130C: Conductive circuit

[0044] 132: Sealing ring structure

[0045] 134A: Line

[0046] 134B: Line

[0047] 140: Dielectric layer

[0048] 142: Conductive circuit

[0049] 144: Contact pad

[0050] 146: Protective layer

[0051] 148: Under Bump Metallization

[0052] 150: Conductive connector

[0053] 152: Interconnection Structure

[0054] 160: Conductive through hole

[0055] 170: Carrier substrate

[0056] 172: Bottom filler

[0057] 180: Joint head

[0058] 190: Sealant

[0059] 200: Semiconductor package

[0060] 210: Tape

[0061] 218: Cutting area

[0062] 220: Conductive connector

[0063] 300: Semiconductor package

[0064] 320: Dielectric layer

[0065] 322: Metallized pattern

[0066] 324: Dielectric layer

[0067] 326: Metallized pattern

[0068] 328: Dielectric layer

[0069] 330: Tape

[0070] 332: Cutting area

[0071] 334: Conductive connector

[0072] 350: Redistribution Structure

[0073] 400: Package, semiconductor package

[0074] 402: Carrier substrate

[0075] 404: Release layer

[0076] 406: Adhesive

[0077] 410: Module

[0078] 412: Module

[0079] 413: Semiconductor substrate

[0080] 414: Device

[0081] 416: Interlayer Dielectric

[0082] 418: Conductive plug

[0083] 419: Interconnection Structure

[0084] 420: Pad

[0085] 422: Protective film

[0086] 424: Bare die connector

[0087] 426: Dielectric layer

[0088] 430: Sealant

[0089] 432: Dielectric layer

[0090] 434: Metallized pattern

[0091] 436: Dielectric layer

[0092] 438: Metallized pattern

[0093] 440: Dielectric layer

[0094] 442: Metallized pattern

[0095] 444: Dielectric layer

[0096] 446: Metallized pattern

[0097] 448: Dielectric layer

[0098] 450: Pad

[0099] 452: Fine feature part

[0100] 454: Coarse feature part

[0101] 456: Redistribution Structure

[0102] 458: Conductive connector

[0103] 500: Substrate

[0104] 504: Bonding pad

[0105] 506: Conductive vias

[0106] 508: Bonding pad

[0107] 510: Conductive connector

[0108] 512: Underfill

[0109] 600: First Area

[0110] 602: Second Area

[0111] 700: Encapsulation

[0112] D1: Depth

[0113] H1: Thickness

[0114] H2: Thickness

[0115] H3: Thickness

[0116] H4: Thickness

[0117] H5: Height

[0118] H6: Height

[0119] H7: Height

[0120] H8: Height

[0121] H9: Height

[0122] T1: Thickness

[0123] T2: Thickness

[0124] T3: Thickness

[0125] T4: Thickness

[0126] W1: Width

[0127] W1: Width

[0128] W2: Width

[0129] W3: Width

[0130] W4: Width

[0131] W5: Width DETAILED DESCRIPTION

[0132] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0133] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "beneath," "above," "on," etc. may be used herein to facilitate description of the relationship of one element or feature to other elements or features as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0134] The embodiments discussed herein may be discussed in a specific context, namely a package structure (e.g., an integrated fan-out (INFO) package structure or a chip-on-wafer-on-substrate (CoWoS) package structure) having one or more semiconductor devices stacked or connected vertically to effectively form a larger semiconductor device. In some embodiments, the semiconductor device may be an integrated passive device (IPD) including a capacitor, such as a deep trench capacitor (DTCs), a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or the like or a combination thereof. By vertically stacking the integrated passive devices, an efficient capacitor that can be used as a decoupling capacitor may be formed. Moreover, a package structure including one or more vertically stacked and coupled capacitors may provide a lower capacitor equivalent series resistance (ESR).

[0135] In addition, the teachings of the present disclosure may be applied to any integrated passive component packaging structure. Other embodiments contemplate other applications, such as different packaging types or different configurations, which will be apparent to those with ordinary knowledge in the art after reading the present disclosure. It should be noted that the embodiments discussed herein may not necessarily illustrate every component or feature that may be present in the structure. For example, when discussing one component, for example, it may be sufficient to convey various aspects of the embodiment, multiple components may be omitted from the figure. In addition, the method embodiments discussed herein may be discussed as being performed in a particular order. However, other method embodiments may be performed in any logical order.

[0136] Figures 1 to 5 Cross-sectional views of various intermediate stages of fabrication of a semiconductor device 100 are shown in accordance with some embodiments. Figure 1A cross-sectional view of an edge portion of semiconductor device 100 is shown, and sidewall 101 is an edge of semiconductor device 100. In some embodiments, semiconductor device 100 includes substrate 102. Substrate 102 may include, for example, doped or undoped bulk silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. Typically, a semiconductor-on-insulator substrate includes a layer of semiconductor material such as silicon formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is disposed on a substrate such as a silicon or glass substrate. Alternatively, the substrate 102 may include another basic semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0137] In some embodiments, one or more recesses 104 are formed on the substrate 102 (in Figure 1 104). In some embodiments, the substrate 102 may be patterned using appropriate lithography and etching methods to form the recesses 104. For example, a photoresist (not shown) may be formed on the substrate 102 and patterned, and one or more etching processes (e.g., a dry etching process) may be used to remove the desired locations of the recesses 104 on the substrate 102. In some embodiments, the recess 104 may have a width W1 between about 20 nanometers (nm) and about 2000 nanometers. In some embodiments, the recess 104 may have a depth D1 between about 500 nanometers and about 10000 nanometers. In some embodiments, the ratio of W1 / D1 is between about 0.002 and about 4. As described in more detail below, a deep trench capacitor (DTC) is formed on the recess 104.

[0138] Reference Figure 2 , deep trench capacitors (DTCs) are formed in the recess 104 (see Figure 1). In some embodiments, a liner layer 110 is formed on the substrate 102 and is formed along the sidewalls and the bottom of the recess 104. In some embodiments, the liner layer 110 may include a dielectric material such as silicon oxide, silicon oxynitride (SiON), silicon carboxynitride (SICON), a combination thereof, and the like, and may be formed using atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof. In some embodiments, the liner layer 110 has a thickness between about 5 nanometers and about 100 nanometers. In some embodiments, the liner layer 110 is patterned to expose the top surface of the substrate 102. In some embodiments, the patterning process may include suitable lithography and etching methods.

[0139] In some embodiments, after forming the liner layer 110, the conductive layers 112A to 112D and the dielectric layers 114A to 114D are formed in the recesses 104 in an alternating manner (see Figure 1). The conductive layers 112A to 112D may also be referred to as capacitor electrodes 112A to 112D. In some embodiments, each conductive layer 112A to 112D may include a conductive material, such as doped silicon, polysilicon, copper, tungsten, aluminum, or copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, and the like, and may be formed using plating, physical vapor deposition (PVD), atomic layer deposition, chemical vapor deposition, combinations thereof, and the like. In some embodiments, each conductive layer 112A to 112D has a thickness between about 10 nanometers and about 100 nanometers. In some embodiments, each dielectric layer 114A to 114D may include a high-k dielectric material, such as aluminum oxide, zirconium oxide, combinations thereof, multilayers thereof, etc. In one embodiment, each dielectric layer 114A to 114D includes a multilayer including two layers of zirconium oxide and a layer of aluminum oxide interposed between the two layers of zirconium oxide. In some embodiments, each dielectric layer 114A to 114D has a thickness between about 0.3 nanometers and about 50 nanometers.

[0140] In some embodiments, after forming the conductive layer 112A on the liner layer 110, the conductive layer 112A is patterned to expose the top surface of a portion of the liner layer 110. In some embodiments, the patterning process may include suitable lithography and etching methods. Next, spacers 116A are formed along the opposite sidewalls of the conductive layer 112A. Each spacer 116A may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, a multilayer thereof, etc. In some embodiments, the dielectric material is blanket deposited using atomic layer deposition, chemical vapor deposition, a combination thereof, etc., and the dielectric material is anisotropically etched to remove the horizontal portion of the dielectric material to form the spacer 116A. The vertical portion of the remaining dielectric material forms the spacer 116A. In some embodiments, each spacer 116A has a width between about 5 nanometers and about 50 nanometers. Subsequently, a dielectric layer 114A is formed on the conductive layer 112A and the spacer 116A. In some embodiments, dielectric layer 114A is patterned to remove portions of dielectric layer 114A extending beyond spacers 116A. In some embodiments, the patterning process may include suitable photolithography and etching methods.

[0141] Next, a conductive layer 112B is blanket formed on the dielectric layer 114A and the substrate 102. Then, the conductive layer 112B is patterned to expose the top surface of a portion of the dielectric layer 114A. In some embodiments, the patterning process may include suitable lithography and etching methods. Next, spacers 116B are formed along the opposite sidewalls of the conductive layer 112B. In some embodiments, spacers 116B may be formed using materials and methods similar to those used to form spacers 116A, and are not described repeatedly here. In some embodiments, each spaced 116B has a width between about 5 nanometers and about 50 nanometers. Subsequently, a dielectric layer 114B is formed on the conductive layer 112B and the spacers 116B. In some embodiments, the dielectric layer 114B is patterned to remove portions of the dielectric layer 114B that extend beyond the spacers 116B. In some embodiments, the patterning process may include suitable lithography and etching methods.

[0142] Next, the process steps described above regarding the formation of conductive layer 112B, spacer 116B, and dielectric layer 114B are repeated to form conductive layer 112C, spacer 116C, and dielectric layer 114C on dielectric layer 114B, and to form conductive layer 112D, spacer 116D, and dielectric layer 114C. In some embodiments, spacers 116C and 116D may be formed using materials and methods similar to those used to form spacer 116A, and are not described again here. In some embodiments, each spacer 116C has a width between approximately 5 nanometers and approximately 50 nanometers. In some embodiments, each spacer 116D has a width between approximately 5 nanometers and approximately 50 nanometers. Figure 2 In the illustrated embodiment, the deep trench capacitor 121 has four capacitor electrodes. Figure 2 In the illustrated embodiment, the deep trench capacitor 121 is formed in two separate recesses 104 of the substrate 102. In other embodiments, based on the design requirements for the deep trench capacitor 121, the deep trench capacitor 121 may have more or less than four capacitor electrodes, and / or may be formed in only a single recess 104. As will be appreciated by those of ordinary skill in the art, the above-described method for forming a deep trench capacitor is only one method of forming a deep trench capacitor, and other methods are fully intended to be included within the scope of the embodiments.

[0143] Further references Figure 2 After forming the deep trench capacitor 121 in the substrate 102, the remaining portion of the recess 104 (see Figure 1 ) is filled with dielectric material 118. In some embodiments, dielectric material 118 may include an oxide such as silicon oxide, a nitride such as silicon nitride, a combination thereof, multiple layers thereof, etc. In some embodiments, dielectric material 118 is patterned to remove portions of dielectric material 118 extending beyond spacer 116D. In some embodiments, the patterning process may include suitable photolithography and etching methods.

[0144] In some embodiments, after the dielectric material 118 is formed and patterned, an etch stop layer 120 is formed on the deep trench capacitor 121. In some embodiments, the etch stop layer 120 may include one or more layers of dielectric material. Suitable dielectric materials may include oxides (e.g., silicon oxide, aluminum oxide, etc.), nitrides (e.g., silicon nitride, etc.), oxynitrides (e.g., silicon oxynitride (SiON), etc.), oxycarbides (e.g., silicon oxycarbide (SiOC), etc.), carbonitrides (e.g., silicon carbonitride (SiCN), etc.), carbides (e.g., silicon carbide (SiC), etc.), combinations thereof, etc., and the dielectric material may be formed using spin-on coating, chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition, combinations thereof, etc. In some embodiments, the etch stop layer 120 has a thickness between about 3 nanometers and about 30 nanometers. In some embodiments, the etch stop layer 120 is used to assist in forming conductive vias that provide electrical connections to the conductive layers 112A to 112D of the deep trench capacitor 121. The etch stop layer 120 may also be referred to as a contact etch stop layer (CESL).

[0145] refer to Figures 3 to 5 After forming the deep trench capacitor 121, an interconnect structure 152 is formed on the substrate 102 and the deep trench capacitor 121. In some embodiments, the interconnect structure 152 includes a plurality of dielectric layers having conductive features embedded in the plurality of dielectric layers. Figure 3 In the illustrated embodiment, the interconnect structure 152 includes a dielectric layer 122 and a dielectric layer 128 , wherein the conductive vias 124A- 124E are embedded within the dielectric layer 122 , and the conductive lines 130A- 130C are embedded within the dielectric layer 128 .

[0146] In some embodiments, dielectric layers 122 and 128 may include low-k dielectric materials, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, etc., and the low-k dielectric materials may be formed by any suitable method, such as spin coating, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, combinations thereof, etc. Conductive features (such as conductive vias 124A to 124E and conductive lines 130A to 130C) may be formed using any suitable method (such as a damascene method, etc.). In some embodiments, the steps for forming the conductive features include forming openings in respective dielectric layers, depositing one or more barrier / adhesion layers (not shown) in the openings, depositing seed layers (not shown) on top of the one or more barrier / adhesion layers, and filling the openings with conductive material. Chemical mechanical polishing (CMP) is then performed to remove excess material of the one or more barrier / adhesion layers, the seed layers, and the conductive material that overfills the openings.

[0147] In some embodiments, one or more barrier / adhesion layers may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, etc., and the barrier / adhesion layers may be formed using physical vapor deposition, chemical vapor deposition, atomic layer deposition, combinations thereof, etc. The seed layer may include copper, titanium, nickel, gold, manganese, combinations thereof, etc., and the seed layer may be formed by plating, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, combinations thereof, etc. The conductive material may include copper, aluminum, tungsten, combinations thereof, alloys thereof, etc., and the conductive material may be formed using, for example, plating, or other suitable methods.

[0148] In some embodiments, interconnect structure 152 further includes an etch stop layer 126 formed between dielectric layers 122 and 128. The material for etch stop layer 126 is selected such that an etch rate of etch stop layer 126 is less than an etch rate of corresponding ones of dielectric layers 122 and 128. In some embodiments, an etch rate of etch stop layer 126 is less than an etch rate of dielectric layer 128.

[0149] In some embodiments, the etching rate of the etch stop layer 126 is less than the etching rate of the dielectric layer 122 .

[0150] In some embodiments, the etch stop layer 126 may include a Figure 2 The material of the etch stop layer 120 is described above and will not be repeatedly described here.

[0151] In some embodiments, conductive via 124A extends through dielectric layer 122, etch stop layer 120, and liner layer 110, and physically contacts substrate 102. Conductive via 124A electrically couples substrate 102 to conductive trace 130A. Conductive via 124B extends through dielectric layer 122, etch stop layer 120, and dielectric layer 114A, and physically contacts conductive layer 112A. Conductive via 124B electrically couples conductive layer 112A to conductive trace 130B. Conductive via 124C extends through dielectric layer 122, etch stop layer 120, and dielectric layer 114C, and physically contacts conductive layer 112C. Conductive via 124C electrically couples conductive layer 112C to conductive trace 130B. Conductive via 124D extends through dielectric layer 122, etch stop layer 120, dielectric material 118, and dielectric layer 114D, and physically contacts conductive layer 112D. Conductive via 124D electrically couples conductive layer 112D to conductive trace 130C. Conductive via 124E extends through dielectric layer 122, etch stop layer 120, dielectric material 118, dielectric layers 114B to 114D, conductive layers 112C and 112D, and physically contacts conductive layer 112B. Conductive via 124E electrically couples conductive layer 112B to conductive trace 130C. Figure 3 In the illustrated embodiment, conductive vias 124A-124E extend partially into respective ones of conductive layers 112A-112D. In other embodiments, one or more conductive vias 124A-124E may extend completely through respective conductive layers 112A-112D.

[0152] In some embodiments, conductive trace 130B may represent a bottom electrode (e.g., a capacitor electrode at a lower potential) of deep trench capacitor 121, and conductive trace 130C may represent a top electrode (e.g., a capacitor electrode at a higher potential) of deep trench capacitor 121. Although in some embodiments, these directions may be reversed.

[0153] Further references Figure 3 In some embodiments, the interconnect structure 152 of some conductive features near the edge 101 of the semiconductor device 100 forms a seal ring structure 132. Figure 3In the illustrated embodiment, the seal ring structure 132 includes the conductive via 124A and the conductive line 130A. In some embodiments, the seal ring structure 132 extends along the edge 101 of the semiconductor device 100 and surrounds an inner portion of the semiconductor device 100 in a plan view.

[0154] Figure 4 An embodiment having a plurality of deep trench capacitors 121 in the substrate 102 is shown, and exemplary electrical connections between the deep trench capacitors 121 are shown. Figure 4 In the embodiment, there is a deep trench capacitor 121 in the first region 600, and another deep trench capacitor 121 in the second region 602. Each deep trench capacitor 121 is formed as described above, and may be formed simultaneously.

[0155] In some embodiments, two adjacent deep trench capacitors 121 are electrically coupled such that conductive trace 130B (e.g., bottom electrode) of deep trench capacitor 121 is coupled together through trace 134B of deep trench capacitor 121, and conductive trace 130C (e.g., top electrode) is coupled together through trace 134A. Thus, in this configuration, deep trench capacitors 121 are coupled in parallel and can provide a greater effective capacitance according to design requirements. In some embodiments, the conductive trace 130B of deep trench capacitor 121 (e.g., bottom electrode) is coupled together through trace 134B of deep trench capacitor 121, and conductive trace 130C (e.g., top electrode) is coupled together through trace 134A. Figure 3 and Figure 4 Interconnect structure 152 is shown in which more dielectric layers with more embedded conductive features are formed to implement lines 134A and 134B.

[0156] Figure 5 Shows the Figure 3 and Figure 4 The structure is further processed to complete the interconnect structure 152. Figure 5 In the embodiment, one or more dielectric layers having embedded conductive properties are formed between the dielectric layer 128 and the conductive lines 130A to 130C to connect the conductive lines 130A to 130C to a desired configuration. Figure 5 In the embodiment of the present invention, a dielectric layer 140 is formed on one or more dielectric layers and has a conductive trace 142 embedded therein. The conductive trace 142 can be electrically coupled to the underlying conductive features to achieve the desired electrical configuration. The overlying dielectric layers and conductive features can be similar to the dielectric layers 122, 126, and 128, and the conductive traces 130A to 130C described above, and will not be repeated here.

[0157] Further in Figure 5In the embodiment, contact pads 144 are formed on interconnect structures 152. Contact pads 144 are in electrical contact with one or more corresponding conductive lines 142. In some embodiments, contact pads 144 may include a conductive material such as aluminum, copper, tungsten, silver, gold, combinations thereof, etc. In some embodiments, the conductive material may be formed on interconnect structures 152 using, for example, physical vapor deposition, atomic layer deposition, electrochemical plating, electroless plating, combinations thereof, etc. Subsequently, the conductive material is patterned to form contact pads 144. In some embodiments, the conductive material may be patterned using suitable lithography and etching methods.

[0158] Further in Figure 5 In the embodiment of the present invention, a passivation layer 146 is formed on the interconnect structure 152 and the contact pad 144. In some embodiments, the passivation layer 146 may include one or more layers of non-photo-patternable insulating materials, one or more layers of photo-patternable insulating materials, combinations thereof, and the like. The non-photo-patternable insulating materials may include silicon nitride, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), combinations thereof, and the like, and the non-photo-patternable insulating materials may be formed using chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating processes, combinations thereof, and the like. The photo-patternable insulating materials may include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), combinations thereof, and the like, and the photo-patternable insulating materials may be formed using a spin coating process, and the like. In some embodiments, protection layer 146 has a thickness between about 5 nanometers and about 50 nanometers.

[0159] In some embodiments, openings are formed in the protection layer 146 to respectively expose portions of the contact pads 144. In some embodiments, suitable photolithography and etching methods may be used to pattern the protection layer 146. In some embodiments, the openings have a width between about 500 nanometers and about 5000 nanometers.

[0160] Further in Figure 5, the formation of underbump metallizations (UBMs) 148 above contact pads 144 is shown. In some embodiments, each underbump metallization 148 may include multiple layers of conductive materials, such as titanium layers, copper layers, and nickel layers. However, those with ordinary knowledge in the art will recognize that there are many materials and suitable arrangements of layers suitable for forming underbump metallizations 148, such as chrome / chrome-copper alloy / copper / gold arrangements, titanium / titanium-tungsten / copper arrangements, or copper / nickel / gold arrangements. Any suitable material or material layer that can be used for underbump metallization 148 is fully intended to be included within the scope of the present disclosure.

[0161] The formation of the under bump metallization 148 may include a mask layer (not shown) formed over the protective layer 146. In some embodiments, the mask layer includes a photoresist, or the like, and is patterned to form an opening in the mask layer. In some embodiments where the mask layer includes a photoresist, the patterning process may include a suitable lithography method. The opening exposes the opening in the protective layer 146.

[0162] After the mask layer forms the opening, a conductive layer is formed on the mask layer, and the sidewalls and bottom of the combined opening of the mask layer and the protective layer 146. In some embodiments, the conductive layer includes titanium, copper, nickel, chromium, gold, tungsten, alloys thereof, multilayers thereof, etc., and the conductive layer can be formed using physical vapor deposition, atomic layer deposition, chemical vapor deposition, electrochemical plating, electroless plating, combinations thereof, etc. In some embodiments, the conductive layer has a thickness between about 5 nanometers and about 100 nanometers.

[0163] After forming the conductive layer, the mask layer and the portion of the conductive layer formed on the mask layer are removed. The remaining portion of the conductive layer forms under bump metallization 148 over contact pad 144. In some embodiments where the mask layer includes photoresist, the removal process may include an ashing process followed by a wet cleaning process.

[0164] Further in Figure 5In the embodiment, conductive connectors 150 are formed on the under bump metallization 148 and electrically coupled to the under bump metallization 148. In some embodiments, each conductive connector 150 can be a solder ball, a controlled collapse chip connection (C4) bump, a ball grid array (BGA) ball, a micro bump, a bump formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG) technology, a copper pillar, a combination thereof, etc. In some embodiments where the conductive connectors 150 are formed of solder material, a reflow process can be performed to shape the solder material into a desired bump shape. In some embodiments, after the conductive connectors 150 are formed, the semiconductor device 100 is diced to form individual semiconductor devices. The dicing process may include sawing, laser ablation methods, etching processes, combinations thereof, etc. Each individual semiconductor device may then be tested to identify known good dies (KGDs) for further processing.

[0165] Figure 6 FIG. 1 shows a cross-sectional view of a semiconductor device 100 according to some embodiments. Figures 1 to 5 The embodiment shown is similar. The details in this embodiment similar to the previously described embodiment will not be repeated here.

[0166] In this embodiment, a conductive through via 160 is formed through the substrate 102 and / or the interconnect structure 152 to provide the ability to electrically couple the semiconductor device 100 to adjacent devices (e.g., devices above and below the semiconductor device 100). In some embodiments, the conductive through via 160 is formed only through the substrate 102 and is coupled to the interconnect structure 152, and can be coupled to other devices using the conductive features of the interconnect structure and the conductive connector 150. In some embodiments, the conductive through via 160 is formed through the substrate 102 and the interconnect structure 152, and can be coupled to other devices using the conductive connector 150. The conductive through via 160 can be formed by patterning a hole in the substrate 102 and / or the interconnect structure, and forming a conductive material in the hole. The conductive material can be formed by a process similar to that described above for the conductive features in the interconnect structure 152, and will not be repeated here.

[0167] although Figures 1 to 6 The formation of semiconductor device 100 with deep trench capacitors is shown, but the disclosure is not limited thereto. In some embodiments, semiconductor device 100 is formed to include other types of capacitors, such as metal oxide metal (MOM) capacitors, metal insulator metal (MIM) capacitors, etc., or combinations thereof.

[0168] Figures 7 to 15 Cross-sectional views of various intermediate stages of fabrication of a semiconductor package 200 are shown in accordance with some embodiments. The semiconductor package 200 will incorporate one or more semiconductor devices 100 . Figure 7 A carrier substrate 170 and a semiconductor device 100 bonded to the carrier substrate 170 are shown.

[0169] The semiconductor device 100 in this embodiment includes a deep trench capacitor 121 in each semiconductor device 100. Figure 7 As shown, the semiconductor device 100 bonded to the carrier substrate 170 has a conductive through hole 160 extending through the semiconductor device 100. In addition, the conductive through hole 160 and the conductive connector 150 (see, for example, Figure 8 and Fig. 9 ) is a deep trench capacitor 121 for coupling different semiconductor devices 100 in parallel and provides the semiconductor package 200 with an effective capacitance that may be larger than that of a single semiconductor device 100.

[0170] The carrier substrate 170 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 170 may be a wafer so that a plurality of semiconductor devices 100 may be bonded to different regions in the carrier substrate 170 at the same time. In some embodiments, an adhesive layer (not shown) such as a release layer is used to bond the semiconductor device 100 to the carrier substrate 170. The release layer may be formed of a polymer-based material that may be removed from an overlying structure to be formed in a subsequent step along with the carrier substrate 170. In some embodiments, the release layer is an epoxy-based thermal-release material (e.g., a light-to-heat-conversion (LTHC) release coating) that loses its adhesive properties when heated. In other embodiments, the release layer may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to ultraviolet light. The release layer may be dispensed in the form of a liquid and cured, may be a laminate film laminated on the carrier substrate 170, or may be the like. The top surface of the release layer may be leveled and may have a high degree of coplanarity.

[0171] exist Figure 8 In the present invention, an underfill 172 is formed on the bonded semiconductor device 100, and another semiconductor device 100 is bonded to the already bonded semiconductor device 100. The underfill 172 is formed on the already bonded semiconductor device 100. The underfill 172 may be formed of liquid epoxy, deformable gel, silicon rubber, non-conductive film, polymer, polybenzoxazole (PBO), polyimide, solder resist, or a combination thereof. The underfill 172 provides structural support for the subsequently bonded conductive connector 150 and may be deposited on the semiconductor device 100. In some embodiments, the underfill 172 is formed to leave an opening on the semiconductor device 100.

[0172] Figure 8Also shown is another semiconductor device 100, which is bonded to the top side of the already bonded semiconductor device 100. The semiconductor device 100 may be placed over the bonded semiconductor device 100 using, for example, a pick-and-place tool.

[0173] After the semiconductor device 100 is placed over the bonded semiconductor device 100 , the semiconductor device 100 is mechanically and electrically bonded to the underlying semiconductor device 100 through the conductive connector 150 , via the conductive through via 160 , and the contact pad 144 .

[0174] In some embodiments, the conductive connector 150 is coated with a flux (not shown), such as a no-clean flux, before being joined to the conductive connector 150. The conductive connector 150 may be dipped into the flux, or the flux may be sprayed onto the conductive connector 150. In another embodiment, the flux may be applied to the surfaces of the conductive through-hole 160 and the contact pad 144.

[0175] In some embodiments, after attaching the semiconductor device 100 to the underlying semiconductor device 100, before the epoxy flux reflows, while at least some epoxy portion of the epoxy flux remains, the conductive connector 150 may have an optional epoxy flux (not shown) formed thereon.

[0176] The bonding between the semiconductor devices 100 may be a solder bonding. In one embodiment, the semiconductor devices 100 are bonded to each other by a reflow process. During the reflow process, the conductive connector 150 contacts the conductive through-hole 160 and / or the contact pad 144 to physically and electrically couple the semiconductor devices 100. After the bonding process, an intermetallic compound (IMC) (not shown) may be formed at the interface of the conductive through-hole 160 and the conductive connector 150, and also at the interface between the conductive connector 150 and the contact pad 144 (not shown).

[0177] exist Fig. 9 In, repeat Figure 8 The process shown and described in is continued until a desired number of semiconductor devices 100 are bonded together in the semiconductor package 200. In addition, Fig. 9 Two semiconductor packages 200 are shown formed adjacent to each other on a carrier substrate 170. Fig. 9In the illustrated embodiment, the semiconductor package 200 includes seven stacked semiconductor devices 100. In other embodiments, based on the design requirements of the semiconductor package, the semiconductor package 200 may have more or less than seven semiconductor devices 100. In a specific embodiment, each semiconductor device 100 may have an effective capacitance of about 10 to about 100 microFarads (μF), so that the semiconductor package 200 having seven stacked semiconductor devices 100 may have an effective capacitance of about 50 to about 10,000 microFarads.

[0178] In some embodiments, the conductive through vias 160 of the stacked semiconductor devices 100 may be substantially aligned so that the stack of conductive through vias 160 are electrically and mechanically connected together through the conductive connector 150 (and the contact pad 144 and the under bump metallization 148, if any). In this embodiment, one or more of the stacked conductive through vias 160 may be a terminal of a top electrode of an effective capacitor formed by the semiconductor package 200, and another one or more of the stacked conductive through vias 160 may be a terminal of a bottom electrode of an effective capacitor formed by the semiconductor package 200.

[0179] Fig.10 1 shows an exemplary bonding of a pair of adjacent stacked semiconductor devices 100. It should be noted that the bottom filler 172 is not shown. Fig.10 As shown, the conductive connector 150 may be coupled to the under bump metallization 148 and / or the contact pad 144 of the semiconductor device 100 to form a semiconductor package 200 that includes two or more semiconductor devices 100 stacked and electrically and mechanically coupled together.

[0180] Although each layer of semiconductor devices 100 can be individually bonded to an underlying semiconductor device 100 after each layer of semiconductor devices 100 is placed, in some embodiments, all layers of semiconductor devices 100 can be placed without bonding, and the semiconductor devices 100 are finally bonded in a single bonding process. FIG. 11 shows a process of bonding all corresponding semiconductor devices 100 of semiconductor packages 200 in a single process using a bonding head 180. The bonding head 180 can apply heat and / or pressure to bond the conductive connectors 150 to the under bump metallization 148 and / or the contact pads 144. In some embodiments, the conductive through vias 160 can transfer heat and / or pressure from the bonding head 180 to each layer of conductive connectors 150, the under bump metallization 148, and / or the contact pads 144 to help mechanically and electrically bond the semiconductor devices 100.

[0181] exist Fig.12In the embodiment, after the bonding head 180 is removed, an encapsulant 190 is formed on the semiconductor package 200 and the carrier substrate 170. The encapsulant 190 may be a molding compound, an epoxy resin, etc., and the encapsulant 190 may be applied by compression molding, transfer molding, etc. The encapsulant 190 may be formed on the carrier substrate 170 so that the conductive through vias 160 and / or the contact pads 144 of the semiconductor device 100 are buried or covered. Then, the encapsulant 190 is cured.

[0182] In some embodiments, a planarization process is performed on the sealant 190. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etc.

[0183] exist Fig.13 In the embodiment, carrier substrate de-bonding is performed to separate (debond) carrier substrate 170 from semiconductor package 200. According to some embodiments, de-bonding includes projecting light such as laser or ultraviolet light on the release layer (if present) so that the release layer decomposes under the heat of the light and carrier substrate 170 can be removed. This structure is then turned over and placed on tape 210.

[0184] In addition, Fig.13 In the embodiment of the present invention, a planarization process may be performed on the flipped structure to expose the conductive via 160 and / or the contact pad 144. The planarization process may also grind the sealant 190. After the planarization process, the top surfaces of the conductive via 160, the contact pad 144, and the sealant 190 are coplanar. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, for example, if the conductive via 160 and the contact pad 144 are already exposed, the planarization may be omitted.

[0185] The singulation process is performed by sawing along scribe line regions 218 (eg, between individual stacked semiconductor devices 100 ). Thus, singulated semiconductor packages 200 are derived from individual stacked semiconductor devices 100 on the tape 210 .

[0186] Further in Fig.14, the conductive connector 220 is formed over the conductive through via 160 and the contact pad 144 and / or the under bump metallization 148, and is electrically coupled to the conductive through via 160 and the contact pad 144 and / or the under bump metallization 148. The conductive connector 220 allows the semiconductor package 200 to be mechanically and electrically coupled to another packaging structure. The conductive connector 220 may be similar to the conductive connector 150 described above, and will not be described again herein.

[0187] Fig.15 The semiconductor package 200 is shown after having been removed from the tape 20 . Fig.16 2 shows the dimensions of the semiconductor package 200. Fig.16 , the thickness of each semiconductor device 100 from the front side to the back side is represented by H1, H2, and H3, where H1 is the thickness of the top semiconductor device 100, H2 is the thickness of the middle semiconductor device 100, and H3 is the thickness of the bottom semiconductor device 100. In some embodiments, H3 is greater than H2 and H1. In some embodiments, all thicknesses H1, H2, and H3 are equal.

[0188] exist Fig.16 In FIG. 1 , the thickness of the encapsulant above the top semiconductor device 100 is denoted by H4. In some embodiments, H1, H2, and H3 are each greater than or equal to H4. Fig.16 In the embodiment, the height of the conductive connector 150 is represented by H5 and H6, and the height of the conductive connector 220 is represented by H7. In some embodiments, H7 is greater than or equal to H5 and H6.

[0189] exist Fig.16 , the width of the sealant from each semiconductor device 100 to the sidewall of the sealant 190 is represented by W1, W2, and W3, where W1 is the width of the sealant from the top semiconductor device 100 to the sidewall of the sealant 190, where W2 is the width of the sealant from the middle semiconductor device 100 to the sidewall of the sealant 190, and where W3 is the width of the sealant from the bottom semiconductor device 100 to the sidewall of the sealant 190. In some embodiments, W3 is greater than W2 and W1. In some embodiments, all thicknesses W1, W2, and W3 are equal.

[0190] Figures 17 to 20 1 shows a cross-sectional view of an intermediate step during the manufacturing process of a semiconductor package 300 according to some embodiments. In addition to the semiconductor package 300 of this embodiment including a redistribution structure 350, Figures 17 to 20 The example is similar to Figures 1 to 16 The details of this embodiment similar to those of the previously described embodiment will not be repeated here.

[0191] Fig.17 shows a similar Fig.13 The intermediate stages of the process described in , and the description of the intermediate stages forming this process is not repeated here. Fig.17 In, with Fig.13 In contrast to the embodiment of FIG. 1 , after the carrier substrate 170 is peeled off, the encapsulated stack of the semiconductor device 100 is bonded flipped over and bonded to a second carrier substrate 310 relative to the tape.

[0192] The carrier substrate 310 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 310 may be a wafer so that a plurality of semiconductor devices 100 may be bonded to different regions of the carrier substrate 310 at the same time. In some embodiments, an adhesive layer (not shown) such as a release layer is used to bond the semiconductor device 100 to the carrier substrate 310. The release layer may be formed of a polymer-based material, which may be removed from an overlying structure to be formed in a subsequent step together with the carrier substrate 310. In some embodiments, the release layer is an epoxy-based thermal release material (e.g., a light-to-heat conversion (LTHC) release coating) that loses its adhesive properties when heated. In other embodiments, the release layer may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to an ultraviolet lamp. The release layer may be dispensed and cured in the form of a liquid, may be a laminated film laminated on the carrier substrate 310, or may be the like. The top surface of the release layer may be horizontal and may have a high degree of flatness.

[0193] In addition, Fig.17 In the embodiment of the present invention, a planarization process may be performed on the flipped structure to expose the conductive via 160 and / or the contact pad 144. The planarization process may also grind the sealant 190. After the planarization process, the top surfaces of the conductive via 160, the contact pad 144, and the sealant 190 are coplanar. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, for example, if the conductive via 160 and the contact pad 144 are already exposed, the planarization may be omitted.

[0194] exist Fig.18In the embodiment of the present invention, a front-side redistribution structure 350 is formed on the stack of the encapsulant 190 and the semiconductor device 100. The front-side redistribution structure 350 includes dielectric layers 320, 324 and 328, and metallization patterns 322 and 326. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The front-side redistribution structure 350 is shown as an example having two metallization pattern layers. More or fewer dielectric layers and metallization patterns may be formed in the front-side redistribution structure 350. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

[0195] As an example of forming the front side redistribution structure 350, a dielectric layer 320 may be deposited on the stack of the encapsulant 190 and the semiconductor device 100. In some embodiments, the dielectric layer 320 is formed of a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc., which may be patterned using a lithography mask. The dielectric layer 320 may be formed by spin coating, lamination, chemical vapor deposition, etc., or a combination thereof. Then, the dielectric layer 320 is patterned. The patterning forms an opening that exposes a portion of the conductive through hole 160 and / or the contact pad 144. The patterning may be performed by an acceptable process, such as when the dielectric layer 320 is a photosensitive material, by exposing the dielectric layer 320 to light or by etching using, for example, anisotropic etching. If the dielectric layer 320 is a photosensitive material, the dielectric layer 320 may be developed after exposure.

[0196] Then, a metallization pattern 322 is formed. The metallization pattern 322 includes a line portion (also referred to as a conductive line) extending on and along the major surface of the dielectric layer 320. The metallization pattern 322 also includes a conductive via portion (also referred to as a conductive via) extending through the dielectric layer 320 to connect to the conductive through hole 160 and / or the contact pad 144. As an example of forming the metallization pattern 322, a seed layer is formed on the dielectric layer 320 and in the opening extending through the dielectric layer 320. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on the titanium layer. The seed layer can be formed using, for example, physical vapor deposition. Then, a photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 322. The pattern forms an opening through the photoresist to expose the seed layer. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electrochemical plating, electroless plating, etc. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the underlying portion of the seed layer forms a metallization pattern 322. The portion of the photoresist and the seed layer where the conductive material is not formed is removed. The photoresist can be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma, etc.). Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

[0197] Then, a dielectric layer 324 is deposited on the metallization pattern 322 and the dielectric layer 320. The dielectric layer 324 can be formed in a manner and with materials similar to those used to form the dielectric layer 320.

[0198] Then, a metallization pattern 326 is formed. The metallization pattern 326 includes a line portion extending on and along the main surface of the dielectric layer 324. The metallization pattern 326 also includes a conductive via portion extending through the dielectric layer 324 to connect to the metallization pattern 322. The metallization pattern 326 can be formed in a manner and material similar to that of the metallization pattern 322. In some embodiments, the metallization pattern 326 has a different size from the metallization pattern 322. For example, the conductive lines and / or conductive vias of the metallization pattern 326 can be wider or thicker than the conductive lines and / or conductive vias of the metallization pattern 322. In addition, the metallization pattern 326 can be formed to have a larger pitch than the metallization pattern 322.

[0199] Then, a dielectric layer 328 is deposited on the metallization pattern 326 and the dielectric layer 324. The dielectric layer 328 may be formed in a manner and using materials similar to those used to form the dielectric layer 320.

[0200] exist Fig.19 In the embodiment, carrier substrate de-bonding is performed to separate (debond) carrier substrate 310 from semiconductor package 300. According to some embodiments, de-bonding includes projecting light such as laser or ultraviolet light on the release layer (if present) so that the release layer decomposes under the heat of the light and carrier substrate 310 can be removed. This structure is then turned over and placed on tape 330.

[0201] The singulation process is performed by sawing along the scribe line regions 332 (eg, between the stack of individual semiconductor devices 100 ). Thus, singulated semiconductor packages 300 are obtained from the individual stacked semiconductor devices 100 on the tape 330 .

[0202] Further in Fig.19 , the conductive connector 334 is formed on the redistribution structure 350 and is electrically coupled to the redistribution structure 350. The conductive connector 334 allows the semiconductor package 300 to be mechanically and electrically coupled to another packaging structure. An under bump metallization (not shown) may also be formed before the conductive connector 334 to electrically couple the conductive connector 334 to the metallization pattern of the redistribution structure 350. These under bump metallizations may be similar to the under bump metallization 148 described above and are not described again herein. The conductive connector 334 may be similar to the conductive connector 150 described above and are not described again herein.

[0203] Fig. 20 The semiconductor package 300 is shown having been removed from the tape 330 . Fig. 20 The dimensions of the semiconductor package 300 are also shown. Fig. 20 In FIG. 3 , the height of the redistribution structure 350 is denoted by H8, and the height of the encapsulant 190 of the semiconductor package 300 is denoted by H9. In some embodiments, H9 is greater than H8. Fig. 20 In FIG. 1 , the width of the semiconductor device 100 from the outer wall to the outer wall is represented by W4. Fig. 20 In the embodiment, the width of the bottom filler 172 from the outer sidewall to the outer sidewall is represented by W5. In some embodiments, W4 is greater than W5. In some embodiments, W5 is greater than W4. In some embodiments, W4 is equal to W5.

[0204] Figure 21 to Figure 29A cross-sectional view is shown of an intermediate step in the process of forming a package 700 according to some embodiments. Details regarding this embodiment that are similar to previously described embodiments will not be repeated here.

[0205] Figures 21 to 28 4 shows a cross-sectional view of an intermediate step in the process of forming a package 400 (which may be a package or a passive package) according to some embodiments. Fig.21 In the embodiment, a carrier substrate 402 is provided, and a release layer 404 is formed on the carrier substrate 402. The carrier substrate 402 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 402 may be a wafer, so that a plurality of packages may be formed on the carrier substrate 402 at the same time.

[0206] Release layer 404 may be formed of a polymer-based material that can be removed from an overlying structure to be formed in a subsequent step along with carrier substrate 402. In some embodiments, release layer 404 is an epoxy-based thermal release material (e.g., a light-to-heat conversion (LTHC) release coating) that loses its adhesive properties when heated. In other embodiments, the release layer may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to an ultraviolet lamp. The release layer may be dispensed and cured in the form of a liquid, may be a laminated film laminated on carrier substrate 402, or may be the like. The top surface of release layer 404 may be horizontal and may have a high degree of flatness.

[0207] exist Fig.214, modules 410 and 412 (sometimes referred to as bare die 410 and 412) and semiconductor package 200 are bonded to release layer 404 by adhesive 406. Although two modules 410 and 412 are shown bonded, it should be understood that more or fewer modules 410 and / or 412 may be bonded to release layer 404. For example, three or four modules 410 and / or 412 may be bonded to release layer 404. In some embodiments, modules 410 and / or 412 are integrated circuit dies, and may be logic dies (e.g., central processing unit, microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) die, sensor dies, micro-electro-mechanical-system (MEMS) die, signal processing dies (e.g., digital signal processing (DSP) die), front-end dies (e.g., analog front-end (AFE) die), etc., or a combination thereof. In some embodiments, modules 410 and / or 412 may be passive devices, such as integrated passive devices (IPDs), or discrete passive devices. In some embodiments, modules 410 and / or 412 may be power supply modules, memory modules, voltage regulator modules, integrated passive devices (IPDs), etc., or a combination thereof.In one embodiment, module 410 is a system-on-a-chip (SoC) and module 412 is a high bandwidth memory module. Moreover, in some embodiments, modules 410 and / or 412 may have different sizes (e.g., different heights and / or surface areas), and in other embodiments, modules 410 and / or 412 may have the same size (e.g., the same height and / or surface area). In the following with respect to. Fig. 22 Modules 410 and / or 412 are described in more detail.

[0208] In some embodiments, a back-side redistribution structure may be formed on the release layer 404 before the modules 410 and 412 and the semiconductor package 200 are bonded together, so that the modules 410 and 412 and the semiconductor package 200 are bonded to the back-side redistribution structure. In one embodiment, the back-side redistribution structure includes one or more dielectric layers, wherein the dielectric layers have one or more metallization patterns (sometimes referred to as redistribution layers or redistribution lines). In some embodiments, a dielectric layer without a metallization pattern is formed on the release layer before the modules 410 and 412 and the semiconductor package 200 are bonded to the dielectric layer.

[0209] Fig. 22 One of the modules 410 / 412 is shown according to some embodiments. The modules 410 / 412 will be packaged in subsequent processing to form an integrated circuit package. The modules 410 / 412 can be formed on a wafer, which can include different device areas that are separated in subsequent steps to form multiple active device dies. The modules 410 / 412 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the modules 410 / 412 include a semiconductor substrate 413, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 413 can include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used. The semiconductor substrate 413 has an active surface (e.g., at Fig. 22 The upward-facing surface in the middle is sometimes called the front-side, and the inactive surface (e.g., Fig. 22 The downward-facing surface of the membrane is sometimes called the back-side.

[0210] Device 414 may be formed on the front side of semiconductor substrate 413. Device 414 may be an active element (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc. Interlayer dielectric (ILD) 416 is formed on the front side of semiconductor substrate 413. Interlayer dielectric 416 surrounds and may cover device 414. Interlayer dielectric 416 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0211] Conductive plugs 418 extend through the interlayer dielectric 416 to electrically and physically couple the device 414. For example, when the device 414 is a transistor, the conductive plugs 418 can couple the gates and source / drain regions of the transistor. The conductive plugs 418 can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or a combination thereof. An interconnect structure 419 is included on the interlayer dielectric 416 and the conductive plugs 418. The interconnect structure 419 interconnects the devices 414 to form an integrated circuit. The interconnect structure 419 can be formed by, for example, a metallization pattern in a dielectric layer on the interlayer dielectric 416. The metallization pattern includes metal lines and conductive vias formed in one or more low-k dielectric layers. The metallization pattern of the interconnect structure 419 is electrically coupled to the device 414 through the conductive plugs 418.

[0212] Modules 410 / 412 also include pads 420 (e.g., aluminum pads) in which external connections are made. Pads 420 are on the active side of modules 410 / 412, such as in and / or on interconnect structures 419. One or more passivation films 422 are located on modules 410 / 412, such as on portions of interconnect structures 419 and pads 420. Openings extend through passivation films 422 to pads 420. Die connectors 424 (e.g., conductive posts (e.g., formed of a metal such as copper)) extend through the openings in passivation films 422 and are physically and electrically coupled to corresponding ones of pads 420. For example, die connectors 424 may be formed by plating, etc. The die connectors 424 electrically couple corresponding integrated circuits of modules 410 / 412.

[0213] Optionally, solder areas (e.g., solder balls or solder bumps) may be provided on pad 420. Solder balls may be used to perform chip probe (CP) testing on module 410 / 412. A chip probe test may be performed on module 410 / 412 to determine whether module 410 / 412 is a known good die (KGD). Therefore, only modules 410 / 412 that are known good die undergo subsequent processing and are packaged, while bare die that fail the chip probe test are not packaged. After testing, the solder area may be removed in a subsequent processing step.

[0214] The dielectric layer 426 may be on the front side of the module 410 / 412, for example, on the protective film 422 and the bare die connector 424. The dielectric layer 426 laterally encapsulates the bare die connector 424, and the dielectric layer 426 laterally coterminous the module 410 / 412. Initially, the dielectric layer 426 may bury the bare die connector 424 so that the uppermost surface of the dielectric layer 426 is above the uppermost surface of the bare die connector 424. In some embodiments where the solder region is disposed on the bare die connector 424, the dielectric layer 426 may also bury the solder region. Alternatively, the solder region may be removed before the dielectric layer 426 is formed.

[0215] The dielectric layer 426 may be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.; a nitride, such as silicon nitride, etc.; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; etc., or a combination thereof. The dielectric layer 426 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, during the formation of the module 410 / 412, the bare die connector 424 is exposed through the dielectric layer 426. In some embodiments, the bare die connector 424 remains covered and is exposed in the subsequent process of packaging the module 410 / 412. Exposing the bare die connector 424 may remove any solder area that may be present in the bare die connector 424.

[0216] In some embodiments, the module 410 / 412 is a stacked device including a plurality of semiconductor substrates 413. For example, the module 410 / 412 may be a memory device including a plurality of memory die, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. In such an embodiment, the module 410 / 412 includes a plurality of semiconductor substrates 413 interconnected by through-substrate vias (TSVs). Each semiconductor substrate 413 may have an interconnect structure 419.

[0217] Adhesive 406 is located on the backside of module 410 / 412 and semiconductor package 200 and adheres module 410 / 412 and semiconductor package 200 to release layer 404. Adhesive 406 can be any suitable adhesive, epoxy, die attach film (DAF), etc. Adhesive 406 can be applied to the backside of module 410 / 412 and semiconductor package 200, such as to the backside of a corresponding semiconductor wafer, or can be applied on the surface of carrier substrate 402. Module 410 / 412 can be singulated, for example, by sawing or dicing, and adhered to release layer 404 through adhesive 406 using, for example, a pick and place tool.

[0218] exist Fig.23 In the embodiment of the present invention, an encapsulant 430 is formed on and around the module 410 / 412 and the semiconductor package 200. After being formed, the encapsulant 430 encapsulates the module 410 / 412 and the semiconductor package 200. The encapsulant 430 can be a molding compound, an epoxy resin, etc. The encapsulant 430 can be applied by compression molding, transfer molding, etc., and can be formed on the carrier substrate 402 so that the module 410 / 412 and the semiconductor package 200 are covered or covered. The encapsulant 430 is further formed in the gap regions between the module 410 / 412 and the semiconductor package 200. The encapsulant 430 can be applied in a liquid or semi-liquid form and then cured.

[0219] exist Fig.24In the embodiment of the present invention, a planarization process is performed on the encapsulant 430 to expose the bare die connector 424, the conductive connector 220, and the dielectric layer 426. The planarization process may also remove material of the dielectric layer 426, the conductive connector 220, and / or the bare die connector 424 until the conductive connector 220 and the bare die connector 424 are exposed. After the planarization process, the top surfaces of the conductive connector 220, the bare die connector 424, the dielectric layer 426, and the encapsulant 430 may be flush with each other (e.g., coplanar). The planarization process may be, for example, a chemical mechanical polishing (CMP) process, a grinding process, an etch-back process, etc. In some embodiments, for example, if the bare die connector 424 and the conductive connector 220 are already exposed, the planarization process may be omitted.

[0220] exist Figure 25 to Figure 27 In the redistribution structure 456 (see Fig. 27 ) has a fine-featured portion 452 and a coarse-featured portion 454 formed on the encapsulant 430 and the module 410 / 412 and the semiconductor package 200. The redistribution structure 456 includes a metallization pattern, a dielectric layer, and under-bump metallization (UBMs). The metallization pattern may also be referred to as a redistribution layer or a redistribution line. The redistribution structure 456 is shown as an example having a four-layer metallization pattern. More or fewer dielectric layers and metallization patterns may be formed in the redistribution structure 456. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated. The fine-featured portion 452 and the coarse-featured portion 454 of the redistribution structure 456 include metallization patterns and dielectric layers of different sizes.

[0221] Fig.25 An example of a fine feature portion 452 forming a redistribution structure 456 is shown. Fig.25 4, dielectric layer 432 is deposited on encapsulant 430, dielectric layer 426, conductive connector 220, and bare die connector 424. In some embodiments, dielectric layer 432 is formed of a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc., which can be patterned using a lithography mask. Dielectric layer 432 can be formed by spin coating, lamination, chemical vapor deposition, etc., or a combination thereof.

[0222] Then, the dielectric layer 432 is patterned and a metallization pattern 434 is formed. The patterning forms openings that expose portions of the conductive connector 220 and the bare die connector 424. The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 432 to light or by etching using, for example, anisotropic etching when the dielectric layer 432 is a photosensitive material. If the dielectric layer 432 is a photosensitive material, the dielectric layer 432 can be developed after exposure.

[0223] Then, a metallization pattern 434 is formed. The metallization pattern 434 has a line portion (also referred to as a conductive line or trace) extending on and along the major surface of the dielectric layer 432, and the metallization pattern 434 has a conductive via portion (also referred to as a conductive via) extending through the dielectric layer 432 to physically and electrically couple to the bare die connector 424 of the module 410 / 412 and the conductive connector 220 of the semiconductor package 200. As an example, the metallization pattern 434 can be formed by forming a seed layer on the dielectric layer 432 and in the opening extending through the dielectric layer 432. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD) or the like. Then, a photoresist is formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 434. The pattern forms an opening through the photoresist to expose the seed layer. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electrochemical plating, electroless plating, etc. The conductive material can include a metal, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the underlying portion of the seed layer forms the metallization pattern 434. The portion where the conductive material is not formed on the photoresist and the seed layer is removed. The photoresist can be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma, etc.). Once the photoresist is removed, an acceptable etching process (such as by wet etching or dry etching) is used to remove the exposed portion of the seed layer.

[0224] Then, a dielectric layer 436 is deposited over the metallization pattern 434 and the dielectric layer 432. The dielectric layer 436 can be formed in a manner similar to the formation of the dielectric layer 432 and can be formed from materials similar to the formation of the dielectric layer 432.

[0225] Then, the dielectric layer 436 is patterned and a metallization pattern 438 is formed. The pattern forms an opening that exposes a portion of the metallization pattern 434. The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 436 to light or by etching using, for example, anisotropic etching when the dielectric layer 436 is a photosensitive material. If the dielectric layer 436 is a photosensitive material, the dielectric layer 436 can be developed after exposure.

[0226] Then, a metallization pattern 438 is formed. The metallization pattern 438 has a line portion extending over and along a major surface of the dielectric layer 436, and the metallization pattern 438 has a conductive via portion extending through the dielectric layer 436 to be physically and electrically coupled to the metallization pattern 434. The metallization pattern 438 may be formed in a manner similar to that of the metallization pattern 434, and may be formed using a material similar to that of the metallization pattern 434. Although the fine feature portion 452 is shown to include two dielectric layers and two metallization patterns, any number of dielectric layers and metallization patterns may be formed in the fine feature portion 452.

[0227] The fine feature portion 452 of the redistribution structure 456 includes dielectric layers 432 and 436; and metallization patterns 434 and 438. In some embodiments, the dielectric layers 432 and 436 are formed of the same dielectric material and are formed with the same thickness. Likewise, in some embodiments, the conductive features of the metallization patterns 434 and 438 are formed of the same conductive material and are formed with the same thickness. Specifically, the dielectric layers 432 and 436 have a thickness T2, such as in the range of about 1 micrometer (μm) to about 40 micrometers, and the conductive features of the metallization patterns 434 and 438 have a thickness T1, such as in the range of about 1 micrometer to about 40 micrometers.

[0228] Fig.26 An example of a coarse feature portion 454 forming a redistribution structure 456 is shown. Fig.26 In the embodiment of the present invention, dielectric layer 440 can be deposited on metallization pattern 438 and dielectric layer 436. Dielectric layer 440 can be formed in a manner similar to that of dielectric layer 432 and can be formed of materials similar to that of dielectric layer 432.

[0229] The dielectric layer 440 may be patterned and then a metallization pattern 442 may be formed. The metallization pattern 442 may have a line portion extending over and along a major surface of the dielectric layer 440, and the metallization pattern 442 may have a conductive via portion extending through the dielectric layer 440 to be physically and electrically coupled to the metallization pattern 438. The metallization pattern 442 may be formed in a manner similar to that of the metallization pattern 434 and may be formed using materials similar to those used to form the metallization pattern 434.

[0230] Then, a dielectric layer 444 is deposited on the metallization pattern 442 and the dielectric layer 440. The dielectric layer 444 can be formed in a manner similar to the formation of the dielectric layer 432 and can be formed of similar materials as the dielectric layer 432 is formed.

[0231] exist Fig.26 , patterning the dielectric layer 444, and then forming the metallization pattern 446. The dielectric layer 444 may be patterned in a manner similar to the patterning of the dielectric layer 432. The metallization pattern 446 has a line portion extending over and along the major surface of the dielectric layer 444, and the metallization pattern 446 has a conductive via portion extending through the dielectric layer 444 to be physically and electrically coupled to the metallization pattern 442. The metallization pattern 446 may be formed in a manner similar to that of the metallization pattern 434, and may be formed with a material similar to that of the metallization pattern 434.

[0232] Then, a dielectric layer 448 is deposited on the metallization pattern 446 and the dielectric layer 444. The dielectric layer 448 may be formed in a manner similar to the formation of the dielectric layer 432 and may be formed of a material similar to the formation of the dielectric layer 432. Although the coarse feature portion 454 is shown as including three dielectric layers and two metallization patterns, any number of dielectric layers and metallization patterns may be formed in the coarse feature portion 454. In some embodiments, the fine feature portion 452 and the coarse feature portion 454 may each include three dielectric layers and three metallization patterns.

[0233] The coarse feature portion 454 of the redistribution structure 456 includes dielectric layers 440, 444, and 448; and metallization patterns 442 and 446. In some embodiments, the dielectric layers 440, 444, and 448 are formed of the same dielectric material and are formed with the same thickness. Similarly, in some embodiments, the conductive features of the metallization patterns 442 and 446 are formed of the same conductive material and are formed with the same thickness. Specifically, the dielectric layers 440, 444, and 448 have a thickness T4, such as in the range of about 1 micron to about 40 microns, and the conductive features of the metallization patterns 442 and 446 have a thickness T3, such as in the range of about 1 micron to about 40 microns. In various embodiments, the thickness T3 can be greater than the thickness T1 (see Fig.25 ), and the thickness T4 may be greater than the thickness T2 (see Fig.25 ).

[0234] Due to the thickness of the metallization pattern included in coarse feature portion 454 and fine feature portion 452, coarse feature portion 454 can have a lower resistance than fine feature portion 452. Due to the lower resistance, coarse feature portion 454 can be used to route power lines. Fine feature portion 452 can be used to route signal lines, which do not require lower resistance. Including both coarse feature portion 454 and fine feature portion 452 allows power lines and signal lines to be routed while minimizing the thickness of redistribution structure 456.

[0235] exist Fig. 27 In the embodiment of the present invention, a pad 450 is formed on the dielectric layer 448 and in the opening of the dielectric layer 448 leading to the metallization pattern 446. The pad 450 is used to couple to the conductive connector 458 and can be referred to as under bump metallurgies (UBMs) 450. The under bump metallurgies 450 are formed as external connections for the redistribution structure 456. The under bump metallization 450 has a bump portion extending on and along the main surface of the dielectric layer 448, and has a through hole portion extending through the dielectric layer 448 to physically and electrically couple the metallization pattern 446. Therefore, the under bump metallization 450 is electrically coupled to the module 410 / 412 and the semiconductor package 200. In some embodiments, the under bump metallization 450 has a different size from the metallization patterns 434, 438, 442, and 446.

[0236] As an example, the under-bump metallization 450 may be formed by forming a seed layer on the dielectric layer 448 and in an opening extending through the dielectric layer 448. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD). Then, a photoresist is formed on the seed layer and patterned. The photoresist may be formed by spin coating, etc., and may be exposed to light for patterning. The pattern of the photoresist corresponds to the under-bump metallization 450. The pattern forms an opening through the photoresist to expose the seed layer. Then, a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electrochemical plating, electroless plating, etc. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, etc. In some embodiments, the under bump metallization 450 may include an alloy such as electroless nickel, immersion gold (ENEPIG), chemical nickel gold (ENIG), etc. The combination of the conductive material and the underlying portion of the seed layer forms the under bump metallization 450. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process (e.g., using oxygen plasma, etc.). Once the photoresist is removed, an acceptable etching process (such as by wet etching or dry etching) is used to remove the exposed portion of the seed layer.

[0237] exist Fig.28 4, a conductive connector 458 is formed on the pad 450. The conductive connector 458 allows the semiconductor package 400 to be mechanically and electrically coupled to another packaging structure (e.g., Fig.29 The conductive connector 458 may be similar to the conductive connector 150 described above and will not be described again herein.

[0238] Then, in Fig.29, the semiconductor package 400 is attached to the package substrate 500 using the conductive connector 458 to form the package 700. The package substrate 500 can be made of a semiconductor material, such as silicon, germanium, diamond, etc. Alternatively, compounds such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, etc. can also be used. In addition, the package substrate 500 can be a semiconductor substrate on an insulator (SOI substrate). Typically, the semiconductor substrate on an insulator includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, semiconductor on insulator silicon germanium on insulator (SGOI), or a combination thereof. In another embodiment, the package substrate 500 is an insulating core based on, for example, a fiberglass reinforced resin core. An exemplary core material is a fiberglass resin, such as FR4. Alternative materials to the core material include bismaleimide-triazine (BT) resin, or other printed circuit board (PCB) materials or films. Build-up films such as Ajinomoto build-up film (ABF) or other laminates can be used for the package substrate 500.

[0239] The packaging substrate 500 may include active and passive components (not shown). Devices such as transistors, capacitors, resistors, combinations thereof, and the like may be used to generate the structural and functional requirements of the system design. Any suitable method may be used to form the device.

[0240] The package substrate 500 may also include a metallization layer and conductive vias 506 and bonding pads 504 and 508 coupled to the metallization layer and conductive vias 506. The metallization layer 506 may be formed over the active and passive components and is designed to connect various devices to form functional circuitry. The metallization layer 506 may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) and have conductive vias interconnecting the conductive material layers, and the metallization layer 506 may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, the package substrate 500 is substantially free of active and passive components.

[0241] The conductive connector 458 is reflowed to attach the under bump metallization 450 to the bonding pad 504. The conductive connector 458 connects the package substrate 500 (including the metallization layer 506 in the package substrate 500) to the semiconductor package 400 (including the metallization pattern of the redistribution structure 456). In some embodiments, surface mount passive devices (e.g., surface mount parts (SMD)) (not shown) can be attached to the package substrate 500, for example, to the bonding pads 504 and / or 508.

[0242] After the semiconductor package 400 is attached to the packaging substrate 500, the conductive connector 458 may have epoxy flux (not shown) formed thereon before the conductive connector 458 reflows with at least some of the epoxy resin portion of the remaining epoxy flux. This remaining epoxy flux may be used as an underfill to reduce stress and protect joints caused by the reflow of the conductive connector 458. In some embodiments, an underfill 512 may be formed between the semiconductor package 400 and the packaging substrate 500, surrounding the conductive connector 458. The underfill 512 may be formed by a capillary flow process after the semiconductor package 400 is attached or may be formed by a suitable deposition method before the semiconductor package 400 is attached.

[0243] Likewise, if Fig.29 As shown, the bonding pads 508 of the package substrate 500 may have conductive connectors 510 formed thereon. These conductive connectors 510 allow the package body 700 to be mechanically and electrically coupled to another package structure. The conductive connectors 510 may be similar to the conductive connectors 150 described above and will not be described again herein.

[0244] Although the embodiment is shown with a deep trench capacitor, the present disclosure is not limited thereto. In some embodiments, the semiconductor device includes other types of capacitors, such as metal oxide metal (MOM) capacitors, metal insulator metal (MIM) capacitors, etc., or combinations thereof.

[0245] Embodiments can achieve advantages. Embodiments include a semiconductor device, which can be an integrated passive device (IPD), including capacitors, such as deep trench capacitors (DTCs), metal-oxide-metal (MOM) capacitors, metal-insulator-metal (MIM) capacitors, etc., or a combination thereof. The semiconductor device is vertically stacked and connected to effectively form a larger semiconductor device. By vertically stacking the integrated passive components, a high-efficiency capacitor that can be used as a decoupling capacitor can be formed. Moreover, a packaging structure including one or more vertically stacked and coupled capacitors can provide a lower capacitor equivalent series resistance (ESR). In some instances, these semiconductor devices can be incorporated into a packaging structure (e.g., an integrated fan-out (INFO) packaging structure or a chip-on-wafer-on-substrate (CoWoS) packaging structure) to provide a capacitor with a large capacitance value.

[0246] According to some embodiments of the present disclosure, a semiconductor structure is provided, comprising: a first semiconductor device, a second semiconductor device, a first group of conductive connectors, a first bottom filler, a first sealant, and a second group of conductive connectors. The first semiconductor device comprises: a plurality of first capacitors, and a first conductive through hole. The second semiconductor device comprises: a plurality of second capacitors, and a second conductive through hole. The first capacitor is formed on a first substrate. The first conductive through hole extends through the first substrate, and the first conductive through hole is electrically coupled to the first capacitor. The second capacitor is formed on a second substrate. The second conductive through hole extends through the second substrate, and the second conductive through hole is electrically coupled to the second capacitor. The first group of conductive connectors mechanically and electrically joins the first semiconductor device and the second semiconductor device, and at least one of the first group of conductive connectors electrically couples the first conductive through hole and the second conductive through hole. The first bottom filler is located between the first semiconductor device and the second semiconductor device, and surrounds the first group of conductive connectors. The first sealant is located on at least the sidewalls of the first semiconductor device and the second semiconductor device and the first bottom filler. The second group of conductive connectors is electrically coupled to the first semiconductor device, and the second group of conductive connectors and the first group of conductive connectors are located on opposite sides of the first semiconductor device.

[0247] In some embodiments, the first capacitors are electrically coupled together in parallel. In some embodiments, the first capacitors and the second capacitors are electrically coupled together in parallel. In some embodiments, the second group of conductive connectors is larger than the first group of conductive connectors. In some embodiments, the first conductive through hole is mechanically and electrically coupled to at least one of the first group of conductive connectors and at least one of the second group of conductive connectors. In some embodiments, the semiconductor structure further comprises a first redistribution structure. The first redistribution structure is located on the first sealant and the first semiconductor device. The first redistribution structure comprises a plurality of dielectric layers having metallization patterns therein. The metallization pattern of the first redistribution structure is electrically coupled to the first conductive through hole and the second group of conductive connectors. In some embodiments, the semiconductor structure further comprises a third semiconductor device and a fourth semiconductor device. The third semiconductor device comprises a plurality of third capacitors and a third conductive through hole. The fourth semiconductor device comprises a plurality of fourth capacitors and a fourth conductive through hole. The third capacitor is formed on a third substrate. The third conductive through hole extends through the third substrate, and the third conductive through hole is electrically coupled to the third capacitor and the second conductive through hole. The fourth capacitor is formed on a fourth substrate. The fourth conductive through hole extends through the fourth substrate, and the fourth conductive through hole is electrically coupled to the fourth capacitor and the third conductive through hole. The third semiconductor device and the fourth semiconductor device are located on the opposite side of the second semiconductor device from the first semiconductor device. In some embodiments, the semiconductor structure also includes a first integrated circuit structure, a second sealant, and a first redistribution structure. The first integrated circuit structure includes a first integrated circuit die, and the first integrated circuit die includes an active device. The second sealant encapsulates the first integrated circuit structure, the first sealant, and the second group of conductive connectors at least laterally. The first redistribution structure is located on the second sealant, the first integrated circuit structure, and the first semiconductor device. The first redistribution structure includes a plurality of dielectric layers having a metallization pattern therein, and the metallization pattern of the first redistribution structure is electrically coupled to the first integrated circuit die and the second group of conductive connectors. In some embodiments, the semiconductor structure also includes a third group of conductive connectors and a packaging substrate. The third group of conductive connectors is located on the first redistribution structure. The packaging substrate is mechanically and electrically coupled to the first redistribution structure through the third group of conductive connectors.

[0248] According to other embodiments of the present disclosure, a packaging structure is provided, including: a first passive package, a first integrated circuit package, a first sealant, and a first redistribution structure. The first passive package includes a passive die stack. Each passive die in the passive die stack includes a plurality of passive components on a substrate and a conductive through hole extending through the substrate. The first integrated circuit package includes at least one integrated circuit die, and the at least one integrated circuit die includes a plurality of active components. The first sealant at least laterally encapsulates the first passive package and the first integrated circuit package. The first redistribution structure is located on the first sealant, the first integrated circuit package, and the first passive package, and the first redistribution structure includes a plurality of dielectric layers having metallization patterns therein, and the metallization patterns of the first redistribution structure are electrically coupled to the first integrated circuit package and the first passive package.

[0249] In some embodiments, the passive element of each passive die is a plurality of deep trench capacitors. In some embodiments, the deep trench capacitor of a first passive die in the passive die stack is electrically coupled in parallel to the deep trench capacitor of a second passive die in the passive die stack. In some embodiments, the first passive package also includes a second redistribution structure. The second redistribution structure is located at a bottommost passive die in the passive die stack, the second redistribution structure includes a plurality of dielectric layers having metallization patterns therein, the metallization patterns of the second redistribution structure are electrically coupled to the conductive through-holes of the bottommost passive die in the passive die stack, and are electrically coupled to the metallization patterns of the first redistribution structure. In some embodiments, the packaging structure also includes a first set of conductive connectors, and a packaging substrate. The first set of conductive connectors is located on the first redistribution structure. The packaging substrate is mechanically and electrically coupled to the first redistribution structure through the first set of conductive connectors.

[0250] According to some other embodiments of the present disclosure, a packaging method is provided, including forming a first passive package; forming a first semiconductor device, including: forming a plurality of first capacitors in a first substrate; and forming a first conductive through hole extending through the first substrate, the first conductive through hole being electrically coupled to the first capacitor; forming a second semiconductor device, including: forming a plurality of second capacitors in a second substrate; and forming a second conductive through hole extending through the second substrate, the second conductive through hole being electrically coupled to the second capacitor; attaching the first semiconductor device to a first carrier substrate; forming a first bottom filler on the attached first semiconductor device; bonding the second semiconductor device to the first semiconductor device with a first set of conductive connectors, the first set of conductive connectors being located in the first bottom filler, at least one of the first set of conductive connectors being electrically coupled to the first conductive through hole and the second conductive through hole; encapsulating the first semiconductor device and the second semiconductor device and the first bottom filler with a first sealant; removing the first carrier substrate; and forming a second set of conductive connectors on the first semiconductor device, the second set of conductive connectors being electrically coupled to the first semiconductor device, the second set of conductive connectors being located on opposite sides of the first semiconductor device as the first set of conductive connectors.

[0251] In some embodiments, the first capacitor and the second capacitor are electrically coupled together in parallel. In some embodiments, forming the first passive package further comprises: forming a first redistribution structure on the first sealant and the first semiconductor device, the first redistribution structure comprising a plurality of dielectric layers having a metallization pattern therein, the metallization pattern of the first redistribution structure being electrically coupled to the first conductive through hole and the second group of conductive connectors. In some embodiments, the packaging method further comprises: forming a first package, comprising: forming a first integrated circuit package, comprising at least one integrated circuit die, the at least one integrated circuit die comprising a plurality of active components; encapsulating the first passive package and the first integrated circuit package with a second sealant; and forming a first redistribution structure on the second sealant, the first integrated circuit package, and the first passive package, the first redistribution structure comprising a plurality of dielectric layers having a metallization pattern therein, the dielectric layers of the first redistribution structure being electrically coupled to the first integrated circuit package and the first passive package. In some embodiments, the packaging method further comprises: bonding the first package to a packaging substrate with a third group of conductive connectors; and forming a second bottom filler between the first package and the packaging substrate, the second bottom filler surrounding the third group of conductive connectors. In some embodiments, forming the first passive package also includes: forming a third semiconductor device, including: forming a plurality of third capacitors in a third substrate; and forming a third conductive through-hole extending through the third substrate, the third conductive through-hole electrically coupled to the third capacitor; forming a fourth semiconductor device, including: forming a plurality of fourth capacitors in a fourth substrate; and forming a fourth conductive through-hole extending through the fourth substrate, the fourth conductive through-hole electrically coupled to the fourth capacitor; forming a second bottom filler on the second semiconductor device; joining the third semiconductor device to the second semiconductor device with a third group of conductive connectors, the third group of conductive connectors being located in the second bottom filler, at least one of the third group of conductive connectors being electrically coupled to the second conductive through-hole and the third conductive through-hole; forming a third bottom filler on the third semiconductor device; and joining the fourth semiconductor device to the third semiconductor device with a fourth group of conductive connectors, the fourth group of conductive connectors being located in the third bottom filler, at least one of the fourth group of conductive connectors being electrically coupled to the third conductive through-hole and the fourth conductive through-hole.

[0252] The foregoing summarizes the features of several embodiments so that those having ordinary knowledge in the art may better understand the various aspects of the present disclosure. Those having ordinary knowledge in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those having ordinary knowledge in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: A first semiconductor device comprising: A plurality of first capacitors are formed on a first substrate; and a first conductive through hole extending through the first substrate, the first conductive through hole being electrically coupled to the first capacitor; A second semiconductor device comprising: A plurality of second capacitors are formed on a second substrate; and a second conductive through hole extending through the second substrate, the second conductive through hole being electrically coupled to the second capacitor; a first set of conductive connectors mechanically and electrically joining the first semiconductor device and the second semiconductor device, at least one of the first set of conductive connectors electrically coupling the first conductive through via and the second conductive through via; a first underfill disposed between the first semiconductor device and the second semiconductor device and surrounding the first set of conductive connectors; a first encapsulant disposed on at least sidewalls of the first semiconductor device and the second semiconductor device and the first underfill; and A second set of conductive connectors is electrically coupled to the first semiconductor device, and the second set of conductive connectors and the first set of conductive connectors are located on an opposite side of the first semiconductor device.

2. The semiconductor structure according to claim 1, wherein: The first capacitors are electrically coupled together in parallel.

3. The semiconductor structure according to claim 1, wherein: The first capacitor and the second capacitor are electrically coupled together in parallel.

4. The semiconductor structure according to claim 1, wherein: The second set of conductive connectors is larger than the first set of conductive connectors.

5. The semiconductor structure according to claim 1, wherein: The first conductive via is mechanically and electrically coupled to at least one of the first set of conductive connectors and at least one of the second set of conductive connectors.

6. The semiconductor structure of claim 1, further comprising: A first redistribution structure is located on the first encapsulant and the first semiconductor device, the first redistribution structure comprising a plurality of dielectric layers having metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first conductive through vias and the second set of conductive connectors.

7. The semiconductor structure of claim 1, further comprising: A third semiconductor device comprising: A plurality of third capacitors formed on a third substrate; and a third conductive through hole extending through the third substrate, the third conductive through hole being electrically coupled to the third capacitor and the second conductive through hole; and A fourth semiconductor device comprising: A plurality of fourth capacitors are formed on a fourth substrate; and a fourth conductive through hole extending through the fourth substrate, the fourth conductive through hole being electrically coupled to the fourth capacitor and the third conductive through hole; The third semiconductor device and the fourth semiconductor device are located on an opposite side of the second semiconductor device as the first semiconductor device.

8. The semiconductor structure of claim 1, further comprising: A first integrated circuit structure includes a first integrated circuit die, wherein the first integrated circuit die includes an active device; a second encapsulant at least laterally encapsulating the first integrated circuit structure, the first encapsulant, and the second set of conductive connectors; as well as A first redistribution structure is located on the second encapsulant, the first integrated circuit structure, and the first semiconductor device, the first redistribution structure including a plurality of dielectric layers having metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first integrated circuit die and the second set of conductive connectors.

9. The semiconductor structure of claim 8, further comprising: a third set of conductive connectors located on the first redistribution structure; as well as A packaging substrate is mechanically and electrically coupled to the first redistribution structure through the third set of conductive connectors.

10. A packaging structure, comprising: A first passive package, comprising: A passive die stack, each passive die in the passive die stack includes a plurality of passive components on a substrate and a conductive through hole extending through the substrate and electrically coupled to the passive components, wherein a first passive die in the passive die stack is electrically coupled to a second passive die in the passive die stack through a first set of conductive connectors, and at least one of the first set of conductive connectors electrically couples the conductive through hole of the first passive die and the conductive through hole of the second passive die; A first integrated circuit package includes at least one integrated circuit die, wherein the at least one integrated circuit die includes a plurality of active components; a first encapsulant at least laterally encapsulating the first passive package and the first integrated circuit package; and A first redistribution structure is located on the first sealant, the first integrated circuit package, and the first passive package body, and the first redistribution structure includes a plurality of dielectric layers having metallization patterns therein, and the metallization patterns of the first redistribution structure are electrically coupled to the first integrated circuit package and the first passive package body.

11. The package structure according to claim 10, wherein: The passive components of each passive die are multiple deep trench capacitors.

12. The package structure according to claim 11, wherein: The deep trench capacitor of the first passive die of the passive die stack is electrically coupled in parallel to the deep trench capacitor of the second passive die of the passive die stack.

13. The package structure according to claim 10, wherein: The first passive package also includes: A second redistribution structure is located on a bottommost passive die of the passive die stack, the second redistribution structure includes a plurality of dielectric layers having metallization patterns therein, the metallization patterns of the second redistribution structure are electrically coupled to the conductive through hole of the bottommost passive die of the passive die stack, and are electrically coupled to the metallization patterns of the first redistribution structure.

14. The package structure according to claim 13, further comprising: a second set of conductive connectors located on the first redistribution structure; as well as A packaging substrate is mechanically and electrically coupled to the first redistribution structure through the second set of conductive connectors.

15. A packaging method, comprising: forming a first passive packaging body; A first semiconductor device is formed, comprising: forming a plurality of first capacitors in a first substrate; and forming a first conductive through hole extending through the first substrate, wherein the first conductive through hole is electrically coupled to the first capacitor; forming a second semiconductor device, comprising: forming a plurality of second capacitors in a second substrate; and forming a second conductive through hole extending through the second substrate, the second conductive through hole being electrically coupled to the second capacitor; attaching the first semiconductor device to a first carrier substrate; forming a first underfill over the attached first semiconductor device; bonding the second semiconductor device to the first semiconductor device with a first set of conductive connectors, the first set of conductive connectors being located in the first underfill, at least one of the first set of conductive connectors electrically coupling the first conductive through via and the second conductive through via; encapsulating the first semiconductor device and the second semiconductor device and the first underfill with a first sealant; removing the first carrier substrate; and A second set of conductive connectors is formed on the first semiconductor device. The second set of conductive connectors is electrically coupled to the first semiconductor device. The second set of conductive connectors and the first set of conductive connectors are located on opposite sides of the first semiconductor device.

16. The packaging method according to claim 15, wherein: The first capacitor and the second capacitor are electrically coupled together in parallel.

17. The packaging method according to claim 15, wherein: Forming the first passive package also includes: A first redistribution structure is formed on the first encapsulant and the first semiconductor device. The first redistribution structure includes a plurality of dielectric layers having metallization patterns therein. The metallization patterns of the first redistribution structure are electrically coupled to the first conductive through vias and the second set of conductive connectors.

18. The packaging method according to claim 15, further comprising: A first package is formed, comprising: forming a first integrated circuit package, comprising at least one integrated circuit die, the at least one integrated circuit die comprising a plurality of active components; encapsulating the first passive package and the first integrated circuit package with a second encapsulant; and A first redistribution structure is formed on the second encapsulant, the first integrated circuit package, and the first passive package body, the first redistribution structure including a plurality of dielectric layers having metallization patterns therein, the dielectric layers of the first redistribution structure being electrically coupled to the first integrated circuit package and the first passive package body.

19. The packaging method according to claim 18, further comprising: bonding the first package body to a package substrate with a third set of conductive connectors; as well as A second bottom filler is formed between the first package body and the package substrate, and the second bottom filler surrounds the third group of conductive connectors.

20. The packaging method according to claim 15, wherein: Forming the first passive package also includes: forming a third semiconductor device, comprising: forming a plurality of third capacitors in a third substrate; and forming a third conductive through hole extending through the third substrate, wherein the third conductive through hole is electrically coupled to the third capacitor; forming a fourth semiconductor device, comprising: forming a plurality of fourth capacitors in a fourth substrate; and forming a fourth conductive through hole extending through the fourth substrate, wherein the fourth conductive through hole is electrically coupled to the fourth capacitor; forming a second underfill over the second semiconductor device; bonding the third semiconductor device to the second semiconductor device with a third set of conductive connectors, the third set of conductive connectors being located in the second underfill, at least one of the third set of conductive connectors electrically coupling the second conductive through via and the third conductive through via; forming a third underfill over the third semiconductor device; and The fourth semiconductor device is bonded to the third semiconductor device by a fourth set of conductive connectors, the fourth set of conductive connectors is located in the third bottom filler, and at least one of the fourth set of conductive connectors electrically couples the third conductive through via and the fourth conductive through via.

Images