Three-dimensional memory and methods of making the same

Abstract

A three-dimensional memory and a method of fabricating the same are provided. The method of fabricating the three-dimensional memory includes providing a semiconductor substrate having at least one fin; forming an isolation material in a trench of the semiconductor substrate to fill at least a portion of the trench; forming a gate layer on the fin and a blocking layer on a top surface of the gate layer; and performing a first ion implantation on the semiconductor substrate, wherein the blocking layer is configured to block ions from penetrating the gate layer during the first ion implantation.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and its fabrication method. Background Technology

[0002] Currently, in the peripheral processes of 3D NAND flash memory based on the X-tacking architecture, the requirements for the area of ​​the MOS region (such as the CMOS region) become increasingly stringent as the number of stacked layers increases. Many 3D NAND manufacturers are adopting X-FET technology to reduce the area of ​​the MOS region, which involves transforming planar memory devices into three-dimensional memory devices.

[0003] While applying X-FET technology to 3D NAND MOS processes can significantly reduce the area of ​​the MOS region, the performance requirements for MOS devices using X-FET technology are gradually increasing with the development of semiconductor technology. For example, the gate layer height is relatively large under traditional X-FET process conditions. Although the MOS region area is reduced, the large gate layer height will lead to poor MOS device performance, such as slower operating speed. In addition, simply reducing the gate layer height may seriously affect other processes. For example, during ion implantation of high-voltage devices, a thin gate layer will be largely broken down by ions.

[0004] Therefore, how to reduce the height of the gate layer without affecting other processes is one of the problems that many semiconductor designers urgently need to solve. Summary of the Invention

[0005] This application provides a method for fabricating a three-dimensional memory, the method comprising: providing a semiconductor substrate having at least one fin; forming an isolation material in a trench of the semiconductor substrate to fill at least a portion of the trench; forming a gate layer on the fin and forming a barrier layer on the top surface of the gate layer; and performing a first ion implantation on the semiconductor substrate, wherein the barrier layer is configured to prevent ions from breaking down the gate layer during the first ion implantation.

[0006] In one embodiment, the fin includes: at least one first fin with a first width; and at least one second fin with a second width, wherein the first width is greater than the second width.

[0007] In one embodiment, the semiconductor substrate includes a high-voltage device region and a low-voltage device region, with the first fin disposed in the high-voltage device region and the second fin disposed in the low-voltage device region.

[0008] In one embodiment, forming an isolation material in a trench of the semiconductor substrate to fill at least a portion of the trench includes: forming an isolation material of a first height in the trench of the semiconductor substrate in the high-voltage device region; and forming an isolation material of a second height in the trench of the semiconductor substrate in the low-voltage device region, wherein the first height is smaller than the second height.

[0009] In one embodiment, forming a gate layer on each fin and forming a barrier layer on the top surface of the gate layer includes: forming an initial gate layer on the substrate to fill the trench and cover the top surface of the plurality of fins; forming an initial barrier layer on the top surface of the initial gate layer; removing portions of the initial gate layer and the initial barrier layer to form a first gate layer on the first fin, wherein the first gate layer has a third height; forming a second gate layer on the second fin, wherein the second gate layer has a fourth height, the third height being greater than the fourth height; and forming a first barrier layer and a second barrier layer on the top surfaces of the first gate layer and the second gate layer, respectively.

[0010] In one embodiment, the initial gate layer is planarized.

[0011] In one embodiment, performing a first ion implantation on the semiconductor substrate, wherein the barrier layer is configured to prevent ions from penetrating the gate layer during the first ion implantation includes: performing a first ion implantation on the semiconductor substrate of the high-voltage device region, wherein the first barrier layer is configured to prevent ions from penetrating the first gate layer during the first ion implantation.

[0012] In one embodiment, the method further includes: performing a second ion implantation on the semiconductor substrate of the low-voltage device region, wherein the energy of the second ion is lower than the energy of the first ion.

[0013] In one embodiment, after performing a first ion implantation step on the semiconductor substrate, the method further includes removing the first barrier layer and the second barrier layer.

[0014] In one implementation, the third height is less than or equal to 440 angstroms; and the fourth height is less than or equal to 70 angstroms.

[0015] In one embodiment, the method further includes: forming a source region and a drain region in a portion of the semiconductor substrate located on both sides of the first gate layer in the high-voltage device region; and forming a source region and a drain region in a portion of the semiconductor substrate located on both sides of the second gate layer in the low-voltage device region.

[0016] In one embodiment, the gate layer includes a semiconductor layer; and the barrier layer includes a silicon nitride layer.

[0017] This application also provides a method for fabricating a three-dimensional memory. The method includes: providing a semiconductor substrate having fins, wherein the fins include a first fin disposed in a high-voltage device region of the semiconductor substrate, and a second fin disposed in a low-voltage device region of the semiconductor substrate; forming a first gate layer and a second gate layer on the first fin and the second fin, respectively, wherein the height of the second gate layer is less than the height of the first gate layer.

[0018] In one embodiment, the height of the first gate layer is less than or equal to 440 angstroms; and the height of the second gate layer is less than or equal to 70 angstroms.

[0019] In one embodiment, the width of the first fin is greater than the width of the second fin.

[0020] In one embodiment, forming a first gate layer on the first fin and forming a second gate layer on the second fin, wherein the height of the second gate layer is less than the height of the first gate layer includes: forming an isolation material of a first height in a trench of the semiconductor substrate in the high-voltage device region; forming an isolation material of a second height in a trench of the semiconductor substrate in the low-voltage device region, wherein the first height is less than the second height; forming an initial gate layer on the substrate to fill the trench and cover the top surface of the plurality of fins; removing a portion of the initial gate layer to form a first initial gate layer on the first fin; and forming a second initial gate layer on the second fin.

[0021] In one embodiment, the method further includes: performing a first ion implantation on the semiconductor substrate of the high-voltage device region, wherein the first initial gate layer is configured to prevent ions from breaking down the first initial gate layer during the first ion implantation process.

[0022] In one embodiment, the method further includes: performing a second ion implantation on the semiconductor substrate of the low-voltage device region, wherein the energy of the second ion is lower than the energy of the first ion.

[0023] In one embodiment, after performing a first ion implantation step on the semiconductor substrate, the method further includes: removing a portion of the first initial gate layer to form a first gate layer on the first fin, wherein the first gate layer has a third height; and removing a portion of the second initial gate layer to form a second gate layer on the second fin, wherein the second gate layer has a fourth height, the third height being greater than the fourth height.

[0024] In one embodiment, the method further includes: forming a source region and a drain region in a portion of the semiconductor substrate located on both sides of the first gate layer in the high-voltage device region; and forming a source region and a drain region in a portion of the semiconductor substrate located on both sides of the second gate layer in the low-voltage device region.

[0025] In one embodiment, the gate layer includes a semiconductor layer.

[0026] Another aspect of this application provides a three-dimensional memory, comprising: a semiconductor substrate having at least one fin formed on its surface, wherein the plurality of fins includes a first fin disposed in a high-voltage device region of the semiconductor substrate and a second fin disposed in a low-voltage device region of the semiconductor substrate; a first gate layer disposed on the first fin; and a second gate layer disposed on the second fin, wherein the height of the second gate layer is less than the height of the first gate layer.

[0027] In one embodiment, the height of the first gate layer is less than or equal to 440 angstroms; and the height of the second gate layer is less than or equal to 70 angstroms.

[0028] In one embodiment, the width of the first fin is greater than the width of the second fin.

[0029] In one embodiment, the three-dimensional memory further includes: an isolation material having a first height formed in a trench of the semiconductor substrate in the high-voltage device region; and an isolation material having a second height formed in a trench of the semiconductor substrate in the high-voltage device region, wherein the first height is smaller than the second height.

[0030] In one embodiment, the three-dimensional memory further includes: a source region and a drain region in a portion of the semiconductor substrate located on both sides of the first gate layer; and a source region and a drain region in a portion of the semiconductor substrate located on both sides of the second gate layer.

[0031] In one embodiment, the gate layer comprises a semiconductor layer.

[0032] In one embodiment, the three-dimensional memory further includes an isolation layer disposed between the high-voltage device region and the low-voltage device region.

[0033] The three-dimensional memory and its fabrication method provided in this application have at least one of the following advantages:

[0034] 1) By reducing the height of the gate layer in the high-voltage and low-voltage device regions on the semiconductor substrate, the performance of both regions can be effectively improved, especially the performance of the low-voltage device region can be greatly improved; and

[0035] 2) By providing a first barrier layer on the top surface of the first gate layer in the high-voltage device region, the breakdown of the first gate layer during high-energy, high-voltage first ion implantation can be effectively prevented; and

[0036] 3) By increasing the height of the first initial gate layer in the high-voltage device region, the first initial gate layer can be effectively blocked from being broken down during the first ion implantation with high energy and high voltage. After the first ion implantation is completed, part of the first initial gate layer and part of the second initial gate layer can be removed to form the first gate layer and the second gate layer. This can effectively improve the performance of the high-voltage device region and the low-voltage device region, especially greatly improve the performance of the low-voltage device region. Attached Figure Description

[0037] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0038] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0039] Figures 2 to 6 This is a process step diagram of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0040] Figure 7 This is a flowchart of a method for fabricating a three-dimensional memory according to another exemplary embodiment of this application; and

[0041] Figure 8 and Figure 9 This is a process step diagram of a method for fabricating a three-dimensional memory according to another exemplary embodiment of this application. Detailed Implementation

[0042] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0043] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0044] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0045] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0046] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a range smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can contain multiple layers.

[0047] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application.

[0048] like Figure 1 As shown, the method 1000 for fabricating a three-dimensional memory provided in this application may include: S1, providing a semiconductor substrate having at least one fin; S2, forming an isolation material in a trench of the semiconductor substrate to fill at least a portion of the trench; S3, forming a gate layer on the fin and forming a barrier layer on the top surface of the gate layer; and S4, performing a first ion implantation on the semiconductor substrate, wherein the barrier layer is configured to prevent ions from penetrating the gate layer during the first ion implantation. Steps S1 to S4 will be further described below.

[0049] Step S1

[0050] like Figure 2As shown, the materials used to fabricate the substrate 100 for the three-dimensional memory may include single-crystal silicon, polycrystalline silicon, amorphous silicon, germanium (Ge) substrate, silicon germanide (SiGe), gallium arsenide (GaAs), SOI (Silicon-on-insulator) substrate or GOI (Germanium-on-insulator), self-aligned silicide, or any other suitable material. Exemplarily, the substrate 100 may be, for example, a silicon wafer, but this application is not limited thereto. The semiconductor substrate 100 provided in this application may include a high-voltage device region 110 and a low-voltage device region 120, wherein the high-voltage device region 110 and the low-voltage device region 120 may be isolated by an isolation layer 1, for example, the high-voltage device region 110 and the low-voltage device region 120 may be separated by a shallow trench isolation structure.

[0051] This application provides a semiconductor substrate having at least one fin. For example, a plurality of fins can be formed on the semiconductor substrate 100 by etching. Exemplarily, at least one first fin 111 can be formed by etching the surface of the high-voltage device region 110 of the semiconductor substrate 100, and at least one second fin 121 can be formed by etching the surface of the low-voltage device region 120 of the semiconductor substrate 100. The first fin 111 may have a first width H1, and the second fin 121 may have a second width H2, wherein the first width H1 may be greater than the second width H2. In other words, the width of the first fin 111 in the high-voltage device region 110 may be larger than the width of the second fin 121 in the low-voltage device region 120.

[0052] Step S2

[0053] For example, forming an isolation material in a trench of a semiconductor substrate to fill at least a portion of the trench can be, for instance, forming an isolation material in a trench between multiple fins to fill at least a portion of the trench. Specifically, forming an isolation material in a trench between multiple fins to fill at least a portion of the trench may include: forming an isolation material A of a first height h1 in a trench between multiple first fins 111 in a high-voltage device region 110; and forming an isolation material A of a second height h2 in a trench between multiple second fins 121 in a low-voltage device region 120, wherein the first height h1 is smaller than the second height h2. Figure 2 As shown, the first height h1 is the vertical distance between the surface of the isolation material A in contact with the substrate 100 and the surface of the isolation material A away from the substrate 100 between the plurality of first fins 111, and the second height h2 is the vertical distance between the surface of the isolation material A in contact with the substrate 100 and the surface of the isolation material A away from the substrate 100 between the plurality of second fins 121.

[0054] Step S3

[0055] Exemplarily, forming a gate layer on the fin and forming a barrier layer on the top surface of the gate layer may include: firstly, as... Figure 3 As shown, an initial gate layer 200 can be formed on the substrate 100 to fill the trenches and cover the top surface of the plurality of fins. Then, as Figure 4 As shown, an initial barrier layer 300 can be formed on the top surface of the initial gate layer 200. Then, as... Figure 5 As shown, a portion of the initial gate layer 200 and the initial barrier layer 300 can be removed. Specifically, the purpose of removing a portion of the initial gate layer 200 and the initial barrier layer 300 is to allow both the formation of the first gate layer 210 on the first fin 111 and the formation of the second gate layer 220 on the second fin 121. The first gate layer 210 has a third height h3, and the second gate layer 220 has a fourth height h4, wherein the third height h3 is greater than the fourth height h4. A first barrier layer 310 and a second barrier layer 320 can also be formed on the top surfaces of the first gate layer 210 and the second gate layer 220, respectively. Figure 5 As shown, the third height h3 is the vertical distance between the surface of the first gate layer 210 in contact with the isolation material A and the surface of the first gate layer 210 away from the isolation material A, and the fourth height h4 is the vertical distance between the surface of the second gate layer 220 in contact with the isolation material A and the surface of the second gate layer 220 away from the isolation material A.

[0056] Due to different device requirements, the heights of the first gate layer 210 in the high-voltage device region 110 and the second gate layer 220 in the low-voltage device region 120 are different. For example, as... Figure 5 As shown, the third height h3 of the first gate layer 210 in the high-voltage device region 110 may be greater than the fourth height h4 of the second gate layer 220 in the low-voltage device region 120. Optionally, the third height h3 of the first gate layer 210 may be less than or equal to 440 angstroms, and the fourth height h4 of the second gate layer 220 may be less than or equal to 70 angstroms.

[0057] Exemplarily, the first gate layer 210 and the second gate layer 220 may include semiconductor layers, such as polysilicon layers, and the first barrier layer 310 and the second barrier layer 320 may include silicon nitride layers. For semiconductor processes with increasingly smaller feature sizes, the heights of the first gate layer 210 and the second gate layer 220 provided in this application are both relatively small; for example, the third height h3 of the first gate layer 210 may be less than or equal to 440 angstroms, and the fourth height h4 of the second gate layer 220 may be less than or equal to 70 angstroms. Exemplarily, after forming the initial gate layer 200 on the substrate 100 and before forming the initial barrier layer 300 on the top surface of the initial gate layer 200, the initial gate layer 200 may also be planarized.

[0058] Step S4

[0059] Performing a first ion implantation on a semiconductor substrate, wherein a barrier layer is configured to prevent ions from penetrating the gate layer during the first ion implantation process, may include: performing a first ion implantation on the semiconductor substrate 100 of the high-voltage device region 110, wherein a first barrier layer 310 may be configured to prevent ions from penetrating the first gate layer 210 during the first ion implantation process. Since the relatively short first gate layer 210 in the high-voltage device region 110 is insufficient to effectively act as an ion implantation barrier layer during high-energy ion implantation, this application introduces a first barrier layer 310 to effectively block high-energy ion implantation, preventing unintended ions from penetrating the first gate layer 210 and affecting device performance. It should be understood that the material and height of the first barrier layer 310 can be adjusted according to the gate process and ion implantation conditions. During the first ion implantation process in the high-voltage device region 110, the first ion implantation in the low-voltage device region 120 can also be blocked by a second barrier layer 220, or by using photoresist or other methods.

[0060] For example, after the first ion implantation is performed on the high-voltage device region 110, a second ion implantation can be performed on the semiconductor substrate 100 of the low-voltage device region 120, wherein the energy of the second ion is lower than that of the first ion.

[0061] Exemplarily, after performing a first ion implantation step on the semiconductor substrate 100, the method further includes: removing the first barrier layer 310 and the second barrier layer 320 to form as shown in the figure. Figure 6 The structure of the three-dimensional memory is shown. For example, in the high-voltage device region 110 and the low-voltage device region 120, the first barrier layer 310 and the second barrier layer 320 made of silicon nitride material can be removed by etching processes such as phosphoric acid wet etching.

[0062] During the second ion implantation process in the low-voltage device region 120, the second ion implantation can also be performed simultaneously in the high-voltage device region 110, or the second ion implantation can be blocked by using photoresist or other methods. This embodiment forms lightly doped drain (LDD) regions in both the high-voltage device region 110 and the low-voltage device region 120 through two ion implantation processes with different energies, effectively integrating high-voltage and low-voltage device processes in the same device fabrication process. Furthermore, the fabrication method of this application can also be used in other process technologies such as CMOS wafer fabrication for 3D NAND, similarly addressing the problem that existing processes cannot effectively block high-energy, high-voltage, low-doped drain ion implantation by the gate structure, and addressing the issue of improving the performance of the low-voltage device region by reducing the gate structure height. It should also be noted that although a first blocking layer 310 is introduced in this application to block high-voltage, low-doped drain ion implantation, this application does not specifically limit the blocked ion implantation process to high-voltage, low-doped drain ion implantation; it should be understood that it can also be any other high-energy implantation process with a relatively thin gate layer.

[0063] Exemplarily, the fabrication of a three-dimensional memory may further include forming source and drain regions in the portion of the semiconductor substrate 100 located on both sides of the first gate layer 210 in the high-voltage device region 110; and forming source and drain regions in the portion of the semiconductor substrate 100 located on both sides of the second gate layer in the low-voltage device region 120. Optionally, the source and drain regions can be formed by ion implantation, and self-aligned metal silicide layers can be formed in the source and drain regions. Furthermore, after the above processes, conventional back-end processes can be used to further form structures such as interlayer dielectric layers, contact hole structures, and metal wiring layers to achieve electrical connection between the high-voltage device region and the low-voltage device region.

[0064] Figure 7 This is a flowchart of a method for preparing a three-dimensional memory according to another exemplary embodiment of this application, 2000.

[0065] like Figure 7 As shown, the fabrication method 2000 of the three-dimensional memory provided in this application may include: S1', providing a semiconductor substrate with fins, wherein the fins include a first fin disposed in a high-voltage device region of the semiconductor substrate, and a second fin disposed in a low-voltage device region of the semiconductor substrate; S2', forming a first gate layer and a second gate layer on the first fin and the second fin respectively, wherein the height of the second gate layer is less than the height of the first gate layer. For the sake of brevity, some descriptions similar to those above will be omitted below, and step S2' will be further described.

[0066] Step S2 '

[0067] Forming a first gate layer on a first fin; and forming a second gate layer on a second fin, wherein the height of the second gate layer is less than the height of the first gate layer, may include: First, refer to Figure 2 As shown, a first height H1 of insulating material A can be formed in the grooves between the plurality of first fins 111. Then, similarly, refer to... Figure 2 As shown, a separating material A with a second height H2 can be formed in the grooves between multiple second fins 121, wherein the first height H1 may be smaller than the second height H2. Then, as... Figure 8 As shown, an initial gate layer 200' can be formed on the substrate 100 to fill the trenches and cover the top surface of the multiple fins. The initial gate layer 200' can have a large height. Finally, as... Figure 9 As shown, a portion of the initial gate layer 200' can be removed to form a first initial gate layer 10 on the first fin 121; and a second initial gate layer 20 is formed on the second fin 121. The first initial gate layer 10 and the second initial gate layer 20 have a large height.

[0068] After the formation of the first initial gate layer 10 and the second initial gate layer 20, the semiconductor substrate 100 of the high voltage device region 110 can be subjected to a first ion implantation, wherein the first initial gate layer 10 can be configured to prevent ions from breaking down the first initial gate layer 10 during the first ion implantation process.

[0069] After performing a first ion implantation step on the semiconductor substrate 100, the method further includes: removing a portion of the first initial gate layer 10 and a portion of the second initial gate layer 20 to form a structure as shown in the figure. Figure 6 The three-dimensional memory structure is shown. Specifically, a portion of the first initial gate layer 10 is removed to form a first gate layer 210 on the first fin 111, wherein the first gate layer 210 has a third height h3; and a portion of the second initial gate layer 20 is removed to form a second gate layer 220 on the second fin 121, wherein the second gate layer 220 has a fourth height h4, and the third height h3 may be greater than the fourth height h4.

[0070] For example, a second ion implantation can also be performed on the semiconductor substrate 100 of the low-voltage device region 120, wherein the energy of the second ion is lower than that of the first ion.

[0071] Exemplarily, the fabrication of a three-dimensional memory may further include forming source and drain regions in the portion of the semiconductor substrate 100 located on both sides of the first gate layer 210 in the high-voltage device region 110; and forming source and drain regions in the portion of the semiconductor substrate 100 located on both sides of the second gate layer in the low-voltage device region 120. Optionally, the source and drain regions can be formed by ion implantation, and self-aligned metal silicide layers can be formed in the source and drain regions. Furthermore, after the above processes, conventional back-end processes can be used to further form structures such as interlayer dielectric layers, contact hole structures, and metal wiring layers to achieve electrical connection between the high-voltage device region and the low-voltage device region.

[0072] This application also provides a three-dimensional memory. Specifically, see reference... Figure 6 A schematic diagram of the structure of a three-dimensional memory according to an exemplary embodiment of this application is shown.

[0073] like Figure 6 As shown, the three-dimensional memory may include a semiconductor substrate 100, a first gate layer 210, and a second gate layer 220.

[0074] At least one fin may be formed on the surface of the semiconductor substrate 100, wherein the plurality of fins include a first fin 111 disposed in the high voltage device region 110 of the semiconductor substrate 100, and a second fin 121 disposed in the low voltage device region 120 of the semiconductor substrate 100. The width of the first fin 111 is greater than the width of the second fin 121.

[0075] A first gate layer 210 may be disposed on the first fin. The height of the first gate layer 210 may be less than or equal to 440 angstroms. The first gate layer 210 may include a semiconductor layer.

[0076] A second gate layer 220 may be disposed on the second fin, wherein the height of the second gate layer is less than the height of the first gate layer. The height of the second gate layer 220 may be less than or equal to 70 angstroms. The second gate layer 220 may include a semiconductor layer.

[0077] In an exemplary embodiment, the three-dimensional memory may further include: an isolation material having a first height and an isolation material having a second height. The isolation material having the first height may be formed in a groove between a plurality of first fins. The isolation material having the second height may be formed in a groove between a plurality of second fins, wherein the first height is smaller than the second height.

[0078] In an exemplary embodiment, the three-dimensional memory may further include: a source region and a drain region in a portion of a semiconductor substrate located on both sides of a first gate layer; and a source region and a drain region in a portion of a semiconductor substrate located on both sides of a second gate layer.

[0079] In an exemplary embodiment, the three-dimensional memory may further include an isolation layer disposed between the high-voltage device region and the low-voltage device region.

[0080] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A semiconductor substrate having fins is provided, wherein the fins include a first fin disposed in a high-voltage device region of the semiconductor substrate and a second fin disposed in a low-voltage device region of the semiconductor substrate; A first initial gate layer and a second initial gate layer are formed on the first fin and the second fin, respectively, wherein the height of the first initial gate layer is greater than the height of the second initial gate layer; A first ion implantation is performed on the semiconductor substrate of the high-voltage device region, wherein the first initial gate layer is configured to prevent ions from breaking down the first initial gate layer during the first ion implantation process; as well as After performing a first ion implantation step on the semiconductor substrate, a portion of the first initial gate layer located on the top surface of the first fin and a portion of the second initial gate layer located on the top surface of the second fin are removed along a first direction to form a first gate layer and a second gate layer on the first fin and the second fin, respectively, wherein the height of the second gate layer is less than the height of the first gate layer, the height of the first gate layer is less than or equal to 440 angstroms, and the height of the second gate layer is less than or equal to 70 angstroms; wherein the height of the first gate layer is the dimension of the first gate layer along the first direction, the semiconductor substrate extends along a second direction perpendicular to the first direction, the first gate layer and the second gate layer distributed along the second direction are discontinuous, and the first gate layer covers a portion of the isolation material located in the semiconductor substrate along the second direction.

2. The preparation method according to claim 1, characterized in that, The width of the first fin is greater than the width of the second fin.

3. The preparation method according to claim 1, characterized in that, A first initial gate layer and a second initial gate layer are formed on the first fin and the second fin, respectively, including: An isolation material of a first height is formed in the trench of the semiconductor substrate in the high-voltage device region; An isolation material of a second height is formed in a trench of the semiconductor substrate in the low-voltage device region, wherein the first height is smaller than the second height; An initial gate layer is formed on the substrate to fill the trench and cover the top surface of the plurality of fins; Remove part of the initial gate layer to The first initial gate layer is formed on the first fin; and The second initial gate layer is formed on the second fin.

4. The preparation method according to claim 1, characterized in that, The method further includes: performing a second ion implantation on the semiconductor substrate of the low-voltage device region, wherein the energy of the second ion is lower than that of the first ion.

5. The preparation method according to claim 1, characterized in that, The method further includes: A source region and a drain region are formed in the portion of the semiconductor substrate located on both sides of the first gate layer in the high-voltage device region; and A source region and a drain region are formed in the portion of the semiconductor substrate located on both sides of the second gate layer in the low-voltage device region.

6. The preparation method according to any one of claims 1-5, characterized in that, The gate layer includes a semiconductor layer.

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