Memory device, memory integrated circuit, and method of manufacturing the same

Abstract

Provided are a memory device, a memory integrated circuit, and a method of manufacturing a memory device. The memory device includes a composite bottom electrode, a top electrode, and a resistive variable layer disposed between the composite bottom electrode and the top electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed on top of the first bottom electrode. The sidewall of the second bottom electrode is recessed laterally with respect to the sidewall of the first bottom electrode layer and the sidewall of the resistive variable layer.

Description

Technical Field

[0001] The present disclosure relates to a memory device, a memory integrated circuit, and a method of manufacturing the same. Background Art

[0002] Many modern electronic devices include an electronic memory configured to store data. The electronic memory may be a volatile memory or a non-volatile memory. The volatile memory stores data when powered, while the non-volatile memory can store data even when the power is removed. Resistive random access memory (RRAM) has become a potential candidate for the next-generation non-volatile memory technology due to its simple structure and its compatibility with the complementary metal-oxide-semiconductor (CMOS) logic circuit manufacturing process. Summary of the Invention

[0003] In one aspect of the present disclosure, a memory device is provided. The memory device includes a composite bottom electrode, a top electrode, and a resistive variable layer disposed between the composite bottom electrode and the top electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed on the first bottom electrode. The sidewall of the second bottom electrode is recessed laterally relative to the sidewall of the first bottom electrode layer and the sidewall of the resistive variable layer.

[0004] In another aspect of the present disclosure, a memory integrated circuit is provided. The memory integrated circuit includes a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. The plurality of memory cells are arranged in an array. Each of the plurality of memory cells includes a memory device, and the memory device includes a composite bottom electrode, a top electrode, a resistive variable layer disposed between the composite bottom electrode and the top electrode, and a passivation layer covering the top electrode, the resistive variable layer, and the composite bottom electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed on the first bottom electrode. The sidewall of the second bottom electrode is recessed laterally relative to the sidewall of the first bottom electrode and the sidewall of the resistive variable layer. The plurality of bit lines extend along a first direction. The plurality of word lines extend along a second direction intersecting the first direction. Each of the memory devices is electrically connected between one of the plurality of bit lines and one of the plurality of word lines.

[0005] In yet another aspect of the present disclosure, a method of manufacturing a memory device is provided. The method includes: sequentially forming a first bottom electrode layer, a second bottom electrode layer, a resistive variable material layer, a top electrode layer, and a hard mask layer over a device substrate; patterning the hard mask layer to form a hard mask; using the hard mask as a mask to pattern the top electrode layer, pattern the resistive variable material layer, pattern the second bottom electrode layer, and pattern the first bottom electrode layer; and causing the second bottom electrode layer to be recessed laterally relative to the patterned resistive variable material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 is a flowchart illustrating a method of manufacturing a memory device according to some embodiments of the present disclosure.

[0008] Figures 2A to 2I is at Figure 1 schematic cross-sectional views of structures at various stages during the method of manufacturing the memory device shown in

[0009] Figure 3A is an equivalent circuit diagram illustrating a memory integrated circuit according to some embodiments of the present disclosure.

[0010] Figure 3B is illustrating Figure 3A a schematic view of one of the memory cells shown in

[0011] Figures 4A to 4C schematic cross-sectional views of structures at various stages during the method of manufacturing a memory device according to some embodiments of the present disclosure.

[0012] Figure 5A and Figure 5B is at Figure 4C schematic cross-sectional views of structures at various stages during the method of manufacturing the memory cell shown in

[0013] Figure 6A and Figure 6B are schematic cross-sectional views illustrating a memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The following disclosure provides numerous different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, the present disclosure may reuse reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or feature illustrated in a figure and another (other) element or feature. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and likewise, the spatially relative descriptive terms used herein may be interpreted accordingly.

[0016] It should be understood that the following embodiments of the present disclosure provide applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments are intended to provide further illustration and not to limit the scope of the present disclosure.

[0017] Figure 1 is a flowchart illustrating a method of manufacturing a memory device according to some embodiments of the present disclosure. Figures 2A to 2I is in Figure 1 schematic cross-sectional views of structures at various stages during the method of manufacturing the memory device shown in. In some embodiments, the method of manufacturing a memory device includes the following steps.

[0018] Referring to Figure 1 and Figure 2A , step S100 is performed, and a device substrate 100 is provided. In some embodiments, the device substrate 100 is a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer, and the device substrate 100 is pre-formed with a plurality of electronic devices (not shown) and an interconnect structure located above the electronic devices ( Figure 2A partially shown in). It should be noted that Figure 2AOnly the top portion of the interconnect structure including the conductive trace 102 is illustrated, and other portions of the interconnect structure and the electronic devices are omitted for simplicity. The electronic devices may include active devices and / or passive devices. For example, the active devices may include field effect transistors, diodes, similar devices, or combinations thereof, while the passive devices may include resistors, capacitors, similar devices, or combinations thereof. Additionally, the interconnect structure may include a combination of conductive traces and vias. The electronic devices and the interconnect structure formed in the device substrate 100 together with the structures to be formed over the device substrate 100 in the following steps constitute an integrated circuit, such as a memory integrated circuit. In some embodiments, the memory integrated circuit is a resistive random access memory (RRAM) integrated circuit. As Figure 2A shown, the top portion of the interconnect structure includes conductive traces 102 that are laterally spaced apart from each other. The material of the conductive traces 102 may include Al, Cu, Ti, TiN, Ta, TaN, W, similar materials, or combinations thereof. Additionally, the conductive traces 102 may be formed in a dielectric layer 104. The material of the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant dielectric material (e.g., a dielectric material having a dielectric constant of about 1.5 or less), similar materials, or combinations thereof. In some embodiments, the top surface of the conductive traces 102 is substantially coplanar with the top surface of the dielectric layer 104. Further, a passivation pattern 106 may be disposed over the conductive traces 102 and the dielectric layer 104. The passivation pattern 106 has openings 106a that respectively expose a portion of the underlying conductive traces 102. The memory cells MU (as Figure 2G shown) to be formed in the following steps may extend into these openings 106a to be electrically connected to the conductive traces 102. The material of the passivation layer pattern 106 may include silicon carbide, silicon oxynitride, silicon carbonitride, silicon nitride, similar materials, or combinations thereof.

[0019] Refer to Figure 1 and Figure 2B , step S102 is performed, and a stack of a bottom electrode layer 108, a bottom electrode layer 110, a resistive variable material layer 112, and a top electrode layer 114 is sequentially formed over the device substrate 100. In some embodiments, the bottom electrode layer 108, the bottom electrode layer 110, the resistive variable material layer 112, and the top electrode layer 114 are conformally formed over the device substrate 100. Thus, at least the bottom electrode layer 108 and the bottom electrode layer 110 extend into the openings 106a (as Figure 2AAs shown in [reference], the top surfaces of the bottom electrode layer 108 and the bottom electrode layer 110, the top surface of the resistive variable layer 112, and the top surface of the top electrode layer 114 may be recessed at positions corresponding to the opening 106a. Additionally, in some embodiments, the bottom electrode layer 110 has sufficient etch selectivity with respect to the resistive variable material layer 112 and the top electrode layer 114, and the patterning of the bottom electrode layer 110 and the patterning of the resistive variable material layer 112 and the top electrode layer 114 can be performed in different steps by selecting a suitable etchant (as shown in Figure 2E and Figure 2F shown). Similarly, the bottom electrode layer 110 may also have sufficient etch selectivity with respect to the bottom electrode layer 108, and the bottom electrode layer 108 and the bottom electrode layer 110 can be patterned in different etching steps by selecting a suitable etchant (as shown in Figure 2F and Figure 2G shown). For example, the material of the bottom electrode layer 108 may include titanium nitride, tantalum nitride, tungsten, titanium, tantalum, similar materials, or combinations thereof. On the other hand, the material of the bottom electrode layer 110 may include ruthenium, iridium, platinum, or combinations thereof. Additionally, the material of the resistive variable layer 112 may include tantalum oxide, hafnium oxide, tantalum aluminum oxide (TaAlO), similar materials, or combinations thereof, and the material of the top electrode layer 114 may include titanium nitride, tantalum nitride, tungsten, titanium, tantalum, similar materials, or combinations thereof. Furthermore, the thickness of the bottom electrode layer 108 may be in the range of to . The thickness of the bottom electrode layer 110 may be in the range of to . The thickness of the resistive variable layer 112 may be in the range of to . The thickness of the top electrode layer 114 may be in the range of to . In addition, the formation methods of the bottom electrode layers 108 and 110 and the formation method of the top electrode layer 114 may respectively include deposition processes, such as atomic layer deposition (ALD) processes. Additionally, the formation method of the resistive variable layer 112 may include a chemical vapor deposition (CVD) process.

[0020] Refer to Figure 1 and Figure 2C , perform step S104, and sequentially form a hard mask layer 116 and a photoresist pattern 118 on the top electrode layer 114. In some embodiments, the hard mask layer 116 is globally formed on the structure shown in Figure 2B . The hard mask layer 116 can be patterned in the following processes (such as Figure 2DDuring the period shown in (e.g., the top electrode layer 114) to protect the underlying layer from being damaged. In some embodiments, the hard mask layer 116 is formed with a thickness large enough such that the hard mask layer 116 may have a substantially flat top surface. In an alternative embodiment, a planarization process (e.g., a chemical mechanical polishing (CMP) process, an etching process, a grinding process, or a combination thereof) may be performed on the initially formed hard mask layer to form a hard mask layer 116 having a substantially flat top surface. In addition, in some embodiments, the bottom portion of the hard mask layer 116 may protrude downward into a recess in the top surface of the top electrode layer 114. The material of the hard mask layer 116 may include silicon carbide, silicon oxynitride, silicon carbonitride, silicon nitride, similar materials, or a combination thereof, and the thickness of the hard mask layer 116 may be in the range of to . In addition, the method of forming the hard mask layer 116 may include a CVD process or a solution process (e.g., a spin coating process). On the other hand, the photoresist pattern 118 defines the position, size, and shape of the hard mask 120 (as shown in Figure 2D ) to be formed in the following steps. The photoresist pattern 118 may be made of a photosensitive material and may have a thickness in the range of to . In addition, the method of forming the photoresist pattern 118 may include a solution process (e.g., a spin coating process) and a photolithography process.

[0021] As will be described with reference to Figures 2D to 2G , in some embodiments, the hard mask layer 116, the top electrode layer 114, the resistive variable material layer 112, and the bottom electrode layer 110 and the bottom electrode layer 108 are patterned in multiple steps.

[0022] Referring to Figure 1 and Figure 2D , step S106 is performed, and the hard mask layer 116 is patterned using the photoresist pattern 118 as a mask to form the hard mask 120. The hard mask 120 stands on the top electrode layer 114 and may also be used as a mask for patterning the underlying top electrode layer 114, the resistive variable material layer 112, and the bottom electrode layer 110 and the bottom electrode layer 108 in the following steps (as shown in Figures 2E to 2G ). In some embodiments, the patterning process for forming the hard mask 120 includes an anisotropic etching process. In these embodiments, the width of the hard mask 120 may gradually increase toward the underlying top electrode layer 114. In addition, the hard mask 120 may have sufficient etching selectivity with respect to the underlying top electrode layer 114, and the top electrode layer 114 may be used as an etch stop layer during the formation of the hard mask 120. In terms of the top view of the hard mask, as in Figure 2DAs shown in the region surrounded by the dashed line, the top view shape of the hard mask 120 is substantially rectangular or oval, and the hard masks 120 are arranged in an array. However, those skilled in the art can modify the top view shape and arrangement of the hard mask 120 according to the design requirements, and the present disclosure is not limited thereto. In some embodiments, after the hard mask 120 is formed, the photoresist pattern 108 is removed by, for example, an ashing process or a stripping process.

[0023] Refer to Figure 1 and Figure 2E , step S108 is performed, and the top electrode layer 114 and the resistive variable material layer 112 are patterned to form the top electrode 122 and the resistive variable layer 124. In some embodiments, the patterning process for forming the top electrode 122 and the resistive variable layer 124 uses the overlying hard mask 120 as a mask instead of using a photoresist pattern defined by a lithography process. In these embodiments, such a patterning process can be regarded as a self-aligned patterning process. The obtained stacks (each including the hard mask 120 and one of the underlying top electrode 122 and resistive variable layer 124) stand on the bottom electrode layer 110, and can also be used as a mask for patterning the bottom electrode layer 110 and the bottom electrode layer 108 in the following steps (as shown in Figure 2F and Figure 2G ). In some embodiments, the patterning process for forming the top electrode 122 and the resistive variable layer 124 includes an anisotropic etching process. In these embodiments, the width of the above stack can gradually increase towards the underlying bottom electrode layer 110. Additionally, the bottom electrode layer 110 can have sufficient etching selectivity relative to the resistive variable layer 124 and the top electrode 122, and the bottom electrode layer 110 can be used as an etch stop layer when forming the top electrode 122 and the resistive variable layer 124. In some embodiments, the hard mask 120 can be thinned during the formation of the top electrode 122 and the resistive variable layer 124. For example, the thinned hard mask 120 has a thickness in the range of to .

[0024] Refer to Figure 1 and Figure 2F , step S110 is performed, and the bottom electrode layer 110 is patterned to form the bottom electrode 126. Each of the bottom electrodes 126 is located between one of the bottom electrode layers 108 and the overlying resistive variable layer 124, and the sidewall 126S of the bottom electrode 126 is recessed and concave laterally from the sidewall 124S of the resistive variable layer 124. In some embodiments, an isotropic etching process is used to perform the patterning of the bottom electrode layer 110 to form the bottom electrode 126. When the bottom electrode layer 108 is relative to the bottom electrode 126 (or as Figure 2EIn these embodiments where the bottom electrode layer 110 shown has sufficient etch selectivity, the bottom electrode layer 108 can be used as an etch stop layer during the isotropic etching process. Additionally, a stack including a hard mask 120 and one of the underlying top electrode 122 and the resistive variable layer 124 is used as a mask during the isotropic etching process to remove the portion of the bottom electrode layer 110 that is not covered by the stack. Further, during the isotropic etching process, the portion of the bottom electrode layer 110 covered by the above stack is etched further in the lateral direction such that the formed bottom electrode 126 is recessed laterally and reduced in size compared to the pattern of the overlying stack. As shown in the enlarged view (i.e., Figure 2F the region surrounded by the dashed line in), the sidewall 126S is recessed from the sidewall 124S (recessed from the sidewall of the overlying stack), and the sidewall 126S has a curved surface. From the enlarged view, the most recessed portion (the most indented portion) of the recessed sidewall 126S of the bottom electrode 126 is close to the bottom surface of the resistive variable layer 124 because during the isotropic etching process, the portion of the bottom electrode layer 110 closer to the bottom surface of the resistive variable layer 124 (i.e., the upper portion) can be exposed to the etchant for a longer time than the portion of the bottom electrode layer 110 farther from the bottom surface of the resistive variable layer 124 (i.e., the lower portion). Since the bottom electrode 126 has its most indented portion (i.e., the portion most etched laterally) close to the resistive variable layer 124, it can be ensured that the possible leakage paths along the sidewalls of the top electrode 122 and the resistive variable layer 124 do not extend to the sidewall of the bottom electrode 126. In some embodiments, when measuring the recess depth RD of the bottom electrode 126 from the extension line (dotted line) along the sidewall of the overlying stack to the curved surface of the sidewall 126S, the recess depth RD can gradually decrease from the top surface to the bottom surface of the bottom electrode 126. As an alternative, the sidewall 126S of the bottom electrode 126 can be an inclined sidewall. The sidewall 126S of the bottom electrode 126 can be adjusted by tuning the process parameters of the isotropic etching process, and the present disclosure is not limited thereto. In some embodiments, the recess depth RD of the bottom electrode 126 can be in the range of to , while the thickness T of the bottom electrode 126 126 can be in the range of to . In these embodiments where the recess depth RD decreases downward, the maximum value of the recess depth RD can be in the range of to , while the minimum value of the recess depth RD can be in the range of to Within a range. Additionally, in some embodiments, the etchant for the isotropic etching process used to form the bottom electrode 126 is different from the etchant for the anisotropic etching process used to form the hard mask 120, the top electrode 122, and the variable resistance layer 124 (as referenced Figure 2D and Figure 2E as described). For example, when the material of the bottom electrode 126 includes ruthenium, the etchant for the isotropic etching process may include oxygen. On the other hand, the etchant for the anisotropic etching process used to form the hard mask 120 may include fluorine, fluorocarbons (e.g., CH 2 F 2 , CF 4 , CHF 3 , etc.), carbon-sulfur compounds (e.g., SF 6 , etc.), similar etchants, or combinations thereof, and the etchant for the anisotropic etching process used to form the hard mask 120, the top electrode 122, and the variable resistance layer 124 may include chlorine compounds or bromine compounds (e.g., Cl 2 , HBr, BCl 3 , etc.).

[0025] Referencing Figure 1 and Figure 2G , step S112 is performed, and the bottom electrode layer 108 is patterned to form the bottom electrode 128. Each bottom electrode 128 and the overlying bottom electrode 126 may be collectively regarded as the composite bottom electrode 130. The composite bottom electrode 130 is electrically connected to an electronic device (not shown) through an interconnection structure (e.g., including conductive traces 102) formed in the device substrate 100. In some embodiments, the patterning process used to form the bottom electrode 128 includes an anisotropic etching process that uses the overlying stack as a mask. In these embodiments, the patterning process used to form the bottom electrode 128 can be regarded as a self-alignment process. Additionally, the stack used as a mask may respectively include the variable resistance layer 124, the top electrode 122, and the hard mask 120. The sidewall 128S of each bottom electrode 128 may extend along the extension direction of the sidewalls of the overlying stack in these stacks. Since the sidewall 126S of the bottom electrode 126 is recessed laterally from the sidewalls of these overlying stacks, the sidewall 126S of the bottom electrode 126 can now be recessed and indented laterally from the sidewall 128S of the underlying bottom electrode 128 patterned using these stacks as a mask. Additionally, as shown in an enlarged view (i.e., Figure 2GAs shown in the region surrounded by the dashed line, in these embodiments where the recess depth of the bottom electrode 126 decreases downward, the area of the top surface of each bottom electrode 126 can be smaller than the area of the underlying bottom electrode 128, while the area of the bottom surface of each bottom electrode 126 can be close to or substantially the same as the area of the underlying bottom electrode 128. In some embodiments, the etchant for the anisotropic etching process used to form the bottom electrode 128 is different from the isotropic etching process used to form the bottom electrode 126 (as described in the reference Figure 2F ). For example, the etchant for the anisotropic etching used to form the bottom electrode 128 can include halogen chemicals (e.g., CF 4 , Cl 2 , BCl 3 , HBr, etc.), while the etchant for the isotropic etching used to form the bottom electrode 126 can include oxygen when the material of the bottom electrode 126 includes ruthenium. In some embodiments, the portion of the passivation pattern 106 not covered by the above stacks is thinned, while the thickness of other portions of the passivation pattern 106 located under these stacks can remain unchanged. In these embodiments, the step height H 106 between different portions of the passivation pattern 106 can be in the range of to . Additionally, in some embodiments, the hard mask 120 is also thinned during the formation of the bottom electrode 128. Those skilled in the art can adjust the amount of thickness reduction of the hard mask 120 by tuning the process parameters of the anisotropic etching process, as long as the thinned hard mask 120 still covers the underlying top electrode 122. The present disclosure is not limited to the described amount of thickness reduction of the hard mask 120.

[0026] Thus far, a plurality of memory cells MU are formed over the device substrate 100. Each memory cell MU includes a top electrode 122, a composite bottom electrode 130, and a resistive variable layer 124 located between the top electrode 122 and the composite bottom electrode 130. Additionally, each memory cell MU can further include a hard mask 120 disposed over the top electrode 122. In some embodiments, the memory cells MU are disposed over the passivation pattern 106 and can be considered to penetrate through the passivation pattern 106 and be in electrical contact with the conductive traces 102.

[0027] Reference Figure 1 and Figure 2H, step S114 is performed, and a passivation layer 132, a dielectric layer 134, and a dielectric layer 136 are sequentially formed over the device substrate 100 and the memory cell MU. In some embodiments, the passivation layer 132 is conformally formed over the device substrate 100 and the memory cell MU. In this way, the exposed surfaces of the passivation pattern 106 and the memory cell MU are currently covered by the passivation layer 132. In certain embodiments, the passivation layer 132 does not physically contact the bottom electrode 126. In these embodiments, an air gap AG may be formed between each bottom electrode 126 and the passivation layer 132. The air gap AG may surround the bottom electrode 126 respectively. The dielectric layer 134 is formed over the passivation layer 132. In some embodiments, the recesses defined between adjacent memory cells MU are filled with the dielectric layer 134, and the portion of the passivation layer 132 located above the memory cell MU may be covered by the dielectric layer 134. Additionally, in some embodiments, a planarization process may be performed on the dielectric layer 134 so that the dielectric layer 134 may have a substantially flat top surface. The dielectric layer 136 is formed over the dielectric layer 134, and the dielectric layer 136 may also have a substantially flat top surface. The material of the passivation layer 132 may include silicon carbide, silicon oxynitride, silicon carbonitride, silicon nitride, similar materials, or a combination thereof, while the materials of the dielectric layers 134 and 136 may include silicon oxide, a low-k dielectric material (e.g., a dielectric material having a dielectric constant of about 1.5 or less), similar materials, or a combination thereof. Additionally, the method for forming the passivation layer 132 may include a CVD process, while the methods for forming the dielectric layers 134 and 136 may include a CVD process or a solution process (e.g., a spin coating process).

[0028] Reference Figure 1 and Figure 2I , step S116 is performed, and vias 138 and conductive traces 140 are formed. The vias 138 penetrate the dielectric layer 134, the passivation layer 132, and the hard mask 120 to electrically connect to the top electrode 122. In some embodiments, the bottom surface of the via 138 may protrude downward into the recess at the top surface of the top electrode 122. The conductive traces 140 are formed in the dielectric layer 136, and the conductive traces 140 are in electrical contact with the underlying vias 138 respectively. In some embodiments, the conductive traces 140 are in Figure 3AIt is used as a bit line in the memory integrated circuit exemplarily shown. In some embodiments, the materials of the vias 138 and the conductive traces 140 may include copper, aluminum, aluminum-copper alloy, similar materials, or combinations thereof. Additionally, in some embodiments, the vias 138 and the conductive traces 140 may be formed by a dual-damascene process. In these embodiments, vias and trenches are formed in the dielectric layers 134 and 136 through a variety of lithography processes and etching processes, and then conductive materials are formed in these vias and trenches through a deposition process (e.g., a PVD process), a plating process (e.g., an electroplating process or an electroless plating process), or a combination thereof to form the vias 138 and the conductive traces 140.

[0029] Thus far, a plurality of memory devices 10 are formed. Each memory device 10 includes one of the memory cells MU, and may also include a via 138 electrically connected to this memory cell MU, as well as conductive traces 102 and conductive traces 140. During a set operation (or what is referred to as a forming process), a conductive filament (not shown) that penetrates through the resistive variable layer 124 is formed, causing the resistive variable layer 124 to be in a low-resistance state (or what is referred to as an on state). On the other hand, during a reset operation, the conductive filament is cut off or there is no conductive filament in the resistive variable layer 124, such that the resistive variable layer 124 is in a high-resistance state (or what is referred to as an off state). In some embodiments, the conductive traces 102 and the conductive traces 140 are configured to receive a voltage and provide a bias voltage at both the bottom end and the top end of the resistive variable layer 124 to perform the above-mentioned set operation and reset operation.

[0030] As described above, the memory device 10 includes a memory cell MU, which includes a composite bottom electrode 130, a top electrode 122, and a resistive variable layer 124 sandwiched between the composite bottom electrode 130 and the top electrode 122. The composite bottom electrode 130 includes a bottom electrode 128 and a bottom electrode 126 disposed on the bottom electrode 128. The sidewall 126S of the bottom electrode 126 is recessed and indented laterally from the sidewalls of the other parts of the memory cell MU. Accordingly, the isolation distance along the sidewall of the memory cell MU from the top electrode 122 to the composite bottom electrode 130 increases. Additionally, during the lateral indentation of the bottom electrode 126, conductive materials that may remain between the top electrode 122 and the composite bottom electrode 130 can be removed. Accordingly, the isolation between the top electrode 122 and the composite bottom electrode 130 is improved. Compared with disposing a spacer around the top electrode 122 (the pattern of the composite bottom electrode 130 will be defined by the outer contour of the surrounding spacer), since a smaller mask without the surrounding spacer is used to pattern the composite bottom electrode 130 according to an embodiment of the present disclosure, the composite bottom electrode 130 can have a smaller occupied area. In this way, the isolation between the top electrode 122 and the composite bottom electrode 130 can be ensured without reducing the spacing between laterally adjacent memory cells MU (i.e., the spacing between laterally adjacent composite bottom electrodes 130), and thus the isolation between laterally adjacent memory cells MU can also be improved. Furthermore, by omitting the formation of the above-mentioned spacer, at least one deposition step and at least one etching step can be saved. Accordingly, the manufacturing cost is reduced.

[0031] Figure 3A is an equivalent circuit diagram illustrating a memory integrated circuit according to some embodiments of the present disclosure.

[0032] Reference Figure 3A , in some embodiments, each resistive memory RM and a transistor T serially connected to the resistive memory RM together constitute a memory cell MC. A plurality of memory cells MC can be arranged in an array and constitute a memory integrated circuit 20, such as an RRAM integrated circuit. The resistive memory RM shown in Figure 2I can be implemented by the memory device 10 shown in Figure 3A , and the memory cell MU of the memory device 10 shown in Figure 2I is depicted as a variable resistor in Figure 3A . The transistor T can be formed on Figures 2A to 2ISome of the electronic devices in the device substrate 100 shown. The gate terminal of each transistor T is electrically connected to a word line WL extending, for example, in the direction X, and the source terminal and the drain terminal of each transistor T are electrically connected to a source line SL extending, for example, in the direction X and one of the memory cells MU of the resistive memory RM, respectively. A row of transistors T can share one of the word lines WL and one of the source lines SL. In addition, the electrical connection between the drain terminal and the memory cell MU can be realized by an interconnect structure formed in the Figures 2A to 2I device substrate 100 shown, and such an interconnect structure can include a conductive trace 102. In addition, the memory cell MU is also electrically connected to a bit line BL extending, for example, in the direction Y, so that each memory cell MU is electrically connected between one of the transistors T and one of the bit lines BL. A column of memory cells MU can share one of the bit lines BL. In some embodiments, the bit line BL can be implemented as Figure 2I the conductive trace 140 shown.

[0033] As described above, since each transistor T is electrically connected to one of the resistive memories RM. Therefore, the memory integrated circuit 20 has a "1T1R" configuration. However, the memory integrated circuit of the present disclosure can be formed into other configurations, including a "1TNR" configuration (i.e., each transistor T is electrically connected to multiple resistive memories RM), a "cross-point" configuration (i.e., there is no transistor in each memory cell), etc. Those skilled in the art can modify the configuration of the memory integrated circuit according to design requirements, and the present disclosure is not limited thereto.

[0034] Figure 3B is a schematic diagram illustrating Figure 3A one of the memory cells MC shown. As Figure 3BAs shown, each memory cell MC includes one of the transistors T and one of the resistive memories RM. The transistor T is formed in the device substrate 100, and the resistive memory RM is formed on the device substrate 100. The device substrate 100 may include a semiconductor substrate W. The gate terminal G of the transistor T is formed on the semiconductor substrate W. In some embodiments, the source terminal S and the drain terminal D of the transistor T are embedded in the semiconductor substrate W. On the other hand, the interconnection structure of the device substrate 100 is formed on the semiconductor substrate W and may include contact plugs CP standing on the source terminal S and the drain terminal D, and includes a plurality of metallization layers. The metallization layers may include conductive traces M1, conductive traces M2, conductive traces M3, and conductive traces M4, and include vias V1 and V2. The conductive traces M1, conductive traces M2, conductive traces M3, and conductive traces M4 extend along a direction substantially parallel to the top surface of the semiconductor substrate W and are stacked on the semiconductor substrate W in numerical order. Each of the vias V1 and V2 is electrically connected between the conductive traces adjacent in the vertical direction (e.g., conductive trace M1 and conductive trace M2). In some embodiments, the resistive memory RM is electrically connected between the conductive trace M3 and the conductive trace M4. In these embodiments, the conductive trace M4 can be used as the bit line BL, as Figure 3A shown. Additionally, the conductive traces M3 and M4 can be implemented as Figure 2I the conductive trace 102 and the conductive trace 140 shown, and Figure 3B the via 138 shown in Figure 2I is omitted.

[0035] Figures 4A to 4C are schematic cross-sectional views of the structures at various stages during the manufacturing method of a memory device according to some embodiments of the present disclosure. The embodiments to be described with reference to Figures 4A to 4C are similar to the embodiments detailed with reference to Figure 1 and Figures 2A to 2I . Only the differences between the two will be described, and the same or similar components will not be repeated.

[0036] Referring to Figure 1 , Figure 2D and Figure 4A , after performing step S100, step S102, step S104, and step S106, Figure 2DThe top electrode layer 114, the resistive variable material layer 112, and the bottom electrode layer 110 shown in [reference] are patterned to form the top electrode 122, the resistive variable layer 124, and the initial bottom electrode 126'. In some embodiments, the patterning process for forming the top electrode 122, the resistive variable layer 124, and the initial bottom electrode 126' includes an anisotropic etching process. The hard mask 120 can be used as a mask during this anisotropic etching process. In this way, the portions of the top electrode layer 114, the resistive variable material layer 112, and the bottom electrode layer 110 that are not covered by the hard mask 120 can be removed, while the portions of these layers covered by the hard mask 120 can be retained. In some embodiments, the underlying bottom electrode layer 108 can be used as an etch stop layer during this anisotropic etching process and can be exposed when this anisotropic etching process is completed. Since an anisotropic etching process is used to form the top electrode 122, the resistive variable layer 124, and the initial bottom electrode 126', the sidewalls of these layers may not be recessed or protruded from each other. In some embodiments, the sidewalls of the top electrode 122, the sidewalls of the resistive variable layer 124, and the sidewalls of the initial bottom electrode 126' are substantially coplanar with each other. The etchant used in this anisotropic etching process may be capable of removing the material of the top electrode layer 114, the material of the resistive variable material layer 112, and the material of the bottom electrode layer 110. For example, the etchant used in this anisotropic etching process may include an argon-based etchant, an oxygen-based etchant, and a fluorochloride mixture-based etchant.

[0037] Reference Figure 4A and Figure 4B , the sidewalls of the initial bottom electrode 126' are recessed and indented laterally relative to the sidewalls of the overlying layer to form the bottom electrode 126a. In some embodiments, an isotropic etching process is used to form the bottom electrode 126a, and the peripheral region of the initial bottom electrode 126' is removed. The recess depth RD of the sidewall 126aS of the bottom electrode 126a can be controlled by adjusting the process time of this isotropic etching process. As shown in the enlarged view (i.e., the region surrounded by the dashed line in Figure 4B ) illustrating the sidewall 126aS of one of the bottom electrodes 126a, the recess depth RD of the indented sidewall 126aS of each bottom electrode 126a may not be the largest at the topmost portion of the bottom electrode 126a (as shown in reference Figure 2Fas described), because substantially the entire sidewall of the bottom electrode 126a is equally exposed to the etchant. In some embodiments, the recess depth RD may be maximum at approximately half the thickness of the bottom electrode 126a and minimum near the top and bottom surfaces of the bottom electrode 126a. In other words, the most concave portion of the sidewall 126aS of each bottom electrode 126a may be located at approximately half the thickness of the bottom electrode 126a. For example, the sidewall 126aS of the bottom electrode 126a may substantially exhibit a parabolic recessed surface. Additionally, this parabolic recessed surface may be symmetric about a substantially horizontal axis. In some embodiments, the maximum value of the recess depth RD may be in to range, while the minimum value of the recess depth RD may be in to range.

[0038] Subsequently, referring to Figure 1 and Figure 4C , steps S112, S114, and S116 are performed, and the memory device 10a is formed. Figure 4C The memory device 10a shown in Figure 2I is similar to the memory device 10 shown in Figure 4C except that the shape of the sidewall 126aS of each bottom electrode 126a shown in Figure 2I is different from the shape of the sidewall 126S of each bottom electrode 126 shown in

[0039] Figure 5A and Figure 5B are schematic cross-sectional views of the structure at various stages during the manufacturing method of the memory cell shown in Figure 4C . The embodiments to be described with reference to Figure 5A and Figure 5B are similar to the embodiments described in detail with reference to Figures 4A to 4C . Only the differences between the two will be described, and the same or similar components will not be repeated.

[0040] Referring to Figure 1 and Figure 5A, after performing steps S100, S102, S104, and S106, the top electrode layer 114, the resistive variable material layer 112, the bottom electrode layer 110, and the bottom electrode layer 108 are patterned to form the top electrode 122, the resistive variable layer 124, the initial bottom electrode 126', and the bottom electrode 128. In some embodiments, the patterning process for forming the top electrode 122, the resistive variable layer 124, the initial bottom electrode 126', and the bottom electrode 128 includes an anisotropic etching process. The hard mask 120 can be used as a mask during this anisotropic etching process. In this way, the portions of the top electrode layer 114, the resistive variable material layer 112, the bottom electrode layer 110, and the bottom electrode layer 108 that are not covered by the hard mask 120 can be removed, while the portions of these layers covered by the hard mask 120 can be retained. In some embodiments, this anisotropic etching process stops at the passivation pattern 106. In certain embodiments, the portion of the passivation pattern 106 that is not covered by the hard mask 120 is thinned, while the thickness of the other portions of the passivation pattern 106 located under the hard mask 120 can remain unchanged. Since an anisotropic etching process is used to form the top electrode 122, the resistive variable layer 124, the initial bottom electrode 126', and the bottom electrode 128, the sidewalls of these layers may not be recessed or protruded from each other. In some embodiments, the sidewalls of the top electrode 122, the sidewalls of the resistive variable layer 124, the sidewalls of the initial bottom electrode 126', and the sidewalls of the bottom electrode 128 are substantially coplanar with each other. The etchant used in this anisotropic etching process may be capable of removing the material of the top electrode layer 114, the material of the resistive variable material layer 112, the material of the bottom electrode layer 110, and the material of the bottom electrode layer 108. For example, the etchant used in this anisotropic etching process may include an argon-based etchant, an oxygen-based etchant, and a mixture-based etchant of fluorine and chlorine.

[0041] Reference Figure 5A and Figure 5B , the sidewall of the initial bottom electrode 126' is recessed and indented laterally relative to the sidewalls of the overlying layer and the underlying layer to form the bottom electrode 126a. The method for forming Figure 5B the bottom electrode 126a shown in Figure 4B is similar to the method for forming Figure 5B the bottom electrode 126a shown in Figure 5B , but Figure 4B the bottom electrode 126a shown in

[0042] is formed after the underlying bottom electrode 128 is formed. Therefore, Figure 1 the sidewall 126aS of the bottom electrode 126a shown inFigure 4C Steps S114 and S116 are performed, and the memory device 10a is formed.

[0043] Figure 6A and Figure 6B are schematic cross-sectional views illustrating a memory device 10b and a memory device 10c according to some embodiments of the present disclosure. Figure 6A and Figure 6B The memory devices 10b and 10c shown in Figure 2I and Figure 4C are similar to the memory devices 10 and 10a shown in

[0044] Referring to Figure 2I and Figure 6A , Figure 6A the memory device 10b shown in Figure 2I is similar to the memory device 10 shown in Figure 6A except that there is no air gap between the passivation layer 132a and the bottom electrode 126 shown in Figure 6A . In some embodiments, the passivation layer 132a fills the cavity defined by the bottom electrode 126, the overlying resistive variable layer 124, and the underlying bottom electrode 128, and is in physical contact with the sidewall 126S of the bottom electrode 126. In these embodiments, the surface of the passivation layer 132a may also have a depression corresponding to these currently filled cavities. The method for forming the passivation layer 132a shown in Figure 6A may include an ALD process.

[0045] Referring to Figure 4C and Figure 6B , similarly, Figure 6B the difference between the memory device 10c shown in Figure 4C and the memory device 10a shown in Figure 6B is that there is no air gap between the passivation layer 132a and the bottom electrode 126a shown in Figure 6B . In some embodiments, the passivation layer 132a fills the cavity defined by the bottom electrode 126a, the overlying resistive variable layer 124, and the underlying bottom electrode 128, and the passivation layer 132a is in physical contact with the sidewall 126aS of the bottom electrode 126a. Additionally, the surface of the passivation layer 132a may be recessed at the corresponding locations of these currently filled cavities. The method for forming the passivation layer 132a shown in Figure 6B may include an ALD process.

[0046] As described above, a memory device according to an embodiment of the present disclosure includes a memory cell, the memory cell including a composite bottom electrode, a top electrode, and a resistive variable layer sandwiched between the composite bottom electrode and the top electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed on the first bottom electrode. Sidewalls of the second bottom electrode are recessed and indented laterally from other portions of the memory cell. Accordingly, an isolation distance from the top electrode to the composite bottom electrode along the sidewall of the memory cell is increased. Additionally, during the lateral indentation of the bottom electrode, possible residues of conductive materials remaining between the top electrode and the composite bottom electrode can be removed. Accordingly, isolation between the top electrode and the composite bottom electrode is improved. Compared with providing a spacer surrounding the top electrode (the pattern of the composite bottom electrode will be defined by an outer contour of the surrounding spacer), since a smaller mask without the surrounding spacer is used to pattern the composite bottom electrode according to an embodiment of the present disclosure, the composite bottom electrode can have a smaller occupied area. In this way, isolation between the top electrode and the composite bottom electrode can be ensured without reducing a spacing between laterally adjacent memory cells (i.e., a spacing between laterally adjacent composite bottom electrodes), and thus isolation between laterally adjacent memory cells can also be improved. Further, by omitting the formation of the above spacer, at least one deposition step and at least one etching step can be saved. Accordingly, manufacturing costs are reduced.

[0047] In one aspect of the present disclosure, a memory device is provided. The memory device includes a composite bottom electrode, a top electrode, and a resistive variable layer disposed between the composite bottom electrode and the top electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed on the first bottom electrode. Sidewalls of the second bottom electrode are recessed laterally relative to sidewalls of the first bottom electrode layer and sidewalls of the resistive variable layer.

[0048] In some embodiments, the memory device further includes: a hard mask disposed over the top electrode. In some embodiments, wherein sidewalls of the hard mask are substantially coplanar with sidewalls of the top electrode, sidewalls of the resistive variable layer, and sidewalls of the first bottom electrode. In some embodiments, the memory device further includes: a passivation layer covering the composite bottom electrode, the resistive variable layer, and the top electrode. In some embodiments, wherein the passivation layer is in physical contact with sidewalls of the top electrode. In some embodiments, wherein the passivation layer is in physical contact with sidewalls of the second bottom electrode of the composite bottom electrode. In some embodiments, wherein an air gap is located between sidewalls of the second bottom electrode and the passivation layer. In some embodiments, wherein the second bottom electrode is surrounded by the air gap. In some embodiments, wherein sidewalls of the second bottom electrode have a curved surface, and a most concave portion of the sidewalls of the second bottom electrode is located at a bottom surface of the resistive variable layer. In some embodiments, wherein sidewalls of the second bottom electrode have a curved surface, and a most concave portion of the sidewalls of the second bottom electrode is located at approximately half of a thickness of the second bottom electrode.

[0049] In another aspect of the present disclosure, there is provided a memory integrated circuit. The memory integrated circuit includes a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. The plurality of memory cells are arranged in an array. Each of the plurality of memory cells includes a memory device, and the memory device includes a composite bottom electrode, a top electrode, a resistive variable layer located between the composite bottom electrode and the top electrode, and a passivation layer covering the top electrode, the resistive variable layer, and the composite bottom electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed over the first bottom electrode. Sidewalls of the second bottom electrode are recessed laterally relative to sidewalls of the first bottom electrode and sidewalls of the resistive variable layer. The plurality of bit lines extend along a first direction. The plurality of word lines extend along a second direction intersecting the first direction. Each of the memory devices is electrically connected between one of the plurality of bit lines and one of the plurality of word lines.

[0050] In some embodiments, the passivation layer is in physical contact with the sidewalls of the second bottom electrode of the composite bottom electrode. In some embodiments, an air gap is located between the sidewalls of the second bottom electrode and the passivation layer. In some embodiments, an air gap surrounding the second bottom electrode is located between the sidewalls of the second bottom electrode and the passivation layer. In some embodiments, each of the plurality of memory cells further includes a transistor, one of a source terminal and a drain terminal of the transistor being electrically connected to the memory device, the other of the source terminal and the drain terminal being electrically connected to a source line, and a gate terminal of the transistor being connected to one of the plurality of word lines.

[0051] In yet another aspect of the present disclosure, a method of manufacturing a memory device is provided. The method includes: sequentially forming a first bottom electrode layer, a second bottom electrode layer, a resistive variable material layer, a top electrode layer, and a hard mask layer over a device substrate; patterning the hard mask layer to form a hard mask; using the hard mask as a mask to pattern the top electrode layer, pattern the resistive variable material layer, pattern the second bottom electrode layer, and pattern the first bottom electrode layer; and causing the second bottom electrode layer to be recessed laterally with respect to the patterned resistive variable material layer.

[0052] In some embodiments, after patterning the resistive variable material layer and before patterning the first bottom electrode layer, a single etching process is performed using the hard mask as the mask to pattern the second bottom electrode layer and cause the second bottom electrode layer to be recessed laterally. In some embodiments, a first etching process is performed using the hard mask as the mask to pattern the second bottom electrode layer, and a second etching process is performed to cause the second bottom electrode layer to be recessed laterally, and the first etching process and the second etching process are different etching processes. In some embodiments, the second etching process for causing the second bottom electrode layer to be recessed laterally is performed before patterning the first bottom electrode layer. In some embodiments, the second etching process for causing the second bottom electrode layer to be recessed laterally is performed after patterning the first bottom electrode layer.

[0053] The foregoing has outlined features of several embodiments in order that the skilled person in the art may better understand aspects of the present disclosure. The skilled person should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. The skilled person should also realize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: a composite bottom electrode; a top electrode; and a resistive variable layer disposed between the composite bottom electrode and the top electrode, wherein the composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed on the first bottom electrode, a side wall of the second bottom electrode is recessed laterally relative to a side wall of the first bottom electrode and a side wall of the resistive variable layer, the second bottom electrode has substantially the same shape as the first bottom electrode, and a contour of the second bottom electrode is shrunk inward relative to a contour of the first bottom electrode.

2. The memory device according to claim 1, further comprising: a hard mask disposed on the top electrode.

3. The memory device according to claim 2, wherein a side wall of the hard mask is substantially coplanar with a side wall of the top electrode, the side wall of the resistive variable layer, and the side wall of the first bottom electrode.

4. The memory device according to claim 1, further comprising: a passivation layer covering the composite bottom electrode, the resistive variable layer, and the top electrode.

5. The memory device according to claim 4, wherein the passivation layer is in physical contact with a side wall of the top electrode.

6. The memory device according to claim 4, wherein the passivation layer is in physical contact with a side wall of the second bottom electrode of the composite bottom electrode.

7. The memory device according to claim 4, wherein an air gap is located between the side wall of the second bottom electrode and the passivation layer.

8. The memory device according to claim 7, wherein the second bottom electrode is surrounded by the air gap.

9. The memory device according to claim 1, wherein the side wall of the second bottom electrode has a curved surface, and a most recessed portion of the side wall of the second bottom electrode is located at a bottom surface of the resistive variable layer.

10. The memory device according to claim 1, wherein the side wall of the second bottom electrode has a curved surface, and a most recessed portion of the side wall of the second bottom electrode is located at a half thickness of the second bottom electrode.

11. A memory integrated circuit, comprising: a plurality of memory cells arranged in an array, wherein each of the plurality of memory cells includes a memory device, and the memory device includes a composite bottom electrode, a top electrode, a resistive variable layer located between the composite bottom electrode and the top electrode, and a passivation layer covering the top electrode, the resistive variable layer, and the composite bottom electrode, wherein the composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed on the first bottom electrode, a side wall of the second bottom electrode is recessed laterally relative to a side wall of the first bottom electrode and a side wall of the resistive variable layer, the second bottom electrode has substantially the same shape as the first bottom electrode, and a contour of the second bottom electrode is shrunk inward relative to a contour of the first bottom electrode; a plurality of bit lines extending along a first direction; and A plurality of word lines extending along a second direction intersecting the first direction, wherein each of the memory devices is electrically connected between one of the plurality of bit lines and one of the plurality of word lines.

12. The memory integrated circuit according to claim 11, wherein the passivation layer is physically in contact with the sidewall of the second bottom electrode of the composite bottom electrode.

13. The memory integrated circuit according to claim 11, wherein an air gap is located between the sidewall of the second bottom electrode and the passivation layer.

14. The memory integrated circuit according to claim 11, wherein an air gap surrounding the second bottom electrode is located between the sidewall of the second bottom electrode and the passivation layer.

15. The memory integrated circuit according to claim 11, wherein each of the plurality of memory cells further includes a transistor, one of the source terminal and the drain terminal of the transistor is electrically connected to the memory device, the other of the source terminal and the drain terminal is electrically connected to a source line, and the gate terminal of the transistor is connected to one of the plurality of word lines.

16. A method of manufacturing a memory device, comprising: sequentially forming a first bottom electrode layer, a second bottom electrode layer, a resistive variable material layer, a top electrode layer, and a hard mask layer over a device substrate; patterning the hard mask layer to form a hard mask; using the hard mask as a mask to pattern the top electrode layer, pattern the resistive variable material layer, pattern the second bottom electrode layer, and pattern the first bottom electrode layer; and lateral recessing the second bottom electrode layer relative to the patterned resistive variable material layer.

17. The method of manufacturing a memory device according to claim 16, wherein after patterning the resistive variable material layer and before patterning the first bottom electrode layer, a single etching process is performed using the hard mask as the mask to pattern the second bottom electrode layer and laterally recess the second bottom electrode layer.

18. The method of manufacturing a memory device according to claim 16, wherein a first etching process is performed using the hard mask as the mask to pattern the second bottom electrode layer, and a second etching process is performed to laterally recess the second bottom electrode layer, and the first etching process and the second etching process are different etching processes.

19. The method of manufacturing a memory device according to claim 18, wherein the second etching process for laterally recessing the second bottom electrode layer is performed before patterning the first bottom electrode layer.

20. The method of manufacturing a memory device according to claim 18, wherein the second etching process for laterally recessing the second bottom electrode layer is performed after patterning the first bottom electrode layer.

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