Semiconductor device and power conversion device

Abstract

The present invention provides a semiconductor device and a power conversion device. In a semiconductor device having a terminal structure in which a semiconductor active region is surrounded by a guard ring, corrosion of a metal layer connected to the guard ring can be suppressed, and the reliability is high. The semiconductor device is characterized in that it includes an active region formed on a main surface of a semiconductor substrate and a guard ring region formed on the main surface so as to surround the active region. The guard ring region has: a guard ring formed on the semiconductor substrate; an interlayer insulating film formed on the semiconductor substrate so as to cover the guard ring; a field plate disposed on the interlayer insulating film and electrically connected to the guard ring via a contact penetrating the interlayer insulating film; and a protective film covering the field plate. The field plate is composed of a stacked structure of a first metal in contact with the guard ring and a second metal disposed in contact with the ground on the first metal and having a standard potential lower than that of the first metal. The ratio of the contact area of the first metal with the protective film to the contact area of the second metal with the protective film is 0.05 or less.

Description

Technical Field

[0001] The present invention relates to a structure of a semiconductor device, and particularly to a technique effective for a semiconductor device having a terminal structure in which a semiconductor active region is surrounded by a guard ring. Background Art

[0002] Semiconductor devices are used in a wide range of fields such as system LSIs (Large Scale Integration), power conversion devices, control devices for hybrid vehicles, electric vehicles, etc. For example, an IGBT module (Insulated Gate Bipolar Transistor: hereinafter, simply referred to as IGBT), which is a main component of a power conversion device such as an inverter, is used for railways, power, and electric vehicles. In addition to cost reduction and miniaturization, a highly reliable power module is also required even in a high-temperature and high-humidity environment. Similarly, for power device chips in a power module, in addition to cost reduction and miniaturization, new technologies for achieving high reliability in a high-temperature and high-humidity environment are also required.

[0003] In such a background, as a miniaturization technique for a terminal structure that surrounds an active region of a power device chip, for example, a technique is proposed in Patent Document 1, which is characterized by having a stacked structure of a barrier metal layer and a field electrode connected to a guard ring, and in a direction crossing a terminal region, a part of the barrier metal layer protrudes from both sides of the field electrode.

[0004] Thereby, high breakdown voltage and miniaturization can be achieved at the same time.

[0005] In addition, in FIG. 19 of Patent Document 2, the following technique is proposed: in an SBD element having an active region of a Schottky Barrier Diode (hereinafter, referred to as SBD) provided on a main surface of a semiconductor substrate and a PSG (Phosphorus Silicate Glass) film coating region provided from an end portion thereof to the outside, an organic-based final passivation film and a UBM (Under Bump Metal) layer are provided complementarily on an aluminum-based metal film constituting an anode electrode, and an anode electrode and a field plate electrode are constituted by a multilayer aluminum-based metal composed of a lower aluminum-based metal film, an aluminum diffusion barrier metal film, an upper aluminum-based metal film, etc.

[0006] Thereby, crack generation can be suppressed.

[0007] In addition, Patent Document 3 proposes the following structure: an edge terminal region surrounding the active region has an electric field relaxation mechanism, which includes a guard ring, a first field plate in contact with the guard ring, and a second field plate provided on the first field plate with an interlayer insulating film interposed therebetween. The thickness of the second field plate is thicker than that of the first field plate, and the interval between the second field plates is wider than the interval between the first field plates. A barrier metal film in conductive contact with the second field plate is provided between the second field plate and the interlayer insulating film, and the interval between the barrier metal films is equal to the interval between the first field plates.

[0008] Thereby, the shielding effect against external charges can be improved.

[0009] Prior art documents

[0010] Patent documents

[0011] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2010-251404

[0012] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2011-100811

[0013] Patent Document 3: International Publication No. 2014 / 084124 Summary of the invention

[0014] Problems to be solved by the invention

[0015] However, the inventors of the present application have found through research that in the case where a part of the barrier metal layer protrudes from both sides of the field electrode in the direction across the terminal region as in Patent Documents 1 and 3, there is a problem of electrochemical corrosion in which dissimilar metals become local cells and corrode under high temperature and high humidity.

[0016] Electrochemical corrosion is a form of local corrosion caused by the standard potential difference between dissimilar metals and has the following relationship of formula (1).

[0017] [Equation 1]

[0018]

[0019] Here, P is the corrosion amount, P0 is the corrosion amount when the metal is alone, A is the area of the metal with a higher standard potential, and B is the area of the metal with a lower standard potential. In addition, the area in this formula is the surface area.

[0020] In Patent Documents 1 and 3, since the standard potential of the barrier metal layer is high and the standard potential of the field electrode formed of aluminum alloy is low, A / B (the area of the barrier metal layer / the area of the field electrode) in the above formula (1) becomes large, so electrochemical corrosion is accelerated and there are problems in terms of reliability under high temperature and high humidity.

[0021] In addition, in a three-layer structure such as Al / barrier metal film / Al as described in Patent Document 2, when the barrier metal film does not protrude and the end positions are the same, the surface area of the upper-layer Al is the upper surface portion and the side surface portion. In contrast, the surface areas of the barrier metal film and the lower-layer Al are only the side surface portions. Therefore, the surface area of the lower-layer Al is smaller than that of the upper-layer Al. Thus, there is a problem that in the lower-layer Al, the A / B (area of the barrier metal film / area of the field electrode) in the above formula (1) becomes larger than that in the upper-layer Al, and the lower-layer Al is more likely to be electrochemically corroded than the upper-layer Al.

[0022] Accordingly, an object of the present invention is to provide a semiconductor device and a power conversion device using the semiconductor device, the semiconductor device having a terminal structure in which a semiconductor active region is surrounded by a guard ring, and capable of suppressing corrosion of a metal layer connected to the guard ring and having high reliability.

[0023] Means for Solving the Problem

[0024] To solve the above problems, a semiconductor device according to the present invention is characterized by including: an active region formed on a main surface of a semiconductor substrate; and a guard ring region formed on the main surface so as to surround the active region, the guard ring region having: a guard ring formed on the semiconductor substrate; an interlayer insulating film formed on the semiconductor substrate so as to cover the guard ring; a field plate disposed on the interlayer insulating film and electrically connected to the guard ring via a contact penetrating the interlayer insulating film; and a protective film covering the field plate, the field plate being constituted by a stacked structure of a first metal and a second metal, the first metal being in contact with the guard ring, the second metal being disposed in contact with the first metal and having a standard potential lower than that of the first metal, and a ratio of a contact area of the first metal with the protective film to a contact area of the second metal with the protective film being 0.05 or less.

[0025] In addition, a power conversion device according to the present invention includes: a pair of DC terminals; AC terminals having the same number as the number of phases of an alternating current; and a power conversion unit connected between the pair of DC terminals and having a structure in which two parallel circuits are connected in series and having the same number as the number of phases of the alternating current of AC terminals at different connection points of the parallel circuits, the parallel circuits being connected in parallel with a switching element and a diode of opposite polarity, and the power conversion device being characterized in that the switching element is the above semiconductor device.

[0026] Advantageous Effects of the Invention

[0027] According to the present invention, a semiconductor device can be provided which has a terminal structure in which a semiconductor active region is surrounded by a guard ring, and in which corrosion of a metal layer connected to the guard ring can be suppressed and the reliability is high.

[0028] Thereby, it is possible to contribute to improving the reliability and extending the life of the semiconductor device and the power conversion device using the semiconductor device.

[0029] Through the description of the following embodiments, problems, structures, and effects other than the above are clarified. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a top view of the semiconductor device (IGBT semiconductor chip) of Embodiment 1 of the present invention.

[0031] Figure 2 It is a cross-sectional view of the semiconductor device of Embodiment 1 of the present invention.

[0032] Figure 3 It is a schematic diagram showing a first metal and a second metal in a main part cross-section of a guard ring portion.

[0033] Figure 4 It is a diagram showing the effect of the present invention.

[0034] Figure 5 It is a schematic diagram showing a first metal and a second metal in a main part cross-section of a guard ring portion.

[0035] Figure 6 It is a diagram showing the effect of the present invention.

[0036] Figure 7 It is a cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 1 of the present invention.

[0037] Figure 8 It is a cross-sectional view of the semiconductor device of Embodiment 2 of the present invention.

[0038] Figure 9 It is a cross-sectional view of the semiconductor device of Embodiment 3 of the present invention.

[0039] Figure 10 It is a circuit block diagram of the power conversion device of Embodiment 4 of the present invention.

[0040] In the figure:

[0041] 101 - IGBT semiconductor chip, 102 - chip terminal guard ring region, 103 - active region, 104 - gate electrode PAD, 201 - emitter electrode (first metal layer), 202 - interlayer insulating film, 203 - contact, 204 - n+ source layer, 205 - p+ layer, 206 - p base layer, 207 - trench gate, 208 - gate insulating film, 209 - n- semiconductor substrate, 210 - n-type buffer layer, 211 - p-type collector layer, 212 - collector electrode, 213 - gate electrode, 214 - polysilicon gate wiring, 215 - guard ring of the second conductivity type (p-type), 216 - channel cutoff ring of the first conductivity type (n-type), 217 - second metal layer, 218 - third metal layer, 219 - first metal, 220 - second metal, 221 - organic passivation film (protective film), 222 - field oxide film, 301 - P well, 600 - power conversion device, 601 to 606 - power switch elements, 621 to 626 - diodes, 611 to 616 - gate drive circuits, 631, 632 - DC terminals, 633 to 635 - AC terminals, 801 - inorganic passivation film. Detailed implementation manners

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, parts with the same reference numerals denote the same components or components having similar functions. Further, p-, p, p+ indicate that the conductivity type of the semiconductor layer is p-type, and in this order, the relative impurity concentration becomes higher. Similarly, n-, n, n+ indicate that the conductivity type of the semiconductor layer is n-type, and in this order, the relative impurity concentration becomes higher.

[0043] Embodiment 1

[0044] Refer to Figures 1 to 7 to describe the semiconductor device and its manufacturing method according to Embodiment 1 of the present invention.

[0045] Figure 1 is a top view of the IGBT semiconductor chip 101 which is the semiconductor device of this embodiment. An active region 103 of the IGBT is provided at the center of the chip. In addition, a gate electrode PAD 104 for applying a gate voltage of the IGBT is provided. A chip terminal guard ring region 102 is provided at the outer peripheral portion of the IGBT semiconductor chip 101.

[0046] Figure 2 is a cross-sectional view of the active region 103 and the chip terminal guard ring region 102 of the IGBT semiconductor chip 101. Trench gates 207 are periodically arranged in the active region 103, and contacts 203 are provided between adjacent trench gates 207. The contacts 203 penetrate through an insulating layer (interlayer insulating film 202) and are connected to the emitter electrode 201 which is a first metal layer.

[0047] The trench gate 207 is composed of a gate insulating film 208 and polysilicon (Poly-Si) buried in the trench, and constitutes a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) through a p base layer 206 and an n+ source layer 204 formed on the surface of an n- semiconductor substrate 209, and has the function of turning on / off the IGBT semiconductor chip 101. In addition, a p+ layer 205 is provided in the p base layer 206 to reduce the contact resistance with the contact 203.

[0048] The trench gate 207 is connected to the polysilicon gate wiring 214 on the field oxide film 222 through the polysilicon (Poly-Si) buried in the trench, and is connected to the gate electrode 213 through the contact 203 via the insulating layer (interlayer insulating film 202).

[0049] In the chip terminal guard ring region 102 , a plurality of second conductivity type (p type) guard rings 215 are arranged on the surface of the n- semiconductor substrate 209 . At the chip terminal, a first conductivity type (n type) channel stopper ring 216 is arranged on the surface of the n- semiconductor substrate 209 .

[0050] Each of the plurality of second conductivity type (p-type) guard rings 215 is connected to the corresponding second metal layer 217 through the field oxide film 222 and the insulating layer (interlayer insulating film 202) through the corresponding contact 203. The first conductivity type (n-type) channel stopper ring 216 is connected to the third metal layer 218 through the contact 203 through the insulating layer (interlayer insulating film 202).

[0051] The second metal layer 217 covers the surface of the corresponding second conductive type (p-type) guard ring 215, and is composed of a stacked structure of at least two or more heterogeneous metals, in which the stacked structure of heterogeneous metals forms a first metal 219 in contact with the corresponding second conductive type (p-type) guard ring 215, and a second metal 220 with a standard potential lower than that of the first metal 219 is formed in contact with the first metal 219.

[0052] In addition, the second metal layer 217 connected to the second conductivity type (p-type) guard ring 215 and the third metal layer 218 connected to the first conductivity type (n-type) channel stopper 216 are covered by an organic passivation film (protective film) 221 .

[0053] Here, the stacked structure of the first metal 219 and the second metal 220 is formed so that the ratio of the contact area of ​​the first metal 219 with the organic passivation film (protective film) 221 to the contact area of ​​the second metal 220 with the organic passivation film (protective film) 221 is 0.05 or less.

[0054] On the back surface of the n-semiconductor substrate 209, that is, on the main surface (back surface) of the n-semiconductor substrate 209 opposite to the main surface (front surface) on the side where the trench gate 207 is formed, an n-type buffer layer 210, a p-type collector layer 211, and a collector electrode 212 are formed in sequence.

[0055] Using Figures 3 to 6 , the relationship between the above-mentioned first metal 219 and the second metal 220 will be described in detail. In addition, for easier understanding of the description, in Figure 3 and Figure 5 , the state before the second metal layer 217 is covered with the organic passivation film (protective film) 221 is shown, that is, the state where the upper surface and side surfaces of the second metal 220 and the upper surface and side surfaces of the first metal 219 not covered by the second metal 220 are exposed.

[0056] Figure 3 is a schematic diagram showing the relationship between the exposed surface area A of the first metal 219 and the exposed surface area B of the second metal 220 in the main part cross-section of the guard ring portion. Figure 3 The left figure (a) of Figure 3 shows the case where the ratio of the exposed surface area A of the first metal 219 to the exposed surface area B of the second metal 220 is relatively large,

[0057] Figure 4 is a characteristic diagram showing the relationship between the corrosion amount of the first metal 219 and the ratio of the exposed surface area A of the first metal 219 to the exposed surface area B of the second metal 220. According to the research of the inventors of the present application, it has been found that because the above-mentioned electrochemical reaction has the relationship of formula (1), so, as Figure 4 shows, when the ratio of the exposed surface area A of the first metal 219 to the exposed surface area B of the second metal 220 is 0.05 or less, the corrosion of the first metal 219 can be suppressed.

[0058] Figure 5 is a schematic diagram showing the ratio of the area Ts1 of the upper surface of the first metal 219 covered by the area Bs1 of the second metal 220 in the main part cross-section of the guard ring portion. Figure 5 The left figure (a) of Figure 5 shows the case where the ratio of the upper surface (area: Ts1) of the first metal 219 covered by the second metal 220 (area: Bs1) is relatively small,

[0059] Figure 6is a characteristic diagram showing the relationship between the corrosion amount of the first metal 219 and the ratio of the upper surface (area: Ts1) of the first metal 219 covered by the second metal 220 (area: Bs1). Under high-temperature and high-humidity conditions, sometimes bromide ions (Br - ) or chloride ions (Cl - ), fluoride ions (F - ) etc. remaining in the package or in the wafer processing process dissolve into the moisture, and these halogen components move to the + potential side of the chip terminal guard ring region 102, becoming the main cause of leakage paths or corrosion. Moreover, dissimilar metals form local batteries, becoming the main cause of accelerated corrosion.

[0060] According to the research of the inventors of the present application, it has been found that, as Figure 6 shown, when the ratio of the upper surface (area: Ts1) of the first metal 219 covered by the second metal 220 (area: Bs1) is 90% or more, the corrosion of the first metal 219 can be suppressed. In addition, in Figure 5 , Bs1 is defined as the part excluding the contact 203. Additionally, in Figure 5 , the contact 203 is formed continuously in the depth direction of the paper surface. Even when including the part where the contact 203 is cut off, since it is about 1% of the whole, it is within the error range in the calculation results shown in Figure 6 .

[0061] Figure 7 is a diagram showing the manufacturing process of the IGBT semiconductor chip 101 of this embodiment ( Figure 2 ).

[0062] "(a) P-well formation"

[0063] First, prepare an n-semiconductor substrate 209 (such as a semiconductor wafer like an Si wafer).

[0064] Next, form an insulating film (such as an SiO2 film) on the main surface (surface) of the n-semiconductor substrate 209. After coating a photoresist on the insulating film, the photoresist is patterned by lithography for P-well 301 formation.

[0065] Next, using the patterned photoresist as a mask, p-type impurities (such as boron) are implanted into the n-semiconductor substrate 209 by ion implantation. After removing the photoresist, the p-type impurities are diffused by annealing to form the P-well 301. The P-well 301 constitutes the guard ring 215 of the second conductivity type (p-type) in the chip terminal guard ring region 102 and constitutes a p-type layer for potential stabilization under the polysilicon gate wiring 214 in the active region 103.

[0066] "(b) Trench gate formation"

[0067] Next, an insulating film (e.g., SiO2 film) is formed on the main surface (surface) of the n-semiconductor substrate 209. After applying a photoresist on the insulating film, the photoresist is patterned by photolithography for forming the field oxide film 222. After removing the photoresist, the patterned insulating film is used as a mask, and the main surface (surface) of the n-semiconductor substrate 209 is thermally oxidized to selectively form the field oxide film 222 on the main surface (surface) of the n-semiconductor substrate 209.

[0068] After removing the patterned insulating film, an insulating film (e.g., SiO2 film) is formed on the main surface (surface) of the n-semiconductor substrate 209. After applying a photoresist on the insulating film, the photoresist and the insulating film are patterned by photolithography for forming a trench. After removing the photoresist, the patterned insulating film is used as a mask, and a trench is formed by anisotropic etching.

[0069] Next, a gate insulating film 208 is formed in the trench, and then a polysilicon film is deposited in a manner to fill the trench, and the trench gate 207 and the polysilicon gate wiring 214 are formed by photolithographic processing.

[0070] 《(c) Formation of p-base layer, n+-source layer, and channel cutoff ring》

[0071] Next, the photoresist patterned for forming the p-base layer 206 is used as a mask, and p-type impurity ions are implanted, followed by heat treatment, thereby forming the p-base layer 206.

[0072] Then, the photoresist patterned for forming the n+-source layer 204 and the channel cutoff ring 216 of the first conductivity type (n-type) is used as a mask, and n-type impurity ions are implanted to form the n+-source layer 204 and the channel cutoff ring 216 of the first conductivity type (n-type).

[0073] 《(d) Contact formation》

[0074] Next, an interlayer insulating film 202 is deposited on the main surface (surface) of the n-semiconductor substrate 209, and the interlayer insulating film 202 is planarized. Planarization methods such as reflow soldering of, for example, a BPSG (Boron-Phosphors Silicate Glass) film, CMP (Chemical Mechanical Polishing), etc. are applied in the planarization.

[0075] After planarization of the interlayer insulating film 202, contact holes are formed by photolithography and anisotropic etching. At this time, the contact holes penetrate the interlayer insulating film 202 and further reach the p-base layer 206, the P-well 301, the polysilicon gate wiring 214, and the channel stopper ring 216 of the first conductivity type (n-type). As a result, when observing the p-base layer 206 in cross section, a pair of n+ source layers 204 are formed, and a groove portion for contact with the contact metal layer formed in a subsequent process is formed.

[0076] Next, using the interlayer insulating film 202 having the contact holes formed therein as a mask, a p+ layer 205 is formed at the bottom of the contact holes by ion implantation of p-type impurities.

[0077] Next, a metal that will be a barrier layer for the Al electrode, such as Mo, TiW, TiN, Ti, Co, Ni, which can react with Si to form a silicide and lower the resistance of the Si contact surface, is deposited by sputtering, for example, and annealed to form a silicide layer.

[0078] Next, a contact hole is filled with a metal film composed of a high-hardness and high-melting-point metal such as W, and further planarized by etching or CMP to form a contact metal layer (contact 203). At this time, the portion other than the contact holes is not removed even after planarization of W and remains on the interlayer insulating film 202.

[0079] Here, in order to suppress the electrochemical reaction, the metal that is a barrier layer for the Al electrode is preferably a metal having a small potential difference from the standard potential of Al (-1.66V). For example, the standard potential of Ti is -1.63V, Co is -0.277V, Ni is -0.23V, and Mo is -0.2V.

[0080] 《(e) Surface electrode, formation of organic passivation film》

[0081] After that, a metal layer mainly composed of aluminum (Al) is deposited, and an emitter electrode 201, a second metal layer 217, and a gate electrode 213 as the first metal layer are formed by photolithography and etching. The etching of aluminum is performed by anisotropic dry etching, and at the same time, a barrier layer is also formed.

[0082] As a result, the ratio of the area Ts1 of the upper surface of the first metal 219 (e.g., Ti) as the barrier layer covered by the area Bs1 of the second metal 220 (Al) becomes larger, the electrochemical reaction can be suppressed, and the corrosion of the barrier layer (the first metal 219) can be suppressed.

[0083] Moreover, the ratio of the exposed surface area A of the first metal 219 (barrier layer: e.g., Ti) to the exposed surface area B of the second metal 220 (Al) becomes smaller, and similarly, the electrochemical reaction can be suppressed, and the corrosion of the barrier layer (the first metal 219) can be suppressed.

[0084] In addition, the second metal layer 217 is configured to cover the surface of the second conductive type (p-type) guard ring 215, and can improve the shielding effect against external charges such as moisture, ionic substances, and mobile ions. Therefore, the potential of the n-semiconductor substrate 209 during high voltage application is stabilized, the electric field is not likely to change, and the blocking voltage is stable.

[0085] Thereafter, an organic passivation film 221 made of polyimide or the like is formed and patterned to expose the emitter electrode 201.

[0086] The above steps (a) to (e) are surface side treatments of the n-semiconductor substrate 209.

[0087] 《(f) Backside n-Buffer, p-Collector Layer, and Collector Electrode Formation》

[0088] Next, the n-semiconductor substrate 209 is ground from the backside to a desired thickness by back grinding. Thereafter, n-type and p-type impurity ions are implanted into the n-semiconductor substrate 209 from the backside, and then laser annealing is performed to form an n-type buffer layer 210 and a p-type collector layer 211.

[0089] In addition, by appropriately adjusting the acceleration energy during ion implantation, n-type buffer layer 210 and p-type collector layer 211 with different depths from the backside of the n-semiconductor substrate 209 can be formed.

[0090] Thereafter, a laminated metal layer such as Al-Ti-Ni-Au is formed by sputtering on the backside of the n-semiconductor substrate 209 to form a collector electrode 212.

[0091] In the semiconductor device of this embodiment, the second metal layer 217 covers the surface of the second conductive type (p-type) guard ring 215, and can improve the shielding effect against external charges such as moisture, ionic substances, and mobile ions. Therefore, the potential of the n-semiconductor substrate 209 during high voltage application is stabilized, the electric field is not likely to change, and the blocking voltage can be stabilized.

[0092] In addition, the second metal layer 217 is formed of a stacked structure of dissimilar metals. In the stacked structure of dissimilar metals, the first metal 219 is formed in contact with the second-conductive-type (p-type) guard ring 215, and the second metal 220 having a standard potential lower than that of the first metal 219 is formed in contact with the first metal 219. More than 90% of the area of the upper portion of the first metal 219 is covered by the second metal 220. The ratio of the area Ts1 of the upper surface of the first metal 219 (barrier layer: e.g., Ti) covered by the area Bs1 of the second metal 220 (Al) increases, which can suppress the electrochemical reaction and can suppress the corrosion of the barrier layer (the first metal 219).

[0093] Moreover, the ratio of the exposed surface area A of the first metal 219 (barrier layer: e.g., Ti) to the exposed surface area B of the second metal 220 (Al) decreases. Similarly, the electrochemical reaction can be suppressed, and the corrosion of the barrier layer (the first metal 219) can be suppressed.

[0094] In addition, the chip terminal guard ring region 102 is covered with an organic passivation film 221 to mechanically protect the surface and to protect against external charges such as moisture, ionic substances, and mobile ions.

[0095] As described above, the semiconductor device of this embodiment is configured to include an active region 103 formed on the main surface of the n-semiconductor substrate 209 and a chip terminal guard ring region 102 formed on the main surface of the n-semiconductor substrate 209 so as to surround the active region 103. The chip terminal guard ring region 102 has a second-conductive-type (p-type) guard ring 215 formed on the n-semiconductor substrate 209, an interlayer insulating film 202 formed on the n-semiconductor substrate 209 so as to cover the second-conductive-type (p-type) guard ring 215, a field plate (second metal layer 217) disposed on the interlayer insulating film 202 and electrically connected to the second-conductive-type (p-type) guard ring 215 via a contact 203 penetrating the interlayer insulating film 202, and an organic passivation film (protective film) 221 covering the field plate (second metal layer 217). The field plate (second metal layer 217) is formed of a stacked structure of the first metal 219 and the second metal 220. The first metal 219 is in contact with the second-conductive-type (p-type) guard ring 215, and the second metal 220 is disposed in contact with the first metal 219 and has a standard potential lower than that of the first metal 219. The ratio of the contact area of the first metal 219 with the organic passivation film (protective film) 221 to the contact area of the second metal 220 with the organic passivation film (protective film) 221 is 0.05 or less.

[0096] In addition, more than 90% of the area of the upper surface of the first metal 219 is covered by the second metal 220.

[0097] In addition, the chip terminal guard ring region 102 has a channel cutoff ring 216 of a first conductivity type (n-type) formed on the n-semiconductor substrate 209 so as to surround the guard ring 215 of a second conductivity type (p-type).

[0098] As a result, it is possible to realize a highly reliable semiconductor device and a power conversion device using the semiconductor device, which suppress corrosion of the metal layer connected to the guard ring under high temperature and high humidity and suppress deterioration of withstand voltage and increase of leakage current during long-term operation under high temperature and high humidity.

[0099] In addition, substantially all (about 100%) of the upper surface of the first metal 219 is covered by the second metal 220. More preferably, when the field plate (second metal layer 217) is cross-sectioned, the ends of the first metal 219 and the second metal 220 are aligned. As a result, electrochemical corrosion of the field plate (second metal layer 217) can be reliably suppressed.

[0100] In addition, preferably, when the IGBT semiconductor chip 101 is cross-sectioned, both ends of the field plate (second metal layer 217) protrude from both ends of the guard ring 215 of the second conductivity type (p-type). The reason is that the electric field relaxation effect of the field plate (second metal layer 217) on the chip terminal can be improved.

[0101] In addition, in this embodiment ( Figure 2 ), the following example is shown: A plurality of guard rings 215 of the second conductivity type (p-type) are formed on the n-semiconductor substrate 209, and each of the plurality of guard rings 215 of the second conductivity type (p-type) is connected to a plurality of field plates (second metal layers 217) via a plurality of contacts 203. However, the number of combinations of the guard rings 215 of the second conductivity type (p-type) and the field plates (second metal layers 217) is not limited to this.

[0102] For example, in the case where one guard ring 215 of the second conductivity type (p-type) and one field plate (second metal layer 217) are respectively formed in the chip terminal guard ring region 102, or it may be configured that a plurality of guard rings 215 of the second conductivity type (p-type) are formed on the n-semiconductor substrate 209 and are connected to one large-area field plate (second metal layer 217) that covers the entire plurality of guard rings 215 of the second conductivity type (p-type) via a plurality of contacts 203.

[0103] In any case, electrochemical corrosion of the field plate (second metal layer 217) can be suppressed by setting the areas of the first metal 219 and the second metal 220 constituting the field plate (second metal layer 217) to the above-described structure.

[0104] Embodiment 2

[0105] Refer to Figure 8, the semiconductor device of Embodiment 2 of the present invention will be described. Figure 8 It is a cross-sectional view of the IGBT semiconductor chip 101 of this embodiment, which is a modification of Embodiment 1 ( Figure 2 ).

[0106] In Embodiment 1 ( Figure 2 ), the chip terminal guard ring region 102 is covered with an organic passivation film 221 as a protective film. In contrast, the chip terminal guard ring region 102 of this embodiment ( Figure 8 ) is different from Embodiment 1 in that it is covered with an inorganic passivation film 801. Other structures are the same as those of Embodiment 1 ( Figure 2 ). The organic passivation film 221 has hygroscopicity and has little effect on suppressing the diffusion of moisture and ionic substances. Therefore, by setting the protective film of the chip terminal guard ring region 102 to an inorganic passivation film 801 such as SiN, SiON, or SiO2, the intrusion of moisture and the diffusion of ionic substances can be suppressed.

[0107] In the semiconductor device of this embodiment, compared with Embodiment 1, the intrusion of moisture, ionic substances, etc. can be further prevented. Therefore, a semiconductor device with higher reliability that suppresses the corrosion of the metal layer connected to the guard ring under high temperature and high humidity and suppresses the deterioration of withstand voltage and the increase of leakage current during long-term operation under high temperature and high humidity, and a power conversion device using the semiconductor device can be realized.

[0108] Embodiment 3

[0109] Refer to Figure 9 , the semiconductor device of Embodiment 3 of the present invention will be described. Figure 9 It is a cross-sectional view of the IGBT semiconductor chip 101 of this embodiment, which is a modification of Embodiment 1 ( Figure 2 ) and Embodiment 2 ( Figure 8 ).

[0110] The chip terminal guard ring region 102 of this embodiment is different from Embodiment 1 and Embodiment 2 in that it is covered with a laminated film of an inorganic passivation film 801 and an organic passivation film 221. Other structures are the same as those of Embodiment 1 and Embodiment 2.

[0111] The inorganic passivation film 801 is formed on the second metal layer 217. The passivation film mechanically protects the surface and plays a role in protecting against external charges such as moisture, ionic substances, and mobile ions. Regarding mechanical surface protection, thickening the passivation film is effective.

[0112] However, the surface of the second metal layer 217 has irregularities. If, for example, SiN is used as the inorganic passivation film 801 and thickened, cracks may occur due to the stress during film formation. The cracks become the intrusion paths for moisture and ionic substances, and thus are the causes of the breakdown voltage deterioration against external charges and the increase in leakage current, leading to the corrosion of the barrier layer (the first metal 219).

[0113] Therefore, in the present embodiment, the second metal layer 217 is covered with a stacked film of the inorganic passivation film 801 and the organic passivation film 221, and the inorganic passivation film 801 is thinned to prevent the generation of cracks, achieving a mechanical surface protection effect and preventing the intrusion of moisture, ionic substances, etc. Further, a highly reliable semiconductor device and a power conversion device using the semiconductor device can be realized, which suppress the corrosion of the metal layer connected to the retainer under high temperature and high humidity and suppress the breakdown voltage deterioration and the increase in leakage current during long-term operation under high temperature and high humidity.

[0114] Embodiment 4

[0115] Refer to Figure 10 , and an example of an embodiment in which the semiconductor device of the present invention is applied to a power conversion device will be described. Figure 10 FIG. is a circuit block diagram of a power conversion device 600 using the semiconductor devices of Embodiments 1 to 3 of the present invention as constituent elements. In Figure 10 , the circuit structure of the power conversion device 600 of the present embodiment and the connection relationship between the DC power supply and the three-phase AC motor (AC load) are shown.

[0116] In the power conversion device 600 of the present embodiment, the semiconductor devices of Embodiments 1 to 3 are used as power switch elements 601 to 606. The power switch elements 601 to 606 are, for example, IGBTs.

[0117] As Figure 10 shown, the power conversion device 600 of the present embodiment includes a P terminal 631 and an N terminal 632 as a pair of DC terminals, and a U terminal 633, a V terminal 634, and a W terminal 635 as AC terminals having the same number as the number of phases of the AC output.

[0118] In addition, it includes a switch bridge arm formed by the series connection of a pair of power switch elements 601 and 602 and having the U terminal 633 connected to the series connection point as an output. With the same structure, it includes a switch bridge arm formed by the series connection of power switch elements 603 and 604 and having the V terminal 634 connected to the series connection point as an output. With the same structure, it includes a switch bridge arm formed by the series connection of power switch elements 605 and 606 and having the W terminal 635 connected to the series connection point as an output.

[0119] A switching bridge arm corresponding to three phases and composed of power switching elements 601 to 606 is connected between the DC terminals of the P terminal 631 and the N terminal 632, and DC power is supplied from a DC power supply (not shown). The U terminal 633, the V terminal 634, and the W terminal 635, which are the three-phase AC terminals of the power conversion device 600, are connected to a three-phase AC motor (not shown) as a three-phase AC power supply.

[0120] Diodes 621 to 626 are respectively connected in an antiparallel manner to each of the power switching elements 601 to 606. Gate drive circuits 611 to 616 are connected to the gate input terminals of each of the power switching elements 601 to 606 formed by IGBTs, and are driven and controlled by the respective gate drive circuits 611 to 616.

[0121] That is, the power conversion device 600 of the present embodiment is a power conversion device that inputs DC power from the outside and converts the input DC power into AC power for output, and has the following structure: It has a pair of DC terminals 631 and 632 for inputting DC power and AC terminals 633 to 635 for outputting AC power and having the same number as the number of phases of the AC power. For each of the AC terminals 633 to 635 corresponding to the number of phases, a series circuit having the following structure is connected between one terminal (P terminal 631) and the other terminal (N terminal 632) of the pair of DC terminals 631 and 632: Two parallel circuits (for example, the parallel circuit of the power switching element 601 and the diode 621) formed by connecting a switching element (for example, the power switching element 601) and a diode having a polarity opposite to that of the switching element (for example, the diode 621) in parallel with each other are connected in series (for example, the series circuit of the parallel circuit of the power switching element 601 and the diode 621 and the parallel circuit of the power switching element 602 and the diode 622), and the connection point of the two parallel circuits constituting the series circuit is connected to the AC terminal (for example, the U terminal 633) corresponding to the phase (for example, the U phase) of the series circuit.

[0122] By applying the IGBT semiconductor chip 101 described in the above Embodiments 1 to 3 to the power switching element of the power conversion device as in the present embodiment, the reliability improvement and long life of the power conversion device are achieved.

[0123] In addition, the present invention is not limited to the above-described embodiments, and includes various modification examples. For example, the above-described embodiments are examples described in detail for easily understanding the present invention, and do not have to be limited to having all the structures described. A part of the structure of a certain embodiment can be replaced with the structure of another embodiment, or the structure of another embodiment can be added to the structure of a certain embodiment. In addition, it is also possible to add, delete, or replace other structures to a part of the structure of each embodiment.

Claims

1. A semiconductor device, characterized in that, Comprising: An active region formed on a main surface of a semiconductor substrate; and A guard ring region formed on the main surface so as to surround the active region, The guard ring region having: A guard ring formed on the semiconductor substrate; An interlayer insulating film formed on the semiconductor substrate so as to cover the guard ring; A field plate disposed on the interlayer insulating film and electrically connected to the guard ring via a contact penetrating the interlayer insulating film; and A protective film covering the field plate, The field plate is composed of a stacked structure of a first metal and a second metal, The first metal contacts the guard ring, The second metal is disposed in contact with the first metal and has a standard potential lower than that of the first metal, The ratio of the contact area of the first metal with the protective film to the contact area of the second metal with the protective film is 0.05 or less, and 90% or more of the upper surface area of the first metal is covered with the second metal which is an alloy mainly composed of Al, thereby suppressing the corrosion of the first metal caused by the standard potential difference between the first metal and the second metal, The second metal is covered with a stacked film in which an inorganic passivation film and an organic passivation film are stacked in sequence from the lower layer, and the generation of cracks is prevented by thinning the inorganic passivation film.

2. The semiconductor device according to claim 1, wherein Substantially all of the upper surface of the first metal is covered with the second metal, When the field plate is cross-sectioned, the end of the first metal and the end of the second metal are aligned.

3. The semiconductor device according to claim 1, wherein When the semiconductor device is cross-sectioned, both ends of the field plate protrude from both ends of the guard ring.

4. The semiconductor device according to claim 1, wherein A plurality of the guard rings are formed on the semiconductor substrate, For each of the plurality of guard rings, a corresponding contact and the field plate are formed.

5. The semiconductor device according to claim 1, wherein The guard ring region has a channel stop ring formed on the semiconductor substrate so as to surround the guard ring.

6. The semiconductor device according to claim 1, wherein The first metal is any one of Mo, TiW, TiN, Ti, Co, and Ni.

7. The semiconductor device according to claim 1, wherein The semiconductor device is an IGBT in which a plurality of trench gates are periodically arranged in the active region.

8. A power conversion device comprising: A pair of DC terminals; AC terminals having the same number as the number of phases of the AC; and A power conversion unit connected between the pair of DC terminals, having a structure in which two parallel circuits are connected in series and having the same number as the number of phases of the AC of the AC terminals connected to different connection points of the parallel circuits, and a switching element and a diode of opposite polarity are connected in parallel to the parallel circuit, The power conversion device is characterized in that The switching element is the semiconductor device according to any one of claims 1 to 7.

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