A super junction RB-IGBT device with low turn-on voltage

Abstract

The application discloses a low-onset-voltage super-junction RB-IGBT device, which comprises a metallized collector layer, a heavily doped polysilicon arranged above the metallized collector layer, an oxide layer arranged above the doped polysilicon, and two P-type collector regions symmetrically arranged above the metallized collector layer, wherein the P-type collector regions are arranged adjacent to the metallized collector layer, each P-type collector region is arranged adjacent to an N-type heavily doped region, the N-type heavily doped regions are arranged with a space between each other, and a P-type buried layer is arranged above each P-type collector region and the N-type heavily doped region. According to the application, the structure is simple and reasonable, the on-set voltage of the super-junction IGBT device can be reduced to 0.1 V through the P-type buried layer design on the back of the device, the on-state voltage of the device is greatly reduced, and the on-state loss of the device is reduced.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a superjunction RB-IGBT device with low turn-on voltage. Background Technology

[0002] Insulated Gate Bipolar Transistor (IGBT) has advantages such as high breakdown voltage, high current density, low turn-on voltage, high switching frequency, and low power loss. IGBT has been widely used in frequency converters, UPS, automotive electronics, rail transportation, and smart grids.

[0003] Superjunction IGBTs are novel power semiconductor devices that incorporate repeating PN pillars in the drift region, building upon the traditional IGBT structure. The formation of PN pillars has a similar effect on optimizing parameters such as breakdown voltage and forward voltage drop as superjunction MOS devices. The introduction of PN pillars allows the superjunction IGBT to achieve a transverse electric field generated by the mutual depletion of the PN pillars during forward voltage withstand, in addition to the longitudinal electric field of the Pbody-N-Drift junction. This modulates the triangular electric field distribution of the traditional IGBT into an approximately rectangular distribution, significantly improving the breakdown voltage capability of the superjunction IGBT. While maintaining a certain breakdown voltage, the concentration of the N-Drift layer can be significantly increased, resulting in a significant reduction in the forward voltage drop during forward conduction. The highly doped N-Drift region allows for a smaller total number of electrons and holes injected into the epitaxial layer when the device operates in conductance modulation mode compared to traditional IGBTs. This reduces the total number of holes that need to be extracted during turn-off. Simultaneously, the auxiliary effect of the P pillars enables the superjunction IGBT to turn off rapidly, significantly reducing the tail current time and lowering the turn-off loss.

[0004] A superjunction RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) is an IGBT device with reverse blocking capability, exhibiting equal voltage withstand capability in both forward and reverse directions. Driven by the development and demands of modern digital AC systems and power conversion modules, superjunction RB-IGBTs are crucial for power conversion efficiency, energy utilization, and system reliability. Two superjunction RB-IGBTs connected in anti-parallel can form a bidirectional switch, enabling control of bidirectional current flow. Compared to a traditional bidirectional switch consisting of two ordinary IGBTs and two FRDs, using superjunction RB-IGBTs eliminates the need for additional FRDs, saving on component count and reducing package size. Therefore, superjunction RB-IGBTs are suitable for applications in AC-AC conversion devices such as matrix converters and AC choppers.

[0005] The back of a superjunction RB-IGBT device contains a PN junction formed by a P-type collector region and an N-type drift region. Therefore, when the device is turned on, the collector voltage must exceed the turn-on voltage of the PN junction, typically around 0.7V. The turn-on voltage of the superjunction IGBT device is 0.7V plus the voltage drop across the drift region and the top MOS layer. Therefore, the turn-on voltage of a superjunction RB-IGBT device is necessarily greater than 0.7V, resulting in significant conduction losses. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a low turn-on voltage superjunction RB-IGBT device. Through a P-type buried layer design on the back side of the device, the turn-on voltage of the superjunction IGBT device can be reduced to 0.1V, significantly reducing the on-state voltage and thus lowering the conduction loss. To achieve the above-mentioned objective and other advantages of the present invention, a low turn-on voltage superjunction RB-IGBT device is provided, comprising:

[0007] Metallized current collector layer;

[0008] Heavily doped polycrystalline silicon, wherein the heavily doped polycrystalline silicon is disposed above the metallized collector layer;

[0009] An oxide layer is disposed above the doped polycrystalline silicon;

[0010] The P-type collector region is provided with two P-type collector regions symmetrically arranged about the metallized collector layer, and the P-type collector regions are arranged adjacent to the metallized collector layer.

[0011] Each of the P-type collector regions is adjacent to an N-type heavily doped region, and each N-type heavily doped region is spaced apart from the others.

[0012] A P-type buried layer is disposed above each of the P-type collector regions and the N-type heavily doped regions.

[0013] Preferably, the P-type buried layer is adjacent to an N-type drift zone, and P-type columns are symmetrically arranged in the N-type drift zone.

[0014] Preferably, an N-type epitaxial layer is disposed above the N-type drift region, and a trench gate is formed in the N-type epitaxial layer by reactive ion etching.

[0015] Preferably, the trench gate surface is thermally grown to form a gate oxide layer, and a gate formed of heavily doped polysilicon is deposited inside the trench gate, with P-type body regions formed by ion implantation and high-temperature annealing through a self-aligned process located on both sides of the trench gate.

[0016] Preferably, heavily doped N-type emitter regions are provided on both sides of the top of the trench gate, and borosilicate glass is provided on the side adjacent to the N-type epitaxial layer, with a metallized emitter on the upper surface above the borosilicate glass.

[0017] Preferably, the doping concentration and width of the P-type buried layer and the spacing between the P-type buried layer 4 are determined based on the device breakdown voltage, leakage current level and required turn-on voltage.

[0018] Preferably, the P-type embedded layer is not connected to the P-column.

[0019] Preferably, the P-pillars in the N-type drift region are not connected to the P-type body region in the N-type epitaxial layer.

[0020] Preferably, the P-pillar is formed by multiple epitaxial and ion implantation techniques, high-temperature diffusion processes, or deep trench etching and filling processes.

[0021] Compared with existing technologies, the advantages of this invention are as follows: It utilizes the intrinsic depletion region of the P-type buried layer and the N-type drift region to form a barrier layer, ensuring the device is in a cutoff state during reverse withstand voltage and controlling leakage current to a low level. During forward conduction, a lower collector voltage can reduce the width of the depletion region, forming an electron path, significantly reducing the turn-on voltage of the superjunction RB-IGBT device, reducing the forward conduction voltage drop, and thus reducing the conduction loss during device operation. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of the superjunction RB-IGBT device with low turn-on voltage according to the present invention;

[0023] Figure 2 This is a schematic diagram of an embodiment of the superjunction RB-IGBT device with low turn-on voltage according to the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] Reference Figure 1-2A low turn-on voltage superjunction RB-IGBT device includes: a metallized collector layer 1; heavily doped polysilicon 31 disposed above the metallized collector layer 1; an oxide layer 32 disposed above the doped polysilicon 31; two P-type collector regions 2 symmetrically disposed about the metallized collector layer 1, adjacent to the metallized collector layer 1; an N-type heavily doped region 3 adjacent to each P-type collector region 2, with each N-type heavily doped region 3 spaced apart; each P-type collector region... A P-type buried layer 4 is disposed above the heavily doped N-type region 3. The back side of the device changes from a single P-type collector region 4 to a structure similar to MOS. The two P-type buried layers 4 and the N-type drift region 5 will deplete each other when no external voltage is applied. The resistivity of the N-type drift region 5 is determined by the breakdown voltage of the superjunction RB-IGBT device. Careful design of the doping concentration of the P-type buried layer 4 and the spacing between the two P-type buried layers 4 ensures that the region between the two P-type buried layers 4 is completely depleted when no external voltage is applied. Therefore, the area from the collector 1 to the emitter 14 is off, ensuring the reverse breakdown voltage capability of the superjunction RB-IGBT device. When the gate voltage 10 is greater than the device threshold voltage and the collector voltage is applied, the width of the depletion region between the P-type buried layer 4 and the N-type drift region 5 decreases. When the width of the depletion region on both sides is less than the spacing between the P-type buried layers 4, an electron path is formed, and the superjunction RB-IGBT device is forward-biased. With the control device's reverse leakage current level, the device can be turned on when the collector voltage is as low as 0.1V, greatly reducing the turn-on voltage of the superjunction RB-IGBT device.

[0026] Furthermore, an N-type drift zone 5 is provided adjacent to the P-type buried layer 4, and P-pillars 6 are symmetrically arranged in the N-type drift zone 5.

[0027] Furthermore, an N-type epitaxial layer 7 is disposed above the N-type drift region 5, and a trench gate 8 is formed in the N-type epitaxial layer 7 by reactive ion etching.

[0028] Furthermore, a gate oxide layer 9 is formed on the surface of the trench gate 8 by thermal growth, and a gate 10 formed of heavily doped polysilicon is deposited in the trench gate 8, and P-type body regions 11 are formed by ion implantation and high-temperature annealing through a self-aligned process on both sides of the trench gate 8.

[0029] Furthermore, heavily doped N-type emitter regions 12 are provided on both sides of the top of the trench gate 8, and borosilicate glass 13 is provided on one side adjacent to the N-type epitaxial layer 7, with an upper surface metallized emitter 14 provided above the borosilicate glass 13.

[0030] Furthermore, the doping concentration and width of the P-type buried layer 4, as well as the spacing between the P-type buried layers 4, are determined based on the device breakdown voltage, leakage current level, and required turn-on voltage.

[0031] Furthermore, the P-type buried layer 4 is not connected to the P-column 6.

[0032] Furthermore, the P-pillars 6 in the N-type drift region 5 are not connected to the P-type body region in the N-type epitaxial layer 7.

[0033] Furthermore, the P-pillar 6 is formed through multiple epitaxial and ion implantation techniques, high-temperature diffusion processes, or deep trench etching and filling processes.

[0034] The device can be made of bulk silicon, silicon carbide, gallium arsenide, or silicon germanium, and the back side of the device does not have heavily doped polysilicon or an oxide layer, making the structure and manufacturing process simpler. However, the concentration, width, and spacing of the P-type buried layer need to be carefully designed to control leakage current during reverse breakdown voltage.

[0035] The number of devices and processing scale described herein are for the purpose of simplifying the description of the invention, and applications, modifications and variations thereof will be apparent to those skilled in the art.

[0036] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

Claims

1. A low turn-on voltage super junction RB-IGBT device, characterized in that, It comprises: a metalized collector layer (1); a heavily doped polysilicon (31) disposed above the metalized collector layer (1); an oxide layer (32) disposed above the heavily doped polysilicon (31); a P-type collector region (2), two P-type collector regions (2) are symmetrically disposed with respect to the metalized collector layer (1), and the P-type collector region (2) is disposed adjacent to the metalized collector layer (1); each P-type collector region (2) is disposed adjacent to an N-type heavily doped region (3), and each N-type heavily doped region (3) is disposed with a spacing therebetween; a P-type buried layer (4) is disposed above each P-type collector region (2) and N-type heavily doped region (3); the P-type buried layer (4) is disposed adjacent to an N-type drift region (5), and a P-column (6) is symmetrically disposed in the N-type drift region (5); an N-type epitaxial layer (7) is disposed above the N-type drift region (5), a slot gate (8) is formed in the N-type epitaxial layer (7) by reactive ion etching; a gate oxide layer (9) is formed on the surface of the slot gate (8) by thermal growth, and a gate (10) formed by depositing heavily doped polysilicon in the slot gate (8); a P-type body region (11) is formed by self-aligned ion implantation and high-temperature annealing on both sides of the slot gate (8); the doping concentration of the P-type buried layer (4) and the spacing between the two P-type buried layers (4) are designed so that the region between the two P-type buried layers (4) is completely depleted when no external voltage is applied.

2. The low turn-on voltage super junction RB-IGBT device of claim 1, wherein, a heavily doped N-type emitter region (12) is disposed on both sides of the top of the slot gate (8), and a boron phosphorus silicon glass (13) is disposed adjacent to one side of the N-type epitaxial layer (7), and an upper surface metalized emitter (14) is disposed above the boron phosphorus silicon glass (13).

3. The low turn-on voltage super junction RB-IGBT device of claim 1, wherein, The doping concentration and width of the P-type buried layer (4) and the spacing between the P-type buried layers (4) are determined according to the breakdown voltage, leakage level and required on-voltage of the device.

4. The low turn-on voltage super junction RB-IGBT device of claim 1, wherein, The P-type buried layer (4) is not connected to the P-column (6).

5. The low turn-on voltage super junction RB-IGBT device of claim 1, wherein, The P-column (6) in the N-type drift region (5) is not connected to the P-type body region in the N-type epitaxial layer (7).

6. The low turn-on voltage super junction RB-IGBT device of claim 1, wherein, The P-column (6) is formed by multiple epitaxial and ion implantation techniques, high-temperature diffusion processes, or by deep trench etching and filling processes.

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