A super junction RB-IGBT device structure and a manufacturing method thereof

Abstract

The application discloses a super-junction RB-IGBT device structure and a manufacturing method thereof, which comprises a metalized collector layer, a P-type collector region located above the metalized collector layer, a first N-type epitaxial layer located above the P-type collector region, and a second N-type epitaxial layer located above the first N-type epitaxial layer. A P-type buried layer is formed in the first N-type epitaxial layer by high-energy ion implantation, and a P column is arranged in the first N-type epitaxial layer and spaced from the P-type buried layer, wherein the P column is formed by a deep trench etching and backfilling process. According to the application, the super-junction RB-IGBT device has the ability to withstand reverse voltage, and various optimized structures can be adopted by designing the P-type collector region, so that the electrical performance and reliability of the super-junction RB-IGBT device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor, in particular to a super-junction RB-IGBT device structure and a manufacturing method thereof. BACKGROUND

[0002] RB-IGBT (Reverse Blocking Insulated Gate Bipolar Transistor) is a kind of IGBT device with reverse blocking capability, and has the same level of withstand voltage capability in forward and reverse directions. Driven by modern digital AC system and the development and demand of power conversion module, RB-IGBT is crucial to power conversion efficiency, energy utilization rate, system reliability, etc. Two RB-IGBTs in anti-parallel can form a bidirectional switch, which can control the current flowing in both directions. Compared with the traditional bidirectional switch composed of two ordinary IGBTs and two FRDs, RB-IGBT does not require additional FRD, saving the number of components, and reducing the package size. Therefore, RB-IGBT is suitable for application in matrix converter, AC chopper and other AC-AC conversion devices.

[0003] The conventional RB-IGBT is manufactured by using a non-punch-through (NPT) IGBT structure. However, the NPT-IGBT does not have a junction termination structure when it is in reverse blocking state, and cannot achieve the same withstand voltage capability as in forward direction. Therefore, the current processing method is to manufacture a heavily doped P-type region penetrating the entire chip from top to bottom in the terminal area of the device as a reverse blocking terminal structure (Takei, M; Natio, T; Ueno, K. The Reverse Blocking IGBT for Matrix Converter With Ultra-Thin Wafer Technology. Proceeding ISPSD2003, pp. 129-132). However, for IGBT devices of 600V and above, the manufacturing process of the heavily doped P-type region is complex, and occupies a large chip area, increasing the manufacturing difficulty and cost. In addition, using NPT structure has adverse effects on the forward on-state voltage drop and turn-off loss of the IGBT device. SUMMARY

[0004] In view of the deficiencies in the prior art, the present application aims to provide a super-junction RB-IGBT device structure and a manufacturing method thereof, which has the ability to withstand reverse blocking voltage, and can adopt various optimized structures through the design of the P-type collector region to improve the electrical performance and reliability of the super-junction RB-IGBT device. In order to achieve the above-mentioned purposes and other advantages according to the present application, a super-junction RB-IGBT device structure and a manufacturing method thereof are provided, comprising:

[0005] a metallized collector layer;

[0006] a P-type collector region above the metallized collector layer;

[0007] a first N-type epitaxial layer above the P-type collector region;

[0008] a second N-type epitaxial layer above the first N-type epitaxial layer;

[0009] a P-type buried layer formed by high-energy ion implantation in the first N-type epitaxial layer, and a P-column spaced from the P-type buried layer in the first N-type epitaxial layer, the P-column being formed by a deep trench etching and backfilling process.

[0010] Preferably, a trench gate is formed in the second N-type epitaxial layer by a reactive ion etching process, a gate oxide layer is formed on the surface of the trench gate by thermal growth, and a heavily doped polysilicon is deposited in the trench gate.

[0011] Preferably, a P-type body region is formed above the second N-type epitaxial layer by a self-aligned ion implantation and annealing process.

[0012] Preferably, a heavily doped N-type emitter region is arranged on both sides of an end of the trench gate away from the first N-type epitaxial layer, a boron phosphorus silicon glass is deposited above the second N-type epitaxial layer, and an upper surface metallized emitter is arranged above the boron phosphorus silicon glass.

[0013] Preferably, the thickness and doping concentration of the P-type buried layer are adjusted according to the device, the position of the P-type buried layer relative to the P-type collector region is adjusted according to the device structure, and the width of the P-type buried layer is determined by the P-column in the first N-type epitaxial layer.

[0014] Preferably, when the device architecture is an NPT structure, the P-type buried layer is arranged to be floating, and the P-type buried layer is connected to the P-type collector region.

[0015] When the device architecture is an FS structure, the P-type buried layer is arranged to be floating and is above the FS layer.

[0016] Preferably, the P-column in the first N-type epitaxial layer is not connected to the P-type body region in the second N-type epitaxial layer.

[0017] A manufacturing method of a super-junction RB-IGBT device structure, comprising the following steps:

[0018] S1, forming a P-type collector region and a first N-type epitaxial layer by wafer using an epitaxial wafer;

[0019] S2, forming a deep trench in the first N-type epitaxial layer by a reactive ion etching process;

[0020] S3, using the hard mask as a barrier layer, high-energy ion implantation is used to form a P-type doped layer in the first N-type epitaxial layer;

[0021] S4, using a backfill process to form a super-junction P column in the first N-type epitaxial layer;

[0022] S5, forming a second N-type epitaxial layer by epitaxy, and the resistivity of the second N-type epitaxial layer is greater than that of the first N-type epitaxial layer;

[0023] S6, forming a slot gate in the second N-type epitaxial layer by reactive ion etching;

[0024] S7, growing a gate oxide layer on the surface of the slot gate by dry oxidation;

[0025] S8, depositing heavily doped polysilicon in the slot gate and reverse etching to form a gate;

[0026] S9, forming a P-type body region above the second N-type epitaxial layer by self-alignment process, ion implantation and high-temperature push well, and the P-type doped layer diffuses to form a P-type buried layer finally;

[0027] S10, forming an emitter region by photolithography implantation in the P-type body region;

[0028] S11, depositing boron phosphorus silicon glass above the slot gate, high-temperature reflow, performing contact hole photolithography, etching a thickness of 3000-5000A of silicon, and depositing an upper surface metal to form an emitter;

[0029] S12, thinning the wafer after turning it over, and depositing a metal layer to form a collector.

[0030] Compared with the prior art, the present application has the beneficial effects that: the super-junction structure is manufactured by deep trench etching and backfill process, which can reduce the forward conduction voltage drop of the device and improve the switching speed. The P-type buried layer is manufactured by high-energy ion implantation after deep trench etching to obtain the reverse blocking capability of the device, and the manufacturing process is simple, does not occupy additional area, and saves chip cost. The P-type buried layer floating design does not affect the optimization of the collector side of the IGBT device, and the field stop (FS), transparent collector and other structures can be used on the collector side of the device to optimize the trade-off relationship between the forward conduction voltage drop, turn-off loss and safe operating area of the IGBT device. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a structure schematic diagram of a traditional NPT-IGBT device structure and a manufacturing method thereof;

[0032] Figure 2 It is a structure schematic diagram of a first embodiment of a super-junction RB-IGBT device structure and a manufacturing method thereof according to the present application;

[0033] Figure 3 Structure schematic diagram of a second embodiment of the super-junction RB-IGBT device structure and the manufacturing method thereof according to the present application;

[0034] Figure 4 Structure schematic diagram of a third embodiment of the super-junction RB-IGBT device structure and the manufacturing method thereof according to the present application;

[0035] Figures 5-1 to 5-12 Structure of the step manufacturing process of the super-junction RB-IGBT device structure and the manufacturing method thereof according to the present application is as follows. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the protection scope of the present application.

[0037] Reference Figures 1-4 A super-junction RB-IGBT device structure and the manufacturing method thereof, comprising: a metallized collector layer 1; a P-type collector region 2 located above the metallized collector layer 1; a first N-type epitaxial layer 3 located above the P-type collector region 2; a second N-type epitaxial layer 4 located above the first N-type epitaxial layer 3; a P-type buried layer 102 formed in the first N-type epitaxial layer 3 by high-energy ion implantation, and a P-column 101 spaced apart from the P-type buried layer 102 in the first N-type epitaxial layer 3, the P-column 101 being formed by a deep trench etching and backfilling process. When the super-junction RB-IGBT device of the present application withstands a forward voltage, a longitudinal electric field is generated in the P-type body region in the first N-type epitaxial layer 3 and the second N-type epitaxial layer 4, and a transverse electric field is generated by the super-junction structure formed by the P-column and the N-type epitaxial layer in the first N-type epitaxial layer 3, and the two fields jointly make the device withstand the forward voltage. When the device is in a reverse blocking state, the transverse electric field is still generated by the super-junction structure formed by the P-column and the N-type epitaxial layer in the first N-type epitaxial layer 3, but the longitudinal electric field is jointly formed by the first N-type epitaxial layer 3, the P-type buried layer 102 and the P-type collector region, so that the device has the ability to withstand the reverse voltage. The floating P-type buried layer 102 can be fully depleted or partially depleted when the reverse voltage is applied. Optimizing the design of the P-type buried layer 102 can make the depletion layer generated by the adjacent two P-type buried layers 102 shield the P-type collector region 2, so that the P-type collector region 2 does not participate in the voltage resistance when the reverse voltage is applied. Therefore, the P-type collector region can adopt various optimized structures, which is beneficial to improving the electrical performance and reliability of the super-junction RB-IGBT device.

[0038] Further, a trench gate 5 is formed in the second N-type epitaxial layer 4 by reactive ion etching, a gate oxide layer 6 is formed on the surface of the trench gate 5 by thermal growth, and a heavily doped polysilicon 7 is deposited in the trench gate 5.

[0039] Further, a P-type body region 8 is formed above the second N-type epitaxial layer 4 by self-aligned ion implantation and annealing.

[0040] Further, a heavily doped N-type emitter region 9 is arranged on both sides of the end of the trench gate 5 away from the first N-type epitaxial layer 3, a boron phosphorus silicon glass 10 is deposited above the second N-type epitaxial layer 4, and an upper surface metallization emitter 11 is arranged above the boron phosphorus silicon glass 10.

[0041] Further, the thickness and doping concentration of the P-type buried layer 102 are adjusted according to the device, the position of the P-type buried layer 102 relative to the P-type collector region 2 is adjusted according to the device structure, and the width of the P-type buried layer 102 is determined by the P-pillar 101 in the first N-type epitaxial layer 3.

[0042] Further, when the device architecture is an NPT structure, the P-type buried layer 102 is arranged to be floating, and the P-type buried layer 102 is connected to the P-type collector region 2.

[0043] When the device architecture is an FS structure, the P-type buried layer 102 is arranged to be floating and is located above the FS layer.

[0044] Further, the P-pillar 101 in the first N-type epitaxial layer 3 is not connected to the P-type body region 8 in the second N-type epitaxial layer 4.

[0045] Reference Figures 5-1 to 5-12 A manufacturing method of a super-junction RB-IGBT device structure, comprising the following steps:

[0046] S1, forming a P-type collector region 2 and a first N-type epitaxial layer 3 by wafer using an epitaxial wafer;

[0047] S2, forming a deep trench in the first N-type epitaxial layer 3 by a reactive ion etching process;

[0048] S3, using a hard mask as a barrier layer, forming a P-type doped layer in the first N-type epitaxial layer 3 by high-energy ion implantation;

[0049] S4, forming a super-junction structure P-pillar 101 in the first N-type epitaxial layer 3 by a backfilling process;

[0050] S5, forming a second N-type epitaxial layer 4 by epitaxy, and the resistivity of the second N-type epitaxial layer 4 is greater than that of the first N-type epitaxial layer 3;

[0051] S6, forming a trench gate 5 in the second N-type epitaxial layer 4 by reactive ion etching;

[0052] S7, growing a gate oxide layer 6 on the surface of the trench gate 5 by dry oxidation;

[0053] S8, depositing heavily doped polysilicon 7 in the trench gate 5 and etching back to form a gate;

[0054] S9, forming a P-type body region 8 on the second N-type epitaxial layer 4 by self-alignment process, ion implantation and high temperature push well, and P-type doped layer diffusion to form a P-type buried layer 102;

[0055] S10, forming an emitter region 9 by photoetching implantation on the P-type body region 8;

[0056] S11, depositing boron phosphorus silicon glass 10 on the trench gate 5, high temperature reflow, photoetching a contact hole, etching 3000-5000 A thickness of silicon, and depositing an upper surface metal to form an emitter 11;

[0057] S12, thinning the wafer after turning it over, and depositing a metal layer to form a collector 1.

[0058] The number of devices and the scale of the processes described herein are intended to be illustrative of the application and the application is not limited to the specific details set forth herein. Variations in sizes, components, equipment and processes can be made that are apparent or apparent to one skilled in the art, without departing from the scope of the application.

[0059] While the embodiments of the application have been disclosed as above, it is not limited to the application and the modification and variation thereof as set forth in the specification and the embodiments, and it can be fully applied to various fields suitable for the application, and additional modifications can be easily made by those skilled in the art, and therefore the application is not limited to the specific details and the figures shown and described herein, without departing from the general concept defined by the claims and the equivalent scope.

Claims

1. A method of fabricating a super junction RB-IGBT device structure, the super junction RB-IGBT device structure comprising: A metallized collector layer (1); A P-type collector region (2) is located above the metallized collector layer (1); A first N-type epitaxial layer (3) is located above the P-type collector region (2); A second N-type epitaxial layer (4) is located above the first N-type epitaxial layer (3); A P-type buried layer (102) is formed in the first N-type epitaxial layer (3) by high-energy ion implantation, and a P-column (101) is arranged in the first N-type epitaxial layer (3) at intervals with the P-type buried layer (102), and the P-column (101) is formed by deep trench etching and backfilling process; characterized in that the manufacturing method comprises: S1, forming a P-type collector region (2) and a first N-type epitaxial layer (3) by wafer using an epitaxial wafer; S2, forming a deep trench in the first N-type epitaxial layer (3) by a reactive ion etching process; S3, using a hard mask as a barrier layer, a high-energy ion implantation is used to form a P-type doped layer in the first N-type epitaxial layer (3); S4, using a backfilling process to form a super-junction structure P-column (101) in the first N-type epitaxial layer (3); S5, forming a second N-type epitaxial layer (4) by epitaxy, and the resistivity of the second N-type epitaxial layer (4) is greater than that of the first N-type epitaxial layer (3); S6, forming a slot gate (5) in the second N-type epitaxial layer (4) by a reactive ion etching process; S7, growing a gate oxide layer (6) on the surface of the slot gate (5) by dry oxidation; S8, depositing heavily doped polysilicon (7) in the slot gate (5) and back etching to form a gate; S9, forming a P-type body region (8) above the second N-type epitaxial layer (4) by a self-alignment process, ion implantation and high-temperature push well, and the P-type doped layer diffuses to form a P-type buried layer (102) finally; S10, forming an emitter region (9) by photolithography implantation in the P-type body region (8); S11, depositing boron phosphorus silicon glass (10) above the slot gate (5), high-temperature reflow, performing contact hole lithography, etching silicon with a thickness of 3000-5000A, and depositing an upper surface metal to form an emitter (11); S12, after turning over the wafer, thinning and depositing a metal layer to form a collector (1).

2. The method of manufacturing a super junction RB-IGBT device structure according to claim 1, wherein, The thickness and doping concentration of the P-type buried layer (102) are adjusted according to the device, and the position of the P-type buried layer (102) relative to the P-type collector region (2) is adjusted according to the device structure, and the width of the P-type buried layer (102) is determined by the P-column (101) in the first N-type epitaxial layer (3).

3. The method of manufacturing a super junction RB-IGBT device structure according to claim 2, wherein, When the device architecture is NPT structure, the P-type buried layer (102) is floatingly arranged, and the P-type buried layer (102) is connected with the P-type collector region (2); When the device architecture is FS structure, the P-type buried layer (102) is floatingly arranged and located above the FS layer.

4. The method of manufacturing a super junction RB-IGBT device structure of claim 1, wherein, The P-column (101) in the first N-type epitaxial layer (3) is not connected with the P-type body region (8) in the second N-type epitaxial layer (4).

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