Memory device and calculation result compensation method thereof

Abstract

The present invention discloses a memory device and a method for compensating a calculation result thereof. The memory device includes a memory sub-block, a reference memory sub-block and a control circuit. The memory sub-block is used to receive an input signal in a calculation phase, and to perform a multiplication and addition operation according to the input signal in the calculation phase to generate a calculation result. The reference memory sub-block has a plurality of storage units and is pre-written with a reference weight value. The reference memory sub-block receives a reference input signal in a calibration phase, and performs a multiplication and addition operation according to the reference input signal and the reference weight value to generate a reference calculation value. The control circuit generates an adjustment value according to the reference calculation value and the standard calculation value, and the control circuit adjusts the calculation result according to the adjustment value in the calculation phase to generate an adjusted calculation result.

Description

Technical Field

[0001] The present invention relates to a memory device and a calculation result compensation method thereof, and more particularly to a memory device used for computation in memory (CIM) and a calculation result compensation method thereof. Background Art

[0002] As artificial intelligence technology is gaining more and more attention, the demand for building neural network computing circuits has increased significantly. In order to save circuit area and meet the needs of a large number of possible calculations, a memory calculator has been proposed.

[0003] The calculator in the memory has multiple storage cells, and writes weight values ​​to the storage cells, and then receives input signals through bit lines to generate the result of multiplication and addition operations on the source line according to the input signals and weight values. However, in actual applications, the storage cells may produce electrical changes due to various factors, resulting in incorrect operation results, such as process parameter drift during the manufacturing process, temperature changes during the application process, voltage changes, and degradation of the storage cells.

[0004] Please refer to Figure 1 State curve diagram of memory cell current drift. Figure 1 The horizontal axis of the coordinate is the current of the memory cell, and the vertical axis is the number of memory cells. The ideal current distribution of the memory cell should be as shown by the straight line IL. Under the influence of process parameter drift, temperature drift and / or voltage drift, the current distribution of the memory cell is as shown by curve CV3, in which the distribution range will expand, and the center of the distribution range will shift from the straight line IL. In the case of degradation of the memory cell, the current distribution of the memory cell is as shown by curve CV2. The above changes in the current distribution of the memory cell will cause errors in the calculation results and reduce the working efficiency of the calculator in the memory. Summary of the invention

[0005] The invention provides a memory device and a calculation result compensation method thereof, which can improve the accuracy of the calculation result.

[0006] The memory device of the present invention includes a first memory sub-block, a reference memory sub-block and a control circuit. The first memory sub-block is arranged in the memory block, and is used to receive an input signal in the operation phase, and perform multiplication and addition operations according to the input signal in the operation phase to generate an operation result. The reference memory sub-block is arranged in the same memory block, has a plurality of storage cells and is pre-written with a reference weight value, and receives a reference input signal in the calibration phase, and performs multiplication and addition operations according to the reference input signal and the reference weight value to generate a reference operation value. The control circuit generates an adjustment value according to the reference operation value and the standard operation value, and the control circuit adjusts the operation result according to the adjustment value in the operation phase to generate an adjusted operation result.

[0007] The calculation result compensation method of the present invention is applicable to arithmetic units in a memory. The compensation method comprises: providing a reference memory sub-block, and pre-writing a reference weight value into a plurality of storage units of the reference memory sub-block; in a calibration phase, the reference memory sub-block receives a reference input signal, and performs a multiplication and addition operation according to the reference input signal and the reference weight value to generate a reference calculation value; providing a memory sub-block to receive an input signal in a calculation phase, and performing a multiplication and addition operation according to the input signal in a calculation phase to generate a calculation result; and providing a control circuit to generate an adjustment value according to the reference calculation value and the standard calculation value, and adjusting the calculation result according to the adjustment value in the calculation phase to generate an adjusted calculation result.

[0008] Based on the above, the present invention sets a reference memory sub-block in a memory device. By having a plurality of memory cells of the reference memory sub-block pre-written with reference weight values, a reference operation value is generated according to the reference weight value provided by the reference memory sub-block, and then the reference operation value and the standard operation value are used to generate an adjustment value. The memory device of the present invention compensates the operation result generated by the general memory sub-block by adjusting the value, and can improve the accuracy of the adjusted operation result. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a state curve diagram of the memory cell current drift.

[0010] Figure 2 A schematic diagram of a memory device according to an embodiment of the present invention is shown.

[0011] Figure 3 A schematic diagram of the operation flow of a memory device according to an embodiment of the present invention is shown.

[0012] Figure 4 A schematic diagram of a memory device according to another embodiment of the present invention is shown.

[0013] Figure 5A schematic diagram illustrating a memory device and a current distribution adjustment operation according to another embodiment of the present invention is shown.

[0014] Figure 6 A flow chart of a calculation result compensation method according to an embodiment of the present invention is shown.

[0015]

Explanation of symbols

[0016] 200, 400, 500: Memory device

[0017] 210, 410, 511~51N: memory sub-blocks

[0018] 220, 420, 521~52N: Reference memory sub-blocks

[0019] 230, 430, 531~53N: Control circuit

[0020] 431: Cache

[0021] 432: Quantizer

[0022] 433: Divider

[0023] 434: Multiplier

[0024] 501~50N:Memory block

[0025] ACR: Adjusted Calculation Result

[0026] CPH: Tuning phase

[0027] CR: operation result

[0028] CV2, CV3, ID, RC1~RCN, RC1'~RCN': Curve

[0029] IL: Straight Line

[0030] IN1: Input signal

[0031] INR: Reference input signal

[0032] OPH: Operational Phase

[0033] OUT1, OUT2: output value

[0034] RATIO: Adjustment value

[0035] RCV: Reference calculation value

[0036] Ref: Reference signal

[0037] S311~S313, S321~S322, S610~S640: Steps

[0038] SA: Sense Amplifier

[0039] VCC: power supply voltage

[0040] VSS: Ground voltage DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0042] Please refer to Figure 2 , Figure 2 A schematic diagram of a memory device according to an embodiment of the present invention is shown. The memory device 200 is used to perform an in-memory operation. The memory device 200 includes a memory sub-block 210, a reference memory sub-block 220, and a control circuit 230. The memory sub-block 210 and the reference memory sub-block 220 are arranged in the same physical memory block of the memory device 200. The memory sub-block 210 is used to receive an input signal IN1 during the operation phase, and to perform a multiplication and addition operation according to the input signal IN1 during the operation phase to generate an operation result CR. Before the operation phase, a plurality of storage cells in the memory sub-block 210 may be written with a plurality of weight values, and these weight values ​​may be determined during the operation process of the neural network. In addition, during the operation phase, the storage cells in the memory sub-block 210 may receive the input signal IN1 through the bit line, and the weight value in the storage cell is multiplied by the corresponding received input signal IN1 to generate a product, and then the products generated by the plurality of storage cells are added to obtain the operation result CR.

[0043] On the other hand, a plurality of memory cells in the reference memory sub-block 220 are pre-written with a reference weight value. In the present embodiment, all memory cells in the reference memory sub-block 220 are written with the same reference weight value. Furthermore, in the calibration phase, the reference memory sub-block 220 can receive a reference input signal INR, and perform multiplication and addition operations based on the reference input signal INR and the reference weight value to generate a reference operation value RCV. Among them, the memory cells in the reference memory sub-block 220 receive the corresponding reference input signal INR through the bit line, and multiply the reference input signal INR with the reference weight value provided by the memory cell to obtain a product. Furthermore, the reference memory sub-block 220 adds the multiple products of the corresponding plurality of memory cells to generate the reference operation value RCV.

[0044] On the other hand, the control circuit 230 is coupled to the memory sub-block 210 and the reference memory sub-block 220. In the calibration phase, the control circuit 230 receives the reference operation value RCV generated by the reference memory sub-block 220, and generates an adjustment value according to the reference operation value RCV and the standard operation value. In the operation phase, the control circuit 230 adjusts the operation result CR generated by the memory sub-block 210 according to the adjustment value, and thereby generates an adjusted operation result ACR.

[0045] Here, the standard operation value is a value that can be generated by the reference memory sub-block 220 performing multiplication and addition operations according to the reference weight value and the reference input signal INR under an ideal state. The standard operation value can be stored in the control circuit 230 in advance. The control circuit 230 can divide the standard operation value by the reference operation value RCV, and generate an adjustment value by calculating the ratio of the standard operation value to the reference operation value RCV. In addition, in the operation stage, the control circuit 230 can multiply the adjustment value by the operation result CR to obtain the adjusted operation result ACR, and thereby compensate for the offset of the memory sub-block 210 caused by various variables to improve the accuracy of the operation in the memory.

[0046] Incidentally, in the embodiment of the present invention, the memory cells in the memory sub-block 210 and the reference memory sub-block 220 may be flash memory cells. In the present embodiment, the memory sub-block 210 and the reference memory sub-block 220 may be NAND flash memory sub-blocks, but are not limited thereto. In addition, the memory device 200 may be a memory device arranged in two dimensions or three dimensions, without any particular limitation.

[0047] It should be noted that in the embodiment of the present invention, there may be multiple memory sub-blocks 210 , and the memory sub-blocks 210 and the reference memory sub-blocks 220 may be disposed in the same physical memory block.

[0048] Please refer to Figure 3 , Figure 3 A schematic diagram of the operation flow of a memory device according to an embodiment of the present invention is shown. An input signal as a reference input signal INR is input to a reference memory sub-block, and a calibration phase CPH is performed. In step S311 of the calibration phase CPH, a reference weight value is written to a storage unit in the reference memory sub-block in advance, and a multiplication and addition operation is performed based on the reference weight value and the reference input signal INR. Then, the result of the multiplication and addition operation can be used to generate a digital reference operation value RCV through a sense amplifier (SA) (step S312). And in step S313, an adjustment value RATIO is generated by calculating the ratio of the standard operation value to the reference operation value RCV.

[0049] Then, the operation phase OPH can be performed. In the operation phase OPH, the input signal IN1 is input into the memory sub-block. In step S321, the memory sub-block performs a multiplication and addition operation based on the input signal IN1 and the stored weight value. It is worth mentioning that the weight value stored in the memory sub-block can be adjusted according to the neural network operation action, and the weight values ​​stored in the storage units in the memory sub-block can be the same or different without special restrictions.

[0050] The operation result generated in step S321 can be provided to the sense amplifier SA to generate a digital operation result CR (step S322). Please note that the sense amplifier SA used in step S322 and step S312 can be the same hardware circuit.

[0051] Next, in step S323, the calculation result CR is multiplied by the adjustment value RATIO to obtain the adjusted calculation result ACR.

[0052] It is worth mentioning that in this embodiment, the reference weight value can be set according to the maximum value of the sensing range of the sensing amplifier SA. The reference weight value can be set so that the generated reference operation value is slightly smaller than the maximum value of the sensing range of the sensing amplifier SA, but is not limited thereto.

[0053] Please refer to the following Figure 4 , Figure 4 A schematic diagram of a memory device according to another embodiment of the present invention is shown. The memory device 400 includes one or more memory sub-blocks 410, a reference memory sub-block 420, a sense amplifier SA, and a control circuit 430. The memory sub-block 410 and the reference memory sub-block 420 are arranged in a physical memory block in the memory device 400. The control circuit 430 includes a buffer 431, a quantizer 432, a divider 433, and a multiplier 434. The storage unit in the reference memory sub-block 420 is pre-written with a reference weight value. In the calibration phase, the reference memory sub-block 420 performs a multiplication and addition operation with the reference weight value according to the received reference input signal to generate an output value OUT1. The output value OUT1 is transmitted to the sense amplifier SA for sensing, and a reference operation value RCV is generated. The reference operation value RCV1 is transmitted to the control circuit 430. The divider 433 of the control circuit 430 divides the standard operation value with the reference operation value RCV to generate an adjustment value. In the embodiment of the present invention, the control circuit 430 further provides a quantizer 432 to perform a quantization operation on the adjustment value and generate a quantized adjustment value RATIO. The quantized adjustment value RATIO can be stored in the buffer 431.

[0054] On the other hand, in the operation stage, one of the plurality of memory sub-blocks 410 is selected, and a multiplication and addition operation is performed according to the received input signal and the weight value in the memory sub-block 410, and an output value OUT2 is generated. The output value OUT2 is transmitted to the sense amplifier SA for sensing, and an operation result CR is generated. The operation result CR is transmitted to the multiplier 434. The multiplier 434 multiplies the operation result CR with the adjustment value RATIO, and thereby generates an adjusted operation result ACR.

[0055] In this embodiment, the calibration phase can be generated periodically, and the variation of the working parameters of the memory device 400 and the degradation state of the memory cell can be reflected in real time, and the appropriate adjustment value RATIO can be generated accordingly. Based on the fact that the memory cells in the reference memory sub-block 420 and the memory sub-block 410 may have the same degradation trend, the embodiment of the present invention can also effectively reflect the degradation of the memory cell and effectively compensate the calculation result based on the adjustment value RATIO generated by the reference memory sub-block 420.

[0056] Incidentally, in the present embodiment, the sense amplifier SA operates between the power supply voltage VCC and the ground voltage VSS, and receives the reference signal Ref as a sensing basis. The circuit architecture of the sense amplifier SA can be implemented by any sense amplifier circuit known to those skilled in the art without any particular limitation. In addition, the circuit architecture of the buffer 431, the quantizer 432, the divider 433, and the multiplier 434 in the embodiment of the present invention can also be implemented by related circuits known to those skilled in the art without any particular limitation.

[0057] Please refer to Figure 5 , Figure 5 A schematic diagram illustrating a memory device and a current distribution adjustment operation according to another embodiment of the present invention is shown. Figure 5 The horizontal axis of the coordinate is the current of the memory cell, and the vertical axis is the number of memory cells. The memory device 500 includes a plurality of memory blocks 501-50N and a plurality of control circuits 531-53N. The memory blocks 501-50N respectively include a plurality of memory sub-blocks 511-51N, and respectively include a plurality of reference memory sub-blocks 521-52N. The reference memory sub-blocks 521-52N correspond to the memory sub-blocks 511-51N, respectively, and the memory cells in the reference memory sub-blocks 521-52N can be pre-written with the same reference weight value. The reference memory sub-blocks 521-52N can provide reference operation values ​​to the control circuits 531-53N respectively in the calibration phase. And in the operation phase, the control circuits 531-53N respectively adjust the operation results generated by the memory sub-blocks 511-51N according to the reference operation values, and generate a plurality of adjusted operation results.

[0058] In this embodiment, the standard operation value can be set to define the same standard current distribution curve ID for multiple memory sub-blocks 511-51N. Under the condition that one or more variables occur, the current distribution curves RC1-RCN of the memory sub-blocks 511-51N may not be consistent, but after the adjustment action of the embodiment of the present invention, the center point of the current distribution curve RC1'-RCN' of the adjusted operation result can be aligned with the center point of the standard current distribution curve ID, and the uniformity of the operation results generated by the multiple memory sub-blocks 511-51N is improved, thereby improving the error tolerance of the memory device 500.

[0059] Please refer to Figure 6 , Figure 6 A flow chart of a calculation result compensation method according to an embodiment of the present invention is shown. The calculation result compensation method of this embodiment is applicable to a calculation unit in a memory. In the calculation result compensation method, in step S610, a reference memory sub-block is provided, and a reference weight value is pre-written in a plurality of storage cells of the reference memory sub-block. Among them, the reference weight values ​​pre-written in the plurality of storage cells in the reference memory sub-block may be the same. In step S620, the reference memory sub-block is made to receive a reference input signal in the calibration phase, and a multiplication and addition operation is performed according to the reference input signal and the reference weight value to generate a reference calculation value. In addition, in step S630, a memory sub-block is provided to receive an input signal in the calculation phase, and a multiplication and addition operation is performed according to the input signal in the calculation phase to generate a calculation result. In addition, in step S640, a control circuit is provided to generate an adjustment value according to the reference calculation value and the standard calculation value, and the calculation result is adjusted according to the adjustment value in the calculation phase to generate an adjusted calculation result.

[0060] The implementation details of the above steps have been fully described in the aforementioned multiple embodiments and will not be elaborated here.

[0061] In summary, a reference memory sub-block is set in the memory device of the present invention. A reference weight value is written in the reference memory sub-block, and a reference operation value of a multiplication and addition operation performed by the reference memory sub-block according to the reference weight value is compared with a preset standard operation value to generate an adjustment value. In this way, the operation result generated by a general memory sub-block can be compensated by the adjustment value, and an adjusted operation result with relatively high accuracy can be generated.

[0062] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device, include: A memory sub-block is disposed in a memory block, the memory sub-block is used to receive an input signal in an operation phase, and perform a multiplication and addition operation according to the input signal in the operation phase to generate an operation result; a reference memory sub-block, disposed in the memory block, the reference memory sub-block having a plurality of storage units and pre-written with a reference weight value, the reference memory sub-block receiving a reference input signal in a calibration phase, and performing a multiplication and addition operation according to the reference input signal and the reference weight value to generate a reference operation value; as well as A control circuit generates an adjustment value according to the reference operation value and a standard operation value. The control circuit adjusts the operation result according to the adjustment value in the operation stage to generate an adjusted operation result. 2 . The memory device according to claim 1 , wherein the control circuit calculates a ratio of the standard operation value and the reference operation value to obtain the adjustment value, and the control circuit multiplies the adjustment value and the operation result to generate the adjusted operation result.

3. The memory device according to claim 2, wherein the control circuit include: a divider for calculating a ratio of the standard operation value to the reference operation value to obtain the adjustment value; as well as A multiplier multiplies the adjustment value and the operation result to generate the adjusted operation result.

4. The memory device according to claim 3, wherein the control circuit is further include: A buffer for buffering a quantized adjustment value; as well as A quantizer quantizes the adjustment value to generate the quantized adjustment value.

5. The memory device according to claim 1, further comprising: include: A sense amplifier senses the output of the reference memory sub-block in the calibration phase to generate the reference operation value, and senses the output of the memory sub-block in the operation phase to generate the operation result. 6 . The memory device of claim 5 , wherein the reference weight value is set according to a maximum value of a sensing range of the sense amplifier.

7. A method for compensating a calculation result, applicable to a calculation unit in a memory, include: Providing a reference memory sub-block, and pre-writing a reference weight value into a plurality of storage cells of the reference memory sub-block; In a calibration phase, the reference memory sub-block receives a reference input signal, and performs a multiplication and addition operation according to the reference input signal and the reference weight value to generate a reference operation value; Providing a memory sub-block to receive an input signal in a calculation phase, and performing a multiplication and addition operation according to the input signal in the calculation phase to generate a calculation result; and A control circuit is provided to generate an adjustment value according to the reference operation value and a standard operation value, and to adjust the operation result according to the adjustment value in the operation stage to generate an adjusted operation result.

8. The calculation result compensation method according to claim 7, wherein the control circuit is provided to generate the adjustment value according to the reference calculation value and the standard calculation value, and the calculation result is adjusted according to the adjustment value to generate the adjusted calculation result in the calculation stage. include: Providing the control circuit to calculate the ratio of the standard operation value and the reference operation value to generate the adjustment value; as well as The control circuit is provided to multiply the adjustment value and the operation result to generate the adjusted operation result. 9 . The calculation result compensation method according to claim 7 , further comprising causing the control circuit to quantize the adjustment value.

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