Chip and Electronic Device

Abstract

An embodiment of the present application provides a chip and an electronic device. The chip includes: a first memory; a second memory, the read / write speed of the second memory being less than that of the first memory; a processor electrically connected to the first memory and the second memory, the processor being configured to: when the chip is started, load at least part of the code of the operating system into the first memory for running, and simultaneously initialize the second memory, and after the initialization of the second memory is completed, transfer the part of the code from the first memory to the second memory for running, where the operating system is the operating system of the chip. When the chip is started, the running of the operating system and the initialization of the second memory can be carried out simultaneously, without waiting for the initialization of the second memory to be completed before starting to run the operating system, thereby accelerating the startup speed of the operating system of the chip.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to a chip and an electronic device. Background Art

[0002] In electronic devices such as smart phones, a main chip is usually provided. The main chip is used to process the data of the electronic device and monitor the electronic device as a whole. In addition, a chip for performing special functions is usually provided in the electronic device, such as an image pre-processing chip. The image pre-processing chip can be used to pre-process the image data obtained during the photographing process or the photographed image, such as pre-processing backlit photographing, high-dynamic range (HDR) photographing, etc. However, the chip for performing special functions usually has a slow startup speed. Summary of the Invention

[0003] Embodiments of this application provide a chip and an electronic device, which can accelerate the startup speed of the operating system of the chip.

[0004] Embodiments of this application provide a chip, including:

[0005] A first memory;

[0006] A second memory, the read / write speed of the second memory being less than the read / write speed of the first memory;

[0007] A processor, electrically connected to the first memory and the second memory. The processor is configured to: when the chip starts up, load at least part of the code of the operating system into the first memory for running, and at the same time initialize the second memory. After the initialization of the second memory is completed, transfer the part of the code from the first memory to the second memory for running, where the operating system is the operating system of the chip.

[0008] Embodiments of this application further provide a chip, including:

[0009] A first memory;

[0010] A processor, electrically connected to the first memory. The processor is configured to: when the chip starts up, load at least part of the code of the operating system into the first memory for running, and at the same time initialize a second memory. After the initialization of the second memory is completed, transfer the part of the code from the first memory to the second memory for running, where the operating system is the operating system of the chip, the second memory is an external memory, the processor is electrically connected to the second memory, and the read / write speed of the second memory is less than the read / write speed of the first memory.

[0011] The embodiment of the present application further provides an electronic device, including:

[0012] a chip, which is the above-mentioned chip;

[0013] a main chip, electrically connected to the chip, and the main chip is configured to: receive the interrupt signal sent by the chip and process the interrupt signal.

[0014] In the chip provided by the embodiment of the present application, when the chip starts up, the processor first loads at least part of the code of the operating system into the first memory for running, and at the same time initializes the second memory. After the initialization of the second memory is completed, part of the code stored in the first memory is transferred to the second memory for running. Therefore, the operation of the operating system and the initialization of the second memory can be carried out simultaneously, without waiting for the initialization of the second memory to be completed before starting to run the operating system, thereby accelerating the startup speed of the operating system of the chip. Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0016] Figure 1 It is the first structural schematic diagram of the electronic device provided by the embodiment of the present application.

[0017] Figure 2 It is the first structural schematic diagram of the chip provided by the embodiment of the present application.

[0018] Figure 3 It is the second structural schematic diagram of the electronic device provided by the embodiment of the present application.

[0019] Figure 4 It is the third structural schematic diagram of the electronic device provided by the embodiment of the present application.

[0020] Figure 5 It is the interaction schematic diagram of the chip and the main chip in the electronic device provided by the embodiment of the present application.

[0021] Figure 6 It is the second structural schematic diagram of the chip provided by the embodiment of the present application.

[0022] Figure 7 It is the fourth structural schematic diagram of the electronic device provided by the embodiment of the present application. Detailed Embodiments

[0023] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0024] An embodiment of the present application provides an electronic device. The electronic device may be a device such as a smart phone, a tablet computer, etc., and may also be a game device, an AR (Augmented Reality) device, an automotive device, a data storage device, an audio playback device, a video playback device, a laptop computer, a desktop computing device, etc.

[0025] Referring to Figure 1 , Figure 1 is a first structural schematic diagram of the electronic device 100 provided by the embodiment of the present application.

[0026] The electronic device 100 includes a display screen 11, a housing 12, a circuit board 13, and a battery 14.

[0027] Among them, the display screen 11 is disposed on the housing 12 to form a display surface of the electronic device 100 for displaying information such as images and texts. The display screen 11 may include a display screen of a type such as a liquid crystal display (LCD) or an organic light-emitting diode display (OLED).

[0028] It can be understood that a cover plate may also be disposed on the display screen 11 to protect the display screen 11 from being scratched or damaged by water. Among them, the cover plate may be a transparent glass cover plate, so that the user can observe the content displayed on the display screen 11 through the cover plate. For example, the cover plate may be a glass cover plate made of sapphire material.

[0029] The housing 12 is used to form the external contour of the electronic device 100 to facilitate accommodating the electronic components, functional components, etc. of the electronic device 100, and at the same time form a sealing and protecting effect on the electronic components and functional components inside the electronic device. For example, the camera, circuit board, vibration motor, and other functional components of the electronic device 100 can be disposed inside the housing 12.

[0030] The circuit board 13 is disposed inside the housing 12. Among them, the circuit board 13 may be the main board of the electronic device 100. One or more of functional components such as a camera, a headphone jack, an acceleration sensor, a gyroscope, and a motor may be integrated on the circuit board 13.

[0031] The battery 14 is disposed inside the housing 12. Among them, the battery 14 is electrically connected to the circuit board 13 and the display screen 11 to enable the battery 14 to supply power to the electronic device 100. It can be understood that a power management circuit may be provided on the circuit board 13. The power management circuit is used to distribute the voltage provided by the battery 14 to each electronic component in the electronic device 100.

[0032] In some embodiments, a chip is integrated on the circuit board 13. The chip can be used to execute preset functions. For example, the chip can be used for pre-processing of images, such as pre-processing for backlight photography, high-dynamic range (HDR) photography, etc. For another example, the chip can also be used for processing audio data, such as encrypting / decrypting audio data.

[0033] Reference Figure 2 , Figure 2 is the first structural schematic diagram of the chip 20 provided by the embodiment of the present application.

[0034] Among them, the chip 20 includes a first memory 21, a second memory 22, a processor 23, and a system bus 24.

[0035] In the description of the present application, it should be understood that terms such as "first" and "second" are only used to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.

[0036] Both the first memory 21 and the second memory 22 can be used to store data, such as storing image data, system data, etc. Among them, the read / write speed of the second memory 22 is less than that of the first memory 21.

[0037] It can be understood that for memories with the same storage space, the greater the read / write speed, the higher the cost of the memory. Therefore, in order to save costs, the storage space of the first memory 21 can be set smaller, and the storage space of the second memory 22 can be set larger, that is, the storage space of the first memory 21 is less than that of the second memory 22.

[0038] In some embodiments, the first memory 21 is a static random access memory (SRAM), and the second memory 22 is a double data rate synchronous dynamic random access memory (DDR).

[0039] It should be noted that when the chip 20 is started, the first memory 21 can store data without initialization, while the second memory 22 needs to be initialized before storing data.

[0040] The processor 23 is electrically connected to the first memory 21 and the second memory 22. The processor 23 can be used for data processing. Among them, the processor 23 can be, for example, a processor of types such as an Image Signal Processor (ISP), a Neural-network Processing Unit (NPU), and a Digital Signal Processor (DSP). The ISP can be used for processing such as dead pixel removal, stats statistics, and linearization of image data. The NPU can be used for enhancing image data. It can run an artificial intelligence training network to process image algorithms to improve the image quality while improving the efficiency of processing image data. The DSP can be used for processing image data with relatively small computational amounts. In addition, the DSP can also be used to assist the ISP and NPU in data processing.

[0041] The first memory 21, the second memory 22, and the processor 23 can be electrically connected to the system bus 24 respectively to achieve electrical signal transmission between the first memory 21, the second memory 22, and the processor 23.

[0042] Among them, the chip 20 has an operating system. The operating system can be, for example, a Real Time Operating System (RTOS). After the chip 20 is powered on and started, it first runs the operating system. The operating system can monitor and allocate the resources of the chip 20. Among them, the operating system is used to run application programs, and the application programs are used to implement preset functions. For example, the application program can be an image processing application, and the image processing application is used to process image data. For another example, the application program can be an audio processing application, and the audio processing application is used to process audio data.

[0043] Among them, the processor 23 is configured to: when the chip 20 is started, load at least part of the code of the operating system into the first memory 21 for running, and at the same time initialize the second memory 22. After the initialization of the second memory 22 is completed, transfer the part of the code from the first memory 21 to the second memory 22 for running. The operating system is the operating system of the chip 20.

[0044] It can be understood that when the electronic device 100 controls the chip 20 to power on, the chip 20 starts to boot up. At this time, the processor 23 can execute the above operations.

[0045] In addition, it can also be understood that the storage space required for the processor 23 to load a part of the code into the first memory 21 is smaller than the storage space of the first memory 21. For example, the processor 23 can load the code corresponding to 10 instructions for the initial operation of the operating system into the first memory 21 for running.

[0046] In another startup mode of the chip 20, when the chip 20 starts up, the processor 23 first initializes the second memory 22. When the initialization of the second memory 22 is completed, the processor 23 loads all the code of the operating system of the chip 20 into the second memory for running, thereby starting the operating system. Since the processor 23 cannot run the operating system when initializing the second memory 22, but can only wait for the initialization of the second memory 22 to be completed before starting to run the operating system, the startup speed of the chip 20 is slow.

[0047] In the chip 20 provided by the embodiment of the present application, when the chip 20 starts up, the processor 23 first loads at least part of the code of the operating system into the first memory 21 for running, and at the same time initializes the second memory 22. After the initialization of the second memory 22 is completed, the part of the code stored in the first memory 21 is transferred to the second memory 22 for running. Therefore, the operation of the operating system and the initialization of the second memory 22 can be carried out simultaneously, without waiting for the initialization of the second memory 22 to be completed before starting to run the operating system, thereby accelerating the startup speed of the operating system of the chip 20.

[0048] It can be understood that when the storage space of the first memory 21 is large enough such that the storage space of the first memory 21 is greater than the storage space required for all the code of the operating system, the at least part of the code can be all the code of the operating system. That is, when the chip 20 starts up, the processor 23 loads all the code of the operating system into the first memory 21 for running, and at the same time initializes the second memory 22. After the initialization of the second memory 22 is completed, all the code of the operating system stored in the first memory 21 is transferred to the second memory 22 for running.

[0049] It can also be understood that in some embodiments, when the part of the code loaded into the first memory 21 is less than all the code of the operating system, after the processor 23 transfers part of the code of the operating system from the first memory 21 to the second memory 22 for running, it can also load the remaining code of the operating system into the second memory 22 for running, so that the complete operating system code can be run to start the operating system. Wherein, the remaining code is the code in the complete code of the operating system except for the part of the code loaded into the first memory 21 for running.

[0050] It should be noted that in some embodiments, the second memory 22 may not be included in the chip 20, but be an external memory of the chip 20. And when it is an external memory, the second memory 22 is electrically connected to the processor 23 of the chip 20. For example, the second memory 22 may be the memory of the electronic device 100, such as the memory of the main chip of the electronic device 100, or may also be a memory independent of the chip 20 and the main chip.

[0051] Reference Figure 3 , Figure 3 FIG. 10 is a second schematic structural diagram of the electronic device 100 provided by the embodiment of the present application.

[0052] Wherein, the electronic device 100 includes the above-mentioned chip 20 and the main chip 30. The main chip 30 may also be integrated on the circuit board 13 of the electronic device 100. The main chip 30 can be used to run the operating system of the electronic device 100, such as running systems like Android, IOS, etc., so as to realize the overall monitoring of the electronic device 100 and the allocation and scheduling of the resources of the electronic device 100.

[0053] The chip 20 is electrically connected to the main chip 30, so that the main chip 30 can interact with the chip 20. For example, the main chip 30 can control the startup process of the chip 20. Wherein, the chip 20 can send an interrupt signal to the main chip 30, and the main chip 30 receives the interrupt signal and processes the interrupt signal, so as to realize the interaction with the chip 20.

[0054] Meanwhile, referring to Figure 4 , Figure 4 FIG. 11 is a third schematic structural diagram of the electronic device 100 provided by the embodiment of the present application.

[0055] The chip 20 further includes an interconnect bus interface 25. The interconnect bus interface 25 is electrically connected to the system bus 24, so as to realize the electrical signal transmission between the interconnect bus interface 25 and the first memory 21, the second memory 22, and the processor 23. Among them, the interconnect bus interface 25 is used to realize the electrical connection between the chip 20 and the main chip 30.

[0056] The main chip 30 includes a memory 31, an application processor 32, a system bus 33, and an interconnect bus interface 34.

[0057] Among them, the memory 31 is used to store various data of the electronic device 100. For example, it can be used to store the interaction data between the chip 20 and the main chip 30, can be used to store the operating system of the electronic device 100, can be used to store the instructions corresponding to the computer program, and can also be used to store such as image data, audio data, etc. In addition, it should be noted that the memory 31, as the main memory of the electronic device 100, is continuously in an operating state during the power-on operation of the electronic device 100. Therefore, the memory 31 can also be used to store the operating system of the chip 20.

[0058] The application processor 32 can serve as the control center and computing center of the electronic device 100, connect various parts of the electronic device 100 through various interfaces and lines, and execute various functions of the electronic device 100 and perform data processing by running or calling the computer program and data stored in the memory 31, so as to realize the overall monitoring and scheduling of the electronic device 100.

[0059] The memory 31 and the application processor 32 can be respectively electrically connected to the system bus 33 to realize the electrical signal transmission between the memory 31 and the application processor 32. For example, the application processor 32 can call the computer program and data stored in the memory 31 through the system bus 33.

[0060] The interconnect bus interface 34 is electrically connected to the system bus 33, so as to realize the electrical signal transmission between the interconnect bus interface 34 and the memory 31 and the application processor 32. Among them, the interconnect bus interface 34 is used to realize the electrical connection between the main chip 30 and the chip 20. For example, the interconnect bus interface 34 can be electrically connected to the interconnect bus interface 25 of the chip 20 to realize the electrical connection between the main chip 30 and the chip 20, so that the main chip 30 can realize the interaction with the chip 20.

[0061] Reference Figure 5 , Figure 5 is a schematic diagram of the interaction between the chip 20 and the main chip 30 in the electronic device provided in the embodiment of the present application.

[0062] The following describes the interaction process in which the processor 23 of the chip 20 loads at least part of the code of the operating system into the first memory 21 for running.

[0063] When the electronic device 100 needs to start the chip 20 to execute a preset function, the main chip 30 first controls the chip 20 to power on. After the chip 20 is powered on, the processor 23 of the chip 20 sends a first interrupt signal to the main chip 30. Among them, the first interrupt signal is used to request part of the code of the operating system of the chip 20 from the main chip 30. Subsequently, the main chip 30 inputs at least part of the code of the operating system to the chip 20. The first memory 21 of the chip 20 stores the part of the code in the first memory 21. Subsequently, the processor 23 runs the part of the code stored in the first memory 21, and at the same time the processor 23 initializes the second memory 22 of the chip 20. Thus, the processor 23 can load at least part of the code of the operating system into the first memory 21 for running.

[0064] Subsequently, after the initialization of the second memory 22 is completed, the processor 23 transfers the part of the code from the first memory 21 to the second memory 22. After transferring the part of the code to the second memory 22, the processor 23 can run the part of the code stored in the second memory 22.

[0065] Please also refer to Figure 6 , Figure 6 which is the second structural schematic diagram of the chip 20 provided by the embodiment of the present application.

[0066] Among them, the processor 23 of the chip 20 is built-in with a Direct Memory Access (DMA) 231. The DMA 231 can be used to transfer the part of the code from the first memory 21 to the second memory 22 after the initialization of the second memory 22 is completed.

[0067] Please continue to refer to Figure 5 , and the following describes the interaction process in which the processor 23 of the chip 20 loads the remaining code of the operating system into the second memory for running.

[0068] After the processor 23 transfers the partial code from the first memory 21 to the second memory 22, it sends a second interrupt signal to the main chip 30. The second interrupt signal is used to request the remaining code of the operating system from the main chip 30. Subsequently, the main chip 30 inputs the remaining code of the operating system to the chip 20. The second memory 22 of the chip 20 stores the remaining code in the second memory 22. Subsequently, the processor 23 runs the remaining code stored in the second memory 22. Thus, the processor 23 can load the remaining code of the operating system into the second memory 22 for running.

[0069] In some embodiments, before the processor 23 of the chip 20 loads at least partial code of the operating system into the first memory 21 for running, the processor 23 can also be initialized. For example, after the chip 20 is powered on, the registers in the processor 23 can start running the boot code to initialize the processor 23. The boot code can be solidified in the read-only memory (ROM) of the chip 20. After the initialization of the processor 23 is completed, the processor 23 can initialize the Universal Asynchronous Receiver / Transmitter (UART). The UART can be used to convert the data to be transmitted between serial communication and parallel communication.

[0070] In some embodiments, it can be understood that when the processor 23 initializes the second memory 22, it can first set a Power Management Unit (PMU) for the second memory 22, and the PMU supplies power to the second memory 22. Subsequently, the processor 23 initializes the second memory 22.

[0071] Reference Figure 7 , Figure 7 FIG. 13 is a fourth schematic structural diagram of the electronic device 100 provided by the embodiment of the present application.

[0072] The electronic device 100 further includes an image sensor 40, and the image sensor 40 is used to acquire image data. The image sensor 40 can be, for example, a camera of the electronic device 100. It can be understood that the number of the image sensors 40 can be one or more.

[0073] The chip 20 is electrically connected to the image sensor 40. For example, the chip 20 may be electrically connected to the image sensor 40 through the system bus 24. The operating system of the chip 20 may run an image processing application for processing the image data acquired by the image sensor 40.

[0074] For example, the chip 20 may be a pre-image processing chip (Pre-ISP). The pre-image processing chip may be used to process the photographing process of the electronic device 100, such as processing backlit photographing in the RAW domain, processing HDR (High-Dynamic Range) photographing, etc.

[0075] The chip and the electronic device provided in the embodiments of the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the present application. At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A chip, characterized in that, the chip is electrically connected to the main chip, and the chip includes: A first memory; A second memory, the read / write speed of the second memory being less than that of the first memory; A processor, electrically connected to the first memory and the second memory, the processor being configured to: when the chip is started, send a first interrupt signal to the main chip, the first interrupt signal being used to request part of the code of the operating system of the chip from the main chip, load at least part of the code of the operating system input by the main chip into the first memory for running, initialize the second memory at the same time, and after the initialization of the second memory is completed, transfer the part of the code from the first memory to the second memory for running.

2. The chip according to claim 1, characterized in that, the processor is built-in with a direct memory access controller, and the direct memory access controller is configured to: after the initialization of the second memory is completed, transfer the part of the code from the first memory to the second memory.

3. The chip according to claim 1, characterized in that, after the part of the code is transferred from the first memory to the second memory for running, the processor is further configured to: load the remaining code of the operating system into the second memory for running.

4. The chip according to claim 3, characterized in that, when the remaining code of the operating system is loaded into the second memory for running: the processor is configured to: send a second interrupt signal to the main chip; the second memory is configured to: store the remaining code of the operating system input by the main chip; the processor is further configured to: run the remaining code stored in the second memory.

5. The chip according to any one of claims 1 to 4, characterized in that, before loading at least part of the code of the operating system into the first memory for running, the processor is further configured to: initialize the processor; after the initialization of the processor is completed, initialize the universal asynchronous receiver / transmitter.

6. The chip according to any one of claims 1 to 4, characterized in that, the storage space of the first memory is smaller than that of the second memory.

7. The chip according to any one of claims 1 to 4, characterized in that, the first memory is a static random access memory, and the second memory is a double data rate synchronous dynamic random access memory.

8. The chip according to any one of claims 1 to 4, characterized in that, the operating system is used to run an image processing application, and the image processing application is used to process image data.

9. A chip, characterized in that, the chip is electrically connected to the main chip, and the chip includes: A first memory; A processor, electrically connected to the first memory, is configured to: when the chip is started, send a first interrupt signal to the main chip, where the first interrupt signal is used to request part of the code of the operating system of the chip from the main chip, load at least part of the code of the operating system input by the main chip into the first memory for running, initialize the second memory at the same time, and after the initialization of the second memory is completed, transfer the part of the code from the first memory to the second memory for running. The second memory is an external memory, the processor is electrically connected to the second memory, and the read / write speed of the second memory is less than that of the first memory.

10. The chip according to claim 9, wherein, the processor is built with a direct memory access controller, and the direct memory access controller is configured to: after the initialization of the second memory is completed, transfer the part of the code from the first memory to the second memory.

11. An electronic device, wherein, it includes: a chip, where the chip is the chip according to any one of claims 1 to 10; a main chip, electrically connected to the chip, and the main chip is configured to: receive the interrupt signal sent by the chip and process the interrupt signal.

12. The electronic device according to claim 11, wherein, it further includes: an image sensor, configured to acquire image data; the chip is electrically connected to the image sensor, and the image processing application running on the operating system of the chip is used to process the image data.

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