An FPGA-based SATA IP core and data storage method

Abstract

The application provides a FPGA-based SATA IP core and a data storage method, and relates to the technical field of data storage.A FPGA-based SATA IP core comprises a RAID array logic module, a plurality of SATA interface modules and a plurality of communication interface modules; each SATA interface module and each communication interface module are connected with the RAID array logic module; each SATA interface module is connected with a hard disk, wherein the RAID array logic module is used for acquiring external input data through the communication interface module and writing the external input data into the corresponding hard disk through the plurality of SATA interface modules; the RAID array logic module is also used for reading data from the hard disk through the plurality of SATA interface modules and outputting the data through the communication interface module; the RAID array logic module divides the hard disk into a plurality of array groups, and then adopts the RAID array technology to store data, thereby improving the reliability of data storage.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and more specifically, to an FPGA-based SATA IP core and data storage method. Background Technology

[0002] For real-time storage of high-speed digital signals, the current common approach is to directly write data to the Nandflash array using an FPGA. The Flash control algorithm (FTL algorithm) is implemented within the FPGA. While initial performance is good, after a period of use, common problems include blue screens, disk failures (storage devices disappearing from the system), frequent data loss for clients, and system unavailability. Furthermore, once these problems occur, they are difficult to repair using technical means, requiring replacement with a new card. Even the new card may experience similar issues after a period of use. Therefore, the reliability of current storage solutions is not high. Summary of the Invention

[0003] The purpose of this invention is to provide an FPGA-based SATA IP core and data storage method to improve the problem of low data storage reliability in the prior art.

[0004] In a first aspect, embodiments of this application provide an FPGA-based SATA IP core, including a RAID array logic module, multiple SATA interface modules, and multiple communication interface modules; each SATA interface module and each communication interface module is connected to the RAID array logic module; each SATA interface module is connected to a hard drive, wherein...

[0005] The RAID array logic module is used to acquire external input data through the communication interface module and write the external input data to the corresponding hard drive through multiple SATA interface modules; it is also used to read data from the hard drive through multiple SATA interface modules and output the data through the communication interface module.

[0006] In the above implementation process, the RAID array logic module obtains external input data through the communication interface module and writes the external input data to the corresponding hard drives through multiple SATA interface modules, thereby achieving the purpose of data storage; the RAID array logic module reads data from the hard drives through multiple SATA interface modules and outputs the data through the communication interface module, thereby achieving the purpose of data retrieval. The RAID array logic module divides the hard drives into multiple arrays and then uses RAID array technology for data storage. The aforementioned SATA IP core occupies an independent FPGA chip. By loading this IP core, the FPGA chip becomes a high-performance storage controller chip capable of array control of multiple SATA interface hard drives. External communication typically uses protocols such as RapidIO and Ethernet. Data communication is organized in frames as the basic unit, and each data frame is equipped with a CRC checksum and a frame sequence number, so data transmission errors are fully detectable. When a data communication error occurs, the communication logic will use a retransmission mechanism to retransmit the data until the data transmission is correct, thereby ensuring the reliability of data writing and reading. Meanwhile, based on the SATA protocol, data between the FPGA and each hard drive is organized and transmitted in frame format, and each frame also has a CRC checksum. Therefore, data transmission errors between the FPGA and SATA are fully detectable. Similarly, for occasional data transmission errors, the FPGA will re-initiate the read / write operation until the data transmission is correct. This improves the reliability of data writing and reading.

[0007] Based on the first aspect, in some embodiments of the present invention, a buffer management module is further included, and the RAID array logic module and the external storage chip are respectively connected to the buffer management module;

[0008] The buffer management module is used to buffer data to an external storage chip.

[0009] Based on the first aspect, in some embodiments of the present invention, an intelligent management module is also included. The intelligent management module is connected to the RAID array logic module and is used to monitor the data flow in the RAID array logic module and schedule it according to the monitoring results.

[0010] Based on the first aspect, in some embodiments of the present invention, the RAID array logic module includes a RAID logic unit, multiple SATA control logic units, and multiple FIFOs; the multiple SATA control logic units and multiple FIFOs are all connected to the RAID logic unit, and the multiple FIFOs are connected to a communication interface module; each SATA control logic unit is respectively connected to a respective SATA interface module; wherein,

[0011] The RAID logic unit is used to acquire external input data through multiple FIFOs and control the corresponding SATA interface modules for storage through multiple SATA control logic units; it is also used to read data from the SATA interface modules through multiple SATA control logic units.

[0012] Based on the first aspect, in some embodiments of the present invention, the SATA control logic unit includes a control interface and a data interface.

[0013] The control interface is used to send and receive command information with the RAID logic unit;

[0014] A data interface is used to transmit data information.

[0015] Based on the first aspect, in some embodiments of the present invention, the control interface includes a register interface and an instruction FIFO interface.

[0016] Register interface, used to read runtime status data;

[0017] The instruction FIFO interface is used to write instruction information.

[0018] Based on the first aspect, in some embodiments of the present invention, the data interface includes multiple FIFO interfaces, which are used to write or read data.

[0019] Based on the first aspect, in some embodiments of the present invention, the communication interface module includes an interface management unit and multiple high-speed serial ports, wherein the interface management unit is connected to the RAID array logic module and the multiple high-speed serial ports respectively; wherein,

[0020] High-speed serial port, used for data transmission;

[0021] The interface management unit is used to manage multiple high-speed serial ports.

[0022] Based on the first aspect, in some embodiments of the present invention, an LVDS bus interface is also included, which is connected to the interface management unit.

[0023] Secondly, embodiments of this application provide a data storage method based on an FPGA-based SATA IP core, comprising the following steps:

[0024] Obtain read / write command parameter information;

[0025] Extract the current storage information based on the read / write command parameters and display it to the user;

[0026] Get the start signal input by the user;

[0027] Based on the start signal, a preset FPGA-based SATA IP core is used to perform read and write operations on the data.

[0028] In the above implementation process, read and write instruction parameter information is obtained; then, the current storage information is extracted and displayed to the user based on the read and write instruction parameter information; then, the start signal input by the user is obtained; finally, the data is read and written using a preset FPGA-based SATA IP core according to the start signal. Since the data storage based on the FPGA-based SATA IP core has high reliability, the data reading and writing method can improve the reliability of fast data reading and writing.

[0029] The embodiments of the present invention have at least the following advantages or beneficial effects:

[0030] This invention provides an FPGA-based SATA IP core and data storage method. The hard drives are divided into multiple arrays using a RAID array logic module, and RAID array technology is then used for data storage. The SATA IP core occupies an independent FPGA chip. By loading this IP core, the FPGA chip becomes a high-performance storage controller chip capable of array control of multiple SATA interface hard drives. External communication typically uses protocols such as RapidIO and Ethernet. Data communication is organized in frames, each with a CRC checksum and frame sequence number, making data transmission errors fully detectable. When a data communication error occurs, the communication logic uses a retransmission mechanism to retransmit the data until the data is transmitted correctly, thus ensuring the reliability of data writing and reading. Simultaneously, based on the SATA protocol, data between the FPGA and each hard drive is also organized and transmitted in frame format, with each frame also equipped with a CRC checksum. Therefore, data transmission errors between the FPGA and SATA are also fully detectable. Similarly, for occasional data transmission errors, the FPGA will re-initiate read / write operations until the data is transmitted correctly, thereby improving the reliability of data writing and reading. A buffer pool is formed by connecting the buffer management module to the external storage chip. This buffers the real-time data stream from external inputs, smoothing out temporary bandwidth drops in the hard drive array. It also performs error-correcting caching; data is cached in DDR3 SDRAM until transmission is confirmed correct, at which point it is erased from the DDR3. For example, if an occasional error occurs while writing a data block to the hard drive, data from the buffer pool is retrieved and rewritten until the data is correctly written, thus improving data storage accuracy. The intelligent management module schedules and monitors the global logic, ensuring the IP core operates normally and guaranteeing data storage stability. The SATA control logic unit shields users from the complex SATA protocol, allowing for fast read / write control of SATA interface hard drives through a simple and easy-to-use logic interface. The process involves acquiring read / write command parameter information, extracting current storage information based on these parameters, displaying it to the user, obtaining the user's input start signal, and finally using a pre-configured FPGA-based SATA IP core to perform read / write operations. Since FPGA-based SATA IP cores offer high reliability for data storage, this method improves the reliability of data read / write. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A schematic diagram of an FPGA-based SATA IP core provided for an embodiment of the present invention;

[0033] Figure 2 This is a flowchart illustrating a data storage method based on an FPGA-based SATA IP core, as provided in an embodiment of the present invention.

[0034] Icons: 1-RAID array logic module; 2-Intelligent management module; 3-SATA interface module; 4-Hard disk; 5-Buffer management module; 6-External storage chip; 7-Interface management unit; 8-High-speed serial port; 9-LVDS bus interface. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0036] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0037] Example

[0038] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.

[0039] Please refer to Figure 1 , Figure 1This is a schematic diagram of an FPGA-based SATA IP core provided in an embodiment of the present invention. The FPGA-based SATA IP core includes a RAID array logic module 1, multiple SATA interface modules 3, and multiple communication interface modules. Each SATA interface module 3 and each communication interface module is connected to the RAID array logic module 1. Each SATA interface module 3 is connected to a hard disk 4. The RAID array logic module 1 is used to acquire external input data through the communication interface modules and write the external input data to the corresponding hard disk 4 through the multiple SATA interface modules 3; it is also used to read data from the hard disk 4 through the multiple SATA interface modules 3 and output the data through the communication interface modules.

[0040] The RAID array management logic described above is used to divide the hard drives into multiple array configurations, such as RAID 5, RAID 1, RAID 0, RAID 10, RAID 50, and RAID 51. For example, 10 hard drives can be divided into two groups, A and B, with 5 hard drives in each group. Each group can be configured in either RAID 0 or RAID 5 mode, and the two groups can be configured in RAID 10, RAID 50, or RAID 51 modes.

[0041] For example, the RAID 5 architecture is used. During data storage, RAID 5 generates redundant parity data, ensuring that even if one hard drive (disk 4) is permanently damaged or fails, the data is still completely preserved on the remaining hard drives (disk 4). When a user replaces a failed hard drive (disk 4) with a working one, the data on the new hard drive (disk 4) can be recovered from the remaining hard drives (disk 4). The 10 hard drives (disk 4) operate in parallel in RAID 5 mode. The system uses 8KB as the minimum management space. Each hard drive (disk 4) intermittently and stripes redundant information. Data or redundant information on any one hard drive (disk 4) can be calculated based on the data on the remaining hard drives (disk 4). When data enters the array system, it is organized in 8KB units. The hard drive (disk 4) and its space corresponding to the original data and the redundant data generated from the original data are determined based on the currently used LBA sector address, thus ensuring the reliability of data storage.

[0042] The RAID array logic module 1 includes a RAID logic unit, multiple SATA control logic units, and multiple FIFOs. The multiple SATA control logic units and multiple FIFOs are all connected to the RAID logic unit, and the multiple FIFOs are connected to the communication interface module. Each SATA control logic unit is connected to each SATA interface module 3. The RAID logic unit is used to acquire external input data through multiple FIFOs and control the corresponding SATA interface module 3 for storage through multiple SATA control logic units. It is also used to read data from the SATA interface module 3 through multiple SATA control logic units.

[0043] The aforementioned multiple FIFOs can be used for outputting operational status tracking data, receiving application commands, and inputting and outputting various types of data. The aforementioned RAID logic unit can configure the four hard drives into various array configurations, such as RAID 0, RAID 1, RAID 0, and RAID 5. The aforementioned SATA control logic unit includes the SATA transport layer and the SATA link layer.

[0044] The aforementioned SATA interface module 3 can be SATA 3.0, allowing the hard drive 4 to be selected and adapted to various hard drives 4 and solid-state drives that conform to the SATA 3.0 specification. The number of SATA interface modules 3 can be 10, corresponding to 10 connectable hard drives 4.

[0045] The communication interface module includes an interface management unit 7 and multiple high-speed serial ports 8. The interface management unit 7 is connected to the RAID array logic module 1 and the multiple high-speed serial ports, respectively.

[0046] High-speed serial port 8 is used for data transmission; it supports 4x RapidIO (5G), Fibre Channel (8G), 4x Xilinx Aurora, or PCIe protocols. The number of these high-speed serial ports 8 can vary depending on the specific FPGA model, and multiple data channels can be configured. This IP core typically uses protocols such as RapidIO and Ethernet for external communication. Data communication is organized in frames, each with a CRC checksum and frame sequence number, making data transmission errors fully detectable. When a data communication error occurs, the communication logic will use a retransmission mechanism to retransmit the data until the data is transmitted correctly, thus ensuring the reliability of data writing and reading.

[0047] The interface management unit 7 is used to manage multiple high-speed serial ports 8. The interface management unit 7 is connected to the RAID array logic module 1, thereby controlling the data transmission channels.

[0048] In the above implementation process, the RAID array logic module 1 obtains external input data through the communication interface module and writes the external input data to the corresponding hard disk 4 through multiple SATA interface modules 3, thereby achieving the purpose of data storage; the RAID array logic module 1 reads data from the hard disk 4 through multiple SATA interface modules 3 and outputs the data through the communication interface module, thereby achieving the purpose of data retrieval. The RAID array logic module 1 divides the hard disk 4 into multiple arrays and then uses RAID array technology for data storage. The aforementioned SATA IP core occupies an independent FPGA chip. By loading this IP core, the FPGA chip becomes a high-performance storage controller chip capable of array control of multiple SATA interface hard disks 4. External communication typically uses protocols such as RapidIO and Ethernet. Data communication is organized in frames as the basic unit. Each data frame is equipped with a CRC check word and a frame sequence number, so data transmission errors are fully detectable. When a data communication error occurs, the communication logic will use a retransmission mechanism to retransmit the data until the data transmission is correct, thereby ensuring the reliability of data writing and reading. Meanwhile, based on the SATA protocol, data between the FPGA and each hard drive is organized and transmitted in frame format, with each frame also equipped with a CRC checksum. Therefore, data transmission errors between the FPGA and SATA are fully detectable. Similarly, for occasional data transmission errors, the FPGA will re-initiate the read / write operation until the data transmission is correct. This improves the reliability of data writing and reading.

[0049] This includes a buffer management module 5, with the RAID array logic module 1 and external storage chip 6 connected to the buffer management module 5. The buffer management module 5 is used to buffer data into the external storage chip 6. The buffer management module 5 may be an internally integrated DDR3 SDRAM controller, and the external storage chip 6 may be DDR3 SDRAM. The connection between the buffer management module 5 and the DDR3 SDRAM forms a 2GB data buffer pool based on the DDR3 storage chip.

[0050] In the above implementation process, a buffer pool is formed by connecting the buffer management module 5 to the external storage chip 6. On the one hand, this buffers the real-time data stream input from the outside, thus smoothing out temporary bandwidth drops in the hard disk array 4. On the other hand, it performs error-correcting caching on the data. Before the data transmission is confirmed to be correct, the data is cached in the DDR3 SDRAM and only erased from the DDR3 after the transmission is confirmed to be correct. For example, if an occasional error occurs in the data block written to the hard disk 4, the data in the buffer pool is called up and rewritten until the data is written correctly, thereby improving the accuracy of data storage.

[0051] This also includes an intelligent management module 2, which is connected to the RAID array logic module 1. This module monitors the data flow within the RAID array logic module 1 and performs scheduling based on the monitoring results. The intelligent management module 2 can be implemented using a Xilinx Microblaze processor. It is used for global logic scheduling and monitoring, file system management, and other functions. These include data flow scheduling, instruction flow processing, error management mechanisms, built-in file systems, hard drive detection, data recovery, system monitoring, and work logs.

[0052] In the above implementation process, the IP core can operate normally by using the intelligent management module 2 to schedule and monitor the global logic, thereby ensuring the stability of data storage.

[0053] The SATA control logic unit includes a control interface and a data interface. The control interface is used to send and receive command information with the RAID logic unit; the data interface is used to transmit data information.

[0054] The aforementioned SATA control logic unit can be a SATA controller. This controller can utilize an existing SATA 3.0 host controller digital logic IP core, integrated into an FPGA chip. The FPGA's built-in high-speed serial deserializer (GTX or GTH) implements the SATA protocol physical layer, while the FPGA's internal general-purpose logic resources implement the SATA protocol's link and transport layers. Each controller requires only approximately 5K registers and 50KB of memory. This SATA controller fully complies with the relevant protocol specification (Serial ATA Revision 3.0). The SATA protocol physical layer is implemented using the FPGA's integrated high-speed serial data transceiver controller, performing functions such as clock recovery, comma detection, and 8B10B encoding / decoding. The controller's link and transport layers are entirely implemented through the FPGA's internal programmable logic modules, performing functions such as data CRC checksum verification, scrambling, protocol primitive generation and parsing, frame assembly and parsing. To encapsulate the complex details of the SATA protocol and simplify user interaction with the IP core, the controller employs an extremely simple external interface. External logic only needs to interface drive the most common registers and FIFO modules to achieve read / write control of hard drive 4.

[0055] The control interface includes a register interface and an instruction FIFO interface. The register interface is used to read running status data, and the instruction FIFO interface is used to write instruction information.

[0056] The data interface includes multiple FIFO interfaces, which are used to write or read data.

[0057] In the above implementation process, the SATA control logic unit shields the user from the complex SATA protocol, allowing the user to achieve fast read and write control of the SATA interface hard drive 4 through a simple and easy-to-use logic interface.

[0058] This includes an LVDS bus interface 9, which is connected to the interface management unit 7. The LVDS bus interface 9 can be expanded into a Gigabit Ethernet interface through the LVDS differential bus expansion chip circuit, thereby expanding its application range.

[0059] Based on the same inventive concept, this invention also proposes a data storage method based on an FPGA-based SATA IP core. Please refer to... Figure 2 , Figure 2 The present invention provides a flowchart of a data storage method for a SATA IP core based on an FPGA, which includes the following steps:

[0060] Step S110: Obtain read / write instruction parameter information; the user initiates the write instruction via the instruction port. The read / write instruction parameter information may include a) instruction type, such as: absolute sector control write ReqRAWWrite(0x000A2000); b) write start address, such as 0x0100; c) write capacity, such as 128KB; d) write address of the status feedback frame, such as 0x1234-0000.

[0061] Step S120: Extract the current storage information based on the read / write instruction parameter information and display it to the user; for example, extract the current working status and storage space usage and display them to the user.

[0062] Step S130: Obtain the start signal input by the user; that is, the data write or write signal.

[0063] Step S140: Based on the start signal, use the preset FPGA-based SATA IP core to perform read and write operations on the data.

[0064] In the above implementation process, read and write instruction parameter information is obtained; then, the current storage information is extracted and displayed to the user based on the read and write instruction parameter information; then, the start signal input by the user is obtained; finally, the data is read and written using a preset FPGA-based SATA IP core according to the start signal. Since the data storage based on the FPGA-based SATA IP core has high reliability, the data reading and writing method can improve the reliability of fast data reading and writing.

[0065] In summary, this application provides an FPGA-based SATA IP core and data storage method. The RAID array logic module 1 of the FPGA-based SATA IP core acquires external input data through a communication interface module and writes the external input data to the corresponding hard disk 4 through multiple SATA interface modules 3, thereby achieving data storage. The RAID array logic module 1 reads data from the hard disk 4 through multiple SATA interface modules 3 and outputs the data through the communication interface module, thereby achieving data retrieval. The RAID array logic module 1 divides the hard disk 4 into multiple arrays and then uses RAID array technology for data storage. The aforementioned SATA IP core independently occupies an FPGA chip. By loading this IP core, the FPGA chip becomes a high-performance storage controller chip capable of array control of multiple SATA interface hard disks 4. External communication typically uses protocols such as RapidIO and Ethernet. Data communication is organized in frames, and each data frame is equipped with a CRC checksum and frame sequence number, thus making data transmission errors fully detectable. When a data communication error occurs, the communication logic will use a retransmission mechanism to retransmit the data until the data transmission is correct, thereby ensuring the reliability of data writing and reading. Meanwhile, based on the SATA protocol, data between the FPGA and each hard drive is organized and transmitted in frame format, with each frame also equipped with a CRC checksum. Therefore, data transmission errors between the FPGA and SATA are fully detectable. Similarly, for occasional data transmission errors, the FPGA will re-initiate the read / write operation until the data transmission is correct. This improves the reliability of data writing and reading.

[0066] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0067] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A SATA IP core based on FPGA, characterized in that, It includes a RAID array logic module, multiple SATA interface modules, and multiple communication interface modules; each SATA interface module and each communication interface module is connected to the RAID array logic module; each SATA interface module is connected to a hard drive, wherein... The RAID array logic module is used to acquire external input data through the communication interface module and write the external input data to the corresponding hard disk through multiple SATA interface modules; it is also used to read data from the hard disk through multiple SATA interface modules and output the data through the communication interface module. It also includes an intelligent management module, which is connected to the RAID array logic module and is used to monitor the data flow in the RAID array logic module and schedule it according to the monitoring results; It also includes a buffer management module, with the RAID array logic module and the external storage chip respectively connected to the buffer management module; The buffer management module is used to buffer data into an external storage chip; The RAID array logic module includes a RAID logic unit, multiple SATA control logic units, and multiple FIFOs; the multiple SATA control logic units and multiple FIFOs are all connected to the RAID logic unit, and the multiple FIFOs are connected to the communication interface module; each SATA control logic unit is connected to its respective SATA interface module; wherein... The RAID logic unit is used to acquire external input data through multiple FIFOs and control the corresponding SATA interface modules for storage through multiple SATA control logic units; it is also used to read data from the SATA interface modules through multiple SATA control logic units. The SATA control logic unit includes a control interface and a data interface. The control interface is used to send and receive command information with the RAID logic unit; The data interface is used to transmit data information; The control interface includes a register interface and an instruction FIFO interface. The register interface is used to read running status data; The instruction FIFO interface is used to write instruction information; The communication interface module includes an interface management unit and multiple high-speed serial ports. The interface management unit is connected to the RAID array logic module and the multiple high-speed serial ports, respectively. High-speed serial port, used for data transmission; The interface management unit is used to manage the multiple high-speed serial ports.

2. The FPGA-based SATA IP core according to claim 1, characterized in that, The data interface includes multiple FIFO interfaces, which are used to write or read data.

3. The FPGA-based SATA IP core according to claim 1, characterized in that, It also includes an LVDS bus interface, which is connected to the interface management unit.

4. A data storage method based on an FPGA SATA IP core as described in any one of claims 1-3, characterized in that, Includes the following steps: Obtain read / write command parameter information; Extract the current storage information based on the read / write command parameters and display it to the user; Get the start signal input by the user; Based on the start signal, a preset FPGA-based SATA IP core is used to perform read and write operations on the data.

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