Puf circuit, chip, device, and challenge-response pair generation method

Abstract

The application provides a PUF circuit, a chip, a device and a challenge-response pair generation method. The PUF circuit comprises an RRAM unit, a measurement circuit and a memory. The measurement circuit is connected with the RRAM unit and the memory respectively. The measurement circuit is used for detecting the time when the RRAM unit is in a volatile storage state under a preset limit current and a preset voltage, and generating a digital quantity corresponding to the time. The memory is used for storing the digital quantity as a response of the PUF, and determining a challenge corresponding to the response. A PUF with a large number of CRPs and no correlation between the CPRs can tolerate modeling attacks.

Description

Technical Field

[0001] This application relates to information security technology, and more particularly to a PUF circuit, chip, device, and challenge-response pair generation method. Background Technology

[0002] Physically unclonable functions (PUFs) utilize uncontrollable random process variations in integrated circuit manufacturing to generate hardware fingerprints, possessing uniqueness, randomness, and non-cloning properties. As a hardware method for information security in IoT terminal devices, PUFs are attracting increasing attention.

[0003] When queried with an input called a Challenge, a PUF produces a measurable output called a Response. The corresponding Challenge and Response constitute a Challenge-Response Pair (CRP). Based on the relationship between the number of CRPs and the size of the physical entity, PUFs can be divided into strong PUFs and weak PUFs. Strong PUFs typically generate responses based on comparisons of two combinations of a certain number of cascaded logic devices. Typical examples include arbiter PUFs and ring oscillator PUFs based on gate delay variations. Strong PUFs have a large number of CRPs, which is beneficial for a wide range of security applications. However, this resource reuse in strong PUFs leads to correlations between different CRPs, making them vulnerable to modeling attacks. Such attacks can derive a numerical model from all CRP subsets of a PUF and predict its future responses to other challenges. Weak PUFs generate responses based on parameter mismatches between a pair of identical devices or circuits. Typical examples include butterfly PUFs and flip-flop PUFs. The lack of correlation between different CRPs in a weak PUF can resist modeling attacks. However, weak PUFs typically have only a small number of CRPs, which limits their application and makes them unusable in application scenarios that require a large number of CRPs.

[0004] Therefore, how to provide a PUF that can generate a large number of CRPs and tolerate modeling attacks is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a PUF circuit, chip, device, and challenge-response pair generation method, which realizes a PUF that can generate a large number of CRPs and tolerate modeling attacks.

[0006] In a first aspect, this application provides a physically unclonable function (PUF) circuit, comprising: a resistive random access memory (RRAM) cell, a measurement circuit, and a memory; the measurement circuit is connected to the RRAM cell and the memory respectively.

[0007] The measurement circuit is used to detect the time that the RRAM cell is in a volatile storage state under a preset limit current and a preset voltage, and to generate a digital quantity corresponding to the time.

[0008] The memory is used to store the digital quantity as a response to the PUF and to determine the challenge corresponding to the response.

[0009] In one feasible implementation, the measurement circuit includes a random number detection circuit and a counter;

[0010] The random number detection circuit is used to input a preset voltage to the RRAM unit, detect the current change of the RRAM unit under the preset voltage, and output a corresponding indication signal.

[0011] The counter is used to generate a digital quantity corresponding to the time when the RRAM cell is in a volatile storage state, based on the indication signal.

[0012] In one feasible implementation, the measurement circuit further includes a cutoff circuit; the cutoff circuit is connected to the counter and the memory respectively;

[0013] The truncation circuit is used to truncate the last M bits of the digital quantity;

[0014] The memory is used to store the truncated digital value as the response of the PUF.

[0015] In one possible implementation, the memory is further configured to determine the address where the response is stored as the challenge corresponding to the response.

[0016] In one feasible implementation, the RRAM cell includes an RRAM device and a first switching transistor;

[0017] The first terminal of the first switching transistor is connected to a power supply, which is used to control the preset current limit of the RRAM cell; the second terminal of the first switching transistor is grounded; the third terminal of the first switching transistor is connected to the lower electrode of the RRAM device; and the upper electrode of the RRAM device is connected to the random number detection circuit.

[0018] In one feasible implementation, the random number detection circuit includes a second switch, a third switch, a fourth switch, a mirror constant current source, a comparator, and a NAND gate;

[0019] The first terminal of the third switch is connected to a control signal; the control signal is a high-level signal or a low-level signal; the second terminal of the third switch is connected to a first preset voltage signal; the third terminal of the third switch is connected to the first terminal of the second switch.

[0020] The first terminal of the fourth switch is connected to the control signal; the control signal is a high-level signal or a low-level signal; the second terminal of the fourth switch is connected to the second preset voltage signal; the third terminal of the fourth switch is connected to the first terminal of the second switch; the second preset voltage signal is less than the first preset voltage signal.

[0021] The second terminal of the second switch is connected to the mirror constant current source; the third terminal of the second switch is connected to the upper electrode of the RRAM device.

[0022] The mirror constant current source is connected to the first input terminal of the comparator; the second input terminal of the comparator is connected to the reference power supply.

[0023] The output of the comparator is connected to the first input of the NAND gate; the second input of the NAND gate is connected to the test signal; the test signal has the opposite level to the control signal.

[0024] The output of the NAND gate is connected to the counter.

[0025] In one feasible implementation, the counter starts counting when the output of the NAND gate changes from a high level to a low level, and stops counting when the output of the NAND gate changes from a low level to a high level.

[0026] In one possible implementation, the memory is also used to output a corresponding response based on the received challenge.

[0027] Secondly, this application provides a chip including the PUF circuit as described in any one of the first aspects above.

[0028] Thirdly, this application provides an electronic device including the chip described in the second aspect above.

[0029] Fourthly, this application provides a method for generating challenge-response pairs of a Physically Unclonable Function (PUF), wherein the PUF includes a Resistive Random Access Memory (RRAM) cell, and the method includes:

[0030] A preset voltage is input to the RRAM cell, and the RRAM cell is controlled to operate under a preset current limit.

[0031] The time during which the RRAM cell is in a volatile storage state under the preset limit current and the preset voltage is detected, and a digital quantity corresponding to the time is generated;

[0032] The digital quantity is determined as the response of the PUF, and the challenge corresponding to the response is determined.

[0033] In one feasible implementation, generating the digital quantity corresponding to the time includes:

[0034] Generate a first digital quantity corresponding to the time, wherein the length of the first digital quantity is N;

[0035] Extract the last M bits of the first digital value to form a second digital value, where M is less than N;

[0036] Accordingly, the step of determining the digital quantity as a PUF response includes:

[0037] The second digital quantity is determined as the response.

[0038] In one feasible implementation, determining the challenge corresponding to the response includes:

[0039] The address where the response is stored is determined as the challenge corresponding to the response.

[0040] In one implementation, the method further includes:

[0041] Receive a challenge instruction, which includes a target challenge;

[0042] Output the response corresponding to the target challenge.

[0043] This application provides a PUF circuit, chip, device, and challenge-response pair generation method. The PUF circuit includes an RRAM cell, a measurement circuit, and a memory. The measurement circuit is connected to both the RRAM cell and the memory. The measurement circuit detects the time the RRAM cell is in a volatile storage state under a preset current limit and a preset voltage, and generates a digital quantity corresponding to the time. The memory stores the digital quantity as the response of the PUF and determines the challenge corresponding to the response. This PUF circuit utilizes the duration of the volatile storage state of the RRAM cell when the current limit is small, i.e., the randomness of the short-term memory time, using the RRAM cell as a random source and its short-term memory time as the random number of the PUF. This makes the PUF less vulnerable to attack. Furthermore, because the number of erase / write cycles of the RRAM cell is significantly increased when the current limit is small, a large number of random numbers can be generated using a single RRAM cell. This achieves a PUF with a large number of challenge-response pairs (CRPs) that are uncorrelated and resistant to modeling attacks. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of a security chip;

[0046] Figure 2 A schematic diagram of a PUF circuit provided in this application Figure 1 ;

[0047] Figure 3 A schematic diagram of a PUF circuit provided in this application Figure 2 ;

[0048] Figure 4 A schematic diagram of a PUF circuit provided in this application Figure 3 ;

[0049] Figure 5 A timing diagram of a PUF circuit provided in this application;

[0050] Figure 6 A schematic diagram of a PUF circuit provided in this application Figure 4 ;

[0051] Figure 7 A schematic diagram of the PUF certification process provided in this application;

[0052] Figure 8 This is a flowchart illustrating a method for generating challenge response pairs for a PUF provided in this application. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] With the development of integrated circuit technology and information security technology, the application of security chips has expanded from traditional important sectors such as politics, economy, military and diplomacy to everyday life, such as identity authentication, financial payment, car anti-theft, logistics tracking, anti-counterfeiting labels, and so on.

[0055] As a completely closed hardware device, a security chip is characterized by its high degree of security, difficulty in cracking, and high cost of cracking. Because a security chip integrates a processor module, a memory module, and a cryptographic algorithm module, it can independently perform key generation and encryption / decryption operations, providing services such as data security protection and identity authentication. Security chips will play an increasingly important role in the future of information security.

[0056] However, with the development of attack techniques, security chips are facing increasing threats, such as... Figure 1 As shown. These threats can be broadly categorized into software attacks, physical attacks, and combined software and physical attacks. Physical attacks include invasive and non-invasive attacks. Invasive attacks, also known as brute-force attacks, include micro-probing and laser cutting, using hardware reverse engineering techniques to illegally clone key information, thereby stealing key information or achieving unauthorized authentication. Non-invasive attacks typically refer to various side-channel information related to the key itself leaked by physical devices during the execution of cryptographic algorithms, such as runtime, energy consumption, and electromagnetic radiation. Attackers use this side-channel information to attack encryption devices and steal the key.

[0057] Furthermore, current technologies combine multiple attack modes, including hardware Trojans, reverse engineering, and register write attacks, further increasing the destructiveness of attack techniques. As attack modes evolve, the requirements for security chips are becoming increasingly stringent. Security chips based on PUF circuits are attracting increasing attention due to their uniqueness, randomness, and non-cloning properties.

[0058] In the prior art, PUFs are generally classified into strong PUFs and weak PUFs. Strong PUFs typically generate a response based on a comparison of two combinations of a certain number of cascaded logic devices; typical examples include arbitrator PUFs based on gate delay variations and ring oscillator PUFs. Weak PUFs, on the other hand, typically generate a response based on parameter mismatch between a pair of identical devices or circuits; typical examples include butterfly PUFs and flip-flop PUFs.

[0059] Strong PUFs possess a large number of Response Points (CRPs), which is beneficial for a wide range of security applications. However, the resource reuse of strong PUFs leads to correlations between different CRPs, making them vulnerable to modeling attacks. Such attacks can derive a numerical model from a subset of all CRPs of a PUF and predict its future responses to other challenges. Furthermore, strong PUFs typically require complex hardware, resulting in significant power consumption per response bit, easily exceeding the limitations of electronic devices. Weak PUFs, on the other hand, have no correlation between different CRPs, making them resistant to modeling attacks. However, weak PUFs typically have only a small number of CRPs, limiting their application and making them unusable in scenarios requiring a large number of CRPs. Therefore, considering device power constraints, a fundamental challenge for realizing the application of PUFs in practical security authentication is how to provide a PUF with a large number of CRPs, no correlation between CRPs, and tolerance to modeling attacks.

[0060] To address the aforementioned issues, this application provides a PUF circuit that uses Resistive Random Access Memory (RRAM) cells as the random source for generating random numbers. It leverages the randomness of the duration of the volatile storage state of the RRAM cells when the current limit is low to generate random numbers, making the PUF less vulnerable to attacks. Furthermore, since the number of erase / write cycles of the RRAM cells is significantly increased when the current limit is low, a single RRAM cell can generate a massive number of random numbers. This results in a PUF with a large number of CRPs (Constant Replication Points) that are uncorrelated and resistant to modeling attacks.

[0061] The characteristics of RRAM cells are described in detail below. When the RRAM cell has a large current limit, i.e., a large maximum current through the RRAM, applying a set voltage to the RRAM cell will cause the RRAM cell to enter a low-resistance state, and the cell's retention time can reach 10 years or even longer, thereby achieving non-volatile storage. For example, the large current limit is 120μA to 1mA, and the set voltage can be 1.5V to 2.5V. This embodiment does not impose specific limitations on these values. The specific values ​​of the current limit and the set voltage can be determined according to the actual situation of the RRAM, as long as the RRAM cell is in a non-volatile storage state.

[0062] However, when the limiting current is small, after applying a set voltage to the RRAM cell, although the RRAM cell also enters a low-resistance state, when the set voltage is removed and a small voltage is applied, the RRAM cell will return to a high-resistance state after a period of time. This means the RRAM cell has a short retention time, exhibiting the volatile storage characteristics of short-term memory. For example, this small limiting current can be less than 50μA, and this small voltage can be around 0.5V. Similarly, the specific values ​​of this small limiting current and small voltage can be determined according to the actual situation of the RRAM, as long as it allows the RRAM cell to remain in a volatile storage state. The duration of the low-resistance state of the RRAM cell under this small limiting current and small voltage is the short-term memory time.

[0063] Under the same current limiting condition, the short-time memory (STM) time of an RRAM cell exhibits strong randomness, and the lower the current limiting, the shorter the STM time and the larger the distribution area. Furthermore, under low current limiting conditions, the number of erasable and rewritable cycles of an RRAM cell increases significantly. Based on this characteristic, a large number of random numbers can be generated by repeatedly setting an RRAM cell and measuring its STM time.

[0064] The PUF circuit provided in this application will be described in detail below with reference to specific embodiments. It is understood that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0065] Figure 2 A schematic diagram of a PUF circuit provided in this application Figure 1 .like Figure 2 As shown, the PUF circuit includes: RRAM cell 21, measurement circuit 22 and memory 23; the measurement circuit 22 is connected to RRAM cell 21 and memory 23 respectively.

[0066] Measurement circuit 22 is used to detect the time that RRAM cell 21 is in volatile storage state under preset limit current and preset voltage, and generate a digital quantity corresponding to the time; memory 23 is used to store the digital quantity as the response of PUF and determine the challenge corresponding to the response.

[0067] In this embodiment, random numbers are generated using RRAM cell 21. A preset current limit is set for RRAM cell 21, and a preset voltage is applied to put RRAM cell 21 into a volatile storage state. For example, a small current limit is set for RRAM cell 21, such as 15μA, and a set voltage, such as 2V, is applied to RRAM cell 21 to put RRAM cell 21 into a low-resistance state. After the set voltage is removed, a small preset voltage, such as 0.8V, is applied to RRAM cell 21, and RRAM cell 21 begins to be in a volatile storage state. After a period of time, RRAM cell 21 returns from the low-resistance state to the high-resistance state, and the volatile storage state ends.

[0068] The measurement circuit 22 detects the time that the RRAM cell 21 is in a volatile storage state, i.e., the short-term memory time, and generates a digital value corresponding to this time as a random number generated by the PUF circuit. Since the time that the RRAM cell 21 is in a volatile storage state is random, the randomness of the generated digital value is guaranteed.

[0069] Measurement circuit 22 is paired with RRAM unit 21 to perform detection, for example, Figure 3 As shown, the measurement circuit 22 may include a random number detection circuit 221 and a counter 222.

[0070] The random number detection circuit 221 is used to input a preset voltage to the RRAM cell 21, detect the current change of the RRAM cell 21 under the preset voltage and output the corresponding indication signal; the counter 222 is used to generate a digital quantity corresponding to the time when the RRAM cell is in the volatile storage state according to the indication signal.

[0071] As can be seen from the above description of RRAM cell 21, the change in the storage state of RRAM cell 21 is reflected in the change in its resistance state. Therefore, when its resistance state changes, the current flowing through RRAM cell 21 will also change. Thus, the random number detection circuit 221 detects the change in current of RRAM cell 21 under a preset voltage, and outputs a corresponding indication signal based on the change in current and the voltage signal applied to RRAM cell 21. This indication signal is used to indicate whether RRAM cell 21 is in a volatile storage state. Thus, the counter 222 can generate a digital quantity corresponding to the time when RRAM cell 21 is in a volatile storage state based on the indication signal.

[0072] The memory 23 stores this digital quantity as a response to the PUF and simultaneously determines a challenge corresponding to the response. This challenge and response are uniquely matched and serve as a CRP for the PUF. In this embodiment, the challenge determined by the memory 23 corresponding to the response is not specifically limited, as long as it ensures a one-to-one correspondence between the challenge and the response, and different responses correspond to different challenges.

[0073] The PUF circuit generates a CRP through the above process. It can be understood that if multiple CRPs need to be generated, the measurement circuit 22 repeatedly applies voltage to the RRAM cell 21 and performs detection, repeating the above process to produce multiple CRPs. Since the RRAM has a very large number of erasable / write cycles when the current limit is small, the number of random numbers that can be generated by repeating the above process is also enormous; that is, the number of CRPs that the PUF circuit can generate is enormous.

[0074] In this embodiment, the PUF circuit utilizes the duration of the volatile storage state of the RRAM cell when the current limit is small, i.e., the randomness of the short-term memory time, to use the RRAM cell as a random source and its short-term memory time as the random number of the PUF. This makes the PUF less susceptible to attack. At the same time, since the number of erase and write cycles of the RRAM cell is greatly increased when the current limit is small, a huge number of random numbers can be generated using a single RRAM cell. This results in a PUF with a large number of CRPs, no correlation between CRPs, and tolerance to modeling attacks.

[0075] Based on the above embodiments, the various parts of the PUF circuit will be further described in detail.

[0076] Figure 4 This is a schematic diagram of the structure of a PUF circuit provided in this application. Figure 3 .like Figure 4 As shown, RRAM cell 21 includes RRAM device R1 and first switching transistor M1.

[0077] Figure 4 The RRAM cell 21 is a typical 1T1R RRAM structure. The first switch M1 acts as a selection device. The first terminal of the first switch M1 is connected to the word line WL, which is connected to the power supply. The power supply is used to control the preset current limit of the RRAM cell 21. The second terminal of the first switch M1 is connected to the source line SL, which is grounded. The third terminal of the first switch M1 is connected to the lower electrode of the RRAM device R1. The upper electrode of the RRAM device R1 is connected to the bit line BL, which is connected to the random number detection circuit 221.

[0078] The random number detection circuit 221 includes a second switch M2, a third switch M3, a fourth switch M4, a mirror constant current source 2211, a comparator A1, and a NAND gate G1.

[0079] The first terminal of the third switch M3 is connected to the control signal Soft_Prog; the control signal Soft_Prog is a high-level signal or a low-level signal; the second terminal of the third switch M3 is connected to the first preset voltage signal Vwb; the third terminal of the third switch M3 is connected to the first terminal of the second switch M2.

[0080] The first terminal of the fourth switch M4 is connected to the control signal Soft_Prog; the control signal Soft_Prog is a high-level signal or a low-level signal; the second terminal of the fourth switch M4 is connected to the second preset voltage signal Vsb; the third terminal of the fourth switch M4 is connected to the first terminal of the second switch M2; the second preset voltage signal Vsb is less than the first preset voltage signal Vwb.

[0081] The second terminal of the second switch M2 is connected to the mirror constant current source 2211; the third terminal of the second switch M2 is connected to the upper electrode of the RRAM device R1.

[0082] The mirror constant current source 2211 is connected to the first input terminal of comparator A1; the second input terminal of comparator A1 is connected to the reference power supply Vref.

[0083] The output of comparator A1 is connected to the first input of NAND gate G1; the second input of NAND gate G1 is connected to the test signal Meas; the level of the test signal Meas is opposite to that of the control signal Soft_Prog.

[0084] The output of NAND gate G1 is connected to counter 222.

[0085] Combination Figure 5 The timing diagram shown is for Figure 4 The working principle of the PUF circuit will be explained.

[0086] In each random number generation cycle, the control signal Soft_Prog first goes high. Soft_Prog can be controlled by the software programming unit. The first preset voltage signal Vwb, also known as the write voltage or set voltage, is connected to the gate of the second switch M2 via the third switch M3, clamping the voltage of the bit line BL to perform the set operation of the RRAM cell 21. The current limit of the RRAM cell 21 is limited by its word line WL. Volatile storage of the RRAM cell 21 is achieved by setting a small current limit.

[0087] When the control signal Soft_Prog remains high for a period of time, RRAM cell 21 changes from a high-resistance state to a low-resistance state, and the path current Icell also increases. Through the mirror constant current source 2211 composed of the fifth switch M5 and the sixth switch M6, the current Isense also increases, and the voltage Vsense at one end of the input comparator A1 also increases. When the voltage Vsense is greater than the reference voltage Vref, the Flag signal output by comparator A1 becomes high.

[0088] When the control signal Soft_Prog changes from high to low, the lower second preset voltage signal Vsb, which is the aforementioned smaller preset voltage, can also be used as a bias voltage. This voltage is applied to the gate of the second switch M2 through the fourth switch M3, at which point the short-time memory period of the RRAM cell 21 begins. When the RRAM cell returns from a low-resistance state to a high-resistance state, the path current Icell decreases. Through the mirror constant current source 2211 formed by the fifth switch M5 and the sixth switch M6, the Isense current also decreases, and the Vsense voltage at one end of the input comparator A1 also decreases. When the Vsense voltage is less than the reference voltage Vref, the Flag signal goes low, and the short-time memory period ends.

[0089] Furthermore, when the control signal Soft_Prog changes from high to low, the test signal Meas goes high, and counter 222 is reset. The Meas and Flag signals are then processed by NAND gate G1 to obtain the indicator signal, namely the Stop signal. The time the Stop signal is low is the short-time memory time of RRAM cell 21, that is, the time it is in volatile storage. Counter 222 starts counting when the output of NAND gate G1 changes from high to low and stops counting when the output of NAND gate G1 changes from low to high.

[0090] For example, counter 222 can output a 20-bit digital value CNT[19:0] corresponding to the short-time memory time of RRAM unit 21. In this embodiment, the length of the digital value output by the counter is not specifically limited, and the length of the digital value can be selected and set according to actual needs.

[0091] When the storage control signal Store of memory 23 is active, the digital value CNT[19:0] is written to memory 23 for storage as a response to the PUF. Optionally, memory 23 may also determine the address where the response is stored as the challenge corresponding to the response, thereby obtaining a CRP. With the CRP stored in memory 23, memory 23 can also output a response corresponding to the challenge when an input challenge is received. Figure 4 As shown, the memory 23 receives the challenge signal CHA and outputs a corresponding response signal RES.

[0092] In this embodiment, the random number detection circuit in the measurement circuit detects the short-time memory time of the RRAM cell by applying voltage to the RRAM cell and detecting the current change of the RRAM cell, and outputs the digital quantity corresponding to the short-time memory time through a counter, thereby generating a huge number of uncorrelated CRPs.

[0093] Optionally, based on the above PUF circuit, such as Figure 6As shown, the measurement circuit 22 also includes a cutoff circuit 223; the cutoff circuit 223 is connected to the counter 222 and the memory 23 respectively.

[0094] The cutoff circuit 223 is used to cut off the last M bits of the digital quantity output by the counter 222. Correspondingly, the memory 23 is used to store the cut-off digital quantity as the response of the PUF.

[0095] For example, counter 222 outputs a 20-bit digital value CNT[19:0]. Through truncation circuit 223, the high 4 bits of the 20-bit digital value CNT[19:0] are truncated, leaving the low 16 bits of the digital value CNT[15:0]. When the storage control signal Store of memory 23 is active, the 16-bit digital value CNT[15:0] is written to memory 23 for storage, and its corresponding address is used as the response challenge.

[0096] When counter 222 generates a corresponding digital value based on the short-term memory time of RRAM unit 21, the high-order bits of the generated digital value may be the same each time, while the low-order bits may differ. To further improve randomness, truncation circuit 223 is used to truncate the high-order bits of the digital value, retaining only the low-order bits. This makes the ratio of 1s and 0s in the truncated digital value closer, resulting in higher randomness and making the PUF less susceptible to modeling attacks. It is understood that the aforementioned 20-bit digital value and the truncated 16-bit digital value are merely illustrative examples. In this embodiment, the length truncated by truncation circuit 223 is not specifically limited and can be selected and set according to actual needs.

[0097] This application also provides a chip that includes a PUF circuit as described in any of the above embodiments. It is understood that a chip with the above-described PUF circuit can implement the functions of the PUF circuit and can also be applied to the security application scenarios in which the PUF circuit can be used.

[0098] Furthermore, this application also provides an electronic device that includes the aforementioned chip.

[0099] Based on the PUF circuit provided in the above embodiments, its specific application in the security field is illustrated by examples. For instance, during security authentication of an electronic device, a PUF-based authentication method is used between the terminal and the server. The terminal can be an electronic device, and its chip may include the aforementioned PUF circuit.

[0100] The PUF-based authentication process can include three phases: registration, authentication, and reconfiguration. Figure 7 As shown.

[0101] Registration Phase: Before deployment, each terminal must register. During registration, the PUF in the terminal first generates multiple CRPs. Then, each terminal sends its identifier and corresponding CRPs to the server, which stores the terminal identifier and CRPs, for example, in a CRP database. The terminal identifier can also be generated by the PUF. Because there is no correlation between the different CRPs generated by the PUF, modeling attacks is ineffective.

[0102] Authentication Phase: The terminal sends its identifier to the server. The server looks up the identifier in the CRP database, selects the corresponding CRP, sends the challenge from the CRP to the terminal, and then the terminal outputs the response corresponding to the challenge and sends it to the server. The server determines whether the received response matches the response in the CRP database, i.e., the difference between the two responses does not exceed a predetermined threshold. When checking whether two responses match, the server determines whether the number of different bits between the two digital values ​​exceeds the predetermined threshold. Alternatively, the server can also check whether the two responses are completely identical. If they match, the terminal is authenticated; otherwise, authentication is rejected. Used CRPs are deleted from the CRP database.

[0103] CRP Reconfiguration Phase: In the CRP database, when a terminal's CRPs are nearly exhausted or have already been exhausted, the terminal needs to regenerate new CRPs. During the reconfiguration phase, the server sends a reconfiguration command to the corresponding terminal based on its identifier. After receiving the reconfiguration command, the terminal generates a new CRP and sends it to the server. The server stores the new CRPs sent by the terminal, for example, in the CRP database. Since the PUF of this application can output a huge number of CRPs, and the regenerated CRPs are completely unrelated to the previously stored CRPs, authentication can continue after CRP reconfiguration.

[0104] Understandably, during the registration phase, a terminal can register multiple CRPs with the server, allowing these CRPs to be used for multiple authentications in subsequent authentication phases. CRP reconfiguration is only necessary when multiple CRPs are about to be exhausted or have already been exhausted. CRP reconfiguration is essentially a re-registration process; after reconfiguration, the reconfigured CRPs can be used for authentication.

[0105] Figure 8 This application provides a flowchart illustrating a method for generating challenge responses using a PUF (Programmable Array Component). The PUF includes RRAM (Reference RAM) units; for example, the PUF can be any of the PUFs described in the above embodiments. The method includes:

[0106] S801: Input a preset voltage to the RRAM cell and control the RRAM cell to operate under a preset current limit.

[0107] S802, detect the time the RRAM cell is in a volatile storage state under a preset current limit and a preset voltage, and generate a digital quantity corresponding to the time;

[0108] S803. Determine the digital quantity as the response of the PUF and identify the challenge corresponding to the response.

[0109] Optionally, generate a digital quantity corresponding to time, including:

[0110] The first digital quantity is generated at the time corresponding to the time of the first digital quantity, and the length of the first digital quantity is N. The last M bits of the first digital quantity are extracted to form the second digital quantity, where M is less than N.

[0111] Accordingly, determining the digital quantity as the response of the PUF includes: determining the second digital quantity as the response.

[0112] Optionally, identify the challenges corresponding to the response, including:

[0113] The address where the response is stored is determined to be the challenge corresponding to the response.

[0114] Optionally, the method further includes: receiving a challenge instruction, which includes a target challenge; and outputting a response corresponding to the target challenge.

[0115] The method provided in this embodiment can be implemented by the above-described PUF circuit, and its implementation principle and technical effect are similar, so it will not be described again here.

[0116] All or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, it performs the steps of the above method embodiments; and the aforementioned memory (storage medium) includes: read-only memory (ROM), RAM, flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disk, and any combination thereof.

[0117] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0118] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0119] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0120] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

[0121] In this application, the term "comprising" and its variations can refer to non-limiting inclusion; the term "or" and its variations can refer to "and / or". The terms "first", "second", etc., in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. In this application, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

Claims

1. A physically unclonable function (PUF) circuit, characterized in that, include: Resistive Random Access Memory (RRAM) cells, measurement circuitry, and memory; The measurement circuit is connected to the RRAM unit and the memory, respectively. The measurement circuit is used to detect the time that the RRAM cell is in a volatile storage state under a preset limit current and a preset voltage, and to generate a digital quantity corresponding to the time. The memory is used to store the digital quantity as a response to the PUF and to determine the challenge corresponding to the response.

2. The circuit according to claim 1, characterized in that, The measurement circuit includes a random number detection circuit and a counter; The random number detection circuit is used to input a preset voltage to the RRAM unit, detect the current change of the RRAM unit under the preset voltage, and output a corresponding indication signal. The counter is used to generate a digital quantity corresponding to the time when the RRAM cell is in a volatile storage state, based on the indication signal.

3. The circuit according to claim 2, characterized in that, The measurement circuit further includes a cutoff circuit; the cutoff circuit is connected to the counter and the memory respectively; The truncation circuit is used to truncate the last M bits of the digital quantity; The memory is used to store the truncated digital value as the response of the PUF.

4. The circuit according to claim 1, characterized in that, The memory is also used to determine the address where the response is stored as the challenge corresponding to the response.

5. The circuit according to any one of claims 2, characterized in that, The RRAM unit includes an RRAM device and a first switching transistor; The first terminal of the first switching transistor is connected to a power supply, which is used to control the preset current limit of the RRAM cell; the second terminal of the first switching transistor is grounded; the third terminal of the first switching transistor is connected to the lower electrode of the RRAM device; and the upper electrode of the RRAM device is connected to the random number detection circuit.

6. The circuit according to claim 5, characterized in that, The random number detection circuit includes a second switch, a third switch, a fourth switch, a mirror constant current source, a comparator, and a NAND gate; The first terminal of the third switch is connected to a control signal; the control signal is a high-level signal or a low-level signal; the second terminal of the third switch is connected to a first preset voltage signal; the third terminal of the third switch is connected to the first terminal of the second switch. The first terminal of the fourth switch is connected to the control signal; the control signal is a high-level signal or a low-level signal; the second terminal of the fourth switch is connected to the second preset voltage signal; the third terminal of the fourth switch is connected to the first terminal of the second switch; the second preset voltage signal is less than the first preset voltage signal. The second terminal of the second switch is connected to the mirror constant current source; the third terminal of the second switch is connected to the upper electrode of the RRAM device. The mirror constant current source is connected to the first input terminal of the comparator; the second input terminal of the comparator is connected to the reference power supply. The output of the comparator is connected to the first input of the NAND gate; the second input of the NAND gate is connected to the test signal; the test signal has the opposite level to the control signal. The output of the NAND gate is connected to the counter.

7. The circuit according to claim 6, characterized in that, The counter starts counting when the output of the NAND gate changes from a high level to a low level, and stops counting when the output of the NAND gate changes from a low level to a high level.

8. The circuit according to any one of claims 1-7, characterized in that, The memory is also used to output a corresponding response based on the received challenge.

9. A chip, characterized in that, Includes the PUF circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the chip as described in claim 9.

11. A method for generating challenge-response pairs of a Physically Unclonable Function (PUF), wherein the PUF includes resistive random access memory (RRAM) cells, characterized in that, The method includes: A preset voltage is input to the RRAM cell, and the RRAM cell is controlled to operate under a preset current limit. The time during which the RRAM cell is in a volatile storage state under the preset limit current and the preset voltage is detected, and a digital quantity corresponding to the time is generated; The digital quantity is determined as the response of the PUF, and the challenge corresponding to the response is determined.

12. The method according to claim 11, characterized in that, The generation of the digital quantity corresponding to the time includes: Generate a first digital quantity corresponding to the time, wherein the length of the first digital quantity is N; Extract the last M bits of the first digital value to form a second digital value, where M is less than N; Accordingly, the step of determining the digital quantity as a PUF response includes: The second digital quantity is determined as the response.

13. The method according to claim 11 or 12, characterized in that, The determination of the challenge corresponding to the response includes: The address where the response is stored is determined as the challenge corresponding to the response.

14. The method according to claim 11 or 12, characterized in that, The method further includes: Receive a challenge instruction, which includes a target challenge; Output the response corresponding to the target challenge.

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