Trench sidewall gate with lead-out structure and method of manufacturing the same

Abstract

The present application relates to a trench sidewall gate with lead-out structure and a manufacturing method thereof, the method comprising: etching a first and a second trench on a substrate; filling the first and the second trench with gate material; forming an etching stop layer on the substrate, which exposes the first trench and partially exposes the second trench; etching the gate material in the first trench; after removing the etching stop layer, chemical vapor deposition is performed to form silicon oxide covering the first and the second trench; removing the silicon oxide on the gate material in the first trench by P-etching; etching the gate material in the first trench with the silicon oxide left on the sidewall of the first trench as an etching stop layer, forming a trench sidewall gate on the bottom sidewall of the first trench, and the gate material in the second trench, which is in communication with the trench sidewall gate, as a gate lead-out structure. The top of the gate material in the second trench can stay on the surface of the substrate, and the gate material can be led out to form an electrical connection to the gate through a conventional via process.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and particularly to a trench sidewall gate with an extraction structure, and to a manufacturing method of the trench sidewall gate with an extraction structure. BACKGROUND

[0002] The contradiction between the breakdown voltage of high voltage devices (devices with high breakdown voltage BV) and the device area is a problem faced by the industry. We want the withstand voltage (breakdown voltage) of the device to be as high as possible, and the on-resistance Rdson to be as small as possible (small device area can make Rdson small). When the length of the drift region of the LDMOS (Lateral Double Diffused Metal Oxide Semiconductor Field Effect Transistor) is reduced to a certain length, the length of the drift region cannot be reduced further because a long enough drift region is needed to maintain BV. By changing the drift region from horizontal to vertical, small device area and large BV can be achieved.

[0003] A common vertical drift region device is VDMOS (Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor). However, the exemplary VDMOS drain is extracted from the back, which has compatibility problems with the BCD process (BCD process is an integrated process technology that can manufacture BJT, CMOS and DMOS devices on the same chip). SUMMARY

[0004] Therefore, it is necessary to provide a trench sidewall gate with an extraction structure and a manufacturing method thereof, which have good compatibility with the BCD process.

[0005] A method for manufacturing a trench sidewall gate with a lead-out structure, comprising: etching a trench structure on a substrate, the trench structure comprising a first trench for forming a trench sidewall gate and a second trench for forming a lead-out structure, the first trench being in communication with the second trench; filling the first trench and the second trench with a gate material, the gate material in the first trench and the second trench being integrated; forming an etching stop layer on the substrate, the etching stop layer exposing the first trench and partially exposing the second trench, the second trench being exposed by a width smaller than the width of the second trench; performing anisotropic etching on the gate material in the first trench to a desired height, the second trench being partially exposed so that the gate material in the second trench is etched to form a notch; after removing the etching stop layer, performing chemical vapor deposition to form silicon oxide covering the first trench and the second trench, the silicon oxide on the second trench being affected by the notch so that the thickness of the silicon oxide on the second trench is greater than the thickness of the silicon oxide on the gate material in the first trench; removing the silicon oxide on the gate material in the first trench by general etching, so that the gate material in the first trench is exposed, the silicon oxide on the second trench still being partially retained on the second trench, the general etching using an anisotropic etching process, the sidewall of the first trench still retaining the silicon oxide after the general etching; etching the gate material in the first trench using the silicon oxide retained on the sidewall of the first trench as an etching stop layer, to form the trench sidewall gate on the bottom sidewall of the first trench, the gate material in the second trench being integrated with the trench sidewall gate as a gate lead-out structure.

[0006] In one embodiment, the second trench has a cross section in the shape of a circle surrounding the first trench.

[0007] In one embodiment, the second trench has a cross section in the shape of a rectangular frame surrounding the first trench, and the first trench has a cross section in the shape of a strip parallel to a pair of opposite sides of the rectangular frame.

[0008] In one embodiment, the first trench has a width of 0.8-1.4 microns, and the second trench has a width of 0.6-1 micron.

[0009] In one embodiment, the first trench and the second trench have a depth of 2-5 microns.

[0010] In one embodiment, in the step of forming the etching stop layer on the substrate, the exposed width of the second trench is 0.1-0.5 microns.

[0011] In one embodiment, the method further comprises forming a gate oxide layer on the inner surface of the first trench and the second trench before the step of filling the first trench and the second trench with a gate material.

[0012] In one embodiment, the gate oxide layer formed in the step of forming a gate oxide layer on the inner surface of the first trench and the second trench has a thickness of

[0013] In one embodiment, the method further comprises growing silicon oxide on the surface of the substrate and the inner surface of the trench structure by a furnace tube and then removing the silicon oxide by a wet method before the step of forming a gate oxide layer on the inner surface of the first trench and the second trench.

[0014] In one embodiment, the silicon oxide grown in the step of growing silicon oxide on the surface of the substrate and the inner surface of the trench structure by a furnace tube has a thickness of

[0015] In one embodiment, the step of forming an etch stop layer on the substrate comprises coating a photoresist and then using the photoresist as the etch stop layer after photolithography.

[0016] In one embodiment, the step of performing chemical vapor deposition after removing the etch stop layer uses tetraethyl orthosilicate as the gas source and the deposited silicon oxide has a thickness of

[0017] In one embodiment, the step of removing the silicon oxide on the gate material in the first trench by dry etching leaves a thick silicon oxide on the second trench after the step of removing the silicon oxide on the gate material in the first trench by dry etching.

[0018] The method for manufacturing the trench sidewall gate with the lead-out structure described above has the gate formed on the sidewall of the first trench, so that the active region can be led out from the bottom of the first trench, and each terminal of the DMOS can be led out from the front surface of the device, thus having good compatibility with the BCD process. When etching the gate material in the first trench using the silicon oxide remaining on the sidewall of the first trench as the etch stop layer, the gate material in the second trench is not etched because the silicon oxide remains on the second trench, so that the gate material in the second trench has a height before the silicon oxide is deposited, and the top of the gate material can be stopped on the surface of the substrate, and the gate material can be led out to form an electrical connection to the gate by a conventional via process.

[0019] ​A trench sidewall gate with an extraction structure includes a gate disposed on a first trench bottom sidewall of a substrate, and a gate extraction structure disposed in a second trench of the substrate in communication with the first trench, the gate extraction structure being integral with the gate and made of the same material as the gate, and a top of the gate extraction structure being proximate to a surface of the substrate.

[0020] In one embodiment, the gate is a polysilicon gate.

[0021] In one embodiment, a cross section of the second trench is a rectangular frame surrounding the first trench, and a cross section of the first trench is a strip parallel to a pair of opposite sides of the rectangular frame.

[0022] In one embodiment, the gate extraction structure is formed with a notch at a top of a side close to the gate.

[0023] The trench sidewall gate with the extraction structure described above, since the gate is formed on the first trench bottom sidewall, the active region can be extracted from the first trench bottom, so that each terminal of the DMOS is extracted from the front surface of the device, and thus has good compatibility with the BCD process. The top of the gate extraction structure is proximate to the surface of the substrate, so that a via can be formed by a conventional via process to electrically connect to the top of the gate extraction structure, as an extraction of the gate. BRIEF DESCRIPTION OF DRAWINGS

[0024] For a better description and illustration of the embodiments and / or examples of the inventions disclosed herein, reference can be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode presently understood of these inventions.

[0025] Figure 1 is a flowchart of a manufacturing method of the trench sidewall gate with the extraction structure in one embodiment;

[0026] Figure 2 is a top view of a trench structure in one embodiment;

[0027] Figure 3 is Figure 2 is a cross-sectional view of the trench structure shown;

[0028] Figure 4 is a schematic diagram of a position of the etching stop layer formed in step S130 in one embodiment;

[0029] Figure 5 is a schematic diagram of a cross section of the wafer after step S140 is completed in one embodiment;

[0030] Figure 6is a cross-sectional view of the wafer after step S150 is completed in one embodiment;

[0031] Figure 7 is a cross-sectional view of the wafer after step S160 is completed in one embodiment;

[0032] Figure 8 is a cross-sectional view of the wafer after step S170 is completed in one embodiment;

[0033] Figure 9 is a cross-sectional view of the wafer after the first trench is filled with silicon oxide and the silicon oxide on the surface of the substrate is removed in one embodiment after step S170 is completed;

[0034] Figure 10 is a cross-sectional view of the trench sidewall gate with a pull-out structure in one embodiment;

[0035] Figure 11 is a top view of the trench structure in one embodiment in which a plurality of first trenches are in a circle of second trenches. DETAILED DESCRIPTION

[0036] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] It is to be understood that the terms "over," "under," "between," and "on" as used herein refer to a relative position of one component layered or disposed over or under another component, and can encompass different positions of the one component relative to the other, including upright, upside down, rotated, angularly positioned, in different orientations, etc. Furthermore, to the extent that the terms "front," "back," "side," "edge," "terminal" and the like can be used in the description or claims, these terms are used to aid the reader's understanding of the invention and are not intended to limit the scope of the invention. It is to be understood that the terms "including," "comprising," "consisting" and "consisting essentially of" to the extent they can be used in the description or claims, do not exclude additional, unrecited elements or method steps. Other than where otherwise indicated, the use of relational terms, if any, such as first, second, third and the like, are used solely to distinguish one element or action from another element or action, without necessarily giving the use of these terms a chronological or hierarchical implication.

[0039] When the terms "including," "comprising," "having" and the like are used in the specification, they specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0040] Embodiments of the application are described herein with reference to the drawings, which are intended to be idealized cross-sectional views of schematic diagrams of embodiments of the application (and intermediate structures). As such, variations from the shapes of the regions shown are expected due to, for example, manufacturing techniques and / or tolerances. Thus, embodiments of the application should not be limited to the particular shapes of regions shown herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region that is shown as a rectangle will typically have rounded or curved features at its edges and / or an implanted concentration gradient rather than a binary change from the implanted region to the non-implanted region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implant was performed. Thus, the regions shown in the figures are substantially schematic only and their shapes are not intended to show the actual shape of a region of a device and are not intended to limit the scope of the application.

[0041] A new type of trench DMOS (Double-diffused MOSFET) device needs to form a gate on the bottom sidewall of a trench, so that the active region under the trench can be led out from the bottom of the trench. Taking the trench sidewall gate as a polycrystalline silicon (poly) gate as an example, the position thereof cannot be led out by directly punching a hole to lead out the polycrystalline silicon. Therefore, the new type of trench sidewall gate faces the technical problem of how to lead out for electrical connection.

[0042] For the trench sidewall gate, an exemplary (taking the gate as a polycrystalline silicon material as an example) leading-out mode is to lead out the polycrystalline silicon in the trench to the wafer surface, so that the trench sidewall gate can be applied with an electrical potential by a conductive material in the via hole.

[0043] In an exemplary split gate process, the strip-shaped split gate trench can be covered with photoresist at the other end during split gate etching, and only the polycrystalline silicon at one end is etched. The polycrystalline silicon (poly1) in the trench that is not covered by the photoresist is etched to a specified depth during split gate etching, while the polycrystalline silicon covered by the photoresist is still retained on the wafer surface, and the bottom is connected to the etched poly1 in the trench. The poly1 etched into the trench can still be connected to the wafer surface through the polycrystalline silicon at the other end.

[0044] However, if the trench sidewall gate wants to be led out by using the above-mentioned split gate process, after the polycrystalline silicon in the trench is etched to a specified depth, a sidewall gate needs to be formed on the bottom sidewall of the trench by self-aligned etching. The photoresist is removed during self-aligned etching, so the polycrystalline silicon at the other end is also etched together, and therefore the polycrystalline silicon cannot remain on the wafer surface for easy leading out by a conventional via hole process. If the photoresist is used as an etching stop layer for etching the sidewall gate, the device yield cannot be guaranteed due to the unstable process of filling the photoresist in the trench and exposure.

[0045] Figure 1 is a flowchart of a manufacturing method of a trench sidewall gate with a leading-out structure in an embodiment, including the following steps:

[0046] S110, etching a first trench and a second trench on a substrate.

[0047] A trench structure is etched on a substrate. The substrate includes a semiconductor substrate, which can be made of undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on- stacked insulator (SSOI), silicon-germanium-on-stacked insulator (S-SiGeOI), silicon- germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), etc. The substrate can also be formed with other structures commonly used in integrated circuit manufacturing, such as shallow trench isolation (STI) structures.

[0048] Referring to Figure 2 , the trench structure includes first trenches 21 for forming a trench sidewall gate and second trenches 23 for forming a lead-out structure, the first trenches 21 being connected to the second trenches 23. Figure 2 The substrate structure outside the second trenches 23 is not shown, as the shape and distribution of the trench structure in the plane are mainly demonstrated. In one embodiment, the cross section of the second trenches 23 is a ring surrounding the first trenches 21. In Figure 2 In the embodiment shown, the cross section of the second trenches 23 is a rectangular frame surrounding the first trenches 21, and the cross section of the first trenches 21 is a strip parallel to a pair of opposite sides of the rectangular frame. For an embodiment in which there is only one first trench 21 in a ring of second trenches 23, the trench structure is in the shape of a "sun" character; for an embodiment in which there are two first trenches 21 in a ring of second trenches 23, the trench structure is in the shape of a "eye" character.

[0049] In one embodiment, the width a of the first trenches 21 is 0.8-1.4 microns, and the width b of the second trenches 23 is 0.6-1 micron. In one embodiment, the depth of the first and second trenches is 2-5 microns.

[0050] Figure 3 is a cross-sectional view of the trench structure shown in Figure 2 In the embodiment shown, the etching in step S110 is performed using a hard mask 12 as an etching stop layer, which can be made of silicon dioxide. Figure 3 S120, filling the first and second trenches with a gate material.

[0051] In one embodiment, the gate material is polysilicon. In other embodiments, the gate material can also be a metal, a metal nitride, a metal silicide or a similar compound. In one embodiment, the gate material can be filled into the first and second trenches 21, 23 by a deposition process.

[0052]

[0053] ​In one embodiment, step S120 is preceded by a step of forming a gate dielectric layer 29 on the first and second trench inner surfaces. In one embodiment, the gate dielectric layer 29 is a gate oxide layer. The gate dielectric layer 29 can also comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant of from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 29 can comprise a generally higher dielectric constant dielectric material having a dielectric constant of from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicates, titanium oxide, barium strontium titanate (BSTs) and lead zirconium titanate (PZTs).

[0054] In one embodiment, the gate dielectric layer 29 is formed by growing a gate oxide layer using a furnace tube. In one embodiment, the gate oxide layer is grown to a thickness of

[0055] In one embodiment, the step of forming the gate dielectric layer 29 is preceded by a step of growing silicon oxide on the substrate surface and the trench structure inner surfaces using a furnace tube and then removing it using a wet process. Specifically, a layer of silicon oxide can be grown to a thickness of on the substrate surface and the trench structure inner surfaces using a furnace tube and then removed using a wet etch. This step can reduce surface damage caused by the etching to form the trench structure (deep trench etch) in step S110 and improve the problem of undercuts at the top of the trench and improve the GOI (Gate Oxide Integrity) capability of the trench sidewalls.

[0056] In one embodiment, the step S120 of filling the gate material is preceded by a step of etching back the filled gate material to a height below the substrate surface

[0057] S130, forming an etch stop layer exposing the first trench and partially exposing the second trench to a certain width.

[0058] The etch stop layer is formed on the substrate. Referring to Figure 4 In one embodiment, the etch stop layer of step S130 is a photoresist, Figure 4 The inner and outer contours of the photoresist are shown in dashed lines in FIGS. 1 1 and 12, respectively, and it will be appreciated that Figure 4 The focus is on the inner contour of the photoresist, mainly to show the position where the second trench 23 is exposed by the etch stop layer, Figure 4The outer profile of the photoresist is expanded to avoid coinciding with other lines and thus to be easily recognized. After the photoresist is developed, the first trench 21 is exposed, and the second trench 23 is partially exposed. The width of the exposed second trench 23 is less than the width of the second trench 23. In one embodiment, the width of the exposed second trench 23 is 0.1-0.5 microns. Figure 4 In the embodiment shown, the photoresist exposes the inner side of the second trench 23. The distance c between the inner side of the photoresist and the inner side of the second trench 23 is 0.1-0.5 microns.

[0059] In S140, the gate material in the first trench is etched to a desired height, and the gate material in the second trench is also etched to form a notch.

[0060] Referring to Figure 5 The gate material 22 in the first trench 21 is anisotropically etched to a desired height. In one embodiment, dry etching is performed using an anisotropic etching gas. Since the photoresist 14 partially exposes the second trench 23, the etching gas also enters from the exposed position, so that the gate material 22 in the second trench 23 is partially etched to form a notch. However, since the exposed width is small, the etching depth is shallow, and a step-like structure is formed at the notch (a step difference is formed because the gate material 22 is etched away). The height of the remaining gate material 22 in the first trench 21 after etching in step S140 is the height of the subsequently formed gate, so the thickness of the etched gate material 22 can be set according to the desired height of the gate. In one embodiment, the height of the remaining gate material 22 in the first trench 21 after etching is 0.1-0.5 microns.

[0061] In S150, after the etching stop layer is removed, chemical vapor deposition (CVD) is performed to form silicon oxide covering the first and second trenches.

[0062] Referring to Figure 6 After CVD is completed in step S150, the thickness of the silicon oxide 16 on the second trench 23 is affected by the notch, and the deposition thickness is greater than the deposition thickness d of the silicon oxide 16 on the gate material 22 in the first trench 21 (because CVD deposits thicker at a step difference).

[0063] In S160, the gate material in the first trench is exposed by general etching, and the silicon oxide on the second trench is still partially retained.

[0064] The silicon oxide 16 on the gate material 22 in the first trench 21 is removed by PR etching without using a photoetching plate, so that the gate material 22 in the first trench 21 is exposed (PR etching uses an anisotropic etching process, and the sidewall of the first trench 21 still has the silicon oxide 16 after PR etching), and the silicon oxide 16 on the second trench 23 has a thickness greater than that of the silicon oxide 16 on the gate material 22 in the first trench 21, so that the silicon oxide 16 on the second trench 23 can remain after the silicon oxide 16 on the gate material 22 in the first trench 21 is removed (similar to the formation of a polysilicon gate sidewall of a MOS tube), see Figure 7 .

[0065] In an embodiment, in order to ensure that the gate material 22 in the first trench 21 is exposed after etching, a certain amount of over-etching is performed in step S160.

[0066] In an embodiment, the thickness of the remaining silicon oxide 16 on the second trench 23 after step S160 is completed is

[0067] S170, self-aligned etching to form a trench sidewall gate, and the gate material in the second trench is used as a gate lead-out structure.

[0068] The silicon oxide 16 remaining on the sidewall of the first trench 21 is used as a barrier layer to etch the gate material 22 in the first trench 21, and a trench sidewall gate 24 is formed on the bottom sidewall of the first trench 21, see Figure 8 Since the gate material 22 in the second trench 23 is in communication with the trench sidewall gate 24 as a whole, the gate material 22 in the second trench 23 can be used as a gate lead-out structure. After the silicon oxide 16 on the second trench 23 is removed in the subsequent step, a via hole is formed by a conventional via hole process to electrically connect to the top of the gate lead-out structure, thereby electrically connecting the gate.

[0069] If the etching barrier layer completely covers the second trench 23 in step S130, the gate material 22 in the second trench 23 will not be partially etched to form a notch, and the thickness of the silicon oxide deposited on the second trench 23 in step S150 will be the same as that of the silicon oxide on the gate material 22 in the first trench 21. Therefore, the silicon oxide on the second trench 23 will be completely etched in step S160, and the gate material 22 in the second trench 23 will be etched downward without the protection of the silicon oxide in step S170, so that the top of the gate material cannot remain on the substrate surface.

[0070] Step S170 can use a high-selectivity anisotropic etching recipe for silicon / silicon oxide to form the trench sidewall gate 24 on the bottom sidewall of the first trench 21. In one embodiment, the main etching gases include Cl2and HBr (carrier gas can also be added). In one embodiment, the flow rate of the etching gases is Cl230sccm-50sccm, HBr 60sccm-80sccm, O2 5sccm-15sccm, and helium 5sccm-15sccm. In one embodiment, the etching pressure is controlled at 30mTorr-70mTorr, the Source Power is controlled at 250W-450W, and the BIAS Power is controlled at -180V--240V.

[0071] It can be understood that the thickness e of the trench sidewall gate 24 is determined by the thickness d of the silicon oxide 16 deposited in step S150. In one embodiment, the thickness of the silicon oxide (silicon dioxide) deposited in step S150 is 1000A-2000A, and the thickness e of the trench sidewall gate 24 is 1000A-2000A.

[0072] The method of manufacturing the trench sidewall gate with the lead-out structure described above has the gate formed on the bottom sidewall of the first trench 21, so that the active region can be led out from the bottom of the first trench 21, and each terminal of the DMOS can be led out from the front surface of the device, thus having good compatibility with the BCD process. When etching the gate material 22 in the first trench 21 using the silicon oxide 16 remaining on the sidewall of the first trench 21 as the etching stop layer, the gate material 22 in the second trench 23 will not be etched because the silicon oxide 16 remains on the second trench 23, so that the height of the gate material 22 in the second trench 23 is the same as that before the deposition of the silicon oxide 16, and the top of the gate material 22 in the second trench 23 can be stopped on the surface of the substrate, so that the gate material 22 can be led out to form the electrical connection to the gate through the conventional via process. In addition, the method described above has only one photolithography process in step S130 after the formation of the trench structure, thus having fewer photolithography processes and lower overall cost.

[0073] In one embodiment, after step S170, the method further includes the steps of filling the first trench 21 with silicon oxide 26, and removing the silicon oxide on the surface of the substrate. After the above steps, the surface of the wafer (the surface of the substrate) returns to the state before step S110, i.e., the surface is flat, as shown in FIG. 1A. Figure 9Thus, the manufacturing process of the trench sidewall gate with the lead-out structure is compatible with the CMOS process. In one embodiment, the filling of the silicon oxide 26 into the first trench 21 can be performed by a high density plasma chemical vapor deposition (HDPCVD) process. In one embodiment, the removal of the silicon oxide from the surface of the substrate can be performed by a wet grinding process.

[0074] In one embodiment, the step S120 is to deposit polysilicon. Since the polysilicon in the trench structure is grown from the trench sidewall to the center of the trench, as long as the thickness of the deposited polysilicon is greater than twice the width of the trench, the trench can be completely filled. Thus, the deposited polysilicon can completely fill the first trench 21 with a width of 0.8-1.4 microns.

[0075] In one embodiment, the substrate has an active region and a STI (shallow trench isolation) region formed thereon, and the step S110 is to etch down to form the trench structure in the STI region. Specifically, the STI structure can be formed by the following process: first, depositing a layer of silicon nitride on the surface of the substrate, then performing photolithography and etching the silicon nitride to form a shallow trench in the STI region, then filling the shallow trench with silicon dioxide, then performing chemical mechanical polishing (CMP) using the silicon nitride as a polishing stop layer, and finally removing the silicon nitride by a wet etching process to obtain the STI structure. In the step S110, the silicon dioxide in the STI structure can be directly used as the hard mask 12.

[0076] The present application provides a trench sidewall gate with a lead-out structure. Figure 10 is a schematic diagram of the cross-sectional structure of the trench sidewall gate with the lead-out structure in one embodiment, which includes a gate 124 disposed on the sidewall of the bottom of a first trench 121 of a substrate, and a gate lead-out structure 126 disposed in a second trench 123 of the substrate and communicating with the first trench 121. The gate lead-out structure 126 is integrated with the gate 124 and has the same material as the gate 124, and the height of the top of the gate lead-out structure 126 approaches the surface of the substrate. Figure 10 In the embodiment shown in the figure, an interlayer dielectric (ILD) 128 is further formed on the first trench 121 and the second trench 123, and a gate dielectric layer 129 is further formed on the inner surface of the first trench 121 and the inner surface of the second trench 123.

[0077] ​For the above-mentioned trench sidewall gate with an extraction structure, since the gate 124 is formed on the bottom sidewall of the first trench 121, the active region can be extracted from the bottom of the first trench 121, so that all ends of the DMOS are extracted from the front of the device, thus having good compatibility with the BCD process. The top height of the gate extraction structure 126 approaches the surface of the substrate, so a via 132 electrically connected to the top of the gate extraction structure 126 can be formed by a conventional via process for electrical connection as the extraction of the gate 124.

[0078] In Figure 10 In the illustrated embodiment, the gate extraction structure 126 has a notch formed at the top on the side close to the gate 124. The material filled in the notch can be silicon oxide, such as silicon dioxide.

[0079] In Figure 10 In the illustrated embodiment, the via 134 is the via for the drain, and the via 136 is the via for the source. The vias 132, 134, and 136 are filled with a conductive material, where the conductive material can be any suitable conductive material well-known to those skilled in the art, including but not limited to metal materials; among them, the metal materials can include one or several of Ag, Au, Cu, Pd, Pt, Cr, Mo, Ti, Ta, W, and Al. The conductive material in the via 134 is electrically connected to the doped region on the surface of the substrate ( Figure 10 the doped region is not shown therein), and the conductive material in the via 136 is electrically connected to the doped region in the substrate under the first trench 121 ( Figure 10 the doped region is not shown therein).

[0080] In Figure 10 In the illustrated embodiment, the positions in the first trench 121 except for the conductive material filled in the via 136 and the gate 124 are filled with silicon oxide.

[0081] In one embodiment, the materials of the gate 124 and the gate extraction structure 126 are polysilicon. In other embodiments, the materials of the gate 124 and the gate extraction structure 126 can also be metals, metal nitrides, metal silicides, or similar compounds.

[0082] In one embodiment, the cross-section of the second trench 123 is a circle surrounding the first trench 121. In another embodiment, the cross-section of the second trench 123 is a rectangular frame surrounding the first trench 121, and the cross-section of the first trench 121 is a strip parallel to a set of opposite sides of the rectangular frame. For the embodiment where there is only one first trench 121 in the circle of the second trench 123, the first trench 121 and the second trench 123 form a "day" - shaped structure; for the embodiment where there are two first trenches 121 in the circle of the second trench 123, the first trench 121 and the second trench 123 form a "mu" - shaped structure. Figure 11is a top view schematic diagram of a trench structure of an embodiment in which a plurality of first trenches 21 are in a second trench 23.

[0083] In one embodiment, the first trenches 121 and the second trenches 123 are formed in an STI region.

[0084] In one embodiment, the substrate includes a semiconductor substrate, which can be made of undoped monocrystalline silicon, monocrystalline silicon doped with impurities, silicon-on-insulator (SOI), silicon-on-insulator-on-silicon (SSOI), silicon-germanium-on-insulator-on-silicon (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), germanium-on-insulator (GeOI), etc. The substrate can also be formed with other structures commonly seen in integrated circuit manufacturing, such as shallow trench isolation (STI) structures.

[0085] In one embodiment, the interlayer dielectric 128 can be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed using a thermal CVD manufacturing process or a high-density plasma CVD (HDPCVD) manufacturing process, which can be specifically an undoped silicon glass (USG), a phosphorus silicon glass (PSG), or a boron phosphorus silicon glass (BPSG). In addition, the interlayer dielectric 128 can also be a boron-doped or phosphorus-doped spin-on-glass (SOG), a phosphorus-doped tetraethoxysilane (PTEOS), or a boron-doped tetraethoxysilane (BTEOS).

[0086] In one embodiment, the gate dielectric layer 129 is a gate oxide layer. The gate dielectric layer 129 can also include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer 129 can include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconium titanate (PZTs).

[0087] The technical features of the above-described embodiments can be combined in any manner. For the sake of brevity, the combinations of the technical features in the above-described embodiments are not described in detail, but it should be understood that any combination of the technical features is within the scope of the present disclosure as long as the combination does not result in a contradiction.

[0088] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for manufacturing a trench sidewall gate with a lead-out structure, comprising: etching a trench structure on a substrate, the trench structure comprising a first trench for forming a trench sidewall gate and a second trench for forming a lead-out structure, the first trench and the second trench being in communication; filling a gate material into the first trench and the second trench, the gate material in the first trench and the second trench being in communication as a whole; forming an etching stop layer on the substrate, the etching stop layer exposing the first trench and partially exposing the second trench, the second trench being exposed with a width less than that of the second trench; performing anisotropic etching on the gate material in the first trench to a desired height, the second trench being partially exposed so that the gate material in the second trench is etched to form a notch; after removing the etching stop layer, performing chemical vapor deposition to form a silicon oxide covering the first trench and the second trench, the silicon oxide on the second trench being affected by the notch so that the thickness is greater than that of the silicon oxide on the gate material in the first trench; and etching the gate material in the first trench with the silicon oxide remaining on the sidewall of the first trench as an etching stop layer to form the trench sidewall gate on the bottom sidewall of the first trench, the gate material in the second trench in communication with the trench sidewall gate as a whole serving as a gate lead-out structure. The second trench has a cross section in the shape of a circle surrounding the first trench. The second trench has a cross section in the shape of a rectangular frame surrounding the first trench, and the first trench has a cross section in the shape of a strip parallel to a pair of opposite sides of the rectangular frame. The first trench has a width of 0.8-1.4 microns, and the second trench has a width of 0.6-1 micron. The first trench and the second trench have a depth of 2-5 microns. The step of forming the etching stop layer on the substrate to expose the second trench has a width of 0.1-0.5 microns. The silicon oxide on the gate material in the first trench is removed by a PKE such that the gate material in the first trench is exposed, the silicon oxide on the second trench is still partially remaining on the second trench, and the thickness of the silicon oxide remaining on the second trench is The PKE employs an anisotropic etching process, and the sidewall of the first trench still remains the silicon oxide after the PKE. The step of forming the etching stop layer on the substrate comprises coating a photoresist and performing photolithography to use the photoresist as the etching stop layer.

2. The method of manufacturing a trench sidewall gate with a pull-out structure according to claim 1, wherein The trench sidewall gate with a lead-out structure is formed by the manufacturing method of any one of claims 1-9, and comprises a gate on the bottom sidewall of the first trench of the substrate and a gate lead-out structure in the second trench in communication with the first trench of the substrate, the gate lead-out structure being in communication with the gate as a whole and having the same material as the gate, and the height of the top of the gate lead-out structure being close to the surface of the substrate.

3. The method of manufacturing a trench sidewall gate with a pull-out structure according to claim 2, wherein The second trench has a cross section in the shape of a rectangular frame surrounding the first trench, and the first trench has a cross section in the shape of a strip parallel to a pair of opposite sides of the rectangular frame.

4. The method of manufacturing a trench sidewall gate with a pull-out structure according to any one of claims 1-3, wherein The gate lead-out structure has a notch formed on the top of one side close to the gate.

5. The method of manufacturing a trench sidewall gate with a pull-out structure according to claim 4, wherein ​ 6. The method of manufacturing a trench sidewall gate with a pull-out structure according to claim 4, wherein ​ 7. The method of manufacturing a trench sidewall gate with a pull-out structure according to claim 1, wherein The step of filling the first and second trenches with a gate material is preceded by the step of forming a gate oxide layer on the inner surfaces of the first and second trenches, the gate oxide layer being formed to a thickness of 8. The method of manufacturing a trench sidewall gate with a pull-out structure according to claim 1, wherein ​ 9. The method of manufacturing a trench sidewall gate with a pull-out structure according to claim 1, wherein, The step of chemical vapor deposition after removing the etching barrier layer uses a gas source of tetraethyl orthosilicate, and the thickness of the deposited silicon oxide is 10. A trench sidewall gate having a pull-out structure, characterized by, ​ 11. The trench sidewall gate with a pull-out structure according to claim 10, wherein, ​ 12. The trench sidewall gate with a lead-out structure according to claim 10 or 11, wherein ​

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