Semiconductor Devices

Abstract

The present invention provides a semiconductor device, which includes: a substrate having a first surface on which an active area is arranged and a second surface opposite to the first surface; a buried wire extending in one direction and having a portion buried in the active area; an insulating portion covering the buried wire; a contact structure arranged on the insulating portion and connected to the buried wire; a through hole extending from the second surface to the insulating portion and exposing the buried portion of the buried wire; an insulating isolation film arranged on a side surface of the buried wire and exposing a bottom surface of the buried portion and a side surface adjacent to the bottom surface; a through passage contacting the bottom surface and the adjacent side surface of the buried wire; and an insulating liner surrounding the through passage.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device. Background Art

[0002] In various semiconductor devices such as logic circuits and memories, source / drain electrodes are connected to metal lines of the back end of line (BEOL) through contact structures.

[0003] A method of forming a conductive through structure such as a TSV from the back side of a substrate and landing the conductive through structure on a conductive line located on the front side of the substrate is used to connect at least a portion of the BEOL (e.g., a power line) to a component located on the back side of the substrate. Summary of the invention

[0004] Example embodiments provide a semiconductor device in which contact resistance of a conductive through structure and a buried conductive line can be reduced.

[0005] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a first surface and a second surface opposite to each other, and an active region is provided at the first surface, the active region having a plurality of fins extending in a first direction; a first isolation region defining the active region, the bottom surface of the first isolation region being lower than the highest surface of the first surface of the substrate; a second isolation region defining the plurality of active fins, the bottom surface of the second isolation region being higher than the bottom surface of the first isolation region; a buried conductive line buried in the second isolation region and extending in the first direction; an insulating isolation film including a first portion disposed between the second isolation region and the buried conductive line; and an interlayer insulating layer. , arranged on the first isolation region and the second isolation region and covering the buried wire; a contact structure, penetrating the interlayer insulating layer and connected to the buried wire; a through hole, extending from the second surface of the substrate toward the first surface of the substrate and exposing a portion of the buried wire, the exposed portion of the buried wire extending toward the second surface of the substrate beyond the bottom surface of the second isolation region; a through via, arranged in the through hole and contacting the bottom surface of the exposed portion of the buried wire and the side surface of the exposed portion of the buried wire, the side surface of the exposed portion of the buried wire being adjacent to the bottom surface of the exposed portion of the buried wire; and an insulating liner, arranged between the inner side wall of the through hole and the through via.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface, and an active area is provided at the first surface; a buried wire arranged in the active area and extending in a first direction, the buried wire having a first portion and a second portion, and the second portion of the buried wire is surrounded by the active area; an insulating layer arranged on the first surface of the substrate and covering the buried wire, the first portion of the buried wire being buried in the insulating layer; a contact structure arranged on the insulating layer and connected to the buried wire; a through hole extending from the second surface of the substrate to the insulating layer and exposing the second portion of the buried wire; an insulating isolation film arranged on a side surface of the buried wire and surrounding the buried wire, the insulating isolation film exposing a bottom surface of the second portion of the buried wire and a side surface of the second portion of the buried wire, the side surface of the second portion of the buried wire being adjacent to the bottom surface of the second portion of the buried wire; a through via arranged in the through hole and contacting the bottom surface of the second portion of the buried wire and the side surface of the second portion of the buried wire; an insulating liner arranged between an inner side wall of the through hole and the through via; and a backside wiring arranged on the second surface of the substrate and connected to the through via.

[0007] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a first surface and a second surface opposite to the first surface and having an active area at the first surface; a through-via extending from the second surface of the substrate toward the first surface thereof; an insulating layer disposed on the first surface of the substrate; a buried wire buried in the insulating layer and the through-via and extending in a first direction; a contact structure disposed on the insulating layer and connected to the buried wire; an insulating isolation film disposed on a side surface of the buried wire and surrounding the buried wire, the insulating isolation film exposing a bottom surface of the buried wire and a portion of the side surface of the buried wire, the portion of the side surface of the buried wire being adjacent to the bottom surface thereof; an insulating liner disposed on the side surface of the through-via and configured to insulate the through-via from the active area of ​​the substrate; and a backside wiring disposed on the second surface of the substrate and connected to the through-via. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a top view showing a semiconductor device according to an example embodiment;

[0010] Figure 2 yes Figure 1 sectional views taken along line II' and line II-II' of the semiconductor device shown in FIG.

[0011] Figure 3 It is shown Figure 2An enlarged cross-sectional view of “A1” of the semiconductor device shown;

[0012] Figure 4 is a rear view showing a semiconductor device according to an example embodiment;

[0013] FIG. 5A to FIG. 5C is a partial cross-sectional view showing a semiconductor device according to various embodiments;

[0014] Fig. 6A and Figure 6B is a partial cross-sectional view showing a semiconductor device according to various embodiments;

[0015] Figure 7 is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0016] Figure 8 It is shown Figure 7 An enlarged cross-sectional view of “A2” of the semiconductor device shown;

[0017] Fig. 9 is an enlarged cross-sectional view showing a semiconductor device according to an example embodiment;

[0018] FIG. 10A to FIG. 10E It shows the manufacturing Figure 1 A cross-sectional view of the method of the semiconductor device shown; and

[0019] FIG. 11A to FIG. 11D It shows the manufacturing Figure 1 A cross-sectional view of a semiconductor device method is shown. DETAILED DESCRIPTION

[0020] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 is a top view showing a semiconductor device according to an example embodiment, Figure 2 yes Figure 1 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line II′ and line II-II′. Figure 3 It is shown Figure 2 An enlarged cross-sectional view of “A1” of the semiconductor device is shown.

[0022] refer to Figure 1 and Figure 2 , a semiconductor device 100 according to an example embodiment may include a substrate 101 having an active region 102. A plurality of active fins 105 may be disposed on an upper surface of the active region 102.

[0023] In some embodiments, the substrate 101 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In another example, the substrate 101 may have a silicon-on-insulator (SOI) structure. The active region 102 may be a conductive region such as an impurity-doped well or an impurity-doped structure. In this embodiment, the active region 102 may be an n-type well for a P-MOS transistor or a p-type well for an N-MOS transistor, but is not limited thereto.

[0024] The plurality of active fins 105 each have a structure protruding upward (e.g., in the z direction) from the upper surface of the active region 102. For example, the active fins 105 may protrude from the top surface of the substrate 101. It should be noted that in some embodiments, the active fins 105 may be part of the substrate, in which case protruding from the substrate means protruding beyond the top surface of the substrate 101 (e.g., where the substrate 101 itself has a protrusion extending beyond its main surface). Figure 1 As shown, a plurality of active fins 105 may be arranged side by side on the upper surface of the active region 102 to extend in a first direction (e.g., an x ​​direction). The active fin 105 may be provided as an active region of each transistor. In the present embodiment, each source / drain region 110 may be provided on two active fins 105. The present invention is not limited thereto. In an example embodiment, each source / drain region 110 may be provided on one active fin 105, or three or more active fins 105.

[0025] The source / drain regions 110 (i.e., source / drain) may be formed in partial regions of the active fin 105 located on opposite sides of the gate structure GS, respectively. In the present example embodiment, by forming a recess in a partial region of the active fin 105 and performing selective epitaxial growth (SEG) in the recess, the source / drain region 110 may be formed to have an upper surface at a level higher than that of the upper surface of the active fin 105. The source / drain region 110 is also referred to as a raised source / drain (RSD). For example, the source / drain region 110 may be formed of Si, SiGe, or Ge, and may have one of n-type and p-type conductivity types. When forming the p-type source / drain region 110, re-growth is performed with SiGe, and boron (B), indium (In), gallium (Ga), boron trifluoride (BF), for example, may be used. 3 ) or the like as p-type impurities. When n-type source / drain regions 110 are formed using silicon (Si), phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb), or the like may be used for doping. During the growth process, different shapes may be formed along a crystallographically stable surface. For example, Figure 2As shown, the source / drain region 110 may have a pentagonal cross section (in the case of a p-type), but may alternatively have a hexagonal or polygonal cross section with a gentle angle (in the case of an n-type).

[0026] The semiconductor device 100 according to example embodiments may include a gate structure GS. Figure 1 The gate structure GS may have a line shape extending in a second direction (eg, y direction) intersecting the first direction (eg, x direction). The gate structure GS may overlap a portion of the active fin 105 .

[0027] like Figure 2 As shown, the gate structure GS used in the present embodiment may include a gate spacer 141, a gate dielectric layer 142 and a gate electrode 145 sequentially disposed between the gate spacers 141, and a gate cap layer 147 disposed on the gate electrode 145. For example, the gate spacer 141 may include an insulating material such as SiOCN, SiON, SiCN or SiN. For example, the gate dielectric layer 142 may be formed by a silicon oxide layer, a high-k dielectric layer or a combination thereof. The high-k dielectric layer may include a material having a dielectric constant higher than that of the silicon oxide layer (e.g., about 10 to 25). For example, the high-k dielectric layer may include a material selected from hafnium oxide, hafnium oxynitride, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide and a combination thereof, but the material is not limited thereto. The gate dielectric layer 142 may be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes.

[0028] The semiconductor device 100 according to the present embodiment may include a device isolation layer 162 .

[0029] The device isolation layer 162 may include a first separation region 162a (i.e., a first isolation region) defining the active region 102 and a second separation region 162b (i.e., a second isolation region) defining a plurality of active fins 105 adjacent to the first separation region 162a. The first separation region 162a has a bottom surface that is deeper (i.e., lower) than a bottom surface of the second separation region 162b. The first separation region 162a may also be referred to as a deep trench isolation (DTI) having a first depth, and the second separation region 162b may also be referred to as a shallow trench isolation (STI) having a second depth that is shallower than the first depth. The second separation region 162b may be disposed on the upper surface 102T of the active region 102. The active fins 105 may penetrate the second separation region 162b to partially protrude upward beyond the upper surface of the second separation region 162b.

[0030] For example, the device isolation layer 162 may include silicon oxide or various silicon-based insulating materials. For example, various insulating materials include tetraethyl orthosilicate (TEOS), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluoride silicate glass (FSG), spin-on glass (SOG), toner silazane (TOSZ) or a combination thereof. The device isolation layer 162 may be formed using CVD or spin coating.

[0031] Figure 3 It is shown Figure 2 An enlarged cross-sectional view of “A1” of the semiconductor device is shown.

[0032] Reference Figure 3 as well as Figure 2 , the semiconductor device 100 according to the present embodiment may include a through via 255 and a buried conductive line 120 buried in the second separation region 162 b. A portion of the buried conductive line 120 may be surrounded by the active region 102. The buried conductive line 120 may be divided into a first portion buried in the second separation region 162 b and a second portion buried in the through via 255. The second portion of the buried conductive line 120 may be surrounded by the active region 102. In the present embodiment, the buried conductive line 120 may be disposed between a plurality of active fins 105 and may extend in a first direction (e.g., an x ​​direction), similar to the active fins 105 (see Figure 1 ).

[0033] The insulating isolation film 131 may be disposed around the buried conductive line 120. The insulating isolation film 131 may be disposed between the second separation region 162b and the buried conductive line 120. Figure 3 As shown, the insulating isolation film 131 surrounds the portion of the buried conductive line 120 buried in the second separation region 162b and exposes at least the bottom surface 120B of the buried conductive line 120 and the side surface 120S adjacent to the bottom surface 120B of the buried conductive line 120. These exposed surfaces can be provided as a contact region CT for the through via 255 of the conductive through structure 250.

[0034] like Figure 2As shown, the conductive through-structure 250 may include a through hole TH extending from the lower surface (e.g., the back side) to the upper surface (e.g., the front side) of the substrate 101, a through-via 255 filling the through hole TH, and an insulating liner 251 disposed between the inner sidewall of the through hole TH and the through-via 255. For example, the conductive through-structure 250 may be a through silicon via (TSV). The conductive through-structure 250 may be formed from the back side of the substrate 101 and connected to the contact region CT of the buried conductive line 120. The through-via 255 may contact the bottom surface 120B of the buried conductive line 120 and the side surface 120S adjacent thereto.

[0035] The insulating isolation film 131 employed in the present embodiment may have an extension portion 131E extending on a portion of the side surface of the buried portion (i.e., the second portion) of the buried conductive line 120. The thickness tb of the extension portion 131E may be smaller than the thickness ta of the portion of the insulating isolation film 131 between the second separation region 162b and the buried conductive line 120. For example, the thickness ta of the insulating isolation film 131 may be in the range of 2 to 10 nm, and the extension portion 131E may have a thickness tb smaller than the thickness ta of other portions of the insulating isolation film 131. In the present embodiment, as shown in FIG. Figure 3 As shown, the extension portion 131E of the insulating isolation film 131 may have a thickness tb that increases as it approaches the second separation region 162b.

[0036] Since the extension portion 131E is a portion remaining after the process of etching a portion of the insulating isolation film located on the bottom surface 120B and the adjacent side surface 120S of the buried conductive line 120 (see Fig. 11C ), so the extension portion 131E of the insulating isolation film 131 may be relatively thin compared to a portion of the insulating isolation film 131 between the second separation region 162b and the buried conductive line 120, and may have a gradually decreasing thickness as described above.

[0037] The bottom surface 120B of the buried conductive line 120 may have a rounded edge RE. In the etching process as described above, the exposed portion of the buried conductive line 120 may also be etched according to the etching selectivity relative to the constituent material of the insulating isolation film 131. As in the present embodiment, when the etching selectivity is not relatively high, a portion (in detail, the edge portion) of the exposed portion of the buried conductive line 120 may be etched to have a rounded structure.

[0038] Reference Figure 3As indicated by "BT", the upper end of the through via 255 of the conductive through structure 250 may contact the second separation region 162b. In the present embodiment, the second separation region 162b as an insulator is located around the buried wire 120, and the upper end width Wb of the conductive through structure 250 is greater than the upper end width Wa of the buried wire 120. Since the upper end width Wb of the conductive through structure 250 is greater than the upper end width Wa of the buried wire 120 (the buried wire 120 has a width that becomes smaller and smaller toward the conductive through structure 250), the formation of the conductive through structure 250 may have a process margin, so that the buried wire 120 does not contact the active region 102 (e.g., Si) even when the conductive through structure 250 is not aligned with the buried wire 120. For example, the upper end width Wb of the conductive through structure 250 (e.g., through hole TH) may be 30nm to 100nm.

[0039] In this way, when the conductive through structure 250 is formed to have an upper end width Wb greater than the upper end width Wa of the buried conductive line 120 and the buried conductive line 120 is formed to penetrate the active area 102, an undesirable short circuit can be prevented even when the conductive through structure has a misaligned landing on the buried conductive line 120. In an example embodiment, even when the conductive through structure 250 is formed to have a misaligned landing on the buried conductive line 120, the buried conductive line 120 penetrating the active area 102 is not short-circuited with the active area 102.

[0040] An interlayer insulating layer 165 may be disposed on the device isolation layer 162 to cover the source / drain region 110 and the buried conductive line 120. An insulating cap layer 135 may be further formed in the device isolation layer 162 to cover the buried conductive line 120. The insulating cap layer 135 may have an upper surface 135T that is substantially coplanar with an upper surface 162T of the device isolation layer 162. Terms such as "same," "equal," "planar," or "coplanar" as used herein include approximate sameness, including variations that may occur, for example, due to manufacturing processes. The term "substantially" may be used here to emphasize this meaning, unless the context or other statements indicate otherwise.

[0041] The interlayer insulating layer 165 and / or the insulating cap layer 135 may be formed of the same or similar material as the above-mentioned material of the device isolation layer 162. Even when formed of the same material (e.g., oxide), the insulating cap layer 135, the device isolation layer 162, and / or the interlayer insulating layer 165 may be visually distinguished by their interfaces. In detail, when formed by different processes, the device isolation layer 162, the interlayer insulating layer 165, and the insulating cap layer 135 may have different film qualities, and these different levels of film quality may be visually distinguished. In this specification, the device isolation layer 162 and the interlayer insulating layer 165 are also referred to as "insulating portions" or "insulating layers". The insulating portion may be disposed on the upper surface of the substrate 101 (e.g., the active area 102) to cover the buried wire 120.

[0042] The buried wire 120 used in the present embodiment may have an upper surface 120T lower than the upper end of the active fin 105. The upper surface 120T of the buried wire 120 may have an upper end width Wa. In the process of forming the source / drain region 110, the buried wire 120 is not exposed to the outside. The upper surface 120T of the buried wire 120 may be higher than the upper surface 102T of the active region 102. The buried wire 120 may be electrically connected to the contact structure 180.

[0043] In an example embodiment, the buried conductive line 120 may be formed to have an aspect ratio of 2 or more. For example, the upper end width Wa of the buried conductive line 120 may be 10nm to 50nm, and in a specific example, may be 20nm to 40nm. The height Ha of the buried conductive line 120 may be 30nm to 200nm. The aspect ratio of the buried conductive line 120 may correspond to a value obtained by dividing the height Ha by the upper end width Wa.

[0044] As described above, the buried conductive line 120 may have a second portion buried in the through-via 255 of the conductive through-structure 250 and surrounded by the active region 102. The second portion of the buried conductive line 120 may be provided as a contact region CT with the conductive through-structure 250. For example, in consideration of the contact region CT, the height or depth Hb of the buried portion (i.e., the second portion) may be at least 10 nm, and the height Hc of the exposed side surface 120S provided as the contact region CT may be at least 3 nm. As in the present embodiment, when the bottom surface 120B of the buried conductive line 120 has a rounded edge RE, as in Figure 3 As shown, the height Hc of the exposed side surface 120S may be defined as the height of the highest point of the exposed side surface 120S in the vertical direction based on the lowest point of the bottom surface 120B.

[0045] As described above, in the present embodiment, in addition to the bottom surface 120B, the side surface 120S is provided as the contact area CT with the through via 255, and therefore, the contact resistance of the buried wire 120 and the conductive through structure 250 can be significantly reduced compared to when the contact area CT is formed only by the bottom surface 120B.

[0046] The contact structure 180 employed in the present embodiment may connect the source / drain region 110 and the buried conductive line 120 to each other. The contact structure 180 may include a conductive barrier 182 and a contact plug 185. The contact structure 180 includes a first contact portion 180A connected to the source / drain region 110 and a second contact portion 180B connected to the buried conductive line 120. The second contact portion 180B may extend deeper than the first contact portion 180A to be electrically connected to the buried conductive line 120. An example of the arrangement of the contact point CP between the second contact portion 180B and the buried conductive line 120 may be shown in FIG. Figure 1 It is shown in the.

[0047] The contact structure 180 may be connected to a first wiring portion ML1 constituting a back end of line (BEOL) The first wiring portion ML1 may be configured to interconnect a plurality of devices (eg, transistors) implemented on the upper surface (ie, first side) of the substrate 101, in detail, on the active region 102.

[0048] The first wiring portion ML1 may include a plurality of low dielectric layers 172 and 175, a metal wiring M1, and a metal via V1. The plurality of low dielectric layers (172 and 175) may include a first low dielectric layer 172 and a second low dielectric layer 175 disposed on the interlayer insulating layer 165. The metal wiring M1 may be formed in the second low dielectric layer 175, and the metal via V1 may be formed in the first low dielectric layer 172. Each metal via V1 may connect the contact structure 180 and the metal wiring M1 to each other (see Figure 1 and Figure 2 ).

[0049] For example, the first low dielectric layer 172 and the second low dielectric layer 175 may include a silicon oxide film, a silicon oxynitride film, a SiOC film, a SiCOH film, or a combination thereof. For example, the metal wiring M1 and the metal via V1 may include copper or a copper-containing alloy. The metal wiring M1 and the metal via V1 may be formed together using a dual damascene process.

[0050] As in the present embodiment, an etching stop layer 171 disposed between the interlayer insulating layer 165 and the first low dielectric layer 172 may be further included. The etching stop layer 171 not only serves as an etching stop layer, but also prevents the metal (e.g., Cu) constituting the metal wiring M1 and the metal via V1 from diffusing to the lower region. For example, the material of the etching stop layer 171 is not limited thereto, and may include aluminum nitride (AlN).

[0051] In this embodiment, the contact structure 180 connected to multiple elements (e.g., source / drain regions 110, etc.) formed on the substrate 101 can be connected to the second wiring portion ML2 located on the back side (i.e., the second side) of the substrate 101 through the buried wire 120 and the conductive through structure 250.

[0052] The second wiring portion ML2 used in the present embodiment may be a power supply line and / or a signal line implemented on the back side of the substrate 101, and may be understood as a wiring portion (i.e., wiring) that replaces a portion of the BEOL. The second wiring portion ML2 located on the back side of the substrate 101 may be referred to as a "back side wiring portion" or "back side wiring".

[0053] The second wiring portion ML2 may provide signals and / or power to a plurality of devices (eg, transistors) implemented on the upper surface of the substrate 101 through the buried conductive line 120 and the conductive through structure 250 .

[0054] After forming the back insulating layer 210, a conductive through structure 250 may be formed on the back side of the substrate 101. A second wiring portion ML2 may be provided on the back insulating layer 210. The second wiring portion ML2 may include a plurality of low dielectric layers 272 and 275, a first metal wiring M2 and a second metal wiring M3, and a metal path V2. The plurality of low dielectric layers may include a first low-k dielectric layer 272 and a second low-k dielectric layer 275 sequentially disposed on the back insulating layer 210. The first metal wiring M2 and the second metal wiring M3 are formed on the back insulating layer 210. The first metal wiring M2 and the second metal wiring M3 may be formed in the first low-k dielectric layer 272 and the second low-k dielectric layer 275, respectively. A metal path V2 connecting the first metal wiring M2 and the second metal wiring M3 may be formed in the first low-k dielectric layer 272. The second metal wiring M3 and the metal path V2 may be formed using a dual damascene process. The first metal wiring M2 may be formed to be connected to the conductive through structure 250.

[0055] Figure 4The layout of the conductive penetration structure 250 and the buried wire 120 when viewed from the back side of the substrate 101 is shown. A plurality of conductive penetration structures 250 may be arranged to be connected to the buried wire 120 extending in a first direction (e.g., the x direction). The cross-section of the conductive penetration structure 250 is substantially rectangular, wherein the length in the first direction (e.g., the x direction) is greater than the length in the second direction perpendicular to the first direction. The present invention is not limited thereto. In an example embodiment, the conductive penetration structure 250 may have a variety of different shapes (e.g., circular, elliptical). In an example embodiment, the conductive penetration structure 250 may be arranged on the same line in the second direction (e.g., the y direction), but in another embodiment, the conductive penetration structure 250 may have a different arrangement. For example, the conductive penetration structure 250 may be arranged to be offset from other adjacent conductive penetration structures 250 in the second direction (e.g., the y direction).

[0056] Wiring such as signal lines and power lines required for the semiconductor device 100 may be implemented on the backside of the substrate 101 by using the buried conductive line 120 and the conductive through structure 250 .

[0057] The second wiring portion ML2 employed in the present embodiment is shown in the form of being implemented together with the first wiring portion ML1 disposed on the upper surface (e.g., the upper portion of the device region) of the substrate 101. In an example embodiment, by using the buried wire 120 and the conductive through structure 250, all necessary BEOL may be implemented as the second wiring portion ML2 located on the back side of the substrate 101, or the first wiring portion ML1 may also be significantly reduced or omitted.

[0058] In an example embodiment, the conductive through structure 250 may include a conductive barrier (not shown) formed inside the through hole TH, wherein the insulating liner 251 is formed in the through hole TH. Similarly, the conductive barrier (not shown) may be additionally formed on the bottom surface and the entire side surface of the buried wire 120, and the conductive barrier may remain in the contact area. For example, at least one of the buried wire 120, the contact plug 185, and the through via 255 may include Cu, Co, Mo, Ru, W, or an alloy thereof. For example, the insulating isolation film 131, the insulating cap layer 135, and the insulating liner 251 may include SiO 2 , SiN, SiCN, SiC, SiCOH, SiON, Al 2 O 3, AlN or a porous material thereof. For example, the conductive barrier 182 may include Ta, TaN, Mn, MnN, WN, Ti, TiN or a combination thereof. In addition, the contact structure 180 may include a metal silicide layer (not shown) disposed between the conductive barrier 182 and the source / drain region 110. For example, the metal silicide layer may be formed of a material such as CoSi, NiSi or TiSi.

[0059] The above-mentioned embodiments may be implemented by variously changing, for example, the contact region of the buried conductive line and the position of the conductive through structure.

[0060] FIG. 5A to FIG. 5C is a partial cross-sectional view showing a semiconductor device according to various embodiments.

[0061] Figure 5A is a cross-sectional view showing a semiconductor device according to an example embodiment, and corresponds to Figure 2 The enlarged cross-sectional view of the "A1" region of the semiconductor device shown in FIG. Figure 3 An enlarged cross-sectional view is shown in FIG.

[0062] refer to Figure 5A , the semiconductor device 100A can be understood as having Figures 1 to 3 The semiconductor device 100 shown in FIG. 1 is similar in structure to the semiconductor device 100 shown in FIG. 1 , except for the shapes of the extension portion 131E of the insulating isolation film 131 and the contact region CT of the buried conductive line 120. The components of this embodiment can be referred to as Figures 1 to 3 Descriptions of the same or similar components of the semiconductor device 100 shown in FIG. 1 are understood unless specifically stated otherwise.

[0063] The extension portion 131E of the insulating isolation film 131 adopted in the present embodiment may have a relatively longer length than the previous embodiment. The extension portion 131E may be arranged to expose a portion of the side surface 120S of the buried conductive line 120 adjacent to the bottom surface 120B. The exposed side surface 120S and the bottom surface 120B of the buried conductive line 120 may provide a contact region CT. The thickness of the extension portion 131E may be less than the thickness of other portions (e.g., the portion of the insulating isolation film 131 between the second separation region 162b and the buried conductive line 120). The extension portion 131E may have a thickness that decreases as it approaches the bottom surface 120B.

[0064] On the other hand, the contact area CT of the buried conductive line 120 may have an angled shape. For example, the edge of the bottom surface 120B of the buried conductive line 120 may maintain a relatively angled shape, different from the rounded edge ( Figure 3 RE in ).

[0065] These differences from the previous embodiment (eg, the length of the extension portion 131E and the shape of the contact region) may be caused by differences in the conditions of the local etching process performed on the preliminary insulating liner 251P and the preliminary insulating isolation film 131P for exposing the contact region CT. FIG. 11A to FIG. 11C For example, it can be understood that the present embodiment is obtained as a result of setting the etching process time to be relatively short or setting the etching process conditions to have a relatively high etching selectivity between the material of the insulating liner 251 and the material of the buried conductive line 120 .

[0066] The remaining degree of the extension portion 131E, or the exposed degree of the side surface 120S, for example, the area of ​​the side surface 120S adjacent to the bottom surface 120B provided as the contact region CT may vary according to the tilt angle of the side surface 120S of the buried conductive line 120 relative to its bottom surface 120B. For example, as the tilt angle of the side surface 120S of the buried conductive line 120 is closer to vertical, the etching amount with respect to the extension portion is reduced, and therefore, under the same etching conditions, the area of ​​the side surface 120S adjacent to the bottom surface 120B may be relatively reduced. The local etching conditions for exposing the contact region CT may be controlled such that in order to induce etching on the side surface of the buried conductive line 120 to ensure the area of ​​the side surface 120S adjacent to the bottom surface 120B, the tilt angle of the side surface 120S of the buried conductive line 120 is smaller than the tilt angle of the inner side wall of the through hole TH.

[0067] Figure 5B is a cross-sectional view showing a semiconductor device 100A′ according to an example embodiment.

[0068] refer to Figure 5B The semiconductor device 100A' has almost no extension of the insulating isolation film 131, and can be understood as having Figures 1 to 3 The structure of the semiconductor device 100 shown in FIG. 1 is similar to that of the semiconductor device 100 shown in FIG. 1 , except that the shape of the contact region CT of the buried conductive line 120 is different. Figures 1 to 3 Descriptions of the same or similar components of the semiconductor device 100 shown in FIG. 1 are understood unless specifically stated otherwise.

[0069] The insulating isolation film 131 employed in the present embodiment does not extend onto a portion of the buried conductive line 120 located in the active region 102. For example, in the through hole, the buried conductive line 120 may be exposed in almost the entire portion of the bottom surface 120B and the side surface 120S adjacent thereto, and thus the exposed side surface 120S and the bottom surface 120B may provide a contact region CT. The contact region CT according to the present embodiment may be ensured to have a greater contact area than the previous embodiment ( Figure 3 and Figure 5A Although not clearly shown, the region BT of the second separation region 162b is in contact with the through via 255, and the through via 255 has a recess extending in the upper direction of the substrate.

[0070] The contact region CT of the buried conductive line 120 may have a rounded structure RE so that the boundary between the bottom surface 120B and the side surface 120S is not clear. This embodiment may be understood as a result obtained by setting the etching process time to be relatively long or setting the etching process conditions to have a relatively low etching selectivity between the material of the insulating liner 251 and the material of the buried conductive line 120.

[0071] Figure 5C is a cross-sectional view showing a semiconductor device 100A" according to an example embodiment.

[0072] Reference Figure 5C , the semiconductor device 100A" has Figure 5A The structure of the semiconductor device 100A shown in FIG. 1 is similar to that of the semiconductor device 100A shown in FIG. 1 , except that the insulating liner 251 partially remains on the top of the through hole TH. Figures 1 to 3 and Figure 5A The same or similar components of the semiconductor devices 100 and 100A shown in FIG. 1 are described unless otherwise noted.

[0073] In the present embodiment, the insulating liner 251 may have a remaining portion 251R partially remaining on the upper end of the through hole TH. In the previous embodiment, when the insulating liner portion and the insulating isolation film portion located on the bottom surface 120B of the buried conductive line 120 are removed, the insulating liner portion located on the upper end of the through hole TH is also removed (see Fig. 11C ), so the through passage 255 and the second separation zone 162b are in direct contact with each other (see Figure 3 However, when the gap G between the inner sidewall of the through hole TH and the side surface of the buried conductive line 120 is narrow compared to the required thickness t1 of the insulating liner 251, a considerable portion of the gap G space may be filled with the insulating liner material when the initial insulating liner 251P is deposited (see Fig. 11B ).

[0074] Results, such as Figure 5CAs shown, even when the insulating liner portion and the insulating isolation film portion located on the bottom surface 120B of the buried conductive line 120 are removed, the remaining portion 251R of the insulating liner 251 may remain at the upper end of the through hole TH. The thickness t2 of the remaining portion 251R may be different from the thickness t1 of the insulating liner 251. For example, as in the present embodiment, the thickness t2 of the remaining portion 251R may be less than the thickness t1 of the insulating liner 251.

[0075] As such, the extension portion 131E and the contact region may have various sizes and shapes due to etching process conditions and / or structural differences (eg, a tilt angle of the buried conductive line 120 and a size of the gap G) for exposing the contact region CT.

[0076] Fig. 6A and Figure 6B is a partial cross-sectional view showing a semiconductor device according to various embodiments, corresponding to Figure 2 An enlarged cross-sectional view of the “A1” region of the semiconductor device is shown in FIG.

[0077] First, refer to Fig. 6A , the semiconductor device 100B can be understood as having Figures 1 to 3 The structure of the semiconductor device 100 shown in FIG. 1 is similar to that of the semiconductor device 100 shown in FIG. 1 , except that the buried wire 120 and the conductive through structure 250 are arranged to be slightly offset. Figures 1 to 3 Descriptions of the same or similar components of the semiconductor device 100 shown in FIG. 1 are understood unless specifically stated otherwise.

[0078] In this embodiment, the central axis Z1 of the buried conductive line 120 may deviate from the central axis Z2 of the conductive through structure 250 . Fig. 6A is Figure 1 The cross section is taken along the second direction (eg, the y direction) in the top view of the conductive through-structure 250, and the offset may be an offset in the y direction. The offset may be in the process of forming the through-hole TH for the conductive through-structure 250 (see Fig.11A )occur.

[0079] The buried conductive line 120 has a first side surface 120S1 and a second side surface 120S2 disposed opposite to each other in the y direction. The first side surface 120S1 and the second side surface 120S2 may extend in a direction (eg, an x ​​direction) along which the buried conductive line 120 extends (see Figure 1 ).

[0080] Similar to the previous embodiment, a portion of the first side surface 120S1 contacts the through via 255 and another portion of the first side surface 120S1 may be covered with the extension portion 131E of the first insulating isolation film 131A. The second side surface 120S2 may be electrically separated from the active region 102 by the second insulating isolation film 131B.

[0081] refer to Figure 6B , the semiconductor device 100B' can be understood as having Fig. 6A The structure of the semiconductor device 100B shown in FIG. 1 is similar to that of the semiconductor device 100B shown in FIG. 1 except that the offset position of the conductive through structure 250 is different. Figures 1 to 3 and Fig. 6A Descriptions of the same or similar components of the semiconductor devices 100 and 100B shown in FIG. 1 are understood unless otherwise noted.

[0082] In this embodiment, the offset degree of the conductive through structure 250 is greater than Fig. 6A The conductive through-structure 250 may be connected to only a portion of the bottom surface 120B of the buried conductive line 120 .

[0083] Similar to the previous implementation ( Fig. 6A ), the buried conductive line 120 has a first side surface 120S1 and a second side surface 120S2 opposite to each other, and the first side surface 120S1 and the second side surface 120S2 may extend in a direction along which the buried conductive line 120 extends. In the present embodiment, the first side surface 120S1 may almost completely contact the through via 255, and the second side surface 120S2 may be electrically insulated from the active region 102 by the second insulating isolation film 131B.

[0084] like Fig. 6A and Figure 6B As shown, even when a slight error occurs when the conductive through structure 250 is misaligned and landed on the buried conductive line 120, not only the bottom surface 120B of the buried conductive line 120 but also at least a portion of the first side surface 120S1 adjacent thereto may be exposed. These exposed surfaces 120B and 120S1 may be used as a contact region CT for connecting to the through via 255, thereby reducing contact resistance.

[0085] Figure 7 is a cross-sectional view showing a semiconductor device according to an example embodiment, corresponding to a cross-sectional view along Figure 1 A cross-sectional view taken along line II' of Figure 8 It is shown Figure 7 An enlarged cross-sectional view of “A2” of the semiconductor device is shown.

[0086] refer to Figure 7 and Figure 8 The semiconductor device 100C according to the embodiment can be understood as having Figures 1 to 3 The structure of the semiconductor device 100 shown in FIG. 1 is similar to that of the semiconductor device 100 shown in FIG. 1 , except that the upper surface of the through hole TH for the conductive through structure 250 is positioned lower than the upper surface 102T of the active region 102. The components of this embodiment can be referred to as Figures 1 to 3 Descriptions of the same or similar components of the semiconductor device 100 shown in FIG. 1 are understood unless specifically stated otherwise.

[0087] The semiconductor device 100C according to the present embodiment may include a substrate 101 having an active region 102, similar to Figures 1 to 3 A plurality of active fins 105 may be disposed on the active region 102 .

[0088] The through hole TH has an upper surface 250T lower than the upper surface 102T of the active region 102 . A portion 102R of the active region 102 is exposed by the upper surface 250T of the through hole TH, and the exposed portion 102R of the active region 102 may be electrically insulated from the through via 255 by the insulating liner 251 .

[0089] The remaining portion 251R of the insulating liner 251 may be located on the upper surface 250T of the through hole TH and have a thickness t2 different from the thickness t1 of the portion of the insulating liner 251 located on the inner sidewall of the through hole TH. The remaining portion 251R may connect the portion of the insulating liner 251 located on the inner sidewall of the through hole TH and the insulating isolation film 131 to each other.

[0090] The buried conductive line 120 may provide a contact area CT with the through via 255 through the bottom surface 120B and the side surface 120S adjacent thereto. The bottom surface 120B of the buried conductive line 120 may have a rounded edge RE. Figure 8 As shown, the extension portion 131E of the insulating isolation film 131 may have a thickness that increases as it approaches the second separation region 162b.

[0091] Fig. 9 is a partial cross-sectional view showing a semiconductor device according to an example embodiment, corresponding to Figure 8 An enlarged cross-sectional view of the “A2” region of the semiconductor device is shown in FIG.

[0092] Reference Fig. 9 , the semiconductor device 100C' can be understood as having Figure 7 and Figure 8 The structure of the semiconductor device 100C shown in FIG. 1 is similar to that of the semiconductor device 100C shown in FIG. 1 , except that the buried wire 120 and the conductive through structure 250 are arranged to be slightly offset. Figures 1 to 3 , Figure 7 and Figure 8 Descriptions of the same or similar components of the semiconductor devices 100 and 100C shown in FIG. 1 are understood unless otherwise noted.

[0093] In this embodiment, the central axis of the buried conductive line 120 and the central axis of the conductive through structure 250 may be offset from each other. As described above, the offset may be caused during the process of forming the through hole TH for the conductive through structure 250 (see Fig.11A ) is generated.

[0094] The buried conductive line 120 may have a first side surface 120S1 and a second side surface 120S2 positioned opposite to each other, and the first side surface 120S1 and the second side surface 120S2 may extend in a direction in which the buried conductive line 120 extends. Fig. 6A ), a portion of the second side surface 120S2 contacts the through via 255, and an extension portion 131E of the first insulating isolation film 131A is disposed on another portion of the second side surface 120S2. The first side surface 120S1 may be electrically separated from the active region 102 by the second insulating isolation film 131B.

[0095] The method for manufacturing a semiconductor device according to the present embodiment will be performed by performing a device portion and a first wiring portion forming process (see FIG. 10A to FIG. 10E ) and the conductive through structure and the second wiring portion forming process (see FIG. 11A to FIG. 11D The semiconductor device manufacturing method according to this embodiment can be understood as Figure 3 1 and 2. A method for manufacturing a semiconductor device 100 is shown in FIG.

[0096] FIG. 10A to FIG. 10E Describes manufacturing Figure 1 0 is a cross-sectional view of a method (eg, a process of forming a device portion and a first wiring portion) of a semiconductor device shown in FIG.

[0097] First, refer to Fig. 10A , a first insulating layer 162 ′ covering the plurality of active fins 105 may be formed.

[0098] A fin mask FM may be provided on the plurality of corresponding active fins 105. The fin mask FM may be a mask used in a process for forming the plurality of active fins 105 prior to this process. A first insulating layer 162' is formed on the substrate 101 to cover the plurality of active fins 105. In this process, after the first insulating layer 162' is formed to cover the fin mask FM, a process such as chemical mechanical polishing (CMP) may be used to planarize the first insulating layer 162' to expose the fin mask FM. In some embodiments, prior to this process, a process may be performed to form a buried conductive line ( Fig. 10CA process of removing some active fins in the area 120).

[0099] Reference Fig. 10B , trenches TR may be formed between the plurality of active fins 105 .

[0100] The trench TR may be formed to extend in a first direction along which the plurality of active fins 105 extend. A formation region of the trench TR may be located between the plurality of active fins 105. The trench TR according to the present embodiment may be formed to extend through a portion of the active region 102 by penetrating the first insulating layer 162' (in detail, by penetrating the device isolation layer 162 in the final structure). The bottom surface of the trench TR may be provided by the active region 102.

[0101] Reference Fig. 10C , a preliminary insulating isolation film 131P and a buried conductive line 120 may be formed in the trench TR, and the buried conductive line 120 may be buried with a second insulating layer 135 ′.

[0102] In this process, a material for an initial insulating isolation film 131P of an insulating isolation film 131 may be formed on the upper surface of the first insulating layer 162' and the inner surface of the trench TR, and a process of selectively removing a portion of the material layer located on the upper surface of the first insulating layer 162' may be performed. Through this process, an initial insulating isolation film 131P may be formed on the inner sidewall and bottom surface of the trench TR. Next, after depositing a conductive material on the upper surface of the first insulating layer 162' and in the trench TR, the conductive material portion located on the upper surface of the first insulating layer 162' is removed by applying an etch-back process, and a buried conductive line 120 may be formed by adjusting the height of the conductive material portion in the trench TR. During the adjustment of the height of the conductive material portion in the trench TR, the initial insulating isolation film 131P is removed together so that the initial insulating isolation film 131P in the trench TR is coplanar with the upper surface of the buried conductive line 120. Subsequently, a second insulating layer 135' may be formed so that the buried conductive line 120 may be buried.

[0103] Reference Fig. 10D , a portion of the active fin 105 is exposed by partially removing the second insulating layer 135 ′ and the first insulating layer 162 ′, and a source / drain region 110 is formed on the exposed portion of the active fin 105 .

[0104] This process may remove portions of the second insulating layer 135' and the first insulating layer 162' using a planarization process such as CMP. This process may be performed until the fin mask FM is exposed. After the fin mask FM is removed, a portion of the plurality of active fins 105 may be exposed by performing an etch-back process so that portions of the first insulating layer 162' and the second insulating layer 130' are removed. The first insulating layer 162' obtained by this process may be provided as Figure 3 The device isolation layer 162, and the second insulating layer 135' may be provided as Figure 3 An insulating capping layer 135 is formed. Recesses are formed in exposed portions of the plurality of active fins 105 , and selective epitaxial growth is performed on the recesses to form source / drain regions 110 .

[0105] Reference Fig. 10E , an interlayer insulating layer 165 is formed, a contact structure 180 penetrating the interlayer insulating layer 165 is formed, and a first wiring portion ML1 is formed on the interlayer insulating layer 165 .

[0106] The interlayer insulating layer 165 is formed to cover the source / drain region 110, and a contact hole exposing the source / drain region 110 and the buried conductive line 120 is formed in the interlayer insulating layer 165. In this case, the depth of the hole portion exposing the buried conductive line 120 may be greater than the depth of the hole portion exposing the source / drain region 110.

[0107] After sequentially forming the conductive barrier 182 and the contact plug 185 so that the contact hole is filled, upper surfaces of the contact structure 180 and the interlayer insulating layer 165 may be formed to have substantially flat coplanar surfaces by performing a planarization process such as CMP.

[0108] Next, a first wiring portion ML1 connected to the contact structure 180 is formed on the interlayer insulating layer 165. An etch stop layer 171 may be formed on the interlayer insulating layer 165, and the first wiring portion ML1 having a plurality of low dielectric layers 172 and 175, a metal wiring M1, and a metal via V1 may be formed. The metal wiring M1 and the metal via V1 may be formed together using a dual damascene process.

[0109] FIG. 11A to FIG. 11D Describes manufacturing Figure 1 0 is a cross-sectional view of a method (eg, a process of forming a conductive through structure and a second wiring portion) of a semiconductor device shown in FIG.

[0110] Reference Fig.11A , in Fig. 10E After the device manufactured in the embodiment is attached to the support member, a through hole TH may be formed in the substrate 101 .

[0111] The support may be attached to the Fig. 10E The first wiring portion ML1 of the device manufactured in the embodiment of the present invention is formed by turning the back side of the substrate 101 to face upward. A back insulating layer 210 for passivation may be formed on the back side of the substrate 101. A through hole TH may be formed from the back side of the substrate 101 toward the buried conductive line 120. A local area BC (also referred to as an exposed portion BC) of the buried conductive line 120 may protrude from the bottom surface (also referred to as an “upper surface” in the description of the previous embodiment) of the through hole TH. For example, in the through hole TH, a local area BC of the buried conductive line 120 may be exposed together with the initial insulating isolation film 131P.

[0112] Reference Fig. 11B , a preliminary insulating liner 251P may be formed on the inner surface of the through hole TH.

[0113] In this process, the preliminary insulating liner 251P may be deposited on the inner sidewall and bottom surface of the through hole TH. In this deposition process, the preliminary insulating liner 251P may cover the inner sidewall and bottom surface of the through hole TH and the exposed portion BC of the buried conductive line 120 .

[0114] Reference Fig. 11C , the insulating liner 251 remaining on the inner sidewall of the through hole TH may be formed by removing a portion of the preliminary insulating liner 251P located on the bottom surface of the through hole TH.

[0115] This process can be performed by an anisotropic etching process. In this process, the initial insulating liner 251P and the initial insulating isolation film 131P are removed together, thereby obtaining a contact area CT with the through-hole 255 to be formed in a subsequent process. As described above, since at least a portion of the side surface adjacent to the bottom surface of the buried conductive line is also exposed, a contact area CT having a relatively large area can be provided. The insulating liner 251 can be formed by retaining only a portion of the initial insulating liner 251P located on the inner side wall of the through hole TH.

[0116] Reference Fig.11D , a through via 255 is formed in the through hole TH, and a second wiring portion ML2 connected to the conductive through structure 250 is formed on the back surface of the substrate 101.

[0117] In this process, the through via 255 may be formed to fill the through hole TH, thereby forming the conductive through structure 250 connected to the contact region CT of the buried conductive line 120. In this case, since the through via 255 contacts not only the bottom surface of the buried conductive line 120 but also a portion of the adjacent side surface, a sufficient contact area may be ensured, and as a result, the contact resistance may be reduced. In the formation process of the through via 255, a conductive material is deposited on the back insulating layer 210 to fill the inside of the through hole TH, and then, a portion of the conductive material located on the upper surface of the back insulating layer 210 may be removed by applying a planarization process such as CMP. Through this planarization process, the upper surface of the back insulating layer 210 and the upper surface of the conductive through structure 250 may have a substantially flat coplanar surface.

[0118] Next, a second wiring portion ML2 may be formed on the back insulating layer 210. The second wiring portion ML2 may include a plurality of low dielectric layers 272 and 275, a first metal wiring M2 and a second metal wiring M3, and a metal via V2. The first metal wiring M2 is formed to be connected to the conductive through structure 250, and the second metal wiring M3 and the metal via V2 may be formed using a dual damascene process. The second wiring portion ML2 may provide signals and / or power to a plurality of devices (e.g., transistors) implemented on the upper surface of the substrate 101 through the buried wire 120 and the conductive through structure 250.

[0119] As explained above, by removing a portion of the initial insulating isolation film located on the bottom surface of the buried conductive line exposed to the through hole and on the side surface adjacent to the bottom surface, the contact area between the conductive through structure such as a through silicon via (TSV) and the buried conductive line on the substrate can be increased, thereby reducing the contact resistance and reducing the IR voltage drop of the power transmission network.

[0120] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

[0121] This application claims the benefit of Korean Patent Application No. 10-2020-0065110 filed on May 29, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference for all purposes.

Claims

1. A semiconductor device, comprising: A substrate having a first surface and a second surface opposite to each other, and an active region is provided at the first surface, wherein the active region has a plurality of active fins extending in a first direction; defining a first isolation region of the active region, wherein a bottom surface of the first isolation region is lower than a highest surface of the first surface of the substrate; defining a second isolation region of the plurality of active fins, wherein a bottom surface of the second isolation region is higher than the bottom surface of the first isolation region; a buried conductive line buried in the second isolation region and extending in the first direction; an insulating isolation film, comprising a first portion disposed between the second isolation region and the buried conductive line; an interlayer insulating layer, disposed on the first isolation region and the second isolation region and covering the buried conductive line; a contact structure penetrating the interlayer insulating layer and connected to the buried conductive line; a through hole extending from the second surface of the substrate toward the first surface of the substrate and exposing a portion of the buried conductive line, wherein the exposed portion of the buried conductive line extends beyond the bottom surface of the second isolation region toward the second surface of the substrate; a through via disposed in the through hole and contacting a bottom surface of the exposed portion of the buried conductive line and a side surface of the exposed portion of the buried conductive line, wherein the side surface of the exposed portion of the buried conductive line is adjacent to the bottom surface of the exposed portion of the buried conductive line; as well as The insulating liner is arranged between the inner side wall of the through hole and the through passage.

2. The semiconductor device according to claim 1, The insulating isolation film further includes a second portion extending beyond the bottom surface of the second isolation region and defining the side surface of the exposed portion of the buried conductive line.

3. The semiconductor device according to claim 2, The second portion of the insulating isolation film has a thickness smaller than a thickness of the first portion of the insulating isolation film.

4. The semiconductor device according to claim 2, The second portion of the insulating isolation film has a thickness that increases toward the second isolation region.

5. The semiconductor device according to claim 2, wherein the side surface of the exposed portion of the buried conductive line is in full contact with the through via, and The exposed portion of the buried conductive line is not covered by the second portion of the insulating isolation film.

6. The semiconductor device according to claim 1, wherein the bottom surface of the exposed portion of the buried conductive line has a rounded edge.

7. The semiconductor device according to claim 1, wherein the through hole extends from the second surface of the substrate to the second isolation region to expose a portion of the bottom surface of the second isolation region, and wherein the through via further contacts an exposed portion of the bottom surface of the second isolation region.

8. The semiconductor device according to claim 1, wherein the through via has an upper end spaced apart from an upper surface of the active region and lower than the upper surface of the active region, wherein a portion of the active region is interposed between the upper end of the through via and the bottom surface of the second isolation region, and The insulating liner is interposed between the portion of the active region and the through via to electrically insulate the active region from the through via.

9. The semiconductor device according to claim 1, Wherein in a cross section taken along a second direction intersecting the first direction, a central axis of the buried conductive line deviates from a central axis of the through via.

10. The semiconductor device according to claim 9, wherein the side surface of the exposed portion of the buried conductive line has a first side and a second side opposite to each other, wherein the first side of the buried conductive line is in contact with the through via, and The second side of the buried conductive line is electrically insulated from the active region by the insulating isolation film.

11. The semiconductor device according to claim 1, in, In a cross section taken along a second direction intersecting the first direction, a first width of an upper surface of the through hole is greater than a second width of an upper surface of the buried conductive line, and The first width and the second width are measured in the second direction.

12. The semiconductor device according to claim 1, wherein the height of the buried conductive line is in the range from 30 nm to 200 nm, and wherein a height of a side portion of the buried conductive line in contact with the through via is at least 3 nm.

13. The semiconductor device according to claim 1, The buried conductive line has an upper surface higher than an upper surface of the active region and lower than upper ends of the plurality of active fins.

14. The semiconductor device according to claim 1, further comprising: A source / drain disposed on the plurality of active fins, The contact structure is connected to the source / drain.

15. The semiconductor device according to claim 1, further comprising: a first wiring, disposed on the interlayer insulating layer and electrically connected to the contact structure; as well as A second wiring is provided on the second surface of the substrate and is connected to the through via.

16. A semiconductor device comprising: a substrate having a first surface and a second surface opposite to the first surface, and an active region provided at the first surface; a buried conductive line disposed in the active region and extending in a first direction, wherein the buried conductive line has a first portion and a second portion, and the second portion of the buried conductive line is surrounded by the active region; an insulating layer disposed on the first surface of the substrate and covering the buried conductive line, wherein the first portion of the buried conductive line is buried in the insulating layer; a contact structure disposed on the insulating layer and connected to the buried conductive line; a through hole extending from the second surface of the substrate to the insulating layer and exposing the second portion of the buried conductive line; an insulating isolation film disposed on a side surface of the buried wire and surrounding the buried wire, the insulating isolation film exposing a bottom surface of the second portion of the buried wire and a side surface of the second portion of the buried wire, wherein the side surface of the second portion of the buried wire is adjacent to the bottom surface of the second portion of the buried wire; a through via disposed in the through hole and contacting the bottom surface of the second portion of the buried conductive line and the side surface of the second portion of the buried conductive line; An insulating lining layer is disposed between the inner side wall of the through hole and the through passage; as well as A backside wiring is provided on the second surface of the substrate and connected to the through via.

17. The semiconductor device according to claim 16, wherein the through via is in contact with a portion of the bottom surface of the insulating layer exposed by the through hole.

18. The semiconductor device according to claim 16, wherein the insulating isolation film has a portion extending beyond the bottom surface of the insulating layer toward the second surface of the substrate, and The extending portion of the insulating isolation film has a thickness that increases toward the bottom surface of the insulating layer.

19. A semiconductor device comprising: a substrate having a first surface and a second surface opposite to the first surface, and an active region provided at the first surface; a through via extending from the second surface of the substrate toward the first surface of the substrate; an insulating layer, disposed on the first surface of the substrate; a buried conductive line buried in the insulating layer and the through via and extending in a first direction; a contact structure disposed on the insulating layer and connected to the buried conductive line; an insulating isolation film disposed on a side surface of the buried wire and surrounding the buried wire, the insulating isolation film exposing a bottom surface of the buried wire and a portion of the side surface of the buried wire, wherein the portion of the side surface of the buried wire is adjacent to the bottom surface of the buried wire; an insulating liner disposed on a side surface of the through via and configured to insulate the through via from the active region of the substrate; and A backside wiring is provided on the second surface of the substrate and connected to the through via.

20. The semiconductor device according to claim 19, wherein the insulating liner includes a first portion and a second portion, the first portion extending from the second surface of the substrate toward the bottom surface of the insulating layer, the second portion connecting the first portion of the insulating liner to the insulating isolation film surrounding the buried conductive line, and The first portion of the insulating liner and the second portion of the insulating liner have different thicknesses.

Images