A Modeling Method for Shielded-Gate Trench MOSFET

Abstract

The present invention discloses a modeling method for a shielded gate trench MOSFET, the modeling method comprising: according to the device structure of the shielded gate trench MOSFET, dividing the device structure into an intrinsic region, an electron diffusion region, a JFET region where the shielding gate is located, and a region under the shielding gate; establishing physical models for the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate respectively; establishing a simulation model in a simulation circuit simulator according to the physical model; judging whether the simulation model meets the error requirements, so as to obtain a simulation model that meets the error requirements. In view of the complex physical properties of the drift region and substrate of the shielded gate trench MOSFET, the present invention simply divides the drift region and the substrate into three parts, including the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate; and establishing equivalent resistance models for the divided regions respectively, so as to improve the simulation accuracy of DC and AC, and ensure that the model accurately predicts the I-V characteristics of the device.

Description

Technical Field

[0001] The invention relates to the field of shielded gate trench MOSFET, and in particular to a modeling method of shielded gate trench MOSFET. Background Art

[0002] Shielded Gate Trench MOSFET (SGT MOS) is a new type of vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS). The shielded gate structure can reduce the on-resistance and gate charge of the device, thereby achieving low loss of the device.

[0003] The model of traditional VDMOS devices is usually implemented using intrinsic MOS series voltage-controlled resistors or junction field-effect transistors (JFETs), where voltage-controlled resistors and JFET devices are used to simulate the IV characteristics of the drift region. However, the traditional voltage-controlled resistor model is generally a multi-term expression of resistance with respect to voltage, which is only a simple fit of the equivalent resistance of the drift region within a specific voltage range and cannot cover the entire voltage range; the JFET device model can only represent the drift region corresponding to the shielded gate of the shielded gate trench MOSFET, that is, the JFET region. It is obviously unreasonable to use only the JFET device model to represent the entire drift region.

[0004] In addition, unlike the pn junction control of the JFET device, the control structure of the shielded gate trench MOSFET is a MOS structure, which is quite different from the JFET device model.

[0005] Therefore, considering the particularity of shielded gate trench MOSFET, it is necessary to accurately model the drift region of shielded gate trench MOSFET and improve the accuracy of the overall model in order to accurately predict the IV characteristics of shielded gate trench MOSFET. Summary of the invention

[0006] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0007] In order to overcome the existing problems, the present invention provides a modeling method for a shielded gate trench MOSFET, the modeling method comprising:

[0008] The device structure of the shielded gate trench MOSFET is divided into an intrinsic region, an electron diffusion region, a JFET region where the shielding gate is located, and a region under the shielding gate;

[0009] Establishing physical models for the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate respectively;

[0010] Establishing a simulation model in a simulation circuit simulator according to the physical model;

[0011] It is determined whether the simulation model meets the error requirement to obtain a simulation model that meets the error requirement.

[0012] Optionally, the device structure of the shielded gate trench MOSFET is divided into an intrinsic region, an electron diffusion region, a JFET region where the shielding gate is located, and a region under the shielding gate, including:

[0013] The device structure of the shielded gate trench MOSFET is divided into four layered regions along the direction from the source to the drain. The four layered regions along the direction from the source to the drain are the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate.

[0014] Optionally, the intrinsic region is a layered region where the control gate polycrystalline and source of the shielded gate trench MOSFET are located;

[0015] The JFET region where the shielding gate is located is a layered region where the shielding gate polycrystalline of the shielding gate trench MOSFET is located;

[0016] The electron diffusion region is a layered region between the intrinsic region and the JFET region where the shield gate is located;

[0017] The region under the shielding gate is a layered region below the JFET region where the shielding gate is located.

[0018] Optionally, establishing physical models for the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate respectively includes:

[0019] Using the BSIM4 model, a physical model of the intrinsic region is obtained;

[0020] A physical model is established for the electron diffusion region using formula (1) to simulate the resistance characteristics of the electron diffusion region;

[0021] R DT (T) = R DT (T NOM )·[1+TCRD1·(TT NOM)+TCRD2·(TT NOM ) 2 ] (1);

[0022] Using formula (2) to establish a physical model for the area under the shielding grid to simulate the resistance characteristics of the area under the shielding grid;

[0023] R DB (T) = R DB (T NOM )·[1+TCRD1·(TT NOM )+TCRD2·(TT NOM ) 2 ] (2);

[0024] Using formulas (3) and (4) to establish a physical model for the JFET region where the shielding gate is located, so as to simulate the resistance characteristics of the JFET region where the shielding gate is located;

[0025] R JFET (T) = R JFET (T NOM )·[1+TCRD1·(TT NOM )+TCRD2·(TT NOM ) 2 ] (3);

[0026]

[0027] Among them, R DT (T) is the equivalent resistance of the electron diffusion region at any temperature;

[0028] R DT (T NOM ) is the equivalent resistance of the electron diffusion region at room temperature, and is the fitting parameter of the simulation model;

[0029] R DB (T) is the equivalent resistance of the region under the shielding gate and the substrate at any temperature;

[0030] R DB (T NOM ) is the equivalent resistance of the area under the shielding grid and the substrate at room temperature, and is the fitting parameter of the simulation model;

[0031] R JFET (T) is the equivalent resistance of the JFET region where the shield gate is located at any temperature;

[0032] R JFET (T NOM ) is the equivalent resistance of the JFET region where the shield gate is located at room temperature, and its two-terminal voltage V D1 、VD2 Related;

[0033] T is the actual operating temperature of the shielded gate trench MOSFET device, T NOM is room temperature, TCRD1 and TCRD2 are the fitting coefficients of the linear term and the quadratic term respectively;

[0034] L SH is the length of the shielding grid, beta, P1, and P2 are the fitting parameters of the simulation model;

[0035] V D1 、V D2 、V D3 They are the node voltages of nodes D1, D2, and D3 respectively, and D1 is R DB and R JFET The node between them, D2 is R JFET and R DT The node between them, D3 is R JFET and a node between transistors in the intrinsic region.

[0036] Optionally, establishing physical models for the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate respectively includes:

[0037] The internal capacitance parameters of the transistor in the intrinsic region are turned off, and the total capacitance C between the gate and the drain in the device structure is calculated using formulas (5) and (6): GD Modeling, the following simulation device structure C GD Capacitance characteristics:

[0038]

[0039]

[0040] Among them, Q GD is the total charge between the gate and the drain in the device structure;

[0041] Z is the effective width of the device structure cell;

[0042] V GD is the voltage between the gate and the drain in the device structure;

[0043] V GD-OVER Processing parameters for continuity;

[0044] CGDO_OUT, CGDL_OUT, and CKAPPAD_OUT are all fitting parameters.

[0045] Optionally, establishing a simulation model in a simulation circuit simulator according to the physical model includes:

[0046] Constructing an equivalent circuit structure according to the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, the region under the shielding gate, and the connection relationship;

[0047] According to the equivalent circuit structure, a simulation model is established in the simulation circuit simulator using a syntax that conforms to the simulation circuit simulator.

[0048] Optionally, in the equivalent circuit structure, the transistor in the intrinsic region is connected in series with an equivalent fixed resistance of the electron diffusion region, an equivalent fixed resistance of the area under the shielding gate and the substrate, and an equivalent fixed resistance of the JFET region where the shielding gate is located, and the equivalent fixed resistance of the JFET region where the shielding gate is located is controlled by a two-terminal voltage.

[0049] Optionally, determining whether the simulation model meets the error requirement includes:

[0050] Performing characteristic test on the shielded gate trench MOSFET to obtain measured data points;

[0051] Performing characteristic simulation on the model in the simulation circuit simulator to obtain a simulation curve;

[0052] Fitting the measured data points to the simulation curve;

[0053] It is determined whether the fitting between the measured data point and the simulation curve meets the error requirement.

[0054] Optionally, the performing characteristic simulation on the model in the simulation circuit simulator to obtain a simulation curve includes:

[0055] According to the structural parameters and process parameters of the shielded gate trench MOSFET, inputting the initial values ​​of the adjustable parameters of the simulation model into the simulation circuit simulator;

[0056] According to the input initial values ​​of the parameters, the characteristics of the simulation model are simulated in the simulation circuit simulator to obtain the simulation curve.

[0057] The determining whether the fitting of the measured data point and the simulation curve meets the error requirement includes:

[0058] If the fitting of the measured data points and the simulation curve meets the error requirement, outputting the simulation model;

[0059] If the fitting between the measured data points and the simulation curve does not meet the error requirement, the simulation model is modified until the error requirement is met.

[0060] Aiming at the complex physical properties of the drift region and substrate of the shielded gate trench MOSFET, the present invention simply divides the drift region and the substrate into three parts, including an electron diffusion region, a JFET region where the shielding gate is located, and a region under the shielding gate; and establishes equivalent resistance models for the divided regions respectively, so as to improve the simulation accuracy of DC and AC and ensure that the model accurately predicts the IV characteristics of the device.

[0061] The modeling method described in the present invention is aimed at shielded gate trench MOSFET. The modeling of shielded gate trench MOSFET belongs to a vertical device, and its voltage level is medium and low voltage. The model of the power device is established, including AC and DC models. The present invention fully considers the influence of the right drift region between the gate and the shielding gate, that is, the electron diffusion region. When the distance between the gate and the shielding gate is large, ignoring the electron diffusion region will affect the model accuracy. Using resistance to represent the electron diffusion region can accurately predict the potential of the node between the JFET region and the electron diffusion region, so that the simulation of the JFET region model is more accurate.

[0062] The present invention fully considers the influence of the area under the shielding gate, and uses resistance to represent the area, which can accurately predict the potential of the node between the JFET area and the area under the shielding gate, making the simulation of the JFET area model more accurate. In addition, the resistance model formula of the JFET area of ​​the present invention is derived by analyzing the physical characteristics of the shielding gate-silicon dioxide-drift region structure, which is closer to the physical law of device operation and more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0064] In the attached figure:

[0065] Figure 1 is a schematic cross-sectional structural diagram of an SGT device according to an embodiment of the present invention;

[0066] Figure 2 is an equivalent circuit structure of an SGT device according to an embodiment of the present invention;

[0067] Figure 3 is a fitting comparison diagram of measured data points of gate-source voltage Vgs relative to drain current Ids of an SGT device at 25° C. and a model simulation curve according to an embodiment of the present invention;

[0068] Figure 4 is a fitting comparison diagram of the drain-source voltage Vds of an SGT device at 25° C. relative to the drain current Ids and the model simulation curve according to an embodiment of the present invention;

[0069] Figure 5 is a fitting comparison diagram of the gate-source voltage Vgs of an SGT device at 150° C. relative to the drain current Ids and the model simulation curve according to an embodiment of the present invention;

[0070] Figure 6 is a fitting comparison diagram of the drain-source voltage Vds of an SGT device at 150° C. relative to the drain current Ids and the model simulation curve according to an embodiment of the present invention;

[0071] Figure 7 It is a flowchart of a modeling method of a shielded gate trench MOSFET according to an embodiment of the present invention. DETAILED DESCRIPTION

[0072] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0073] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0074] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0075] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0076] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0077] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0078] In order to fully understand the present invention, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0079] Currently, there are few reports on shielded gate trench MOSFET models. Most of the modeling uses voltage-controlled resistors or JFET devices to simulate the drift region characteristics. However, the model is based on behavior and ignores some of the internal physical mechanisms of shielded gate trench MOSFETs, making it difficult to accurately describe the complex drift region structure of shielded gate trench MOSFETs.

[0080] There are many methods for establishing models at present, but the modeling object is not shielded gate trench MOSFET. For example, some modeling divides the area of ​​operating voltage and establishes different models in different operating voltage ranges, which cannot be applied to shielded gate trench MOSFET.

[0081] In another modeling method, the modeling object is not for shielded gate trench MOSFET, such as the modeling of lateral high-voltage devices, while the present invention is aimed at the modeling of shielded gate trench MOSFET. The modeling of shielded gate trench MOSFET (SGT) is a vertical device with medium and low voltage levels. It will not have the quasi-saturation effects of high-voltage devices. Its modeling principle is completely different, and its method cannot be applied to the shielded gate trench MOSFET of the present invention.

[0082] Since the structure of the lateral high-voltage device is different from that of the shielded gate trench MOSFET, it does not involve the JFET region, and the structure it contains is the field oxide region. Since the device targeted by the above modeling method is different from the device type of the present application, the modeling method is completely different and cannot be applied to the present invention. In order to solve the various problems mentioned above, the present invention provides a modeling method for the shielded gate trench MOSFET, and the modeling method includes:

[0083] The device structure of the shielded gate trench MOSFET is divided into an intrinsic region, an electron diffusion region, a JFET region where the shielding gate is located, and a region under the shielding gate;

[0084] Establishing physical models for the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate respectively;

[0085] Establishing a simulation model in a simulation circuit simulator according to the physical model;

[0086] It is determined whether the simulation model meets the error requirement to obtain a simulation model that meets the error requirement.

[0087] The modeling method described in the present invention is aimed at shielded gate trench MOSFET. The modeling of shielded gate trench MOSFET belongs to a vertical device, and its voltage level is medium and low voltage. The model of the power device is established, including AC and DC models. The present invention fully considers the influence of the right drift region between the gate and the shielding gate, that is, the electron diffusion region. When the distance between the gate and the shielding gate is large, ignoring the electron diffusion region will affect the model accuracy. Using resistance to represent the electron diffusion region can accurately predict the potential of the node between the JFET region and the electron diffusion region, so that the simulation of the JFET region model is more accurate.

[0088] The present invention fully considers the influence of the area under the shielding gate, and uses resistance to represent the area, which can accurately predict the potential of the node between the JFET area and the area under the shielding gate, making the simulation of the JFET area model more accurate. In addition, the resistance model formula of the JFET area of ​​the present invention is derived by analyzing the physical characteristics of the shielding gate-silicon dioxide-drift region structure, which is closer to the physical law of device operation and more accurate.

[0089] Embodiment 1

[0090] Below, refer to Figure 1-Figure 7 To describe the modeling method of the shielded gate trench MOSFET proposed in the embodiment of the present invention, wherein Figure 1 is a schematic cross-sectional structural diagram of an SGT device according to an embodiment of the present invention; Figure 2 is an equivalent circuit structure of an SGT device according to an embodiment of the present invention; Figure 3 is a fitting comparison diagram of measured data points of gate-source voltage Vgs relative to drain current Ids of an SGT device at 25° C. and a model simulation curve according to an embodiment of the present invention; Figure 4 is a fitting comparison diagram of the drain-source voltage Vds of an SGT device at 25° C. relative to the drain current Ids and the model simulation curve according to an embodiment of the present invention; Figure 5 is a fitting comparison diagram of the gate-source voltage Vgs of an SGT device at 150° C. relative to the drain current Ids and the model simulation curve according to an embodiment of the present invention; Figure 6 is a fitting comparison diagram of the drain-source voltage Vds of an SGT device at 150° C. relative to the drain current Ids and the model simulation curve according to an embodiment of the present invention; Figure 7 It is a flow chart of a modeling method of a shielded gate trench MOSFET according to an embodiment of the present invention.

[0091] The device for establishing the model in the present invention is a shielded gate trench MOSFET. The basic structure of the shielded gate trench MOSFET is described below. Figure 1 is a schematic cross-sectional structure diagram of an SGT device according to an embodiment of the present invention, wherein Figure 1 The basic components of the shielded gate trench MOSFET are shown. For simplified schematic diagrams, the actual shape of each part in the figure is not the same, except Figure 1 In addition to the structure shown in , the shielded gate trench MOSFET may also include other structures.

[0092] The shielded gate trench MOSFET includes an active region, a gate bus and a terminal region. The active region is used to form a unit structure of the device, and the terminal region is located on the periphery of the active region. Taking an N-type device as an example, the device structure includes:

[0093] like Figure 1 As shown, a drift region composed of an N-type doped semiconductor substrate such as a silicon substrate has a P well formed in a selected area on the surface of the drift region, the planar layer where the gate is located is the intrinsic region, and a source region composed of an N+ region is formed on the surface of the intrinsic region, and the source region is led out as a source.

[0094] The gate structure includes a shield gate (Shield Gate) formed in the bottom trench and a gate (Gate) formed in the top trench. Specifically, the gate structure includes: a bottom dielectric layer such as an oxide layer on the bottom surface and side of the bottom trench, a gap formed by the bottom dielectric layer filled with source polysilicon, and a gate filled in the top trench.

[0095] A contact hole is formed on the top of the gate in the gate bus area, the top of the contact hole is connected to the gate bus composed of the front metal layer, and each gate in the active area is connected to the gate in the gate bus area and connected to the gate bus through the contact hole.

[0096] A drain region composed of an N+ region is formed on the back side (bottom side) of the drift region, and a drain electrode composed of a back side metal layer is formed on the back side of the drain region.

[0097] The following is combined with Figure 7 The modeling method of shielded gate trench MOSFET is explained in detail. Figure 7 1 is a flow chart of a modeling method of a shielded gate trench MOSFET according to an embodiment of the present invention, which specifically includes the following steps:

[0098] Step 1: Analyze the device structure of shielded gate trench MOSFET. Different from ordinary VDMOS, shielded gate trench MOSFET has a complex drift region.

[0099] Since the JFET device model can only represent the drift region corresponding to the shielding gate of the shielded gate trench MOSFET, that is, the JFET region, the electron diffusion region above the JFET region and the region under the shielding gate below the JFET region also suffer a large amount of voltage drop. It is obviously unreasonable to use only the JFET device model to represent the entire drift region. In order to solve the current technical problems, the present invention improves the division of regions in the modeling process and re-divides the drift region. That is, in the present invention, the drift region not only includes the JFET region (JFET region) where the shielding gate is located, but also adds the electron diffusion region and the region under the shielding gate, such as Figure 1 As shown in the figure, the improvement simply and accurately represents the voltage drop in the two regions when the device is working, and can accurately predict the voltage drop of the attached Figure 2 The potentials of the node D2 and the node D1 shown in , enable a more accurate prediction of the IV characteristics of the JFET region.

[0100] In the actual modeling process, the structural schematic diagram of the shielded gate trench MOSFET can be obtained according to the preparation process of the shielded gate trench MOSFET, such as Figure 1 As shown, the shielded gate trench MOSFET is divided according to the structural schematic diagram.

[0101] In addition, the shielded gate trench MOSFET can be sliced ​​to obtain a cross-sectional structure diagram of the shielded gate trench MOSFET, and its structure can be analyzed according to the cross-sectional structure diagram of the shielded gate trench MOSFET to obtain Figure 1 A simplified structural schematic diagram of a single structural unit (Cell) is shown, and the obtained structural schematic diagram of the single structural unit (Cell) is divided into regions.

[0102] Considering the physical characteristics of the shielded gate trench MOSFET and its parasitic effects, the rationality of the region division directly affects the accuracy and complexity of the model. Therefore, the present invention simply divides the drift region and the substrate into three parts, including the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate, in view of the complex physical characteristics of the drift region and the substrate of the shielded gate trench MOSFET, so that the modeling of the shielded gate trench MOSFET is more accurate.

[0103] Specifically, Figure 1 As shown, the device structure of the shielded gate trench MOSFET is divided into an intrinsic region, an electron diffusion region, a JFET region where the shielding gate is located, and a region under the shielding gate, including:

[0104] The device structure of the shielded gate trench MOSFET is divided into four regions along the direction from the source to the drain. The four regions along the direction from the source to the drain are the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate.

[0105] The region described in the present invention refers to the entire layered region, that is, including all functional devices in the entire layer. Unless otherwise specified, the region refers to this explanation.

[0106] In one embodiment of the present invention, the intrinsic region is the region where the control gate polycrystalline and the source of the shielded gate trench MOSFET are located.

[0107] The JFET region where the shielding gate is located is the region where the shielding gate polycrystalline of the shielding gate trench MOSFET is located,

[0108] The electron diffusion region is a region between the intrinsic region of the shielded gate trench MOSFET and the JFET region where the shielding gate is located.

[0109] The region under the shielding gate is a region below a JFET region where the shielding gate of the shielding gate trench MOSFET is located, wherein the drain is electrically connected to the region under the shielding gate.

[0110] Step 2: Physically model the drift region, model the three regions separately, and use the BSIM4 model for the intrinsic region.

[0111] Specifically, the intrinsic region can be modeled as a common MOSFET based on its structural characteristics, and the existing BSIM4 model is used to obtain the model of the transistor in the intrinsic region.

[0112] Among them, BSIM4 is an industrial standard for test circuit simulation. It is a mature industrial standard simulation model. It is a physics-based software simulation system used for test circuit simulation and CMOS technology development (CMOS technology development). It has the characteristics of accuracy, scalability, robustness, and language. It can provide DC analysis, transient analysis, AC analysis and other data for standard circuits.

[0113] The three regions divided by the drift region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate are modeled separately.

[0114] A physical model is established for the electron diffusion region using formula (1) to simulate the resistance characteristics of the electron diffusion region;

[0115] R DT (T) = R DT (T NOM )·[1+TCRD1·(TT NOM )+TCRD2·(TT NOM ) 2 ] (1);

[0116] Using formula (2) to establish a physical model for the area under the shielding grid to simulate the resistance characteristics of the area under the shielding grid;

[0117] R DB (T) = R DB (T NOM )·[1+TCRD1·(TT NOM )+TCRD2·(TT NOM ) 2 ] (2);

[0118] Using formulas (3) and (4) to establish a physical model for the JFET region where the shielding gate is located, so as to simulate the resistance characteristics of the JFET region where the shielding gate is located;

[0119] R JFET (T) = R JFET (T NOM )·[1+TCRD1·(TT NOM )+TCRD2·(TT NOM ) 2 ] (3);

[0120]

[0121] Among them, R DT (T) is the equivalent resistance of the electron diffusion region at any temperature;

[0122] R DT (T NOM ) is the equivalent resistance of the electron diffusion region at room temperature, and is the fitting parameter of the simulation model;

[0123] R DB (T) is the equivalent resistance of the region under the shielding gate and the substrate at any temperature;

[0124] R DB (T NOM ) is the equivalent resistance of the area under the shielding grid and the substrate at room temperature, and is the fitting parameter of the simulation model;

[0125] R JFET (T) is the equivalent resistance of the JFET region where the shield gate is located at any temperature;

[0126] R JFET (T NOM ) is the equivalent resistance of the JFET region where the shield gate is located at room temperature, and its two-terminal voltage V D1 、V D2 Related;

[0127] T is the actual operating temperature of the shielded gate trench MOSFET device, T NOM is room temperature, TCRD1 and TCRD2 are the fitting coefficients of the linear term and the quadratic term respectively;

[0128] is the length of the shielding grid, beta, P1, and P2 are the fitting parameters of the simulation model;

[0129] V D1 、V D2 、V D3 They are the node voltages of nodes D1, D2, and D3 respectively, and D1 is R DB and R JFET The node between them, D2 is R JFET and R DT The node between them, D3 is R JFET and a node between transistors in the intrinsic region.

[0130] Wherein, R is given in the above formulas (1) to (4) DT (T), R DB (T) and R JFET (T) The formula for establishing the model, where R DT (T NOM ), R DB (T NOM ) and R JFET (T NOM ) are all fitting parameters of the simulation model and can be adjusted.

[0131] Among them, the R DT (T NOM ), R DB (T NOM ) and R JFET (T NOM ) can be simulated according to the following formula:

[0132] Specifically, formula (7) is used to calculate the R DT (T NOM )Build a physical model;

[0133]

[0134] Formula (8) is used to calculate the R DB (T NOM )Build a physical model;

[0135]

[0136] Formula (9) is used to establish a physical model for the JFET region where the shield gate is located;

[0137]

[0138] In the above formula, t ch is the thickness of the LDD region accumulation layer of the shielded gate trench MOSFET;

[0139] t s For R DB1 The width can be approximated as a constant value;

[0140] Z is the cell width of the shielded gate trench MOSFET;

[0141] q is the charge of the elementary charge;

[0142] μ n is the electron mobility;

[0143] N d is the doping concentration of the electron diffusion region;

[0144] LDT is the length of the electron diffusion region under the shielding gate;

[0145] α is the angle of electron diffusion in the electron diffusion region;

[0146] t DB is the distance between the bottom of the shielding grid and the drift region;

[0147] L DB is the length of the drift zone below the bottom trench;

[0148] L SUB is the substrate length;

[0149] W cell is the cell width;

[0150] β is the angle of electron diffusion under the shielding grid;

[0151] is the bias coefficient of the JFET region where the shield gate is located, L SH is the length of the shielding grid, V FBsh is the flat band voltage between the drift region and the shield gate, ts is the width of RDB1, ti is the thickness of the oxide layer between the shield gate and the drift region, ε si is the dielectric constant of silicon, ε ox is the dielectric constant of SiO2, V D1 、V D2 、V D3 are the node voltages of nodes D1, D2, and D3 respectively, such as Figure 2 shown.

[0152] When modeling the electron diffusion region, it should be noted that except for the cell width Z change in formula (7), the others are process parameters, so the resistance R DT It can be considered as a resistor that does not change with voltage and is only related to the cell width Z, which can well fit SGTs of different sizes.

[0153] When modeling the area under the shield gate, it should be noted that except for the change in the cell width Z in formula (8), the others are process parameters. Therefore, this resistor can be considered as a resistor that does not change with voltage and is only related to the cell width Z. It can well fit SGTs of different sizes.

[0154] in, Figure 2 The equivalent circuit structure of the shielded gate trench MOSFET is obtained by analyzing the structure after the shielded gate trench MOSFET is divided according to the present invention. In the equivalent circuit structure, C GD The capacitance data is not the built-in C in BSIM4 of transistor M1 in the intrinsic region. GD Capacitor, so in order to simulate the capacitance data more accurately, an external plug-in and V GD The plug-in refers to adding an additional capacitor outside of M1 in the model to replace C in M1. GD Capacitors are used to obtain more accurate node voltages and improve simulation accuracy.

[0155] Optionally, the internal capacitance parameters of the transistor in the intrinsic region are turned off, and the total capacitance C between the gate and the drain in the device structure is calculated using formulas (5) and (6): GD Modeling, the following simulation device structure C GD Capacitance characteristics:

[0156]

[0157]

[0158] Among them, Q GD is the total charge between the gate and the drain in the device structure;

[0159] Z is the effective width of the device structure cell;

[0160] V GD is the voltage between the gate and the drain in the device structure;

[0161] V GD-OVER Processing parameters for continuity;

[0162] CGDO_OUT, CGDL_OUT, and CKAPPAD_OUT are all fitting parameters.

[0163] Step three: establishing a simulation model in a simulation circuit simulator according to the physical model.

[0164] Among them, what is established in step 2 is a physical model, and it is necessary to construct a simulation model for the physical model. Specifically, for example, the simulation model is established in a simulation program with integrated circuit emphasis (SPICE).

[0165] In one embodiment of the present invention, in order to facilitate the construction of a simulation model, firstly, according to the division of the shielded gate trench MOSFET of the present invention, the structure is analyzed to obtain the following: Figure 2 The equivalent circuit structure of the shielded gate trench MOSFET is implemented in a specific model instance using a syntax that conforms to SPICE based on the connection relationship and nodes of each region in the equivalent circuit structure and the physical model established in the step 2, and then a simulation model is established in a simulation circuit simulator using the syntax.

[0166] In such Figure 2 In the equivalent circuit structure, the transistor M1 in the intrinsic region and the fixed resistor R equivalent to the electron diffusion region DT , the equivalent fixed resistance R of the area under the shielding grid and the substrate DB And the equivalent fixed resistance R of the JFET region where the shield gate is located controlled by the double-terminal voltage JFET Series connection.

[0167] Among them C DS Coupled with the transistor M1 in the intrinsic region, the C DS Simulation of Figure 2 Shown in the dotted box on the right.

[0168] Similarly, C GS The C is coupled to the transistor M1 in the intrinsic region, and the capacitance characteristics of the transistor M1 in the intrinsic region are adjusted to achieve the C GS Simulation of Figure 2 Shown in the dashed box on the left.

[0169] Therefore, C DS and C GS No additional modeling is required. As mentioned above, only C GD Using plug-in and V GDThe external plug-in refers to adding an additional capacitor outside the transistor M1 in the intrinsic region in the model to replace the C in the transistor M1 in the intrinsic region. GD Capacitors are used to obtain more accurate node voltages and improve simulation accuracy.

[0170] The present invention establishes models for different structures of the drift region and the substrate respectively, so that the device model can better reflect the actual physical characteristics. Among them, the shield gate and the transistor in the intrinsic region (MOS structure of the oxide layer) constitute the control structure of the JFET region. According to the physical characteristics of the structure, the JFET region is equivalent to V D2 and V D1 The resistance model can more accurately reflect the IV characteristics of the JFET region than the JFET device model.

[0171] In addition, the present invention respectively equates the electron diffusion region and the region under the shielding gate to fixed value resistors R DT (T) and R DB (T), simply and accurately represents the voltage drop in these two regions when the device is working, and can accurately predict Figure 1 The potentials at the D2 and D1 nodes are shown, allowing a more accurate prediction of the IV characteristics of the JFET region.

[0172] Furthermore, if the built-in capacitance parameters of the transistor M1 in the intrinsic region are used, the CGD capacitance characteristics cannot be accurately reflected, so an external capacitor is used to fit the CGD capacitance characteristics of the shielded gate trench MOSFET, which can achieve higher accuracy, better convergence, and shorter simulation time.

[0173] Step 4: Extracting initial values ​​of parameters in the simulation model according to process parameters and / or actual test structure.

[0174] The initial parameter value in the simulation model refers to the need to assign values ​​to some parameters in the simulation model when the simulation model is used for simulation, that is, inputting corresponding numerical values ​​for the parameters. The initial parameter value is an adjustable variable. When the initial parameter value is closer to the actual situation of the shielded gate trench MOSFET, the obtained simulation model is more accurate and has a smaller error.

[0175] Among them, the electrical gate oxide layer thickness toxe=7E-8, toxm=7E-8, junction depth xj=1.5E-7, etc. can be obtained from the process parameters, the turn-on voltage vth0=2.3, etc. can be obtained from the actual test data, and the cell size data w=1E-5, l=5.2E-7, etc. can be obtained from the cross-sectional view (or layout).

[0176] In this step, the method of obtaining the initial value of the parameter includes the following two methods:

[0177] In the actual modeling process, the process parameters of the shielded gate trench MOSFET can be obtained according to the preparation process of the shielded gate trench MOSFET.

[0178] In addition, the shielded gate trench MOSFET can be sliced ​​to obtain a cross-sectional structure diagram of the shielded gate trench MOSFET, and its structure can be analyzed based on the cross-sectional structure diagram, and the dimensional parameters of the shielded gate trench MOSFET can be obtained by measuring the actual structure of the shielded gate trench MOSFET.

[0179] Among them, the process parameters and / or dimensional parameters include at least one of the following data: the thickness of the LDD region accumulation layer of the shielded gate trench MOSFET; the width of RDB1, which can be approximated as a constant; the cell width of the shielded gate trench MOSFET; the charge amount of the elementary charge; the electron mobility; the doping concentration of the electron diffusion region; the length of the electron diffusion region under the shielding gate; the angle of electron diffusion in the electron diffusion region; the equivalent resistance of the area under the shielding gate and the substrate; the distance between the bottom of the shielding gate and the drift region; the length of the drift region under the groove; the length of the substrate; the cell width; the angle of electron diffusion under the shielding gate; the length of the shielding gate, the width of RDB1, etc., which are not listed one by one here, and of course other data can also be included.

[0180] The initial parameter value may be directly selected from the process parameter and / or dimension parameter, and the process data and / or actual test data may be adjusted according to the actual modeling situation, which is not limited here.

[0181] Step 5: Perform simulation on the simulation model.

[0182] Specifically, for example, simulation is performed using commercial software, for example, after inputting the initial values ​​of the parameters, the established simulation model is simulated to obtain a simulation curve of the shielded gate trench MOSFET.

[0183] In this step, due to the use of external C GD capacitor, so it is preferred to turn off the intrinsic region of transistor M1 in BSIM4 built-in C GD Capacitor parameters and diode parameters, using external capacitors to fit SGT device C GD Capacitance characteristics.

[0184] And C GS The capacitance characteristics of Figure 2 As shown in the dashed box on the left, the transistor M1 contained in the intrinsic region is still fitted using the CGS parameters built into BSIM4.

[0185] Since the SGT parasitic diode structure is relatively complex, an external diode D is used. BODY The method can accurately describe the capacitance-voltage characteristics, leakage characteristics and dynamic parameter characteristics of the parasitic diode and the high-voltage device, and use D BODY Parameter fitting of SGT device reverse recovery characteristics and C DS Capacitance characteristics.

[0186] In order to improve the accuracy of modeling in the present invention, the device characteristics are fitted with the parameters of BSIM4 in the relatively low voltage part, and the parameters of the external resistor are fitted at higher voltages. The parameters of the external resistor are sensitive to the linear region of the output characteristic curve, and special attention should be paid to the rationality of its value during fitting.

[0187] Step six: Determine whether the simulation model meets the error requirements to obtain a simulation model that meets the error requirements.

[0188] Specifically, determining whether the simulation model meets the error requirement includes:

[0189] The shielded gate trench MOSFET is subjected to a characteristic test to obtain measured data points, wherein, in one embodiment of the present invention, Figure 3 is a fitting comparison diagram of measured data points of gate-source voltage Vgs relative to drain current Ids of an SGT device at 25° C. and a model simulation curve according to an embodiment of the present invention;

[0190] Performing corresponding characteristic simulation in the simulation circuit simulator to obtain a simulation curve corresponding to the measured data point;

[0191] The measured data points are fitted to the simulation curve. In one embodiment of the present invention, Figure 4 is a fitting comparison diagram of measured data points of drain-source voltage Vds relative to drain current Ids of an SGT device at 25° C. according to an embodiment of the present invention and a model simulation curve, wherein A is a simulation curve and B is a measured data point;

[0192] It is determined whether the fitting between the measured data point and the simulation curve meets the error requirement.

[0193] The better the fit between the measured data points and the simulation curve, the smaller the error of the simulation model. Figure 5 is a fitting comparison diagram of the gate-source voltage Vgs of an SGT device at 150° C. relative to the drain current Ids and the model simulation curve according to an embodiment of the present invention; Figure 6: is a fitting comparison diagram of the measured data points of the drain-source voltage Vds relative to the drain current Ids of an SGT device at 150°C according to an embodiment of the present invention and the model simulation curve; wherein A is the simulation curve, B is the measured data point, and Figure 3-Figure 6 It is found that the simulation models of the present invention have very high accuracy.

[0194] In the present invention, the error requirement can be set according to actual conditions. After the error requirement is set, if the fitting of the measured data points and the simulation curve meets the error requirement, the simulation model is output;

[0195] If the fitting of the measured data points and the simulation curve does not meet the error requirement, the simulation model is modified until the error requirement is met. Figure 7 As shown, when the error requirement is not met, the simulation model is corrected. In one embodiment of the present invention, the initial value of the parameter input in the simulation circuit simulator is changed to correct the simulation model to obtain a corrected simulation curve.

[0196] The present invention simply divides the drift region and the substrate into three parts, including the electron diffusion region, the JFET region where the shielding gate is located, and the area under the shielding gate. Compared with using a simple voltage-controlled resistor or JFET device to represent the entire drift region and substrate, the present invention establishes models for different structures of the drift region and substrate respectively, so that the device model can better reflect the actual physical properties.

[0197] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A modeling method for shielded gate trench MOSFET, characterized in that: The modeling method comprises: The device structure of the shielded gate trench MOSFET is divided into an intrinsic region, an electron diffusion region, a JFET region where the shielding gate is located, and a region under the shielding gate, including: dividing the device structure of the shielded gate trench MOSFET into four layered regions along the direction from the source to the drain, the four layered regions are the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate in sequence along the direction from the source to the drain, the intrinsic region is the layered region where the control gate polycrystalline and the source of the shielded gate trench MOSFET are located, the JFET region where the shielding gate is located is the layered region where the shielding gate polycrystalline of the shielded gate trench MOSFET is located, the electron diffusion region is the layered region between the intrinsic region and the JFET region where the shielding gate is located, and the region under the shielding gate is the layered region below the JFET region where the shielding gate is located; Establishing physical models for the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate respectively; Establishing a simulation model in a simulation circuit simulator according to the physical model; Determining whether the simulation model meets the error requirement to obtain a simulation model that meets the error requirement; The establishing of physical models for the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate respectively includes: Using the BSIM4 model, a physical model of the intrinsic region is obtained; A physical model is established for the electron diffusion region using formula (1) to simulate the resistance characteristics of the electron diffusion region; R DT (T)=R DT (T NOM )·[1+TCRD1·(T-T NOM )+TCRD2·(T-T NOM ) 2 ] (1); Using formula (2) to establish a physical model for the area under the shielding grid to simulate the resistance characteristics of the area under the shielding grid; R DB (T)=R DB (T NOM )·[1+TCRD1·(T-T NOM )+TCRD2·(T-T NOM ) 2 ](2); Using formula (3) to establish a physical model for the JFET region where the shielding gate is located, so as to simulate the resistance characteristics of the JFET region where the shielding gate is located; R JFET (T)=R JFET (T NOM )·[1+TCRD1·(T-T NOM )+TCRD2·(T-T NOM ) 2 ] (3); Among them, R DT (T) is the equivalent resistance of the electron diffusion region at any temperature; R DT (T NOM ) is the equivalent resistance of the electron diffusion region at room temperature, and is the fitting parameter of the simulation model; R DB (T) is the equivalent resistance of the region under the shielding gate and the substrate at any temperature; R DB (T NOM ) is the equivalent resistance of the region under the shielding grid and the substrate at room temperature, and is the fitting parameter of the simulation model; R JFET (T) is the equivalent resistance of the JFET region where the shield gate is located at any temperature; R JFET (T NOM ) is the equivalent resistance of the JFET region where the shield gate is located at room temperature, and its two-terminal voltage V D1 、V D2 Related; T is the actual operating temperature of the shielded gate trench MOSFET device, T NOM is room temperature, TCRD1 and TCRD2 are the fitting coefficients of the linear term and the quadratic term respectively.

2. The modeling method according to claim 1, characterized in that: Formula (4) is used to calculate the R JFET (T NOM )Build a physical model; in, L SH is the length of the shielding grid, beta, P1, P2 are the fitting parameters of the simulation model, is the bias coefficient of the JFET region where the shield gate is located, Z is the cell width of the shield gate trench MOSFET, q is the charge of the cell, μ n is the electron mobility, N d is the doping concentration of the electron diffusion region, V FBsh is the flat band voltage between the drift region and the shield gate, ti is the thickness of the oxide layer between the shield gate and the drift region, ε si is the dielectric constant of silicon, ε ox is the dielectric constant of SiO2; V D1 、V D2 They are the node voltages of nodes D1 and D2 respectively, and D1 is R DB and R JFET The node between them, D2 is R JFET and R DT The nodes between.

3. The modeling method according to claim 1, characterized in that: The establishing of physical models for the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, and the region under the shielding gate respectively includes: The internal capacitance parameters of the transistor in the intrinsic region are turned off, and the total capacitance C between the gate and the drain in the device structure is calculated using formulas (5) and (6): GD Modeling, the following simulation device structure C GD Capacitance characteristics: Among them, Q GD is the total charge between the gate and the drain in the device structure; Z is the effective width of the device structure cell; V GD is the voltage between the gate and the drain in the device structure; V GD-OVER Processing parameters for continuity; CGDO_OUT, CGDL_OUT, and CKAPPAD_OUT are all fitting parameters.

4. The modeling method according to claim 1, characterized in that: The step of establishing a simulation model in a simulation circuit simulator according to the physical model comprises: Constructing an equivalent circuit structure according to the intrinsic region, the electron diffusion region, the JFET region where the shielding gate is located, the region under the shielding gate, and the connection relationship; According to the equivalent circuit structure, a simulation model is established in the simulation circuit simulator using a syntax that conforms to the simulation circuit simulator.

5. The modeling method according to claim 4, characterized in that: In the equivalent circuit structure, the transistor in the intrinsic region is connected in series with the equivalent fixed resistance of the electron diffusion region, the equivalent fixed resistance of the area under the shielding gate and the substrate, and the equivalent fixed resistance of the JFET region where the shielding gate is located, and the equivalent fixed resistance of the JFET region where the shielding gate is located is controlled by a two-terminal voltage.

6. The modeling method according to claim 1, characterized in that: The determining whether the simulation model meets the error requirement includes: Performing characteristic test on the shielded gate trench MOSFET to obtain measured data points; Performing characteristic simulation on the model in the simulation circuit simulator to obtain a simulation curve; Fitting the measured data points to the simulation curve; It is determined whether the fitting between the measured data point and the simulation curve meets the error requirement.

7. The modeling method according to claim 6, characterized in that: The method of performing characteristic simulation on the model in the simulation circuit simulator to obtain a simulation curve includes: According to the structural parameters and process parameters of the shielded gate trench MOSFET, inputting the initial values ​​of the adjustable parameters of the simulation model into the simulation circuit simulator; According to the input initial values ​​of the parameters, the characteristics of the simulation model are simulated in the simulation circuit simulator to obtain the simulation curve.

8. The modeling method according to claim 6, characterized in that: The determining whether the fitting of the measured data point and the simulation curve meets the error requirement includes: If the fitting of the measured data points and the simulation curve meets the error requirement, outputting the simulation model; If the fitting between the measured data points and the simulation curve does not meet the error requirement, the simulation model is modified until the error requirement is met.

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