Three-phase full-bridge package chip

Abstract

The embodiment of the present invention discloses a three-phase full-bridge packaged chip. It includes a substrate, three first power grains and three second power grains; the three first power grains constitute the upper bridge arm of the three-phase full bridge, and the three second power grains constitute the lower bridge arm of the three-phase full bridge; the substrate includes a first base island area, a second base island area and a ribbed area; the ribbed area surrounds the first base island area and the second base island area; the three first power grains are all arranged in the first base island area, and each second power grain is arranged in each second base island area; the three first power grains are respectively connected to a second power grain. The three-phase full-bridge packaged chip designed in this scheme can reduce the design volume of the power module of the full bridge, and the circuit frame that fixes the first power grain and the second power grain by using the substrate design to replace the connection circuit of part of the power module of the full bridge, which simplifies the circuit connection of the power module of the full bridge and realizes the packaging design of the highly integrated three-phase full-bridge packaged chip.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of chip packaging technology, and in particular to a three-phase full-bridge packaged chip. Background Art

[0002] At present, the full-bridge Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) power modules all use 6 MOSFET single tubes or 3 half-bridge packaged MOSFET single tubes (each MOSFET single tube has 2 MOSFET crystals packaged inside) to be combined on the water pump or motor control board to generate a three-phase working voltage for the pump or motor. The power module using 6 MOSFET single tubes or 3 half-bridge packaged MOSFET single tubes not only needs to fix each MOSFET single tube on the water pump or motor control board, but also needs to connect each MOSFET single tube. In this process, the full-bridge Metal-Oxide-Semiconductor Field-Effect Transistor power module will be too large, low in integration and complex in circuit. Summary of the invention

[0003] The embodiment of the present invention provides a three-phase full-bridge packaged chip to reduce the design volume of a full-bridge power module, simplify the line connection of the full-bridge power module, and realize a highly integrated three-phase full-bridge packaged chip.

[0004] In a first aspect, an embodiment of the present invention provides a three-phase full-bridge packaged chip, which includes a substrate, three first power grains and three second power grains; the three first power grains constitute an upper bridge arm of the three-phase full bridge, and the three second power grains constitute a lower bridge arm of the three-phase full bridge;

[0005] The substrate includes a first base island area, a second base island area and a rib area; the rib area surrounds the first base island area and the second base island area; three first power grains are all arranged in the first base island area, and each second power grain is arranged in each second base island area; the three first power grains are respectively connected to a corresponding second power grain.

[0006] Optionally, a first power die and a second power die form a bridge arm of a three-phase full bridge; the first power die and the second power die each include a first pole, a second pole and a gate;

[0007] The first electrode of the first power grain is connected to the power supply, the gates of the first power grain and the second power grain are both connected to the control signal, the second electrode of the first power grain is connected to the first electrode of the second power grain, and the second electrode of the second power grain is grounded.

[0008] Optionally, the first base island region includes a first edge, a second edge, a third edge and a fourth edge connected end to end, and the second base island region includes a fifth edge, a sixth edge, a seventh edge and an eighth edge connected end to end; the first edge is parallel to and adjacent to the seventh edge;

[0009] The reinforcing bar area includes a first patterned structure, a second patterned structure, and a third patterned structure;

[0010] The first patterned structure is arranged outside the third edge of the first base island region; the second patterned structure is placed between the first edge and the seventh edge; the third patterned structure is arranged outside the second edge, or the third patterned structure is arranged outside the fourth edge.

[0011] Optionally, a first recessed area is provided on a side of the first patterned structure away from the third edge;

[0012] The three-phase full-bridge packaged chip also includes a first pad, which is disposed in the first recessed area.

[0013] Optionally, three second base island areas are arranged adjacent to each other;

[0014] The reinforcement area further includes a fourth patterned structure, a fifth patterned structure, and a sixth patterned structure;

[0015] A portion of the fourth patterned structure is arranged between the sixth edge and the eighth edge of the adjacent second base island area, and another portion of the fourth patterned structure is arranged between the seventh edge of the second base island area on the outside and the second patterned structure; the fifth patterned structure is arranged on the outside of the fifth edge of the second base island area; the sixth patterned structure is arranged on the outside of the sixth edge of the second base island area on the outside, or the sixth patterned structure is arranged on the outside of the eighth edge of the second base island area on the outside.

[0016] Optionally, a second recessed area is provided on a side of the fifth patterned structure away from the fifth edge;

[0017] The three-phase full-bridge packaged chip also includes a second pad and a third pad, and the second pad and the third pad are arranged in the second recessed area.

[0018] Optionally, a first power die and a second power die form a bridge arm of a three-phase full bridge; the first power die and the second power die each include a first pole, a second pole and a gate;

[0019] The first electrode of the first power grain is connected to the first base island area, the gate of the first power grain is connected to a first pad, the second electrode of the first power grain is connected to a second base island area, the first electrode of the second power grain is connected to the second base island area, the second electrode of the second power grain is connected to a second pad, and the gate of the second power grain is connected to a third pad; the first base island area is connected to a power supply, the first pad and the third pad are connected to a control signal interface, and the second pad is grounded.

[0020] Optionally, the three-phase full-bridge packaged chip further includes a packaging layer;

[0021] The encapsulation layer encapsulates all parts of the substrate except the first base island area, the second base island area, the first pad, the second pad and the third pad.

[0022] Optionally, the three-phase full-bridge packaged chip also includes a transition zone, which is located between the tie-rib zones, between the tie-rib zones and the first base island zone, and between the tie-rib zones and the second base island zone; the thickness of the substrate corresponding to the transition zone is less than the thickness of the substrate corresponding to the first base island zone, and the thickness of the substrate corresponding to the transition zone is less than the thickness of the substrate corresponding to the second base island zone.

[0023] Optionally, the area of ​​the substrate corresponding to the reinforcement area is hollowed out.

[0024] The technical solution of this embodiment can reduce the design volume of the full-bridge power module by using a three-phase full-bridge packaged chip designed with a substrate, a first power grain and a second power grain. The circuit frame that is fixedly supported by the substrate design replaces part of the connection circuits of the full-bridge power module, thereby simplifying the circuit connection of the full-bridge power module and realizing a highly integrated three-phase full-bridge packaged chip without epitaxial pins. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, although the drawings described below are some specific embodiments of the present invention, for those skilled in the art, the basic concepts of the device structure, driving method and manufacturing method disclosed and suggested by the various embodiments of the present invention can be expanded and extended to other structures and drawings, and there is no doubt that these should be within the scope of the claims of the present invention.

[0026] Figure 1 A schematic diagram of the internal structure of a three-phase full-bridge packaged chip provided by an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of a three-phase full-bridge package chip equivalent circuit provided by an embodiment of the present invention;

[0028] Figure 3 A schematic diagram of the internal structure of another three-phase full-bridge package chip provided by an embodiment of the present invention;

[0029] Figure 4 A schematic diagram of the internal structure of another three-phase full-bridge package chip provided by an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of the internal structure of another three-phase full-bridge packaged chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] The embodiment of the present invention provides a three-phase full-bridge package chip. Figure 1 The schematic diagram of the structure of a three-phase full-bridge package chip provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the three-phase full-bridge packaged chip includes a substrate 100, three first power grains 111 and three second power grains 121; the three first power grains 111 constitute the upper bridge arm of the three-phase full bridge, and the three second power grains 121 constitute the lower bridge arm of the three-phase full bridge; the substrate 100 includes a first base island area 110, a second base island area 120 and a tie rod area 130; the tie rod area 130 surrounds the first base island area 110, and surrounds the second base island area 120; the three first power grains 111 are all arranged in the first base island area 110, and each second power grain 121 is arranged in each second base island area 120; the three first power grains 111 are respectively connected to a second power grain 121.

[0033] Specifically, the three-phase full-bridge package chip can convert direct current into three-phase alternating current. The three first power grains 111 and the three second power grains 121 are the control core of the three-phase full-bridge package chip, and the substrate 100 is a carrier for the circuit connection between the three first power grains 111 and the three second power grains 121, realizing the electrical connection between the first power grains 111 and the second power grains 121, and can also serve as a bridge for fixing the first power grains 111 and the second power grains 121 and connecting with external devices.

[0034] In addition, the three first power grains 111 are all arranged on the first base island area 110, and the first power grain 111 is electrically connected to the first base island area 110, that is, the first power grain 111 can realize signal transmission through the connection with the first base island area 110. The three second power grains 121 are respectively arranged on each second base island area 120, and the second power grain 121 is electrically connected to the second base island area 120, that is, the second power grain 121 can realize signal transmission through the connection with the second base island area 120. The ribbed area 130 can be fixedly connected to other areas arranged on the substrate 100, thereby improving the stability of other areas. For example, the ribbed area 130 is used to fix the first base island area 110 and the second base island area 120 arranged on the substrate 100, and the ribbed area 130 is arranged around the first base island area 110 and the second base island area 120.

[0035] In summary, this solution can reduce the design volume of the full-bridge power module by designing a three-phase full-bridge packaged chip using the substrate 100, the first power grain 111 and the second power grain 121. The circuit frame designed with the substrate 100 to fix the first power grain 111 and the second power grain 121 replaces part of the connection circuit of the full-bridge power module, thereby simplifying the circuit connection of the full-bridge power module and realizing a highly integrated three-phase full-bridge packaged chip without epitaxial pins.

[0036] Figure 2 The following is a schematic diagram of a three-phase full-bridge package chip equivalent circuit provided by an embodiment of the present invention. Figure 2 As shown, a first power grain 111 and a second power grain 121 constitute a bridge arm 101 of a three-phase full bridge; the first power grain 111 and the second power grain 121 both include a first pole D, a second pole S and a gate G; the first pole D of the first power grain 111 is connected to the power supply VCC, the gates G of the first power grain 111 and the second power grain 121 are both connected to the control signal, the second pole S of the first power grain 111 is connected to the first pole D of the second power grain 121, and the second pole S of the second power grain 121 is grounded GND.

[0037] Wherein, the first power grain 111 and the second power grain 121 can be a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). The output current of each phase of the three-phase full-bridge packaged chip is output under the joint control of the upper bridge arm of the three-phase full bridge and the lower bridge arm of the three-phase full bridge. Wherein, the upper bridge arm of the three-phase full-bridge packaged chip is composed of three first power grains 111 with a common anode, which are turned on in the positive half cycle of the power supply and output a forward current. The lower bridge arm of the three-phase full-bridge packaged chip is composed of three second power grains 121 with a common cathode, which are turned on in the negative half cycle of the power supply and output a reverse current. The three first power grains 111 are respectively connected to a second power grain 121, thereby realizing the series connection of a group of second power grains 121 with a common cathode and a group of first power grains 111 with a common anode, and realizing the conversion of direct current into three-phase alternating current. A first power chip 111 and a second power chip 121 form a bridge arm 101 of a three-phase full bridge, and the A-phase voltage, the B-phase voltage and the C-phase voltage can be respectively drawn from the connection point between the first power chip 111 and the second power chip 121 in each bridge arm 101 .

[0038] Figure 3 A schematic diagram of the structure of another three-phase full-bridge package chip provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the first base island area includes a first edge 001, a second edge 002, a third edge 003 and a fourth edge 004 connected end to end, and the second base island area includes a fifth edge 005, a sixth edge 006, a seventh edge 007 and an eighth edge 008 connected end to end; the first edge 001 and the seventh edge 007 are parallel and adjacent to each other; the reinforcing bar area includes a first patterned structure 131, a second patterned structure 132 and a third patterned structure 133; the first patterned structure 131 is arranged on the outside of the third edge 003 of the first base island area; the second patterned structure 132 is placed between the first edge 001 and the seventh edge 007; the third patterned structure 133 is arranged on the outside of the second edge 002, or the third patterned structure 133 is arranged on the outside of the fourth edge 004.

[0039] Specifically, the first base island area is a quadrilateral formed by connecting the first edge 001, the second edge 002, the third edge 003 and the fourth edge 004 in sequence, such as the first base island area of ​​a rectangular structure. The second base island area is a quadrilateral formed by connecting the fifth edge 005, the sixth edge 006, the seventh edge 007 and the eighth edge 008 in sequence, such as the second base island area of ​​a rectangular structure. The first base island area is used to set three power grains correspondingly, and the second base island area is used to set one power grain correspondingly, and each first power grain 111 on the first base island area is connected to each second power grain 121 set on the second base island, and the first edge 001 of the first base island area is parallel to and adjacent to the seventh edge 007 of the second base island area, thereby facilitating the connection of the first power grain 111 and the second power grain 121 set on the first base island area and the second base island area. The rib area arranged around the first base island area includes a first patterned structure 131, a second patterned structure 132 and a third patterned structure 133. The specific positional relationship between the first patterned structure 131, the second patterned structure 132, and the third patterned structure 133 and the first base island region on the substrate is as follows: the first patterned structure 131 is arranged outside the third edge 003 of the first base island region 110; the second patterned structure 132 is placed between the first edge 001 and the seventh edge 007; the third patterned structure 133 is arranged outside the second edge 002, or the third patterned structure 133 is arranged outside the fourth edge 004. Thus, the first patterned structure 131, the second patterned structure 132, and the third patterned structure 133 surround the first base island region, thereby achieving stable fixation of the first base island region.

[0040] Continue to refer Figure 3 Optionally, a first recessed area 1311 is provided on a side of the first patterned structure 131 away from the third edge 003 ; the three-phase full-bridge packaged chip further includes a first solder pad, which is provided in the first recessed area 1311 .

[0041] Specifically, a first recessed area 1311 is also provided on the substrate of the three-phase full-bridge package chip, and a first pad is also provided in the first recessed area 1311. The first pad is used to be electrically connected to the first power die 111 provided on the first base island area, and serves as a bridge for signal transmission between the first power die 111 provided on the first base island area and an external device. The first recessed area 1311 is provided on the side of the first patterned structure 131 away from the third edge 003, so that the first patterned structure 131 is convenient for stably fixing the first pad, and the first patterned structure 131 also ensures a stable connection between the first pad and the first base island area. It should be noted that the thickness of the substrate corresponding to the first patterned structure 131 is less than the thickness of the first pad provided corresponding to the first recessed area 1311 of the substrate.

[0042] Continue to refer Figure 3 , optionally, three second base island areas are arranged adjacent to each other; the reinforcing bar area also includes a fourth patterned structure 134, a fifth patterned structure 135 and a sixth patterned structure 136; a part of the fourth patterned structure 134 is arranged between the sixth edge 006 and the eighth edge 008 of the adjacent second base island area, and another part of the fourth patterned structure 134 is arranged between the seventh edge 007 of the second base island area on the outside and the second patterned structure 132; the fifth patterned structure 135 is arranged on the outside of the fifth edge 005 of the second base island area; the sixth patterned structure 136 is arranged on the outside of the sixth edge 006 of the second base island area on the outside, or the sixth patterned structure 136 is arranged on the outside of the eighth edge 008 of the second base island area on the outside.

[0043] Specifically, three adjacent second base islands are arranged on the substrate of the three-phase full-bridge package chip, and the seventh edge 007 of each second base island is parallel to and adjacent to the first edge 001 of the first base island, so that the second base island is arranged outside the first edge 001 of the first base island. The rib area also includes a fourth patterned structure 134, a fifth patterned structure 135, and a sixth patterned structure 136. The rib area arranged around the second base island includes a second patterned structure 132, a fourth patterned structure 134, a fifth patterned structure 135, and a sixth patterned structure 136. The specific positional relationship between the second patterned structure 132, the fourth patterned structure 134, the fifth patterned structure 135 and the sixth patterned structure 136 and the second base island region on the substrate is as follows: the second patterned structure 132 is arranged outside the seventh edge 007 of the three second base island regions, a portion of the fourth patterned structure 134 is arranged between the sixth edge 006 and the eighth edge 008 of the adjacent second base island region, and another portion of the fourth patterned structure 134 is arranged between the seventh edge 007 of the second base island region on the outside and the second patterned structure 132; the fifth patterned structure 135 is arranged outside the fifth edge 005 of the second base island region; the sixth patterned structure 136 is arranged outside the sixth edge 006 of the second base island region on the outside, or the sixth patterned structure 136 is arranged outside the eighth edge 008 of the second base island region on the outside. Thus, the second patterned structure 132, the fourth patterned structure 134, the fifth patterned structure 135 and the sixth patterned structure 136 surround the second base island region, thereby achieving stable fixation of the second base island region.

[0044] Continue to refer Figure 3 Optionally, a second recessed area 1351 is provided on a side of the fifth patterned structure 135 away from the fifth edge 005 ; the three-phase full-bridge package chip also includes a second solder pad and a third solder pad, and the second solder pad and the third solder pad are provided in the second recessed area 1351 .

[0045] Specifically, a second recessed area 1351 is also provided on the substrate of the three-phase full-bridge package chip, and a second pad and a third pad are also provided in the second recessed area 1351. The second pad and the third pad are used to be electrically connected to the second power die 121 provided on the second base island area, and serve as a bridge for the second power die 121 provided on the second base island area to transmit signals with an external device. The second recessed area 1351 is provided on the side of the fifth patterned structure 135 away from the fifth edge 005, so that the fifth patterned structure 135 is convenient for stably fixing the second pad and the third pad, and the fifth patterned structure 135 also ensures the stable connection of the second pad, the third pad and the second base island area. It should be noted that the thickness of the substrate corresponding to the fifth patterned structure 135 is less than the thickness of the second pad and the third pad provided corresponding to the first recessed area 1311 of the substrate.

[0046] Figure 4 A schematic diagram of the structure of another three-phase full-bridge package chip provided by an embodiment of the present invention is shown in FIG. Figure 4 As shown, a first power grain 111 and a second power grain 121 constitute a bridge arm of a three-phase full bridge; the first power grain 111 and the second power grain 121 each include a first pole D, a second pole S and a gate G; the first pole D of the first power grain 111 is connected to the first base island region 110, the gate G of the first power grain 111 is connected to a first pad 140, the second pole S of the first power grain 111 is connected to a second base island region 120, the first pole D of the second power grain 121 is connected to the second base island region 120, the second pole S of the second power grain 121 is connected to a second pad 150, and the gate G of the second power grain 121 is connected to a third pad 160; the first base island region 110 is connected to a power supply, the first pad 140 and the third pad 160 are connected to a control signal interface, and the second pad 150 is grounded.

[0047] Specifically, a first power chip 111 and a second power chip 121 form a bridge arm 100 of a three-phase full bridge, and the A phase voltage, the B phase voltage and the C phase voltage can be respectively drawn from the connection between the first power chip 111 and the second power chip 121 of each bridge arm. Figure 4As shown, the first power die 111 and the second power die 121 are metal oxide semiconductor die, wherein the first surface (bottom surface) of the metal oxide semiconductor die is the first pole D, the second surface (front surface) is the second pole S, and the square area on the second surface of the metal oxide semiconductor die is the gate G. The first pole D of the first power die 111 is connected to the first base island area 110, and the first pole D of the first power die 111 can be welded on the first base island area 110. The gate G of the first power die 111 is connected to a first pad 140, and one end of a copper wire or a gold wire can be welded to the gate G of the first power die 111, and the other end of the copper wire or the gold wire can be welded to the first pad 140. The second pole S of the first power die 111 is connected to a second base island area 120, and one end of a copper sheet or an aluminum strip can be welded to the first pole D of the second module, and one end of the copper sheet or the aluminum strip can be connected to the second base island area 120. The first electrode D of the second power die 121 is connected to the second base island region 120, and the first electrode D of the second power die 121 can be welded to the second base island region 120. The second electrode S of the second power die 121 is connected to a second pad 150, and one end of a copper wire or a gold wire can be welded to the second electrode S of the second power die 121, and the other end of the copper wire or the gold wire can be welded to the second pad 150. The gate G of the second power die 121 is connected to a third pad 160, and one end of the copper wire or the gold wire can be welded to the gate G of the second power die 121, and the other end of the copper wire or the gold wire can be welded to the third pad 160. In addition, the first base island region 110 is connected to a power source, the first pad 140 and the third pad 160 are connected to a control signal interface, and the second pad 150 is grounded.

[0048] According to the above connection relationship, it can be known that the first pole D of the first power grain 111 can be connected to the power supply through the first base island area 110, the gate G of the first power grain 111 can be connected to the control signal interface through the first pad 140, the gate G of the second power grain 121 can be connected to the control signal interface through the third pad 160, the second pole S of the first power grain 111 is connected to the first pole D of the second power grain 121 through the second base island area 120, and the second pole S of the second power grain 121 is grounded GND through the second pad 150.

[0049] Optionally, the three-phase full-bridge packaged chip further includes a packaging layer; the packaging layer packages all parts of the substrate except the first base island area, the second base island area, the first pad, the second pad and the third pad.

[0050] Among them, the encapsulation layer can be made of epoxy resin, which has excellent chemical resistance, strong adhesion, good heat resistance and electrical insulation. Therefore, epoxy resin is used as the encapsulation layer to encapsulate all parts except the first base island area, the second base island area, the first pad, the second pad and the third pad, which can well protect the parts wrapped by the encapsulation layer. Since the first power grain and the second power grain need to be arranged on the first base island area and the second base island area respectively, and the first power grain and the second power grain need to be in contact and electrically connected with the external interface, the encapsulation layer does not need to wrap the first base island area and the second base island area. Similarly, the first pad serves as a bridge for the first power grain arranged on the first base island area to transmit signals with an external device, and the second pad and the third pad serve as bridges for the second power grain arranged on the second base island area to transmit signals with an external device, and need to be in contact and electrically connected with the external interface, so the encapsulation layer does not need to wrap the first pad, the second pad and the third pad. In addition, since the thickness of the tie rod area is smaller than that of the first base island area, the second base island area, the first pad, the second pad and the third pad, encapsulating the tie rod area with a packaging layer can reduce the stress in the tie rod area and achieve stress release in the tie rod area through the packaging layer.

[0051] Optionally, the three-phase full-bridge packaged chip also includes a transition zone, which is located between the tie-rib zones, between the tie-rib zones and the first base island zone, and between the tie-rib zones and the second base island zone; the thickness of the substrate corresponding to the transition zone is less than the thickness of the substrate corresponding to the first base island zone, and the thickness of the substrate corresponding to the transition zone is less than the thickness of the substrate corresponding to the second base island zone.

[0052] Among them, the specific function of the transition zone is to connect the first base island area, the second base island and the ribbed area. For example, the transition zone is set between the ribbed area and the ribbed area, between the ribbed area and the first base island area, and between the ribbed area and the second base island area. In order not to affect the later wiring setting of the power grains carried by the first base island area and the second base island area (mainly to prevent the contact short circuit between the lead and the transition zone), the transition zone is set between the ribbed areas, between the ribbed area and the first base island area, and between the ribbed area and the second base island area, and the thickness of the transition zone corresponding to the substrate is set to be less than the thickness of the substrate corresponding to the first base island area, and the thickness of the transition zone corresponding to the substrate is less than the thickness of the substrate corresponding to the second base island area. Exemplarily, the thickness of the transition zone is 0.1mm±0.01mm, and the thickness of the first base island area and the second base island area is 0.2mm. The transition zone on the substrate can be set by a half-etching process to etch the thickness of the transition zone to 0.1mm±0.01mm.

[0053] Figure 5 A schematic diagram of the structure of another three-phase full-bridge package chip provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the area within the substrate corresponding to the reinforcement zone is hollowed out.

[0054] Among them, the area in the substrate corresponding to the reinforcing bar area is hollowed out (the shadow area is hollowed out). Exemplarily, the internal areas of the first patterned structure 131, the second patterned structure 132, the third patterned structure 133, the fourth patterned structure 134, the fifth patterned structure 135 and the sixth patterned structure 136 are hollowed out. Among them, the area in the substrate corresponding to the reinforcing bar area is hollowed out, and an etching process can be used to etch out the internal area of ​​the reinforcing bar area. Thus, the frame of the reinforcing bar area can be fixedly connected to other areas set on the substrate, thereby improving the stability of other areas. In addition, hollowing out the internal area of ​​the reinforcing bar area is to remove unnecessary areas on the basis of ensuring normal electrical isolation, and the retained substrate area can reach more than 70% of the entire chip frame, ensuring rapid heat dissipation of the entire chip frame.

[0055] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A three-phase full-bridge packaged chip, characterized in that: It comprises a substrate, three first power crystals and three second power crystals; the three first power crystals constitute the upper bridge arm of the three-phase full bridge, and the three second power crystals constitute the lower bridge arm of the three-phase full bridge; The substrate includes a first base island area, three second base island areas and a rib area; the rib area surrounds the first base island area and the second base island area, and the rib area is used to fix the first base island area and the second base island area; the thickness of the rib area is set to be smaller than the first base island area and the second base island area, the three first power grains are all set in the first base island area, the first power grain is electrically connected to the first base island area, each second power grain is set in a second base island area, and the second power grain is electrically connected to the second base island area; the three first power grains are respectively connected to a corresponding second power grain; The first base island region includes a first edge, a second edge, a third edge and a fourth edge connected end to end, and the second base island region includes a fifth edge, a sixth edge, a seventh edge and an eighth edge connected end to end; the first edge is parallel to and adjacent to the seventh edge; The reinforcing bar area includes a first patterned structure, a second patterned structure and a third patterned structure; The first patterned structure is arranged outside the third edge of the first base island region; the second patterned structure is placed between the first edge and the seventh edge; the third patterned structure is arranged outside the second edge, or the third patterned structure is arranged outside the fourth edge; The three second base island areas are adjacently arranged; The reinforcing bar area further includes a fourth patterned structure, a fifth patterned structure and a sixth patterned structure; A portion of the fourth patterned structure is arranged between the sixth edge and the eighth edge of the adjacent second base island area, and another portion of the fourth patterned structure is arranged between the seventh edge of the second base island area on the outside and the second patterned structure; the fifth patterned structure is arranged on the outside of the fifth edge of the second base island area; the sixth patterned structure is arranged on the outside of the sixth edge of the second base island area on the outside, or the sixth patterned structure is arranged on the outside of the eighth edge of the second base island area on the outside.

2. The three-phase full-bridge packaged chip according to claim 1, characterized in that: One of the first power crystals and one of the second power crystals constitute one arm of the three-phase full bridge; the first power crystal and the second power crystal each include a first pole, a second pole and a gate; The first electrode of the first power grain is connected to a power source, the gates of the first power grain and the second power grain are both connected to a control signal, the second electrode of the first power grain is connected to the first electrode of the second power grain, and the second electrode of the second power grain is grounded.

3. The three-phase full-bridge packaged chip according to claim 1, characterized in that: A first recessed area is disposed on a side of the first patterned structure away from the third edge; The three-phase full-bridge packaged chip also includes a first pad, which is disposed in the first recessed area, and a thickness of the first patterned structure is smaller than a thickness of the first pad.

4. The three-phase full-bridge packaged chip according to claim 3, characterized in that: A second recessed area is disposed on a side of the fifth patterned structure away from the fifth edge; The three-phase full-bridge packaged chip also includes a second pad and a third pad, the second pad and the third pad are arranged in the second recessed area, and the thickness of the fifth patterned structure is less than the thickness of the second pad and the third pad.

5. The three-phase full-bridge packaged chip according to claim 4, characterized in that: One of the first power crystals and one of the second power crystals constitute one arm of the three-phase full bridge; the first power crystal and the second power crystal each include a first pole, a second pole and a gate; The first electrode of the first power grain is connected to the first base island area, the gate of the first power grain is connected to the first pad, the second electrode of the first power grain is connected to the second base island area, the first electrode of the second power grain is connected to the second base island area, the second electrode of the second power grain is connected to the second pad, and the gate of the second power grain is connected to the third pad; the first base island area is connected to a power supply, the first pad and the third pad are connected to a control signal interface, and the second pad is grounded.

6. The three-phase full-bridge packaged chip according to claim 4, characterized in that: Also includes an encapsulation layer; The encapsulation layer encapsulates all parts of the substrate except the first base island region, the second base island region, the first pad, the second pad, and the third pad.

7. The three-phase full-bridge packaged chip according to claim 1, characterized in that: The substrate also includes a transition zone, which is located between the stretching zones, between the stretching zones and the first base island zone, and between the stretching zones and the second base island zone; the thickness of the substrate corresponding to the transition zone is less than the thickness of the substrate corresponding to the first base island zone, and the thickness of the substrate corresponding to the transition zone is less than the thickness of the substrate corresponding to the second base island zone.

8. The three-phase full-bridge packaged chip according to claim 1, characterized in that: The base is hollowed out in a region corresponding to the reinforcement region.

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