Flash memory chip module and encapsulation method thereof

Abstract

A flash memory chip module and a packaging method thereof. The flash memory chip module includes: a packaging carrier including a plurality of externally shared pins; a flash memory chip located on the packaging carrier, including a plurality of first shared pins and a plurality of first internal pins, the first shared pins being interconnected with the externally shared pins; and a response protection monotonic counter chip located on the packaging carrier, including a plurality of second internal pins, the second internal pins being interconnected with the first internal pins. Thereby, the design complexity and packaging difficulty of the flash memory chip module are reduced, the yield of the flash memory chip module is increased, and the power consumption of the flash memory chip module is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and particularly to a flash memory chip module and a packaging method for the flash memory chip module. Background Art

[0002] A Replay Protection Monotonic Counter (RPMC) refers to a counter with a monotonic counting function. That is, after data is counted in the Replay Protection Monotonic Counter, the Replay Protection Monotonic Counter will only monotonically increase or decrease as the count value changes.

[0003] In order to protect a flash memory (FLASH) chip and increase the confidentiality and integrity of data transmission of the flash memory chip, generally, a Replay Protection Monotonic Counter chip is combined with the flash memory chip to form a flash memory chip module. Thus, a protection mechanism can be generated for the flash memory chip by means of one-way counting of a one-way counter and combining data verification, to resist external attacks on the flash memory chip, such as a Replay Attack or a Probe Attack, etc.

[0004] However, the design complexity of the flash memory chip module is relatively high, the packaging difficulty is large, the yield is low, and the power consumption is relatively high. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a flash memory chip module and a packaging method for the flash memory chip module, so as to reduce the design complexity and packaging difficulty of the flash memory chip module, increase the yield of the flash memory chip module, and reduce the power consumption of the flash memory chip module.

[0006] To solve the above technical problem, the technical solution of the present invention provides a flash memory chip module, including: a packaging carrier, the packaging carrier includes a plurality of external shared pins, and the external shared pins are used to obtain a first external instruction; a flash memory chip located on the packaging carrier, the flash memory chip includes a plurality of first shared pins and a plurality of first internal pins, the first shared pins are interconnected with the external shared pins, the first shared pins are used to input the first external instruction into the flash memory chip, and the first internal pins are used to output a first instruction; a Replay Protection Monotonic Counter chip located on the packaging carrier, the Replay Protection Monotonic Counter chip includes a plurality of second internal pins, the second internal pins are interconnected with the first internal pins, and the second internal pins are used to input the first instruction into the Replay Protection Monotonic Counter chip and transmit a first message from the Replay Protection Monotonic Counter chip to the first internal pins.

[0007] Optionally, the flash memory chip further includes: a first receiving and judging module, configured to judge the first external instruction, and output the first instruction, or output a second instruction, or output the first instruction and the second instruction.

[0008] Optionally, the flash memory chip further includes: a first control module, configured to control the flash memory chip to execute the second instruction, and output a second message.

[0009] Optionally, the flash memory chip further includes: a first output judging module and a first sending module, the first output judging module is configured to judge the first message, and output the first message, the second message, or the first message and the second message to the first sending module, or turn off the first sending module.

[0010] Optionally, the first shared pin is interconnected with the first sending module, and the first shared pin is further configured to transmit the first message, the second message, or the first message and the second message to the external shared pin.

[0011] Optionally, the flash memory chip further includes: a first output judging module and a first sending module, the first output judging module is configured to judge the first message, and output the first message, the second message, the third message, the first message and the second message, or the first message and the third message to the first sending module, where the third message is encrypted data or random error data.

[0012] Optionally, the first shared pin is interconnected with the first sending module, and the first shared pin is further configured to transmit the first message, the second message, the third message, the first message and the second message, or the first message and the third message to the external shared pin.

[0013] Optionally, the packaging carrier further includes a plurality of external independent pins, configured to receive a second external instruction; the flash memory chip further includes: a plurality of first independent pins, the first independent pins are interconnected with the external independent pins, and the first independent pins are configured to input the second external instruction into the flash memory chip, and configured to transmit a fourth message from the flash memory chip to the external independent pins, where the fourth message is data obtained by the flash memory chip after processing the second external instruction.

[0014] Optionally, the external independent pin is further configured to receive a third external instruction; the response protection monotonic counter chip further includes: a plurality of second independent pins, the second independent pins are interconnected with the external independent pins, and the second independent pins are configured to input the third external instruction into the response protection monotonic counter chip, and are configured to transmit the fifth information from the response protection monotonic counter chip to the external independent pin, and the fifth information is data obtained after the response protection monotonic counter chip processes the third external instruction.

[0015] Optionally, the response protection monotonic counter chip further includes a second control module, and the second control module is configured to control the response protection monotonic counter chip to execute the first instruction and output the first information to the second internal pin.

[0016] Optionally, in a direction perpendicular to the surface of the encapsulation carrier, the flash memory chip and the response protection monotonic counter chip are arranged in an overlapping manner.

[0017] Optionally, the flash memory chip and the response protection monotonic counter chip are arranged along the direction of the surface of the encapsulation carrier.

[0018] Correspondingly, the technical solution of the present invention further provides a packaging method for the above flash memory chip module, including: providing an encapsulation carrier, the encapsulation carrier includes a plurality of external shared pins; providing a flash memory chip, the flash memory chip includes a plurality of first shared pins and a plurality of first internal pins; providing a response protection monotonic counter chip, the response protection monotonic counter chip includes a plurality of second internal pins; placing the flash memory chip and the response protection monotonic counter chip on the encapsulation carrier; interconnecting the first internal pins and the second internal pins; interconnecting the first shared pins and the external shared pins; after interconnecting the first shared pins and the external shared pins, and after interconnecting the first internal pins and the second internal pins, encapsulating the flash memory chip, the response protection monotonic counter chip and the encapsulation carrier.

[0019] Optionally, the method for interconnecting the first internal pin and the second internal pin includes: interconnecting the first internal pin and the second internal pin by using a metal lead.

[0020] Optionally, the method for interconnecting the first internal pin and the second internal pin includes: bonding the flash memory chip and the response protection monotonic counter chip before placing the flash memory chip and the response protection monotonic counter chip on the encapsulation carrier.

[0021] Optionally, the method for interconnecting the first shared pin and the external shared pin includes: interconnecting the first shared pin and the external shared pin by using a metal lead.

[0022] Optionally, the encapsulation carrier further includes a plurality of external independent pins, the flash memory chip further includes a plurality of first independent pins, and the encapsulation method further includes: before performing the plastic encapsulation, interconnecting the first independent pins and the external independent pins using metal leads.

[0023] Optionally, the response protection monotonic counter chip further includes a plurality of second independent pins, and the encapsulation method further includes: before performing the plastic encapsulation, interconnecting the second independent pins and the external independent pins using metal leads.

[0024] The technical solution of the present invention further provides a flash memory chip module, including: an encapsulation carrier, the encapsulation carrier includes a plurality of external shared pins, and the external shared pins are used to obtain a first external instruction; a response protection monotonic counter chip located on the encapsulation carrier, the response protection monotonic counter chip includes a plurality of second shared pins and a plurality of second internal pins, the second shared pins are interconnected with the external shared pins, the second shared pins are used to input the first external instruction into the response protection monotonic counter chip, and the second internal pins are used to output a second instruction; a flash memory chip located on the encapsulation carrier, the flash memory chip includes a plurality of first internal pins, the first internal pins are interconnected with the second internal pins, and the first internal pins are used to input the second instruction into the flash memory chip and transmit second information from the flash memory chip to the second internal pins.

[0025] Optionally, the response protection monotonic counter chip further includes: a second reception judgment module, and the second reception judgment module is used to judge the first external instruction and output the first instruction, or output the second instruction, or output the first instruction and the second instruction.

[0026] Optionally, the response protection monotonic counter chip further includes: a second control module, and the second control module is used to control the response protection monotonic counter chip to execute the first instruction and output first information.

[0027] Optionally, the response protection monotonic counter chip further includes: a second output judgment module and a second sending module, the second output judgment module is used to judge the first information and output the first information, the second information or the first information and the second information to the second sending module, or close the second sending module.

[0028] Optionally, the second shared pins are interconnected with the second sending module, and the second shared pins are further used to transmit the first information, the second information or the first information and the second information to the external shared pins.

[0029] Optionally, the response protection monotonic counter chip further includes: a second output determination module and a second transmission module. The second output determination module is configured to determine the first information and output the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the second transmission module, where the third information is encrypted data or random error data.

[0030] Optionally, the second shared pin is interconnected with the second transmission module, and the second shared pin is further configured to transmit the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external shared pin.

[0031] Optionally, the encapsulation carrier further includes a plurality of external independent pins, and the external independent pins are further configured to receive a third external instruction; the response protection monotonic counter chip further includes: a plurality of second independent pins, the second independent pins are interconnected with the external independent pins, and the second independent pins are configured to input the third external instruction into the response protection monotonic counter chip and transmit the fifth information from the response protection monotonic counter chip to the external independent pins, where the fifth information is data obtained by the response protection monotonic counter chip after processing the third external instruction.

[0032] Optionally, the external independent pins are configured to receive a second external instruction; the flash memory chip further includes: a plurality of first independent pins, the first independent pins are interconnected with the external independent pins, and the first independent pins are configured to input the second external instruction into the flash memory chip and transmit the fourth information from the flash memory chip to the external independent pins, where the fourth information is data obtained by the flash memory chip after processing the second external instruction.

[0033] Optionally, the flash memory chip further includes a first control module, and the first control module is configured to control the flash memory chip to execute the second instruction and output the second information to the first internal pin.

[0034] Optionally, in a direction perpendicular to the surface of the encapsulation carrier, the flash memory chip and the response protection monotonic counter chip are arranged overlappingly.

[0035] Optionally, the flash memory chip and the response protection monotonic counter chip are arranged along the surface direction of the encapsulation carrier.

[0036] Correspondingly, the technical solution of the present invention further provides a packaging method for the above flash chip module, including: providing a packaging carrier, the packaging carrier includes a plurality of external shared pins; providing a flash chip, the flash chip includes a plurality of first internal pins; providing a response protection monotonic counter chip, the response protection monotonic counter chip includes a plurality of second shared pins and a plurality of second internal pins; placing the flash chip and the response protection monotonic counter chip on the packaging carrier; interconnecting the first internal pins and the second internal pins; interconnecting the second shared pins and the external shared pins; after interconnecting the second shared pins and the external shared pins, and after interconnecting the first internal pins and the second internal pins, encapsulating the flash chip, the response protection monotonic counter chip and the packaging carrier.

[0037] Optionally, the method for interconnecting the first internal pins and the second internal pins includes: interconnecting the first internal pins and the second internal pins with metal leads.

[0038] Optionally, the method for interconnecting the first internal pins and the second internal pins includes: bonding the flash chip and the response protection monotonic counter chip before placing the flash chip and the response protection monotonic counter chip on the packaging carrier.

[0039] Optionally, the method for interconnecting the second shared pins and the external shared pins includes: interconnecting the second shared pins and the external shared pins with metal leads.

[0040] Optionally, the packaging carrier further includes a plurality of external independent pins, the flash chip further includes a plurality of first independent pins, and the packaging method further includes: before performing the encapsulation, interconnecting the first independent pins and the external independent pins with metal leads.

[0041] Optionally, the response protection monotonic counter chip further includes a plurality of second independent pins, and the packaging method further includes: before performing the encapsulation, interconnecting the second independent pins and the external independent pins with metal leads.

[0042] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0043] In the flash memory chip module provided by the technical solution of the present invention, since the first shared pin is used to input the first external instruction into the flash memory chip, the first internal pin is used to output the first instruction, and the second internal pin is used to input the first instruction into the response protection monotonic counter chip and transmit the first information from the response protection monotonic counter chip to the first internal pin. Therefore, on the one hand, the number of chips directly interconnected with the external shared pins for data transmission is reduced. Since the number of chips directly interconnected with the external shared pins for data transmission is reduced, not only the number of shared pins of the response protection monotonic counter chip is reduced, thus facilitating the simplification of the routing design complexity of the flash memory chip module, reducing the packaging difficulty, and increasing the yield of the flash memory chip module; and the load of the control instructions that the external shared pins need to drive is reduced, thus reducing the design requirements for the driving ability of the external shared pins and reducing the power consumption of the flash memory chip module. On the other hand, the control instructions from the outside and pointing to the response protection monotonic counter chip can be input into the response protection monotonic counter chip through the flash memory chip, and the situation of the response protection monotonic counter chip executing the instructions can be obtained through the flash memory chip, that is, the cooperation between the flash memory chip and the response protection monotonic counter chip can be realized through the flash memory chip. Since the cooperation between the flash memory chip and the response protection monotonic counter chip is realized through the flash memory chip, it is beneficial to simplify and reduce the judgment and monitoring required by the response protection monotonic counter chip. Thus, on the one hand, it is beneficial to reduce the design complexity of the control logic circuit of the response protection monotonic counter chip and reduce the power consumption of the flash memory chip module. On the other hand, it can also reduce the number of internal pins for data transmission between the flash memory chip and the response protection monotonic counter chip, that is, the number of the first internal pin and the second internal pin, so as to facilitate the simplification of the routing design complexity of the flash memory chip module, reduce the packaging difficulty, and increase the yield of the flash memory chip module.

[0044] Furthermore, since the packaging carrier further includes several external independent pins for receiving the second external instruction; the flash memory chip further includes: several first independent pins, and the first independent pins are interconnected with the external independent pins. Therefore, through the external independent pins and the first independent pins, the flexibility of the path for the flash memory chip to receive the instructions independently pointing to the flash memory chip and transmit the data obtained after the flash memory chip independently executes the instructions to the outside is increased.

[0045] In the flash memory chip module provided by the technical solution of the present invention, since the second shared pin is used to input the first external instruction into the response protection monotonic counter chip, the second internal pin is used to output a second instruction, and the first internal pin is used to input the second instruction into the flash memory chip and transfer the second information from the flash memory chip to the second internal pin. Therefore, on the one hand, the number of chips directly interconnected with the external shared pin to generate data transmission is reduced. Since the number of chips directly interconnected with the external shared pin to generate data transmission is reduced, not only the number of shared pins of the flash memory chip is reduced, thus facilitating the simplification of the routing design complexity of the flash memory chip module, reducing the packaging difficulty, and increasing the yield of the flash memory chip module. Also, the load of the control instructions that the external shared pin needs to drive is reduced, thus reducing the design requirements for the driving ability of the external shared pin and reducing the power consumption of the flash memory chip module. On the other hand, the control instructions from the outside and directed to the flash memory chip can be input into the flash memory chip through the response protection monotonic counter chip, and the situation of the flash memory chip executing the instructions can be obtained through the response protection monotonic counter chip, that is, through the response protection monotonic counter chip, the cooperation between the control flash memory chip and the response protection monotonic counter chip is realized. Since the cooperation between the response protection monotonic counter chip and the flash memory chip is realized through the response protection monotonic counter chip, it is not only beneficial to simplify and reduce the judgment and monitoring required by the flash memory chip. Thus, on the one hand, it is beneficial to reduce the design complexity of the control logic circuit of the flash memory chip and reduce the power consumption of the flash memory chip module. On the other hand, it can also reduce the number of internal pins for data transmission between the flash memory chip and the response protection monotonic counter chip, that is, the number of the first internal pin and the second internal pin, so as to facilitate the simplification of the routing design complexity of the flash memory chip module, reduce the packaging difficulty, and increase the yield of the flash memory chip module. At the same time, it is also beneficial to reduce the number of contacts between the flash memory chip and the external instructions, reduce the risk of the flash memory chip being attacked when parsing the external instructions, thus increasing the data security of the flash memory chip and improving the confidentiality and integrity of the data transmission of the flash memory chip module.

[0046] Furthermore, since the packaging carrier further includes a plurality of external independent pins, and the external independent pins are further used to receive a third external instruction; the response protection monotonic counter chip further includes: a plurality of second independent pins, and the second independent pins are interconnected with the external independent pins. Therefore, through the external independent pins and the second independent pins, the flexibility of the path for the response protection monotonic counter chip to receive the instructions independently directed to the response protection monotonic counter chip and the data obtained after the response protection monotonic counter chip independently executes the instructions and transmits them to the outside is increased. Description of the Drawings

[0047] Figure 1It is a schematic connection diagram of a flash memory chip module;

[0048] Figure 2 It is a schematic logical connection diagram of the flash memory chip module according to an embodiment of the present invention;

[0049] Figure 3 It is a schematic diagram of the packaging principle structure of the flash memory chip module according to an embodiment of the present invention;

[0050] Figure 4 It is a schematic logical connection diagram of the flash memory chip module according to another embodiment of the present invention;

[0051] Figure 5 It is a schematic diagram of the packaging principle structure of the flash memory chip module according to another embodiment of the present invention. Detailed implementation manners

[0052] As described in the background art, the design complexity of the flash memory chip module is relatively high, the packaging difficulty is relatively large, the yield is low, and the power consumption is relatively high. The following will analyze and explain in combination with specific embodiments.

[0053] Figure 1 It is a schematic connection diagram of a flash memory chip module.

[0054] Please refer to Figure 1 , the flash memory chip module includes: a flash memory chip 110, the flash memory chip 110 includes a plurality of flash memory chip shared IO pins (such as Figure 1 IO_x_1, IO_x_2,..., IO_x_n in), a plurality of flash memory chip internal IO pins (such as Figure 1 IO_a_1, IO_a_2,..., IO_a_n in) and a flash memory chip controller (not shown); a response protection monotonic counter chip 120, the response protection monotonic counter chip 120 includes: a plurality of response protection monotonic counter chip shared IO pins (such as Figure 1 IO_y_1, IO_y_2,..., IO_y_n in), a plurality of response protection monotonic counter chip internal IO pins (such as Figure 1 IO_b_1, IO_b_2,..., IO_b_n in) and a response protection monotonic counter chip controller (not shown); a plurality of external shared IO pins (such as Figure 1 IO_1, IO_2,..., IO_n in).

[0055] The flash memory chip 110 and the response protection monotonic counter chip 120 are independent of each other.

[0056] The flash memory chip controller is used to receive an external instruction, judge whether the flash memory chip needs to execute the external instruction, and when it is judged that the flash memory chip needs to execute the external instruction, control the flash memory chip to execute the external instruction.

[0057] The response protection monotonic counter chip controller is used to receive external instructions, determine whether the response protection monotonic counter chip needs to execute the external instructions, and when it is determined that the response protection monotonic counter chip needs to execute the external instructions, control the response protection monotonic counter chip to execute the external instructions.

[0058] Metal leads are used to interconnect the shared IO pins of the corresponding flash memory chip, the shared IO pins of the response protection monotonic counter chip, and the same external shared IO pin. Thus, through the external shared IO pin, the shared IO pins of the flash memory chip, and the shared IO pins of the response protection monotonic counter chip, the external instructions are simultaneously transmitted to the flash memory chip controller and the response protection monotonic counter chip controller.

[0059] For example, interconnect the shared IO pin IO_x_1 of the flash memory chip, the shared IO pin IO_y_1 of the response protection monotonic counter chip, and the external shared IO pin IO_1; interconnect the shared IO pin IO_x_2 of the flash memory chip, the shared IO pin IO_y_2 of the response protection monotonic counter chip, and the external shared IO pin IO_2; interconnect the shared IO pin IO_x_n of the flash memory chip, the shared IO pin IO_y_n of the response protection monotonic counter chip, and the external shared IO pin IO_n, etc.

[0060] Metal leads are used to interconnect the internal IO pins of the corresponding flash memory chip and the internal IO pins of the response protection monotonic counter chip. Thus, through the paired internal IO pins of the flash memory chip and the internal IO pins of the response protection monotonic counter chip, the flash memory chip and the response protection monotonic counter chip can obtain each other's current state or the execution state of the external instructions.

[0061] For example, interconnect the internal IO pin IO_a_1 of the flash memory chip and the internal IO pin IO_b_1 of the response protection monotonic counter chip; interconnect the internal IO pin IO_a_2 of the flash memory chip and the internal IO pin IO_b_2 of the response protection monotonic counter chip; interconnect the internal IO pin IO_a_n of the flash memory chip and the internal IO pin IO_b_n of the response protection monotonic counter chip, etc.

[0062] In the above flash memory chip module, since both the flash memory chip and the response protection monotonic counter chip are independent chips, it is possible to use the flash memory chip and the response protection monotonic counter chip together to protect the flash memory chip, while facilitating the reduction of the area of a single chip, the reduction of the package area, the simplification of the design complexity of the flash memory chip module, and the improvement of the design flexibility of the flash memory chip module.

[0063] However, in the above embodiments, on the one hand, in order to use the flash memory chip and the response protection monotonic counter chip in combination, the flash memory chip needs to have flash memory chip shared IO pins, and the response protection monotonic counter chip needs to have response protection monotonic counter chip shared IO pins, so that the flash memory chip controller and the response protection monotonic counter chip controller can respectively obtain external instructions. Therefore, the number of shared IO pins of the flash memory chip module is relatively large. As a result, the routing complexity during the packaging of the flash memory chip module is increased, the difficulty of packaging the flash memory chip module is increased, and the yield of the flash memory chip module is reduced. On the other hand, since the external shared IO pins need to drive the loads of the control instructions of both the flash memory chip and the response protection monotonic counter chip at the same time, the design driving ability requirement of the external shared IO pins is relatively high, resulting in a relatively high power consumption of the flash memory chip module. In addition, since the flash memory chip controller and the response protection monotonic counter chip controller respectively judge and execute external instructions for their respective chips, the power consumption of the flash memory chip module is relatively large. On this basis, in order to use the flash memory chip and the response protection monotonic counter chip in combination, both the flash memory chip controller and the response protection monotonic counter chip controller need to obtain the current state of the other party or the execution state of the external instruction. Therefore, not only will the control logic circuit design of the flash memory chip and the response protection monotonic counter chip become more complex, but at the same time, the number of internal IO pins of the flash memory chip and the number of internal IO pins of the response protection monotonic counter chip will also be relatively large. As a result, it is not conducive to simplifying the design complexity of the flash memory chip module, and at the same time, it further increases the routing complexity during the packaging of the flash memory chip module, increases the difficulty of packaging the flash memory chip module, and reduces the yield of the flash memory chip module.

[0064] In summary, in the above embodiments, the flash memory chip module has a relatively high design complexity, a relatively large packaging difficulty, a low yield, and a relatively high power consumption.

[0065] To solve the above technical problems, an embodiment of the present invention provides a flash memory chip module and a packaging method for the flash memory chip module. The flash memory chip in the flash memory chip module includes a plurality of first shared pins, or the response protection monotonic counter chip in the memory chip module includes a plurality of second shared pins. Moreover, the flash memory chip includes a plurality of first internal pins, the response protection monotonic counter chip includes a plurality of second internal pins, and the second internal pins are interconnected with the first internal pins to reduce the design complexity and packaging difficulty of the flash memory chip module, increase the yield of the flash memory chip module, and reduce the power consumption of the flash memory chip module.

[0066] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description will be given to the specific embodiments of the present invention with reference to the accompanying drawings.

[0067] Figure 2It is a schematic diagram of the logical connection of the flash memory chip module according to an embodiment of the present invention. Figure 3 It is a schematic diagram of the encapsulation principle structure of the flash memory chip module according to an embodiment of the present invention.

[0068] Please refer to Figure 2 and Figure 3 The flash memory chip module includes: a packaging carrier 200, and the packaging carrier 200 includes a plurality of external shared pins (such as Figure 2 IO_W_1, IO_W_2,..., IO_W_n in ), and the external shared pins are used to obtain a first external instruction.

[0069] Please continue to refer to Figure 2 and Figure 3 The flash memory chip module further includes: a flash memory chip 210 located on the packaging carrier 200, and a response protection monotonic counter chip 220 located on the packaging carrier 200.

[0070] The flash memory chip 210 includes: a plurality of first shared pins (such as Figure 2 IO_A_1, IO_A_2,..., IO_A_n in ).

[0071] The first shared pins are interconnected with the external shared pins, and the first shared pins are used to input the first external instruction into the flash memory chip 210.

[0072] In this embodiment, metal leads 231 are used to interconnect the corresponding first shared pins and external shared pins.

[0073] For example, interconnect the first shared pin IO_A_1 with the external shared pin IO_W_1; interconnect the first shared pin IO_A_2 with the external shared pin IO_W_2; interconnect the first shared pin IO_A_n with the external shared pin IO_W_n, etc.

[0074] Thus, the first shared pins can obtain the first external instruction, and the first external instruction can be input into the flash memory chip 210 through the first shared pins.

[0075] In this embodiment, the flash memory chip 210 further includes: a first receiving and judging module 211, and the first receiving and judging module 211 is used to judge the first external instruction and output the first instruction, or output a second instruction, or output the first instruction and the second instruction.

[0076] It should be noted that the first external instruction includes at least one of an instruction pointing to the flash memory chip 210 and an instruction pointing to the response protection monotonic counter chip 220. The first instruction is an instruction formed according to the instruction pointing to the response protection monotonic counter chip 220, and the second instruction is an instruction formed according to the instruction pointing to the flash memory chip 210.

[0077] Specifically, after the first external instruction is input into the flash memory chip 210 through the first shared pin, the first receiving and judging module 211 judges the first external instruction: when the first external instruction only includes an instruction pointing to the response protection monotonic counter chip 220, the first receiving and judging module 211 outputs the first instruction; when the first external instruction only includes an instruction pointing to the flash memory chip 210, the first receiving and judging module 211 outputs the second instruction; when the first external instruction includes both an instruction pointing to the flash memory chip 210 and an instruction pointing to the response protection monotonic counter chip 220, the first receiving and judging module 211 outputs the first instruction and the second instruction.

[0078] In this embodiment, the flash memory chip 210 further includes: a first control module 212, and the first control module 212 is used to control the flash memory chip 210 to execute the second instruction and output second information.

[0079] It should be noted that the second information is the data obtained after the flash memory chip 210 executes the second instruction.

[0080] Specifically, in this embodiment, when the first external instruction includes an instruction pointing to the flash memory chip 210, the first control module 212 obtains the second instruction through the first receiving and judging module 211, and controls the flash memory chip 210 to execute the second instruction and output the second information.

[0081] The flash memory chip 210 further includes: a plurality of first internal pins (such as Figure 2 IO_C_1, IO_C_2,..., IO_C_n), and the first internal pins are used to output the first instruction.

[0082] Specifically, in this embodiment, after the first internal pin obtains the first instruction from the first receiving and judging module 211, it outputs the first instruction to the response protection monotonic counter chip 220.

[0083] The response protection monotonic counter chip 220 includes: a plurality of second internal pins (such as Figure 2Among IO_D_1, IO_D_2, ……, IO_D_n), the second internal pin is interconnected with the first internal pin. The second internal pin is used to input the first instruction into the response protection monotonic counter chip 220 and transmit the first information from the response protection monotonic counter chip 220 to the first internal pin.

[0084] Since the second internal pin is interconnected with the first internal pin, the second internal pin can obtain the first instruction and transmit the first information to the first internal pin. That is, the first instruction is input into the response protection monotonic counter chip 220 through the second internal pin, and the first information is transmitted from the response protection monotonic counter chip 220 to the first internal pin.

[0085] It should be noted that the first information is the data obtained by the response protection monotonic counter chip 220 when executing the first instruction. This data may include the execution status of the response protection monotonic counter chip 220 and the data that needs to be transmitted to the outside after the response protection monotonic counter chip 220 executes the first instruction, etc.

[0086] Since the first shared pin is used to input the first external instruction into the flash chip 210, the first internal pin is used to output the first instruction, and the second internal pin is used to input the first instruction into the response protection monotonic counter chip 220 and transmit the first information from the response protection monotonic counter chip 220 to the first internal pin. Therefore, on the one hand, the number of chips directly interconnected with the external shared pin and generating data transmission is reduced. Since the number of chips directly interconnected with the external shared pin and generating data transmission is reduced, not only the number of shared pins of the response protection monotonic counter chip 220 is reduced, thus facilitating the simplification of the routing design complexity of the flash chip module, reducing the packaging difficulty, and increasing the yield of the flash chip module; moreover, the load of the control instructions that the external shared pin needs to drive is reduced, thus reducing the design requirements for the driving ability of the external shared pin and reducing the power consumption of the flash chip module.

[0087] In a second aspect, the control instructions from the outside and directed to the response protection monotonic counter chip 220 can be input into the response protection monotonic counter chip 220 through the flash memory chip 210, and the situation of the response protection monotonic counter chip 220 executing the instructions can be obtained through the flash memory chip 210. That is, through the flash memory chip 210, the coordinated use of the flash memory chip 210 and the response protection monotonic counter chip 220 is realized. Since the coordinated use of the flash memory chip 210 and the response protection monotonic counter chip 220 is realized through the flash memory chip 210, it is beneficial to simplify and reduce the judgment and monitoring that the response protection monotonic counter chip 220 needs to perform. Thus, on the one hand, it is beneficial to reduce the design complexity of the control logic circuit of the response protection monotonic counter chip 220 and reduce the power consumption of the flash memory chip module. On the other hand, it can also reduce the number of internal pins for data transmission between the flash memory chip 210 and the response protection monotonic counter chip 220, that is, the number of the first internal pin and the second internal pin, so as to facilitate simplifying the routing design complexity of the flash memory chip module, reducing the packaging difficulty, and increasing the yield of the flash memory chip module.

[0088] In this embodiment, the corresponding first internal pin and the second internal pin are interconnected by the metal lead 232.

[0089] For example, the first internal pin IO_C_1 is interconnected with the second internal pin IO_D_1; the first internal pin IO_C_2 is interconnected with the second internal pin IO_D_2; the first internal pin IO_C_n is interconnected with the second internal pin IO_D_n, etc.

[0090] In other embodiments, the flash memory chip 210 and the response protection monotonic counter chip 220 are bonded to realize the interconnection of the first internal pin and the second internal pin.

[0091] In this embodiment, the response protection monotonic counter chip 220 further includes a second control module 221, and the second control module 221 is used to control the response protection monotonic counter chip 220 to execute the first instruction and output the first information to the second internal pin.

[0092] Specifically, in this embodiment, when the first external instruction contains an instruction directed to the response protection monotonic counter chip 220, the second control module 221 obtains the first instruction through the second internal pin, and controls the response protection monotonic counter chip 220 to execute the first instruction and outputs the first information to the second internal pin.

[0093] In this embodiment, the flash memory chip 210 further includes: a first output judgment module 213 and a first transmission module 214. The first output judgment module 213 is configured to judge the first information and output the first information, the second information, or the first information and the second information to the first transmission module 214, or turn off the first transmission module 214.

[0094] In this embodiment, the first shared pin is interconnected with the first transmission module 214, and the first shared pin is further configured to transmit the first information, the second information, or the first information and the second information to the external shared pin.

[0095] Specifically, in this embodiment, after obtaining the first information, the first output judgment module 213 judges the first information: to determine whether the first information includes information that needs to be transmitted externally. When the first information includes information that needs to be transmitted externally, the first output judgment module 213 outputs the first information to the first transmission module 214. And it determines whether the flash memory chip 210 is attacked, that is, whether the current state of the flash memory chip 210 is secure. When the current state of the flash memory chip 210 is secure, the first output judgment module 213 outputs the second information to the first transmission module 214; when the current state of the flash memory chip 210 is not secure, the first transmission module 214 is turned off. After obtaining the first information, the second information, or the first information and the second information, the first transmission module 241 transmits the first information, the second information, or the first information and the second information to the outside through the first shared pin and the external shared pin.

[0096] Thus, on the one hand, the state of the flash memory chip module can be obtained, and on the other hand, a protection mechanism can be generated for the flash memory chip 210 to resist external attacks on the flash memory chip 210, increasing the confidentiality and integrity of data transmission of the flash memory chip 210.

[0097] In other embodiments, the first output judgment module is configured to judge the first information and output the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the first transmission module, and the third information is encrypted data or random error data. The first shared pin is interconnected with the first transmission module, and the first shared pin is further configured to transmit the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external shared pin.

[0098] Specifically, in other embodiments, after obtaining the first information, the first output determination module determines the first information: to determine whether the first information includes information that needs to be transmitted externally. When the first information includes information that needs to be transmitted externally, the first information is output to the first sending module. Further, it is determined whether the flash memory chip is attacked, that is, whether the current state of the flash memory chip is secure. When the current state of the flash memory chip is secure, the second information is output to the first sending module; when the current state of the flash memory chip is not secure, the third information is output to the first sending module. After obtaining the first information, the second information, the third information, the first information and the second information, or the first information and the third information, the first sending module transmits the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the outside through the first shared pin and the external shared pin.

[0099] It should be noted that the third information being encrypted data means that the third information is data obtained by encrypting the second information. The third information being random error data means that the third information is random error data obtained by error injection for misleading attackers.

[0100] In this embodiment, the encapsulation carrier 200 further includes a plurality of external independent pins (such as Figure 2 IO_V_1, IO_V_2,..., IO_V_n in), and the external independent pins are used to receive a second external instruction.

[0101] It should be noted that the second external instruction is a control instruction for the flash memory chip 210, and this control instruction is an instruction that the flash memory chip 210 independently executes to implement the functions of the flash memory chip 210.

[0102] In this embodiment, the flash memory chip 210 further includes: a plurality of first independent pins (such as Figure 2 IO_E_1, IO_E_2,..., IO_E_n in), and the first independent pins are interconnected with the external independent pins.

[0103] In this embodiment, metal leads 233 are used to interconnect the corresponding first independent pins and external independent pins.

[0104] For example, the first independent pin IO_E_1 is interconnected with the external independent pin IO_V_1; the first independent pin IO_E_2 is interconnected with the external independent pin IO_V_2; the first independent pin IO_E_n is interconnected with the external independent pin IO_V_n, etc.

[0105] The first independent pin is used to input the second external instruction into the flash memory chip 210 and to transfer the fourth information from the flash memory chip to the external independent pin, where the fourth information is the data obtained by the flash memory chip after processing the second external instruction.

[0106] Specifically, in this embodiment, the external independent pin receives the second external instruction, the first independent pin obtains the second external instruction from the external independent pin, and inputs the second external instruction into the flash memory chip 210; after the flash memory chip 210 executes the second external instruction, it obtains the fourth information, and the first independent pin transfers the fourth information to the external independent pin.

[0107] Thus, for the external instruction that does not require the flash memory chip 210 to cooperate with the response protection monotonic counter chip 220, it can be input into the flash memory chip 210 not only through the external shared pin and the first shared pin, but also through the external independent pin and the first independent pin. And when the flash memory chip 210 executes this external instruction to obtain data, it can output this data to the outside not only through the external shared pin and the first shared pin, but also through the external independent pin and the first independent pin. Furthermore, on the one hand, the flexibility of the path for the flash memory chip 210 to receive instructions independently directed to the flash memory chip 210 is increased, and on the other hand, the flexibility of the path for the data obtained after the flash memory chip 210 independently executes the instruction to be transmitted to the outside is increased.

[0108] In other embodiments, the flash memory chip does not include a first independent pin.

[0109] In other embodiments, the package carrier does not include an external independent pin.

[0110] In other embodiments, the external independent pin is further used to receive a third external instruction. The response protection monotonic counter chip further includes: a plurality of second independent pins, and the second independent pins are interconnected with the external independent pin. The second independent pin is used to input the third external instruction into the response protection monotonic counter chip and to transfer the fifth information from the response protection monotonic counter chip to the external independent pin, where the fifth information is the data obtained by the response protection monotonic counter chip after processing the third external instruction.

[0111] In other embodiments, the second independent pin and the external independent pin are interconnected by a metal lead.

[0112] It should be noted that the third external instruction is a control instruction pointing to the response protection monotonic counter chip, and this control instruction is an instruction independently executed by the response protection monotonic counter chip to implement the functions of the response protection monotonic counter chip.

[0113] Specifically, in other embodiments, the external independent pin receives the third external instruction, the second independent pin obtains the third external instruction from the external independent pin, and inputs the third external instruction into the flash memory chip; after the flash memory chip executes the third external instruction, it obtains the fifth information, and the second independent pin transmits the fifth information to the external independent pin.

[0114] Thus, there is no need for an external instruction that needs to be executed in cooperation between the flash memory chip and the response protection monotonic counter chip. It can not only be input into the flash memory chip through the external shared pin and the first shared pin and then input into the response protection monotonic counter chip, but also be directly input into the response protection monotonic counter chip through the external independent pin and the second independent pin. And when the response protection monotonic counter chip executes this external instruction to obtain data, it can not only output this data to the outside through the second internal pin, the first internal pin, the first shared pin and the external shared pin, but also directly output this data to the outside through the external independent pin and the second independent pin. Furthermore, on the one hand, it increases the flexibility of the path for the response protection monotonic counter chip to receive instructions independently pointing to the response protection monotonic counter chip, and on the other hand, it increases the flexibility of the path for the data obtained after the response protection monotonic counter chip independently executes the instruction to be transmitted to the outside.

[0115] In yet another embodiment, the response protection monotonic counter chip does not include a second independent pin.

[0116] In this embodiment, in the direction perpendicular to the surface of the package carrier 200, the flash memory chip 210 and the response protection monotonic counter chip 220 are arranged overlappingly.

[0117] Thus, the area occupied by the flash memory chip module is saved.

[0118] In this embodiment, when the area of the flash memory chip 210 is smaller than the area of the response protection monotonic counter chip 220, the flash memory chip 210 is located on the response protection monotonic counter chip 220; when the area of the flash memory chip 210 is larger than the area of the response protection monotonic counter chip 220, the response protection monotonic counter chip 220 is located on the flash memory chip 210.

[0119] It should be noted that Figure 3Only schematically shows the situation where the response protection monotonic counter chip 220 is located on the flash memory chip 210 when the area of the flash memory chip 210 is larger than the area of the response protection monotonic counter chip 220.

[0120] In other embodiments, when the area of the flash memory chip is larger than the area of the response protection monotonic counter chip, the flash memory chip is located on the response protection monotonic counter chip; when the area of the flash memory chip is smaller than the area of the response protection monotonic counter chip, the response protection monotonic counter chip is located on the flash memory chip.

[0121] In yet another embodiment, in a direction perpendicular to the surface of the package carrier, the flash memory chip and the response protection monotonic counter chip are arranged overlappingly.

[0122] Correspondingly, an embodiment of the present invention provides a packaging method for packaging the above-mentioned flash memory chip module.

[0123] Please continue to refer to Figure 3 , the packaging method of the flash memory chip module includes: providing a package carrier 200, the package carrier 200 includes a plurality of external shared pins (such as Figure 3 IO_A_1, IO_A_2,..., IO_A_n in Figure 3 ); providing a flash memory chip 210, the flash memory chip 210 includes a plurality of first shared pins (such as Figure 3 IO_A_1, IO_A_2,..., IO_A_n in Figure 3 ), and a plurality of first internal pins (such as

[0124] IO_C_1, IO_C_2,..., IO_C_n in

[0125] ); providing a response protection monotonic counter chip 220, the response protection monotonic counter chip 220 includes a plurality of second internal pins (such as Figure 3 IO_D_1, IO_D_2,..., IO_D_n in

[0124] ); placing the flash memory chip 210 and the response protection monotonic counter chip 220 on the package carrier 200; interconnecting the first internal pins and the second internal pins; interconnecting the first shared pins and the external shared pins; after interconnecting the first shared pins and the external shared pins, and after interconnecting the first internal pins and the second internal pins, encapsulating the flash memory chip 210, the response protection monotonic counter chip 220, and the package carrierFor example, interconnect the first internal pin IO_C_1 with the second internal pin IO_D_1; interconnect the first internal pin IO_C_2 with the second internal pin IO_D_2; interconnect the first internal pin IO_C_n with the second internal pin IO_D_n, etc.

[0126] In this embodiment, the method for interconnecting the first shared pin and the external shared pin includes: using a metal lead 231 to interconnect the first shared pin and the external shared pin.

[0127] For example, interconnect the first shared pin IO_A_1 with the external shared pin IO_W_1; interconnect the first shared pin IO_A_2 with the external shared pin IO_W_2; interconnect the first shared pin IO_A_n with the external shared pin IO_W_n, etc.

[0128] In other embodiments, the method for interconnecting the first internal pin and the second internal pin includes: bonding the flash memory chip and the response protection monotonic counter chip before placing the flash memory chip and the response protection monotonic counter chip on the package carrier.

[0129] In this embodiment, the package carrier 200 further includes a plurality of external independent pins (such as Figure 3 IO_V_1, IO_V_2,..., IO_V_n in Figure 3 ), the flash memory chip 210 further includes a plurality of first independent pins (such as

[0130] IO_E_1, IO_E_2,..., IO_E_n in

[0131] ), and the packaging method further includes: before performing the plastic encapsulation, using a metal lead 233 to interconnect the first independent pins and the external independent pins.

[0132] In other embodiments, the flash memory chip does not include first independent pins.

[0133] In other embodiments, the response protection monotonic counter chip further includes: a plurality of second independent pins. The packaging method further includes: before performing the plastic encapsulation, using a metal lead to interconnect the second independent pins and the external independent pins.

[0134] Figure 4It is a schematic diagram of the logical connection of a flash memory chip module according to another embodiment of the present invention; Figure 5 It is a schematic diagram of the encapsulation principle structure of a flash memory chip module according to another embodiment of the present invention.

[0135] Please refer to Figure 4 and Figure 5 The flash memory chip module includes: a packaging carrier 300, and the packaging carrier 300 includes a plurality of external shared pins (such as Figure 4 IO_Q_1, IO_Q_2,..., IO_Q_n in ), and the external shared pins are used to obtain a first external instruction.

[0136] Please continue to refer to Figure 4 and Figure 5 The flash memory chip module further includes: a flash memory chip 310 located on the packaging carrier 300, and a response protection monotonic counter chip 320 located on the packaging carrier 300.

[0137] The response protection monotonic counter chip 320 includes: a plurality of second shared pins (such as Figure 4 IO_B_1, IO_B_2,..., IO_B_n in ).

[0138] The second shared pins are interconnected with the external shared pins, and the second shared pins are used to input the first external instruction into the response protection monotonic counter chip 320.

[0139] In this embodiment, metal leads 331 are used to interconnect the corresponding second shared pins and external shared pins.

[0140] For example, the second shared pin IO_B_1 is interconnected with the external shared pin IO_Q_1; the second shared pin IO_B_2 is interconnected with the external shared pin IO_Q_2; the second shared pin IO_B_n is interconnected with the external shared pin IO_Q_n, etc.

[0141] Thus, the second shared pins can obtain the first external instruction, and the first external instruction can be input into the response protection monotonic counter chip 320 through the second shared pins.

[0142] In this embodiment, the response protection monotonic counter chip 320 further includes: a second receiving and judging module 32\alpha, and the second receiving and judging module 32\alpha is used to judge the first external instruction and output the first instruction, or output a second instruction, or output the first instruction and the second instruction.

[0143] It should be noted that the first external instruction includes at least one of an instruction pointing to the flash memory chip 310 and an instruction pointing to the response protection monotonic counter chip 320. The first instruction is an instruction formed according to the instruction pointing to the response protection monotonic counter chip 320, and the second instruction is an instruction formed according to the instruction pointing to the flash memory chip 310.

[0144] Specifically, after the first external instruction is input into the response protection monotonic counter chip 320 through the second shared pin, the second receiving and judging module 321 judges the first external instruction: when the first external instruction only includes an instruction pointing to the response protection monotonic counter chip 320, the second receiving and judging module 321 outputs the first instruction; when the first external instruction only includes an instruction pointing to the flash memory chip 310, the second receiving and judging module 321 outputs the second instruction; when the first external instruction includes both an instruction pointing to the flash memory chip 310 and an instruction pointing to the response protection monotonic counter chip 320, the second receiving and judging module 321 outputs the first instruction and the second instruction.

[0145] In this embodiment, the response protection monotonic counter chip 320 further includes a second control module 322, and the second control module 322 is used to control the response protection monotonic counter chip 320 to execute the first instruction and output first information.

[0146] It should be noted that the first information is data obtained by the response protection monotonic counter chip 320 executing the first instruction, and this data may include the execution state of the response protection monotonic counter chip 320, and data that needs to be transmitted to the outside after the response protection monotonic counter chip 320 executes the first instruction, etc.

[0147] Specifically, in this embodiment, when the first external instruction includes an instruction pointing to the response protection monotonic counter chip 320, the second control module 322 obtains the first instruction through the second receiving and judging module 321, and controls the response protection monotonic counter chip 320 to execute the first instruction and output the first information.

[0148] The response protection monotonic counter chip 320 further includes a plurality of second internal pins (such as Figure 4 IO_P_1, IO_P_2,..., IO_P_n in), and the second internal pins are used to output the second instruction.

[0149] Specifically, in this embodiment, after the second internal pin obtains the second instruction from the second receiving and judging module 321, it outputs the second instruction to the flash chip 310.

[0150] The flash chip 310 further includes: a plurality of first internal pins (such as Figure 4 IO_R_1, IO_R_2,..., IO_R_n in), the first internal pins are interconnected with the second internal pins, and the first internal pins are used to input the second instruction into the flash chip 310 and transmit the second information from the flash chip 310 to the second internal pins.

[0151] Since the first internal pins are interconnected with the second internal pins, the first internal pins can obtain the second instruction and transmit the second information to the second internal pins, that is, the second instruction is input into the flash chip 310 through the first internal pins, and the second information is transmitted from the flash chip 310 to the second internal pins.

[0152] It should be noted that the second information is the data obtained after the flash chip 310 executes the second instruction.

[0153] Since the second shared pin is used to input the first external instruction into the response protection monotonic counter chip 320, the second internal pin is used to output the second instruction, and the first internal pin is used to input the second instruction into the flash chip 310 and transmit the second information from the flash chip 310 to the second internal pin, therefore, on the one hand, the number of chips directly interconnected with the external shared pin and generating data transmission is reduced. Since the number of chips directly interconnected with the external shared pin and generating data transmission is reduced, not only the number of shared pins of the flash chip 310 is reduced, thus facilitating the simplification of the routing design complexity of the flash chip module, reducing the packaging difficulty, and increasing the yield of the flash chip module; and the load of the control instructions that the external shared pin needs to drive is reduced, thus reducing the design requirement for the driving ability of the external shared pin and reducing the power consumption of the flash chip module.

[0154] In a second aspect, the monotonic counter chip 320 can protect the flash memory chip 310 by means of an acknowledgement, input a control instruction from the outside and directed to the flash memory chip 310 into the flash memory chip 310, and can obtain the situation of the flash memory chip 310 executing the instruction by means of the acknowledgement of the monotonic counter chip 320. That is, by means of the monotonic counter chip 320 that protects by means of an acknowledgement, the cooperation of controlling the flash memory chip 310 and the monotonic counter chip 320 that protects by means of an acknowledgement is realized. Since the cooperation of controlling the monotonic counter chip 320 that protects by means of an acknowledgement and the flash memory chip 310 is realized by means of the monotonic counter chip 320 that protects by means of an acknowledgement, it is not only beneficial to simplify and reduce the judgments and monitoring that the flash memory chip 310 needs to perform. Thus, on the one hand, it is beneficial to reduce the design complexity of the control logic circuit of the flash memory chip 310 and reduce the power consumption of the flash memory chip module. On the other hand, it is also possible to reduce the number of internal pins for data transmission between the flash memory chip 310 and the monotonic counter chip 320 that protects by means of an acknowledgement, that is, the number of the first internal pin and the second internal pin, so as to facilitate simplifying the routing design complexity of the flash memory chip module, reducing the packaging difficulty, and increasing the yield of the flash memory chip module. At the same time, it is also beneficial to reduce the number of contacts between the flash memory chip 310 and external instructions, reduce the risk of the flash memory chip 310 being attacked when parsing external instructions, and thus increase the data security of the flash memory chip 310 and improve the confidentiality and integrity of data transmission of the flash memory chip module.

[0155] In this embodiment, corresponding first internal pins and second internal pins are interconnected by a metal lead 332.

[0156] For example, the first internal pin IO_R_1 is interconnected with the second internal pin IO_P_1; the first internal pin IO_R_2 is interconnected with the second internal pin IO_P_2; the first internal pin IO_R_n is interconnected with the second internal pin IO_P_n, etc.

[0157] In other embodiments, the flash memory chip 310 and the monotonic counter chip 320 that protects by means of an acknowledgement are bonded to realize the interconnection of the first internal pin and the second internal pin.

[0158] In this embodiment, the flash memory chip 310 further includes a first control module 311, and the first control module 311 is configured to control the flash memory chip 310 to execute the second instruction and output the second information to the first internal pin.

[0159] Specifically, in this embodiment, when the first external instruction includes an instruction directed to the flash memory chip 310, the first control module 311 obtains the second instruction through the first internal pin, and controls the flash memory chip 310 to execute the second instruction and outputs the second information to the first internal pin.

[0160] In this embodiment, the reply protection monotonic counter chip 320 further includes: a second output judgment module 323 and a second sending module 324. The second output judgment module 323 is configured to judge the first information and output the first information, the second information, or the first information and the second information to the second sending module 324, or turn off the second sending module 324.

[0161] In this embodiment, the second shared pin is interconnected with the second sending module 324, and the second shared pin is further configured to transmit the first information, the second information, or the first information and the second information to the external shared pin.

[0162] Specifically, in this embodiment, after obtaining the first information, the second output judgment module 323 judges the first information: to determine whether the first information includes information that needs to be transmitted to the outside. When the first information includes information that needs to be transmitted to the outside, the first information is output to the second sending module 324. And it is determined whether the flash memory chip 310 is attacked, that is, whether the current state of the flash memory chip 310 is secure. When the current state of the flash memory chip 310 is secure, the second information is output to the second sending module 324; when the current state of the flash memory chip 310 is not secure, the second sending module 324 is turned off. After obtaining the first information, the second information, or the first information and the second information, the second sending module 324 transmits the first information, the second information, or the first information and the second information to the outside through the second shared pin and the external shared pin.

[0163] Thus, on the one hand, the state of the flash memory chip module can be obtained, and on the other hand, a protection mechanism can be generated for the flash memory chip 310 to resist external attacks on the flash memory chip 310, increasing the confidentiality and integrity of data transmission of the flash memory chip 310.

[0164] In other embodiments, the second output judgment module is configured to judge the first information and output the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the second sending module, where the third information is encrypted data or random error data. The second shared pin is interconnected with the second sending module, and the second shared pin is further configured to transmit the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external shared pin.

[0165] Specifically, in other embodiments, after obtaining the first information, the second output determination module determines the first information: to determine whether the first information includes information that needs to be transmitted externally. When the first information includes information that needs to be transmitted externally, the first information is output to the second sending module. And, it is determined whether the flash memory chip is attacked, that is, whether the current state of the flash memory chip is secure. When the current state of the flash memory chip is secure, the second information is output to the second sending module; when the current state of the flash memory chip is not secure, the third information is output to the second sending module. After obtaining the first information, the second information, the third information, the first information and the second information, or the first information and the third information, the second sending module transmits the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the outside through the second shared pin and the external shared pin.

[0166] It should be noted that the third information being encrypted data means that the third information is data obtained by encrypting the second information. The third information being random error data means that the third information is random error data obtained by error injection for misleading attackers.

[0167] In this embodiment, the encapsulation carrier 300 further includes a plurality of external independent pins (such as Figure 4 IO_K_1, IO_K_2,..., IO_K_n in), and the external independent pins are also used to receive a third external instruction.

[0168] It should be noted that the third external instruction is a control instruction pointing to the response protection monotonic counter chip 320, and this control instruction is an instruction that the response protection monotonic counter chip 320 independently executes to implement the functions of the response protection monotonic counter chip 320.

[0169] In this embodiment, the response protection monotonic counter chip 320 further includes: a plurality of second independent pins (such as Figure 4 IO_F_1, IO_F_2,..., IO_F_n in), and the second independent pins and the external independent pins are interconnected.

[0170] In this embodiment, metal leads 333 are used to interconnect the corresponding second independent pins and external independent pins.

[0171] For example, the second independent pin IO_F_1 is interconnected with the external independent pin IO_K_1; the second independent pin IO_F_2 is interconnected with the external independent pin IO_K_2; the second independent pin IO_F_n is interconnected with the external independent pin IO_K_n, etc.

[0172] The second independent pin is used to input the third external instruction into the response protection monotonic counter chip 320, and is used to transfer the fifth information from the response protection monotonic counter chip 320 to the external independent pin, where the fifth information is the data obtained after the response protection monotonic counter chip 320 processes the third external instruction.

[0173] Specifically, in this embodiment, the external independent pin receives the third external instruction, the second independent pin obtains the third external instruction from the external independent pin, and inputs the third external instruction into the response protection monotonic counter chip 320; after the response protection monotonic counter chip 320 executes the third external instruction, it obtains the fifth information, and the second independent pin transfers the fifth information to the external independent pin.

[0174] Therefore, the external instructions that do not require the cooperation of the flash memory chip 310 and the response protection monotonic counter chip 320 can be input into the response protection monotonic counter chip 320 not only through the external shared pin and the second shared pin, but also through the external independent pin and the second independent pin. And when the response protection monotonic counter chip 320 executes the external instruction to obtain data, the data can be output to the outside not only through the external shared pin and the second shared pin, but also through the external independent pin and the second independent pin. Furthermore, on the one hand, the flexibility of the path for the response protection monotonic counter chip 320 to receive instructions independently directed to the response protection monotonic counter chip 320 is increased, and on the other hand, the flexibility of the path for the data obtained after the response protection monotonic counter chip 320 independently executes the instruction to be transmitted to the outside is increased.

[0175] In other embodiments, the response protection monotonic counter chip does not include a second independent pin.

[0176] In other embodiments, the packaging carrier does not include an external independent pin.

[0177] In other embodiments, the external independent pin is used to receive a second external instruction. The flash memory chip further includes: a plurality of first independent pins, the first independent pins and the external independent pin are interconnected, and the first independent pins are used to input the second external instruction into the flash memory chip and to transfer the fourth information from the flash memory chip to the external independent pin, where the fourth information is the data obtained after the flash memory chip processes the second external instruction.

[0178] In other embodiments, the first independent pins and the external independent pin are interconnected by metal leads.

[0179] It should be noted that the second external instruction is a control instruction pointing to the flash memory chip, and this control instruction is an instruction that the flash memory chip independently executes to implement the functions of the flash memory chip.

[0180] Specifically, in other embodiments, the external independent pin receives the second external instruction, the first independent pin obtains the second external instruction from the external independent pin, and inputs the second external instruction into the flash memory chip; after the flash memory chip executes the second external instruction, it obtains the fourth information, and the first independent pin transmits the fourth information to the external independent pin.

[0181] Therefore, there is no need for an external instruction that the flash memory chip and the response protection monotonic counter chip cooperate to execute. Not only can it be input into the response protection monotonic counter chip through the external shared pin and the second shared pin and then input into the flash memory chip, but it can also be directly input into the flash memory chip through the external independent pin and the first independent pin. And when the flash memory chip executes this external instruction to obtain data, not only can the data be output to the outside through the first internal pin, the second internal pin, the second shared pin and the external shared pin, but it can also be directly output to the outside through the external independent pin and the first independent pin. Furthermore, on the one hand, the flexibility of the path for the flash memory chip to receive an instruction independently pointing to the flash memory chip is increased, and on the other hand, the flexibility of the path for the data obtained after the flash memory chip independently executes the instruction to be transmitted to the outside is increased.

[0182] In yet another embodiment, the flash memory chip does not include a first independent pin.

[0183] In this embodiment, in the direction perpendicular to the surface of the package carrier 300, the flash memory chip 310 and the response protection monotonic counter chip 320 are arranged overlappingly.

[0184] Thus, the area occupied by the flash memory chip module is saved.

[0185] In this embodiment, when the area of the flash memory chip 310 is smaller than the area of the response protection monotonic counter chip 320, the flash memory chip 310 is located on the response protection monotonic counter chip 320; when the area of the flash memory chip 310 is larger than the area of the response protection monotonic counter chip 320, the response protection monotonic counter chip 320 is located on the flash memory chip 310.

[0186] It should be noted that Figure 5The figure only schematically shows that when the area of the response protection monotonic counter chip 320 is larger than the area of the flash memory chip 310 , the flash memory chip 310 is located on the response protection monotonic counter chip 320 .

[0187] In other embodiments, when the area of the flash memory chip is larger than the area of the response protection monotonic counter chip, the flash memory chip is located on the response protection monotonic counter chip; when the area of the flash memory chip is smaller than the area of the response protection monotonic counter chip, the response protection monotonic counter chip is located on the flash memory chip.

[0188] In yet another embodiment, in a direction perpendicular to a surface of the package carrier, the flash memory chip and the response protection monotonic counter chip are arranged in an overlapping manner.

[0189] Correspondingly, another embodiment of the present invention provides a packaging method for packaging the above-mentioned flash memory chip module.

[0190] Please continue to refer to Figure 5 The packaging method of the flash memory chip module includes: providing a packaging carrier 300, the packaging carrier 300 including a plurality of external shared pins (such as Figure 5 IO_Q_1, IO_Q_2, ..., IO_Q_n); providing a flash memory chip 310, the flash memory chip 310 includes a plurality of first internal pins (such as Figure 5 IO_R_1, IO_R_2, ..., IO_R_n); providing a response protection monotonic counter chip 320, the response protection monotonic counter chip 320 includes a plurality of second shared pins (such as Figure 5 IO_B_1, IO_B_2, ..., IO_B_n) and several second internal pins (such as Figure 5 IO_P_1, IO_P_2, ..., IO_P_n); placing the flash memory chip 310 and the response protection monotonic counter chip 320 on the packaging carrier 300; interconnecting the first internal pin and the second internal pin; interconnecting the second shared pin and the external shared pin; after interconnecting the second shared pin and the external shared pin, and after interconnecting the first internal pin and the second internal pin, plastic-encapsulating the flash memory chip 310, the response protection monotonic counter chip 320 and the packaging carrier 300.

[0191] In this embodiment, the method of interconnecting the first internal pin and the second internal pin includes: interconnecting the first internal pin and the second internal pin using a metal wire 332 .

[0192] For example, interconnect the first internal pin IO_R_1 with the second internal pin IO_P_1; interconnect the first internal pin IO_R_2 with the second internal pin IO_P_2; interconnect the first internal pin IO_R_n with the second internal pin IO_P_n, etc.

[0193] In this embodiment, the method for interconnecting the second shared pin with the external shared pin includes: using a metal lead 331 to interconnect the second shared pin with the external shared pin.

[0194] For example, interconnect the second shared pin IO_B_1 with the external shared pin IO_Q_1; interconnect the second shared pin IO_B_2 with the external shared pin IO_Q_2; interconnect the second shared pin IO_B_n with the external shared pin IO_Q_n, etc.

[0195] In other embodiments, the method for interconnecting the first internal pin and the second internal pin includes: bonding the flash memory chip and the response protected monotonic counter chip before placing the flash memory chip and the response protected monotonic counter chip on the package carrier.

[0196] In this embodiment, the package carrier 300 further includes a plurality of external independent pins (such as Figure 5 IO_K_1, IO_K_2,..., IO_K_n in Figure 5 ), and the response protected monotonic counter chip 320 further includes a plurality of second independent pins (such as IO_F_1, IO_F_2,..., IO_F_n in

[0197] ), and the packaging method further includes: before performing the plastic encapsulation, using a metal lead 333 to interconnect the second independent pin with the external independent pin.

[0198] For example, interconnect the second independent pin IO_F_1 with the external independent pin IO_K_1; interconnect the second independent pin IO_F_2 with the external independent pin IO_K_2; interconnect the second independent pin IO_F_n with the external independent pin IO_K_n, etc.

[0198] In other embodiments, the response protected monotonic counter chip does not include second independent pins.

[0199] In other embodiments, the package carrier does not include external independent pins.

[0200] In other embodiments, the flash memory chip further includes: a plurality of first independent pins. The packaging method further includes: before performing the plastic encapsulation, using a metal lead to interconnect the first independent pin with the external independent pin.

[0201] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A flash memory chip module, characterized in that: include: A package carrier, the package carrier comprising a plurality of external shared pins, the external shared pins being used to obtain a first external instruction; a flash memory chip located on the package carrier, the flash memory chip comprising a plurality of first shared pins and a plurality of first internal pins, the first shared pins being interconnected with the external shared pins, the first shared pins being used to input the first external instruction into the flash memory chip, and the first internal pins being used to output the first instruction; a response protection monotonic counter chip located on the package carrier, the response protection monotonic counter chip including a plurality of second internal pins, the second internal pins being interconnected with the first internal pins, the second internal pins being used to input the first instruction into the response protection monotonic counter chip and transmit the first information from the response protection monotonic counter chip to the first internal pins; The flash memory chip further includes: a first receiving and judging module, configured to judge the first external instruction and output the first instruction, or output the second instruction, or output the first instruction and the second instruction; the first instruction is an instruction formed based on the instruction directed to the response protection monotonic counter chip, and the second instruction is an instruction formed based on the instruction directed to the flash memory chip; a first control module, configured to control the flash memory chip to execute the second instruction and output second information; When the first external instruction only includes an instruction directed to the response protection monotonic counter chip, the first receiving judgment module outputs the first instruction to the first internal pin, and the first internal pin transmits the first instruction to the response protection monotonic counter chip through the second internal pin; When the first external instruction only includes an instruction directed to the flash memory chip, the first receiving and judging module outputs the second instruction to the first control module, and the first control module controls the flash memory chip to point to the second instruction to output the second information; When the first external instruction includes both an instruction directed to the response protection monotonic counter chip and an instruction directed to the flash memory chip, the first receiving and judging module outputs the first instruction and the second instruction.

2. The flash memory chip module according to claim 1, wherein: The flash memory chip also includes: a first output judgment module and a first sending module, the first output judgment module is used to judge the first information and output the first information, the second information or the first information and the second information to the first sending module, or shut down the first sending module.

3. The flash memory chip module according to claim 2, wherein: The first shared pin is interconnected with the first sending module, and the first shared pin is further used to transmit the first information, the second information, or the first information and the second information to the external shared pin.

4. The flash memory chip module according to claim 1, wherein: The flash memory chip also includes: a first output judgment module and a first sending module, the first output judgment module is used to judge the first information and output the first information, the second information, the third information, the first information and the second information or the first information and the third information to the first sending module, the third information is encrypted data or random error data.

5. The flash memory chip module according to claim 4, wherein: The first shared pin is interconnected with the first sending module, and the first shared pin is further used to transmit the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external shared pin.

6. The flash memory chip module according to claim 1, wherein: The packaging carrier also includes a plurality of external independent pins, which are used to receive a second external instruction; the flash memory chip also includes: a plurality of first independent pins, which are interconnected with the external independent pins, and the first independent pins are used to input the second external instruction into the flash memory chip, and to transmit fourth information from the flash memory chip to the external independent pins, wherein the fourth information is data obtained by the flash memory chip after processing the second external instruction.

7. The flash memory chip module according to claim 6, wherein: The external independent pin is also used to receive a third external instruction; the response protection monotonic counter chip also includes: a plurality of second independent pins, the second independent pins and the external independent pins are interconnected, the second independent pins are used to input the third external instruction into the response protection monotonic counter chip, and to transmit fifth information from the response protection monotonic counter chip to the external independent pins, the fifth information being data obtained after the response protection monotonic counter chip processes the third external instruction.

8. The flash memory chip module according to any one of claims 1 to 7, wherein: The response protection monotonic counter chip further includes a second control module, and the second control module is used to control the response protection monotonic counter chip to execute the first instruction and output the first information to the second internal pin.

9. The flash memory chip module according to any one of claims 1 to 7, wherein: In a direction perpendicular to a surface of the package carrier, the flash memory chip and the response protection monotonic counter chip are arranged in an overlapping manner.

10. The flash memory chip module according to any one of claims 1 to 7, wherein: The flash memory chip and the response protection monotonic counter chip are arranged along the surface of the packaging carrier.

11. A method for packaging a flash memory chip module according to any one of claims 1 to 10, characterized in that: include: providing a package carrier, the package carrier comprising a plurality of external shared pins; A flash memory chip is provided, wherein the flash memory chip includes a plurality of first shared pins and a plurality of first internal pins; Providing a response protection monotonic counter chip, wherein the response protection monotonic counter chip includes a plurality of second internal pins; Placing the flash memory chip and the response protection monotonic counter chip on the packaging carrier; interconnecting the first internal pin and the second internal pin; interconnecting the first shared pin with the external shared pin; After the first shared pin and the external shared pin are interconnected, and after the first internal pin and the second internal pin are interconnected, the flash memory chip, the response protection monotonic counter chip, and the package carrier are plastic-encapsulated.

12. The packaging method according to claim 11, wherein: The method of interconnecting the first internal pin and the second internal pin includes: interconnecting the first internal pin and the second internal pin using a metal wire.

13. The packaging method according to claim 11, wherein: The method of interconnecting the first internal pin and the second internal pin includes bonding the flash memory chip and the response protection monotonic counter chip before placing the flash memory chip and the response protection monotonic counter chip on the package carrier.

14. The packaging method according to claim 11, wherein: The method for interconnecting the first shared pin and the external shared pin includes: interconnecting the first shared pin and the external shared pin using a metal wire.

15. The packaging method according to any one of claims 11 to 14, characterized in that: The packaging carrier further includes a plurality of external independent pins, the flash memory chip further includes a plurality of first independent pins, and the packaging method further includes: before performing the plastic packaging, interconnecting the first independent pins with the external independent pins using metal wires.

16. The packaging method according to claim 15, wherein: The response protection monotonic counter chip further includes a plurality of second independent pins. The packaging method further includes: before the plastic packaging, interconnecting the second independent pins with the external independent pins using metal wires.

17. A flash memory chip module, characterized in that: include: A package carrier, the package carrier comprising a plurality of external shared pins, the external shared pins being used to obtain a first external instruction; a response protection monotonic counter chip located on the package carrier, the response protection monotonic counter chip comprising a plurality of second shared pins and a plurality of second internal pins, the second shared pins being interconnected with the external shared pins, the second shared pins being used to input the first external instruction into the response protection monotonic counter chip, and the second internal pins being used to output a second instruction; a flash memory chip located on the package carrier, the flash memory chip including a plurality of first internal pins, the first internal pins being interconnected with the second internal pins, the first internal pins being used to input the second instruction into the flash memory chip and to transmit second information from the flash memory chip to the second internal pins; The response protection monotonic counter chip further includes: a second receiving and judging module, configured to judge the first external instruction and output the first instruction, or output the second instruction, or output the first instruction and the second instruction; a second control module, configured to control the response protection monotonic counter chip to execute the first instruction and output first information; The first instruction is an instruction formed according to the instruction directed to the response protection monotonic counter chip, and the second instruction is an instruction formed according to the instruction directed to the flash memory chip; When the first external instruction only contains instructions pointing to the response protection monotonic counter chip, the second receiving and judging module outputs the first instruction; when the first external instruction only contains instructions pointing to the flash memory chip, the second receiving and judging module outputs the second instruction; when the first external instruction contains both instructions pointing to the flash memory chip and instructions pointing to the response protection monotonic counter chip, the second receiving and judging module outputs the first instruction and the second instruction.

18. The flash memory chip module according to claim 17, wherein: The response protection monotonic counter chip also includes: a second output judgment module and a second sending module, the second output judgment module is used to judge the first information and output the first information, the second information, or the first information and the second information to the second sending module, or turn off the second sending module.

19. The flash memory chip module according to claim 18, wherein: The second shared pin is interconnected with the second sending module, and the second shared pin is further used to transmit the first information, the second information, or the first information and the second information to the external shared pin.

20. The flash memory chip module according to claim 17, wherein: The response protection monotonic counter chip also includes: a second output judgment module and a second sending module, the second output judgment module is used to judge the first information and output the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the second sending module, where the third information is encrypted data or random error data.

21. The flash memory chip module according to claim 20, wherein: The second shared pin is interconnected with the second sending module, and the second shared pin is further used to transmit the first information, the second information, the third information, the first information and the second information, or the first information and the third information to the external shared pin.

22. The flash memory chip module according to claim 17, wherein: The packaging carrier also includes a plurality of external independent pins, which are also used to receive a third external instruction; the response protection monotonic counter chip also includes: a plurality of second independent pins, which are interconnected with the external independent pins, and the second independent pins are used to input the third external instruction into the response protection monotonic counter chip, and to transmit fifth information from the response protection monotonic counter chip to the external independent pins, wherein the fifth information is data obtained after the response protection monotonic counter chip processes the third external instruction.

23. The flash memory chip module according to claim 22, wherein: The external independent pin is used to receive a second external instruction; the flash memory chip also includes: a plurality of first independent pins, the first independent pins and the external independent pins are interconnected, the first independent pins are used to input the second external instruction into the flash memory chip, and to transmit fourth information from the flash memory chip to the external independent pins, the fourth information being data obtained by the flash memory chip after processing the second external instruction.

24. The flash memory chip module according to any one of claims 17 to 23, wherein: The flash memory chip further includes a first control module, which is configured to control the flash memory chip to execute the second instruction and output second information to the first internal pin.

25. The flash memory chip module according to any one of claims 17 to 23, wherein: In a direction perpendicular to a surface of the package carrier, the flash memory chip and the response protection monotonic counter chip are arranged in an overlapping manner.

26. The flash memory chip module according to any one of claims 17 to 13, wherein: The flash memory chip and the response protection monotonic counter chip are arranged along the surface of the packaging carrier.

27. A method for packaging a flash memory chip module according to any one of claims 17 to 26, characterized in that: include: providing a package carrier, the package carrier comprising a plurality of external shared pins; Providing a flash memory chip, the flash memory chip comprising a plurality of first internal pins; Providing a response protection monotonic counter chip, the response protection monotonic counter chip comprising a plurality of second shared pins and a plurality of second internal pins; Placing the flash memory chip and the response protection monotonic counter chip on the packaging carrier; interconnecting the first internal pin and the second internal pin; interconnecting the second shared pin with the external shared pin; After the second shared pin is interconnected with the external shared pin, and after the first internal pin is interconnected with the second internal pin, the flash memory chip, the response protection monotonic counter chip, and the package carrier are plastic-encapsulated.

28. The packaging method according to claim 27, wherein: The method of interconnecting the first internal pin and the second internal pin includes: interconnecting the first internal pin and the second internal pin using a metal wire.

29. The packaging method according to claim 27, wherein: The method of interconnecting the first internal pin and the second internal pin includes bonding the flash memory chip and the response protection monotonic counter chip before placing the flash memory chip and the response protection monotonic counter chip on the package carrier.

30. The packaging method according to claim 27, wherein: The method for interconnecting the second shared pin with the external shared pin includes: interconnecting the second shared pin with the external shared pin using a metal wire.

31. The packaging method according to any one of claims 27 to 30, characterized in that: The packaging carrier further includes a plurality of external independent pins, the flash memory chip further includes a plurality of first independent pins, and the packaging method further includes: before performing the plastic packaging, interconnecting the first independent pins with the external independent pins using metal wires.

32. The packaging method according to any one of claims 27 to 30, characterized in that: The response protection monotonic counter chip further includes a plurality of second independent pins. The packaging method further includes: before performing the plastic packaging, interconnecting the second independent pins with external independent pins using metal wires.

Images