Transistors containing oxide semiconducting materials and related microelectronic devices, memory devices, electronic systems and methods

Abstract

This patent application relates to transistors comprising oxide semiconducting materials, and to related microelectronic devices, memory devices, electronic systems and methods. A transistor includes a lower contact structure, a channel structure, a dielectric filling structure and an upper contact structure. The lower contact structure includes a first oxide semiconducting material. The channel structure contacts the lower contact structure and includes a second oxide semiconducting material, the atomic concentration of one or more metals of the second oxide semiconducting material being lower than that of the first oxide semiconducting material. The dielectric filling structure contacts the inner surface of the channel structure and has an upper surface that is recessed relative to the channel structure. The upper contact structure includes a third oxide semiconducting material, the atomic concentration of the one or more metals of the third oxide semiconducting material being higher than that of the channel structure. The upper contact structure includes a first portion in contact with the upper surface of the dielectric filling structure and the inner surface of the channel structure, and a second portion in contact with the upper surface of the channel structure.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of the filing date of U.S. patent application Ser. No. 16 / 891,462, filed on June 3, 2020. Technical Field

[0003] In various embodiments, the present disclosure relates generally to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to transistors including oxide semiconducting materials, and to related microelectronic devices, memory devices, electronic systems, and methods. Background Art

[0004] An ongoing goal in the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize a vertical memory array (also referred to as a "three-dimensional (3D) memory array") architecture. Conventional vertical memory arrays include vertical memory strings extending through openings in a layer of conductive structures (e.g., wordline plates) and dielectric material at each junction of the vertical memory strings and the conductive structures. Compared to structures with conventional planar (e.g., two-dimensional) transistor arrangements, this configuration allows a greater number of switching devices (e.g., transistors) to be located within a unit of die area (i.e., the length and width of the active surface consumed) by building the array upward (e.g., vertically) on the die.

[0005] Conventional vertical memory arrays include electrical connections between conductive structures and access lines (e.g., word lines) so that memory cells in the vertical memory array can be uniquely selected for write, read, or erase operations. One method of forming such electrical connections includes forming at least one so-called "staircase" (or "stepped") structure at an edge (e.g., a horizontal end) of a conductive structure layer. The staircase structure includes individual "steps" that define contact areas for the conductive structure, on which a conductive contact structure can be positioned to provide electrical access to the conductive structure.

[0006] As vertical memory array technology has advanced, additional memory density has been provided by forming the vertical memory array to include additional layers of conductive structures and, consequently, to include additional staircase structures and / or additional steps in the individual staircase structures associated therewith. However, increasing the number of conductive structure layers in a stacked structure (and, consequently, increasing the number of staircase structures and / or the number of steps in an individual staircase structure) without unduly increasing the overall width (e.g., lateral footprint) of the stacked structure can result in complex and congested routing paths for electrically connecting the conductive structures to additional components of the memory device (e.g., a string driver). Such complex and congested routing paths can obstruct (or even prevent) desired connection paths from and between other components of the memory device. Furthermore, as the number of conductive structure layers continues to increase, conventional locations and configurations of the additional components of the memory device have become unable to support the increased number of additional components.

[0007] Additionally, many conventional transistors employed in driver devices (e.g., string drivers) of conventional memory device configurations use semiconducting materials, such as polysilicon, for their channel structures. However, the use of such materials can result in some less-than-ideal electrical characteristics in the transistors (e.g., high off-current (I) scattered at the interface between the gate oxide material and the channel). off ), low electron carrier mobility). Additionally, the relatively small band gap of such materials can hinder (or even prevent) improvements to other electrical properties of the transistor (e.g., higher on-current (I on ), faster switching speed, lower operating voltage, reduced current leakage). Other semiconducting materials (e.g., oxide semiconductor materials) have been studied as alternatives to polysilicon for the channel structure of transistors. Such materials may have a larger band gap than polysilicon, and employing such materials may help improve electrical characteristics in transistors (e.g., lower I off However, oxide semiconductor materials can be difficult to dope, which can, for example, adversely affect the flow of current through a channel structure formed therethrough, across the Schottky barrier at the junction between the channel structure and a conventional metal contact structure (e.g., a metal source contact structure, a metal drain contact structure).

[0008] In view of the foregoing, there remains a need for new device (e.g., transistor, microelectronic device, memory device) configurations that facilitate increased memory density while alleviating problems (e.g., electronic performance, routing congestion, connection obstacles) of conventional device configurations, as well as methods of forming such devices and systems (e.g., electronic systems) incorporating such devices. Summary of the Invention

[0009] In some embodiments, a transistor includes a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure includes a first oxide semiconducting material. The channel structure is in physical contact with the lower contact structure and includes a second oxide semiconducting material, wherein the atomic concentration of one or more metals in the second oxide semiconducting material is lower than the atomic concentration of the one or more metals in the first oxide semiconducting material. The dielectric fill structure is in physical contact with the inner surface of the channel structure and has an upper surface that is vertically recessed relative to the upper surface of the channel structure. The upper contact structure includes a third oxide semiconducting material, wherein the atomic concentration of the one or more metals in the third oxide semiconducting material is relatively higher than the atomic concentration of the one or more metals in the channel structure. The upper contact structure includes a first portion in physical contact with the upper surface of the dielectric fill structure and the inner surface of the channel structure, and a second portion in physical contact with the upper surface of the channel structure.

[0010] In another embodiment, a microelectronic device includes a first conductive structure, a first contact structure, a channel structure, a second contact structure, a second conductive structure, a conductive gate structure, a gate, and a dielectric structure. The first conductive structure extends vertically through a first isolation material. The first contact structure is on the first conductive structure. Each of the first contact structures comprises an oxide semiconducting material. The channel structure is on the first contact structure and extends vertically through a second isolation material on the first isolation material and a third isolation material on the second isolation material. Each of the channel structures comprises an additional oxide semiconducting material having a relatively lower metal concentration and a relatively higher oxygen concentration than the metal concentration and oxygen concentration in the oxide semiconducting material. The second contact structure is on the channel structure. Each of the second contact structures comprises the oxide semiconducting material. The second conductive structure is on the second contact structure. The conductive gate structure is on the second isolation material and horizontally adjacent to the channel structure. The gate dielectric structure is horizontally interposed between the channel structure and the conductive gate structure.

[0011] In yet another embodiment, a method of forming a microelectronic device includes forming a lower contact structure comprising a first oxide semiconducting material on a conductive structure extending vertically through a first isolation material. A second isolation material is formed on the first isolation material and the lower contact structure. A gate structure is formed on the second isolation material. A channel structure is formed horizontally adjacent to the gate structure and vertically extending through the second isolation material to the lower contact structure. The channel structure comprises a second oxide semiconducting material. A dielectric structure is formed horizontally adjacent to the channel structure and has an upper surface that is vertically recessed relative to an upper surface of the channel structure. An upper contact structure comprising a third oxide semiconducting material is formed on the channel structure and the dielectric structure.

[0012] In other embodiments, a memory device includes a stacked structure, a stepped structure, a conductive pillar structure, a string driver transistor, and a string of memory cells. The stacked structure includes a vertically alternating sequence of conductive structures and insulating structures arranged in layers. The stepped structure is within the stacked structure and has a step including an edge of the layer. The conductive structure is on the step of the stepped structure. The string driver transistor vertically overlies the stepped structure. Each of the string driver transistors includes a first contact structure, a channel structure, a second contact structure, a gate dielectric structure, and a gate electrode. The first contact structure is on one of the conductive structures and includes a first indium-containing oxide semiconducting material. The channel structure is on the first contact structure and includes a second indium-containing oxide semiconducting material having less indium than the first indium-containing oxide semiconducting material. The second contact structure is on the channel structure and includes a third indium-containing oxide semiconducting material having more indium than the second indium-containing oxide semiconducting material. The gate dielectric structure is horizontally adjacent to an outer sidewall of the channel structure. The gate electrode is horizontally adjacent to an outer sidewall of the gate dielectric structure. The string of memory cells extends vertically through the stacked structure.

[0013] In yet another embodiment, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes a stacked structure, a memory cell string, a conductive pillar structure, and a transistor. The stacked structure includes a layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stacked structure includes a stepped region including a stepped structure having a step including a horizontal end of the layer; and a memory array region horizontally adjacent to the stepped region. The memory cell string is within the memory array region of the stacked structure. The conductive pillar structure is on the step of the stepped structure. The transistor vertically overlaps and is within a horizontal boundary of the stepped region of the stacked structure. Each of the transistors includes a lower contact structure, a channel structure, a dielectric structure, an upper contact structure, a gate dielectric structure, and a gate electrode. The lower contact structure is electrically coupled to one of the conductive pillar structures and includes indium and oxygen. The channel structure is on the lower contact structure and includes less indium and more oxygen than the lower contact structure. The dielectric structure is directly adjacent to a sidewall of the trench structure and has an upper surface that is recessed relative to the trench structure. The upper contact structure is above the trench structure and the dielectric structure and includes more indium and less oxygen than the trench structure. The gate dielectric structure is directly adjacent to an additional sidewall of the trench structure. The gate electrode is directly adjacent to a sidewall of the gate dielectric structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figures 1A to 1K is a simplified partial cross-sectional view illustrating a method of forming a microelectronic device according to an embodiment of the present disclosure.

[0015] Figure 2 is a partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure.

[0016] Figure 3 is a schematic block diagram illustrating an electronic system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The following description provides specific details, such as material composition, shape and size, in order to provide a sufficient description of the embodiments of the present disclosure. However, those skilled in the art will understand that the embodiments of the present disclosure can be practiced without adopting these specific details. In fact, the embodiments of the present disclosure can be practiced in combination with conventional microelectronic device manufacturing techniques adopted in the industry. In addition, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structure described below does not form a complete microelectronic device. Only those process actions and structures necessary to understand the embodiments of the present disclosure are described in detail below. Additional actions to form a complete microelectronic device based on the structure can be performed by conventional manufacturing techniques.

[0018] The figures presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. As a result of, for example, manufacturing techniques and / or tolerances, variations from the shapes depicted in the figures are expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes or regions shown, but rather include shape deviations, for example, caused by manufacturing. For example, a region shown or described as box-shaped may have rough and / or nonlinear features, and a region shown or described as circular may include some rough and / or linear features. In addition, the acute angles shown may be rounded, and vice versa. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and do not limit the scope of the present claims. The figures are not necessarily drawn to scale. In addition, common elements between the figures may retain the same numerical designations.

[0019] As used herein, "memory device" means and includes a microelectronic device that exhibits memory functionality but is not necessarily limited to memory functionality. In other words, and by way of non-limiting example only, the term "memory device" includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also application specific integrated circuits (ASICs) (e.g., systems on a chip (SoCs)), microelectronic devices combining logic and memory, and graphics processing units (GPUs) incorporating memory.

[0020] As used herein, the terms "vertical," "longitudinal," "horizontal," and "transverse" are references to a principal plane of a structure and are not necessarily defined by the Earth's gravitational field. A "horizontal" or "transverse" direction is a direction substantially parallel to the principal plane of a structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to the principal plane of a structure. A principal plane of a structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure.

[0021] As used herein, features (e.g., regions, materials, structures, devices) described as being "adjacent" to one another mean and include features of the disclosed one or more identities that are located in closest proximity (e.g., closest to one another). Additional features (e.g., additional regions, additional materials, additional structures, additional devices) that do not match the disclosed one or more identities of the "adjacent" features may be positioned between the "adjacent" features. In other words, the "adjacent" features may be positioned directly adjacent to one another, such that no other features intervene between them; or the "adjacent" features may be positioned indirectly adjacent to one another, such that at least one feature having an identity other than that associated with at least one "adjacent" feature is positioned between the "adjacent" features. Thus, features described as being "vertically adjacent" to one another mean and include features of the disclosed one or more identities that are located in closest vertical proximity (e.g., closest to one another). Furthermore, features described as being "horizontally adjacent" to one another mean and include features of the disclosed one or more identities that are located in closest horizontal proximity (e.g., closest to one another).

[0022] As used herein, the terms "comprising," "including," "having," and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional unrecited elements or method steps, and also encompass the more restrictive terms "consisting of" and "consisting essentially of," and their grammatical equivalents. As used herein, the term "may" with respect to a material, structure, feature, or method act indicates that such material, structure, feature, or method act is contemplated for use in practicing embodiments of the present disclosure, and such terms are preferred over the more restrictive term "are" to avoid any implication that other compatible materials, structures, features, and methods that may be used in combination therewith should or must be excluded.

[0023] As used herein, spatially relative terms such as "under," "below," "lower," "bottom," "above," "upper," "top," "front," "back," "left," "right," etc. may be used for ease of description to describe the relationship of one element or feature to another element or feature as shown in the figures. Unless otherwise specified, spatially relative terms are intended to encompass different orientations of material in addition to the orientation depicted in the figures. For example, if the material in the figure is reversed, an element described as being "under," "beneath," "below," or "on the bottom" of another element or feature would be oriented "above" or "on the top" of the other element or feature. Thus, the term "under" may encompass both above and below orientations depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, reversed, inverted), and the spatially relative descriptors used herein may be interpreted accordingly.

[0024] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0025] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] As used herein, the term "configuration" refers to the size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device that facilitates operation of the one or more of the structure and the device in a predetermined manner.

[0027] As used herein, the phrase "coupled to" refers to structures that are operatively connected to each other, such as through a direct ohmic connection or through an indirect connection (eg, electrically via another structure).

[0028] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and encompasses the degree to which a person of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with a degree of variance (e.g., within an acceptable tolerance). By way of example, depending on the particular parameter, characteristic, or condition being substantially met, the parameter, characteristic, or condition may be met by at least 90.0%, by at least 95.0%, by at least 99.0%, by at least 99.9%, or even by 100.0%.

[0029] As used herein, "about" or "approximately" with reference to a numerical value of a particular parameter is inclusive of the stated numerical value, and a degree of deviation from the stated numerical value that one of ordinary skill in the art would understand is within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​that are within 90.0% to 110.0% of the stated numerical value, such as within 95.0% to 105.0% of the stated numerical value, within 97.5% to 102.5% of the stated numerical value, within 99.0% to 101.0% of the stated numerical value, within 99.5% to 100.5% of the stated numerical value, or within 99.9% to 100.1% of the stated numerical value.

[0030] Unless the context indicates otherwise, the materials described herein may be formed by any suitable process, including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD) (including sputtering, evaporation, ionized PVD, and / or plasma-enhanced CVD), or epitaxial growth. Depending on the specific material to be formed, the technique used to deposit or grow the material may be selected by one of ordinary skill in the art. Furthermore, unless the context indicates otherwise, the material removal described herein may be achieved by any suitable process, including, but not limited to, photolithographic patterning, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical mechanical planarization (CMP)), or other known methods.

[0031] Figures 1A to 1K 1 is a simplified partial cross-sectional view illustrating an embodiment of a method for forming a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device). It will be apparent to one of ordinary skill in the art, combined with the description provided below, that the methods and structures described herein can be used in a variety of devices and electronic systems.

[0032] refer to Figure 1A , the microelectronic device structure 100 can be formed to include a first isolation material 102 and a lower conductive structure 104 extending vertically (eg, in the Z direction) through the first isolation material 102. Figure 1A As shown in , the lower conductive structure 104 can be formed to extend vertically substantially completely through the first isolation material 102 .

[0033] The first isolation material 102 may be formed of and include at least one dielectric material, such as one or more of: at least one dielectric oxide material (e.g., silicon oxide (SiO x ), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlO x ), hafnium oxide (HfO x ), niobium oxide (NbO x ), titanium oxide (TiO x ), zirconium oxide (ZrO x ), tantalum oxide (TaO x ) and magnesium oxide (MgO x ), at least one dielectric nitride material (e.g., silicon nitride (SiN y )), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiO x N y)) and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO x C z N y )). The chemical formula containing one or more of "x", "y" and "z" herein (e.g., SiO x 、AlO x , HfO x 、NbO x 、TiO x 、SiN y 、SiO x N y 、SiO x C z N y ) represents a material containing an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for each atom of the other element (e.g., Si, Al, Hf, Nb, Ti). Since the chemical formula represents relative atomic ratios rather than strict chemical structures, the first isolation material 102 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes a compound having a composition of an element that cannot be expressed by a ratio of well-defined natural numbers and violates the law of definite proportions. In some embodiments, the first isolation material 102 is composed of SiO x (eg, silicon dioxide (SiO2)) and includes the SiO x .

[0034] First isolation material 102 may be substantially uniform, or non-uniform. As used herein, the term "uniform" means that the relative amounts of an element contained in a feature (e.g., a material, a structure) do not vary across different portions of the feature (e.g., different horizontal portions, different vertical portions). Conversely, as used herein, the term "non-uniform" means that the relative amounts of an element contained in a feature (e.g., a material, a structure) vary across different portions of the feature. If first isolation material 102 is non-uniform, the amount of one or more elements contained in first isolation material 102 may vary gradually (e.g., abruptly) or may vary continuously (e.g., gradually, such as linearly or parabolically) across different portions of first isolation material 102. In some embodiments, first isolation material 102 is substantially uniform. In additional embodiments, first isolation material 102 is non-uniform. First isolation material 102 may, for example, be formed from and include a stack (e.g., a laminate) of at least two different dielectric materials.

[0035] The lower conductive structures 104 may each be formed of and include at least one conductive material, such as one or more of: at least one metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); at least one alloy (e.g., Co-based alloy, Fe-based alloy, The lower conductive structure 104 may be a conductive material comprising a Ni-based alloy, a Fe- and Ni-based alloy, a Co- and Ni-based alloy, a Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, steel, mild steel, or stainless steel); at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped germanium (Ge), or conductively doped silicon germanium (SiGe)); and at least one conductive metal-containing material (e.g., a conductive metal nitride, such as one or more of titanium nitride (TiN) and tungsten nitride (WN); a conductive metal silicide; a conductive metal carbide; or a conductive metal oxide). In some embodiments, the lower conductive structure 104 is formed of and includes W. In additional embodiments, the lower conductive structure 104 is formed of and includes TiN.

[0036] The lower conductive structures 104 may each be substantially uniform, or one or more (e.g., each) of the lower conductive structures 104 may be non-uniform. If an individual conductive structure 104 is non-uniform, the amount of one or more elements included in the conductive structure 104 may change gradually (e.g., abruptly) or may change continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of the conductive structure 104. In some embodiments, each of the lower conductive structures 104 is substantially uniform. In additional embodiments, one or more of the lower conductive structures 104 is non-uniform. One or more of the lower conductive structures 104 may, for example, each be formed from and include a stack of at least two different conductive materials.

[0037] The lower conductive structures 104 can each have a desired geometric configuration (e.g., a desired shape and a desired size). In some embodiments, the lower conductive structures 104 are formed to have a geometric configuration that permits the conductive structures 104 to function as conductive pillar structures for a microelectronic device (e.g., a memory device, such as a 3D NAND flash memory device) that includes the microelectronic device structure 100. By way of non-limiting example, the lower conductive structures 104 can each be formed to have a pillar-like shape having a circular cross-sectional shape, a rectangular cross-sectional shape, an elliptical cross-sectional shape, a square cross-sectional shape, a rectangular cross-sectional shape, a teardrop cross-sectional shape, a semicircular cross-sectional shape, a tombstone cross-sectional shape, a crescent cross-sectional shape, a triangular cross-sectional shape, a kite cross-sectional shape, or an irregular cross-sectional shape. In some embodiments, each of the lower conductive structures 104 has a cylindrical shape. Each of the lower conductive structures 104 can be formed to have substantially the same geometric configuration (e.g., substantially the same shape, substantially the same size) as each other of the lower conductive structures 104, or at least one of the lower conductive structures 104 can be formed to have a different geometric configuration (e.g., a different shape, at least one different size) than at least one other of the lower conductive structures 104. As a non-limiting example, one or more of the lower conductive structures 104 can be formed to have a different vertical dimension (e.g., in the Z direction) than one or more other of the lower conductive structures 104. The different vertical dimensions of at least some of the lower conductive structures 104 can, for example, permit at least some of the lower conductive structures 104 to vertically extend into and contact different structures (e.g., different additional conductive structures) vertically located below the microelectronic device structure 100, as described below with reference to Figure 2 Described in further detail.

[0038] The microelectronic device structure 100 can be formed to include a desired number (eg, quantity, amount) of lower conductive structures 104. Figure 1AThe microelectronic device structure 100 is depicted as being formed to include two (2) lower conductive structures 104, but the microelectronic device structure 100 can be formed to include more than two (2) (e.g., greater than or equal to eight (8), greater than or equal to sixteen (16), greater than or equal to thirty-two (32), greater than or equal to sixty-four (64), greater than or equal to one hundred and twenty-eight (128), greater than or equal to two hundred and fifty-six (256)) lower conductive structures 104, or less than two (2) (e.g., only one (1)) lower conductive structure 104.

[0039] The first isolation material 102 and the lower conductive structure 104 may be formed using conventional processes not described in detail herein (e.g., conventional deposition processes such as spin-on coating, blanket coating, CVD, ALD, and PVD; conventional patterning and material removal processes such as conventional photolithography exposure processes, conventional development processes, and conventional etching processes) and conventional processing equipment.

[0040] Next reference Figure 1B , an upper portion of the lower conductive structure 104 may be selectively removed relative to the first isolation material 102 to form a recessed upper surface 105 of the lower conductive structure 104. Figure 1B , the recessed upper surface 105 of the lower conductive structure 104 can be vertically offset (e.g., in the Z direction) from the upper surface 103 of the first isolation material 102 by a vertical height H1 (e.g., depth, vertical dimension). The vertical height H1 can be selected based at least in part on a predetermined height of a lower contact structure to be subsequently formed on or over the lower conductive structure 104, as described in further detail below. By way of non-limiting example, the vertical height H1 can be in a range from about 5 nanometers (nm) to about 50 nm.

[0041] like Figure 1B As shown in FIG, the selective removal of the upper portion of the lower conductive structure 104 forms an opening 106 (e.g., a recess) at least partially defined by the recessed upper surface 105 of the lower conductive structure 104 and the exposed upper portion of the side surface (e.g., sidewall) of the first isolation material 102. The opening 106 may have a horizontal shape and horizontal dimensions (e.g., in the X direction, in the Y direction) that correspond to (e.g., be substantially the same as) the horizontal shape and horizontal dimensions of the lower conductive structure 104. In additional embodiments, one or more (e.g., each) of the openings 106 may have a horizontal shape and / or horizontal dimensions that are different from the horizontal shape and / or horizontal dimensions of the lower conductive structure 104. By way of non-limiting example, one or more of the openings 106 may be formed to have a horizontal dimension that is different (e.g., a larger horizontal dimension, a smaller horizontal dimension) than the horizontal dimension of one or more of the lower conductive structures 104.

[0042] The upper portion of the lower conductive structure 104 can be selectively removed by treating the microelectronic device structure 100 with at least one etchant (e.g., at least one wet etchant) formulated to remove the exposed portion of the lower conductive structure 104 without substantially removing the exposed portion of the first isolation material 102. The microelectronic device structure 100 can be exposed to the etchant using conventional processes (e.g., spin coating processes, spray coating processes, dip coating processes, vapor coating processes, immersion processes, combinations thereof) and conventional processing equipment not described in detail herein.

[0043] Next reference Figure 1C , the lower contact material 108 may be formed in the opening 106 ( Figure 1B ) is formed on or above the exposed surface of the microelectronic device structure 100. The lower contact material 108 may be formed to substantially fill the opening 106 ( Figure 1B ), and at opening 106 ( Figure 1B ) at and beyond the boundaries (e.g., horizontal boundaries, vertical boundaries) of the microelectronic device structure 100, covering and substantially extending across the exposed surfaces of the microelectronic device structure 100 (e.g., the upper surface 103 of the first isolation material 102, the recessed upper surface 105 of the lower conductive structure 104, and the side surfaces of the first isolation material 102).

[0044] The lower contact material 108 may be formed of and include at least one oxide semiconductive material. For example, the lower contact material 108 may include one or more of the following: zinc tin oxide (ZnO); x Sn y O, commonly known as "ZTO"), indium zinc oxide (In x Zn y O, commonly known as "IZO"), zinc oxide (Zn x O), indium gallium zinc oxide (In x Ga y Zn z O, commonly known as "IGZO"), indium gallium oxide (In x Ga y Si z O, commonly referred to as "IGSO"), indium tungsten oxide (In x W y O, commonly referred to as "IWO"), indium oxide (In x O), tin oxide (Sn x O), titanium oxide (Ti x O), zinc oxide nitride (Zn x ON z ), magnesium zinc oxide (Mg x Zn yO), zirconium indium zinc (Zr x In y Zn z O), hafnium indium zinc oxide (Hf x In y Zn z O), tin indium zinc oxide (Sn x InyZn z O), aluminum oxide, tin indium zinc (Al x Sn y In z Zn a O), silicon indium zinc oxide (Si x In y Zn z O), aluminum zinc tin oxide (Al x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), zirconium oxide zinc tin (Zr x Zn y Sn z O) and other similar materials. A chemical formula containing at least one of the above "x", "y", "z" and "a" (e.g., Zn x Sn y O、In x Zn y O、In x Ga y Zn z O、In x W y O、In x Ga y Si z O、Al x Sn y In z Zn a O) represents a composite material containing an average ratio of "x" atoms of one element, "y" atoms of another element (if present), "z" atoms of an additional element (if present), and "d" atoms of another element (if present) for each atom of oxygen (O) throughout one or more regions thereof. Since the chemical formula represents relative atomic ratios rather than strict chemical structures, the channel structure 128 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", "z", and "a" may be integers or non-integers. In some embodiments, the lower contact material 108 is composed of In x Ga y Zn z O and In xIn some embodiments, the first deposited metal material (e.g., In) is oxidized to form the lower contact material 108 (e.g., In). x O, such as In2O3).

[0045] The oxide semiconductive material of the lower contact material 108 can be formed to have a different (e.g., greater, lesser) atomic concentration of one or more elements (e.g., one or more metals, oxygen) than the oxide semiconductive material of the channel structure to be formed by subsequent processing of the microelectronic device structure 100. By way of non-limiting example, the lower contact material 108 can be formed to have an increased atomic concentration of one or more metals (e.g., one or more of indium (In), tin (Sn), zinc (Zn), gallium (Ga), magnesium (Mg), titanium (Ti), aluminum (Al), and zirconium (Zr)) and / or metalloid (e.g., silicon (Si)) relative to the channel structure to be formed subsequently, and a reduced atomic concentration of oxygen. In other words, the lower contact material 108 can be formed to be rich in metal and low in oxygen relative to the channel structure to be formed subsequently. In some embodiments, such as embodiments in which the channel structure is selected to include an In-containing oxide semiconductor material (described in further detail below), the lower contact material 108 can be formed to include an increased In atomic concentration and / or a reduced oxygen atomic concentration relative to the channel structure.

[0046] The lower contact material 108 may be substantially uniform, or the lower contact material 108 may be non-uniform. If the lower contact material 108 is non-uniform, the amount of one or more elements included in the lower contact material 108 may change gradually (e.g., abruptly) or may change continuously (e.g., gradually, such as linearly or parabolically) throughout different regions of the lower contact material 108. In some embodiments, the lower contact material 108 is substantially uniform. In additional embodiments, the lower contact material 108 is non-uniform. Relatively vertically lower (e.g., in the Z direction) regions of the lower contact material 108 may, for example, be relatively metal-rich (e.g., In-rich) and oxygen-poor compared to relatively vertically higher regions of the lower contact material 108. In some embodiments, the lower contact material 108 comprises substantially the same elements in all of its different vertical regions, but at least one relatively vertically lower region of the lower contact material 108 comprises a different atomic concentration of one or more elements than at least one relatively vertically higher region of the lower contact material 108. By way of non-limiting example, the lower contact material 108 may comprise a non-uniform form of In x Ga y Zn zO, such that each vertical region of the lower contact material 108 includes In, Ga, Zn, and O, but the atomic concentration of one or more of In, Ga, Zn, and O (e.g., In and / or O) in at least one relatively vertically lower region is different (e.g., In is relatively higher and / or O is relatively lower) than the atomic concentration of one or more of In, Ga, Zn, and O (e.g., In and / or O) in at least one relatively vertically higher region. In additional embodiments, the lower contact material 108 includes a different element in at least one of its different vertical regions than in at least one other of its different vertical regions. The lower contact material 108 may, for example, comprise a stack (e.g., a laminate) of two or more (e.g., two, three, or more than three) different oxide semiconductor materials. In some such embodiments, a first oxide semiconductor material positioned relatively vertically lower (e.g., in the Z direction) within the lower contact material 108 may be metal-rich (e.g., In-rich) and / or oxygen-reduced compared to a second oxide semiconductor material positioned relatively vertically higher within the lower contact material 108.

[0047] The lower contact material 108 may be formed using conventional processes (eg, conventional deposition processes such as one or more of spin-on coating, blanket coating, CVD, ALD, and PVD) and conventional processing equipment, which are not described in detail herein.

[0048] Next reference Figure 1D , the lower contact material 108 can be removed ( Figure 1C ) in the opening 106 ( Figure 1B ) outside the boundary (eg, horizontal boundary, vertical boundary), while maintaining the lower contact material 108 ( Figure 1C ) in the opening 106 ( Figure 1B ) to form the lower contact structure 110. The lower contact structure 110 may be substantially confined to the opening 106 ( Figure 1B ) within the boundaries (e.g., horizontal boundaries, vertical boundaries). The upper boundary of the lower contact structure 110 may be substantially coplanar with the upper boundary of the first isolation material 102. By way of non-limiting example, Figure 1D As shown in , the upper surface 111 of the lower contact structure 110 may be formed to be substantially coplanar with the upper surface 103 of the first isolation material 102 .

[0049] The lower contact material 108 ( Figure 1C ) in the opening 106 ( Figure 1B) to form the lower contact structure 110. As a non-limiting example, at least one CMP process may be used to remove the lower contact material 108 ( Figure 1C ) in the opening 106 ( Figure 1B ) to form a lower contact structure 110.

[0050] Next reference Figure 1E , second isolation material 112 may be formed on or over lower contact structure 110 and first isolation material 102; and sacrificial material 114 may be formed on or over second isolation material 112. For example, Figure 1E As shown in FIG. 1 , the second isolation material 112 may be formed on an upper surface (eg, upper surface 111 ( Figure 1D )) and the upper surface of the first isolation material 102 (eg, the upper surface 103 ( Figure 1D and a sacrificial material 114 may be formed on the upper surface of the second isolation material 112.

[0051] Second isolation material 112 may be formed from and include at least one dielectric material having a different etch selectivity than first isolation material 102 and one or more subsequently formed materials (e.g., a conductive material, an additional isolation material). Second isolation material 112 may be selectively etched relative to first isolation material 102 and / or subsequently formed materials during a common (e.g., collective, mutual) exposure to a first etchant, and may be selectively etched relative to second isolation material 112 during a common exposure to a second, different etchant. As used herein, a material is "selectively etchable" relative to another material if the material exhibits an etch rate that is at least about three times (3x) greater than the other material, such as about five times (5x) greater, about ten times (10x) greater, about twenty times (20x) greater, or about forty times (40x) greater. By way of non-limiting example, the second isolation material 112 may be formed of and include one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x One or more of ), at least one dielectric nitride material (e.g., SiN y), at least one dielectric oxynitride material (e.g., SiO x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y In some embodiments, for example, the first isolation material 102 is made of SiO x (e.g., SiO2) is formed and contains the SiO x In some embodiments, the second isolation material 112 is made of SiN y (eg, Si3N4) is formed and includes the SiN y .

[0052] Second isolation material 112 may be substantially uniform, or non-uniform. If non-uniform, the amount of one or more elements contained in second isolation material 112 may change gradually (e.g., abruptly) or may change continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of second isolation material 112. In some embodiments, second isolation material 112 is substantially uniform. In other embodiments, second isolation material 112 is non-uniform. Second isolation material 112 may, for example, be formed from and include a stack (e.g., a laminate) of at least two different dielectric materials.

[0053] The second isolation material 112 can be formed to have a desired vertical height H2. The vertical height H2 of the second isolation material 112 can be selected based at least in part on a desired vertical offset (e.g., in the Z direction) between the lower contact structure 110 and a gate structure (e.g., a gate electrode) to be formed on or above the second isolation material 112 through subsequent processing of the microelectronic device structure 100, as described in further detail below. The deposition process (e.g., a PVD process, a CVD process, an ALD process) used to form the second isolation material 112 can, for example, facilitate relatively more precise control of the vertical offset compared to conventional processes (e.g., conventional gate structure spacing processes) that employ, for example, one or more subtractive processing actions. By way of non-limiting example, the vertical height H2 of the second isolation material 112 can be in the range of approximately 5 nm to approximately 50 nm.

[0054] Sacrificial material 114 may be formed from and include at least one material having a different etch selectivity than second isolation material 112 and one or more subsequently formed materials (e.g., a conductive material, a dielectric material). Sacrificial material 114 may be selectively etched relative to second isolation material 112 and / or subsequently formed materials during a common (e.g., collective, mutual) exposure to a first etchant, and may be selectively etched relative to second isolation material 112 and / or subsequently formed materials during a common exposure to a second, different etchant. By way of non-limiting example, sacrificial material 114 may be formed from and include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon nitride, a carbon-containing material (e.g., SiOCN), carbon, a photoresist material, or another material. In some embodiments, sacrificial material 114 is formed from and includes polycrystalline silicon.

[0055] The sacrificial material 114 can be formed to have a desired vertical height H3. The vertical height H3 of the sacrificial material 114 can be selected based at least in part on the desired vertical height of the channel structure to be formed by subsequent processing of the microelectronic device structure 100, as described in further detail below. By way of non-limiting example, the vertical height H3 of the sacrificial material 114 can be in a range of approximately 30 nm to approximately 200 nm, such as approximately 50 nm to approximately 200 nm, approximately 75 nm to approximately 200 nm, approximately 100 nm to approximately 200 nm, or approximately 150 nm to approximately 200 nm. In some embodiments, the vertical height H3 of the sacrificial material 114 is in a range of approximately 50 nm to approximately 100 nm.

[0056] The second isolation material 112 and the sacrificial material 114 may be formed using conventional processes (eg, conventional deposition processes such as one or more of spin-on coating, blanket coating, CVD, ALD, and PVD) and conventional processing equipment not described in detail herein.

[0057] Next reference Figure 1F , portions of the sacrificial material 114 ( FIG. 1E ) may be removed to form sacrificial post structures 116 and trenches 118; and gate structures 120 (e.g., gate electrodes) may be formed within the trenches 118. The trenches 118 may be horizontally interposed between and separate horizontally adjacent sacrificial post structures 116. Each of the sacrificial post structures 116 may be at least partially horizontally surrounded by at least one of the gate structures 120.

[0058] The sacrificial post structures 116 may each be formed at a desired horizontal position (eg, in the X and Y directions) on or above the second isolation material 112. Figure 1F, in some embodiments, each of the sacrificial post structures 116 is substantially horizontally centered (e.g., in the X-direction and the Y-direction) above one of the lower contact structures 110, respectively. In additional embodiments, one or more of the sacrificial post structures 116 are individually horizontally offset (e.g., in the X-direction and / or in the Y-direction) from the horizontal center of the lower contact structure 110 with which they are associated. For example, the horizontal center of at least one (e.g., all, less than all) of the sacrificial post structures 116 may be horizontally offset in the X-direction from the horizontal center of the lower contact structure 110 to which they are closest. As another example, the horizontal center of at least one (e.g., all, less than all) of the sacrificial post structures 116 may be horizontally offset in the Y-direction from the horizontal center of the lower contact structure 110 to which they are closest. If the horizontal center of an individual sacrificial post structure 116 is horizontally offset from the horizontal center of the lower contact structure 110 to which it is closest, then portions of the sacrificial post structures 116 may still horizontally overlap with portions of the lower contact structure 110.

[0059] The sacrificial post structures 116 can each be formed to have a desired shape. As non-limiting examples, the sacrificial post structures 116 can each be formed to have a columnar shape having a circular cross-sectional shape, a rectangular cross-sectional shape, an elliptical cross-sectional shape, a square cross-sectional shape, a rectangular cross-sectional shape, a teardrop cross-sectional shape, a semicircular cross-sectional shape, a tombstone cross-sectional shape, a crescent cross-sectional shape, a triangular cross-sectional shape, a kite cross-sectional shape, or an irregular cross-sectional shape. In some embodiments, the sacrificial post structures 116 are each formed to have a cylindrical shape.

[0060] The sacrificial post structures 116 may each be formed to have desired dimensions (eg, horizontal dimensions, vertical dimensions). Figure 1F, in some embodiments, the horizontal dimensions (e.g., diameter, width, length) of individual sacrificial post structures 116 are substantially equal to the horizontal dimensions of individual lower contact structures 110. The horizontal area of ​​each of the sacrificial post structures 116 may be substantially equal to the horizontal area of ​​each of the lower contact structures 110. In additional embodiments, the horizontal dimensions of the individual sacrificial post structures 116 in one or more directions (e.g., in the X-direction and / or the Y-direction) are different from the horizontal dimensions of the individual lower contact structures 110 in one or more directions. By way of non-limiting example, the horizontal dimensions of one or more (e.g., each) of the sacrificial post structures 116 in one or more directions (e.g., in the X-direction and / or the Y-direction) may be greater than the horizontal dimensions of one or more (e.g., each) of the lower contact structures 110 in one or more directions (e.g., in the X-direction and / or the Y-direction). The horizontal area of ​​each of the sacrificial post structures 116 may be greater than the horizontal area of ​​each of the lower contact structures 110. As another non-limiting example, the horizontal dimension of one or more (e.g., each) of the sacrificial post structures 116 in one or more directions (e.g., in the X direction and / or the Y direction) may be smaller than the horizontal dimension of one or more (e.g., each) of the lower contact structures 110 in one or more directions (e.g., in the X direction and / or the Y direction). The horizontal area of ​​each of the sacrificial post structures 116 may be smaller than the horizontal area of ​​each of the lower contact structures 110. In addition, the vertical height of the sacrificial post structures 116 may be less than or equal to the vertical height of the sacrificial material 114 ( Figure 1E )’s vertical height H3. Figure 1F As shown in FIG. 1 , in some embodiments, each of the sacrificial post structures 116 is formed to have a substantially uniform thickness relative to the sacrificial material 114 ( Figure 1E ) have essentially the same vertical height H3.

[0061] Each of the sacrificial post structures 116 may be formed to have substantially the same geometric configuration (e.g., substantially the same shape, substantially the same size) as each other of the sacrificial post structures 116, or at least one of the sacrificial post structures 116 may be formed to have a different geometric configuration (e.g., a different shape, at least one different size) than at least one other of the sacrificial post structures 116. In some embodiments, each of the sacrificial post structures 116 is formed to have substantially the same geometric configuration as each other of the sacrificial post structures 116.

[0062] The sacrificial post structures 116 and the trenches 118 may be formed using conventional processes (e.g., conventional material removal processes, such as conventional photolithography patterning processes and / or conventional etching processes) and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, the sacrificial material 114 ( Figure 1E) may be subjected to at least one etching process (eg, at least one anisotropic dry etching process, at least one anisotropic wet etching process) to form the sacrificial post structure 116 and the trench 118.

[0063] Continue to refer Figure 1F , the gate structure 120 may be formed horizontally adjacent to the sacrificial pillar structure 116 within the trench 118. Figure 1F , in some embodiments, the gate structure 120 is formed directly horizontally adjacent to the sacrificial post structure 116. As described in further detail below, in additional embodiments, the gate structure 120 is formed indirectly horizontally adjacent to the sacrificial post structure 116. One or more additional features (e.g., additional materials, additional structures) may be formed horizontally between the gate structure 120 and the sacrificial post structure 116. By way of non-limiting example, a gate dielectric structure may be formed horizontally between the gate structure 120 and the sacrificial post structure 116. As described in further detail below, the gate structure 120 may be configured and positioned relative to the sacrificial post structure 116 to facilitate one or more desirable transistor (e.g., vertical transistor) configurations through subsequent processing of the microelectronic device structure 100.

[0064] In some embodiments, the gate structures 120 are configured and positioned relative to the sacrificial pillar structures 116 to facilitate the subsequent formation of so-called "double-gate" transistors, each of which includes two (2) of the gate structures 120 horizontally adjacent to two (2) opposite sides (e.g., in the X direction) of the channel structure, as described in further detail below. For example, Figure 1F As shown in , each of the trenches 118 horizontally inserted (e.g., in the X direction) between two (2) horizontally adjacent (e.g., in the X direction) sacrificial post structures 116 may include two (2) of the gate structures 120 therein.

[0065] In additional embodiments, the gate structures 120 are configured and positioned relative to the sacrificial post structures 116 to facilitate subsequent formation of so-called "single-gate" transistors that each include one (1) of the gate structures 120 horizontally adjacent to one side of the channel structure, but not the other (1) of the gate structures 120 horizontally adjacent to the opposite side (e.g., in the X direction) of the channel structure. For example, some of the trenches 118 horizontally interposed (e.g., in the X direction) between horizontally adjacent (e.g., in the X direction) sacrificial post structures 116 may each include fewer than two (2) of the gate structures 120 therein. Some of the trenches 118 may include a single (e.g., only one) gate structure 120 therein, or may not include a gate structure 120 therein (e.g., if an additional horizontally adjacent trench 118 includes two (2) of the gate structures 120 therein).

[0066] In other embodiments, the gate structures 120 are configured and positioned relative to the sacrificial post structures 116 to facilitate subsequent formation of so-called "tri-gate" transistors, each of which includes at least one of the gate structures 120 horizontally adjacent to three (3) sides (e.g., in the X direction and in the Y direction) of the channel structure, as described in further detail below. For example, for each of the sacrificial post structures 116, a first portion of a single (e.g., only one) gate structure 120 may be horizontally adjacent to opposite sides (e.g., in the X direction) of the sacrificial post structure 116; and a second portion of the gate structure 120 may extend horizontally from and between the first portion and may be horizontally adjacent to the other side (e.g., in the Y direction) of the sacrificial post structure 116 that is horizontally interposed (e.g., in the X direction) between the opposite sides of the sacrificial post structure 116.

[0067] In yet other embodiments, the gate structures 120 are configured and positioned relative to the sacrificial post structures 116 to facilitate the subsequent formation of so-called "all-around gate" transistors, each of which includes at least one of the gate structures 120 horizontally adjacent to all sides of the channel structure (e.g., in the X direction and in the Y direction), as described in further detail below. For example, for each of the sacrificial post structures 116, a portion of a single (e.g., only one) gate structure 120 may be horizontally adjacent to and substantially horizontally surround all sides of the sacrificial post structure 116 (e.g., in the X direction and in the Y direction). A first portion of the gate structure 120 may be horizontally adjacent to first opposing sides of the sacrificial post structures 116 (e.g., in the X direction); and a second portion of the gate structure 120 may extend horizontally from and between the first portion and may be horizontally adjacent to second opposing sides of the sacrificial post structures 116 (e.g., in the Y direction) that are horizontally interposed (e.g., in the X direction) between the first opposing sides of the sacrificial post structures 116.

[0068] The gate structure 120 may be formed of and include at least one conductive material, such as one or more of: at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al); at least one alloy (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, mild steel, stainless steel); at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe); and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide).

[0069] The gate structures 120 may each be substantially uniform, or one or more (e.g., each) of the gate structures 120 may be non-uniform. If an individual gate structure 120 is non-uniform, the amount of one or more elements included in the gate structure 120 may change gradually (e.g., abruptly) or may change continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of the gate structure 120. In some embodiments, each of the gate structures 120 is substantially uniform. In additional embodiments, one or more of the gate structures 120 is non-uniform. One or more of the gate structures 120 may, for example, each be formed from and include a stack of at least two different conductive materials.

[0070] The gate structures 120 may each be formed to have a desired size (e.g., horizontal size, vertical size). As a non-limiting example, one or more (e.g., each) of the gate structures 120 may each be formed to have a horizontal width W1 (e.g., in one or more directions extending horizontally away from one or more sides of the sacrificial pillar structure 116, such as in Figure 1F ), the width is in the range of about 5 nm to about 15 nm, for example, about 5 nm to about 10 nm, or about 10 nm to about 15 nm. In some embodiments, the horizontal width W1 of each of the gate structures 120 is formed to be in the range of about 5 nm to about 10 nm. In addition, the gate structures 120 may each have a vertical height that is less than the vertical height (for example, vertical height H3) of the sacrificial pillar structure 116. Figure 1FAs shown in , the lower vertical boundary of the gate structure 120 may be substantially coplanar with the lower vertical boundary of the sacrificial post structure 116, and the upper vertical boundary of the gate structure 120 may be vertically offset from (e.g., vertically located below) the upper vertical boundary of the sacrificial post structure 116.

[0071] The gate structure 120 can be formed within the trench 118 using conventional processes and conventional processing equipment not described in detail herein. By way of non-limiting example, at least one conductive material can be conformally formed (e.g., deposited by one or more of a CVD process and an ALD process) over the exposed surface of the microelectronic device structure 100 inside and outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the trench 118; and then at least one etching process can be performed to remove portions of the microelectronic device structure 100 (e.g., from the surface of the microelectronic device structure 100 outside the trench 118; from the floor of at least some of the trenches 118; from upper portions of the sides of the sacrificial post structures 116), while at least partially maintaining additional portions (e.g., lower portions) of the conductive material horizontally adjacent to one or more sides of individual sacrificial post structures 116 to form the gate structure 120.

[0072] Next reference Figure 1G , groove 118( Figure 1F ) can be filled (eg, substantially filled) with the third isolation material 122. Figure 1G As shown in the previous reference Figure 1F At the end of the described processing stage, the third isolation material 122 may substantially surround and cover the side surfaces (eg, sidewalls) of the sacrificial pillar structure 116 and the sidewalls exposed in the trench 118 ( Figure 1F ) within the gate structure 120. The upper vertical boundary of the third isolation material 122 may be formed to be substantially coplanar with the upper vertical boundary of the sacrificial post structure 116; and the lower vertical boundary of the third isolation material 122 may be formed to be substantially coplanar with the lower vertical boundaries of the sacrificial post structure 116 and the gate structure 120.

[0073] The third isolation material 122 may be formed of and include at least one dielectric material having a different etch selectivity than the sacrificial post structure 116, the second isolation material 112, and the gate structure 120. For example, the sacrificial post structure 116 may be selectively etched relative to the third isolation material 122 during common (e.g., collective, mutual) exposure to a first etchant, and the third isolation material 122 may be selectively etched relative to the sacrificial post structure 116 during common exposure to a second, different etchant. As another example, the second isolation material 112 may be selectively etched relative to the third isolation material 122 during common (e.g., collective, mutual) exposure to a first etchant, and the third isolation material 122 may be selectively etched relative to the second isolation material 112 during common exposure to a second, different etchant. The third isolation material 122 may, for example, be formed of and include one or more of the following: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x One or more of ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y The material composition of the third isolation material 122 may be different from the material composition of the second isolation material 112, and may be substantially the same as or different from the material composition of the first isolation material 102. In some embodiments, for example, where the second isolation material 112 is made of SiN y (eg, Si3N4) is formed and contains the SiN y In some embodiments, the third isolation material 122 is made of SiO x (e.g., SiO2) is formed and contains the SiO x .

[0074] Third isolation material 122 may be substantially uniform, or it may be non-uniform. If third isolation material 122 is non-uniform, the amount of one or more elements contained in third isolation material 122 may change gradually (e.g., abruptly) or may change continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of third isolation material 122. In some embodiments, third isolation material 122 is substantially uniform. In other embodiments, third isolation material 122 is non-uniform. Third isolation material 122 may, for example, be formed from and include a stack (e.g., a laminate) of at least two different dielectric materials.

[0075] The third isolation material 122 may be formed using conventional processes not described in detail herein (eg, conventional deposition processes such as one or more of spin-on coating, blanket coating, CVD, ALD, and PVD; conventional material removal processes such as conventional CMP processes) and conventional processing equipment.

[0076] Next reference Figure 1H , the sacrificial pillar structure 116 can be selectively removed ( Figure 1G ) and a portion of the second isolation material 112 vertically thereunder to form an additional opening 124 (eg, a hole, a via) extending vertically to the lower contact structure 110. The sacrificial post structure 116 ( Figure 1G ) and the portion of the second isolation material 112 vertically therebelow can facilitate the subsequent formation (e.g., by a damascene process) of a channel structure (e.g., a vertical channel structure) of the microelectronic device structure 100 without subjecting the material of the channel structure to one or more subtractive material removal (e.g., etching) processes that could otherwise adversely affect desired characteristics of the channel structure (e.g., current flow characteristics), as described in further detail below.

[0077] like Figure 1H As shown in FIG, the additional opening 124 may be positioned horizontally adjacent to the gate structure 120. The horizontal boundary of the additional opening 124 may be adjacent to the sacrificial pillar structure 116 ( Figure 1G ) are substantially the same. In addition, the lower vertical boundary of the additional opening 124 may be at least partially defined by (e.g., substantially coplanar with) the upper vertical boundary (e.g., the upper surface) of the lower contact structure 110. The additional opening 124 may vertically extend from the upper vertical boundary of the third isolation material 122 to the upper vertical boundary of the lower contact structure 110. Figure 1H As shown in , each of the additional openings 124 may have a vertical height H4 corresponding to a combination (eg, a sum) of the vertical height H2 of the second isolation material 112 and the vertical height H3 of the third isolation material 122 .

[0078] The sacrificial post structure 116 may be selectively removed relative to other features of the microelectronic device structure 100 (e.g., the gate structure 120, the third isolation material 122, the lower contact structure 110, the first isolation material 102) using a conventional material removal process (e.g., a conventional etching process, such as one or more of a conventional wet etching process and a conventional dry etching process; a conventional stamping process) which is not described in detail herein. Figure 1G ) and a portion of the second isolation material 112. For example, a first material removal process (eg, an etching process) may be used to selectively remove the sacrificial pillar structure 116 ( Figure 1G ), and then a second material removal process (eg, a stamping process) may be used to selectively remove the sacrificial post structure 116 ( Figure 1G ) to expose a portion of the second isolation material 112 to form an additional opening 124.

[0079] Next reference Figure 1I , the gate dielectric structure 126, the channel structure 128 and the dielectric filling structure 130 may be formed in the additional opening 124 ( Figure 1H ). The gate dielectric structure 126, the channel structure 128, and the dielectric fill structure 130 may together substantially fill the additional opening 124 ( Figure 1H ).like Figure 1I As shown in FIG, the gate dielectric structure 126 can be formed horizontally between the gate dielectric structure 126 and the channel structure 128, and the channel structure 128 can be formed horizontally between the gate dielectric structure 126 and the dielectric filling structure 130. In other words, in the additional opening 124 ( Figure 1H ), the gate dielectric structure 126 may be formed on the horizontal inner side of the gate structure 120, the channel structure 128 may be formed on the horizontal inner side of the gate dielectric structure 126, and the dielectric filling structure 130 may be formed on the horizontal inner side of the channel structure 128.

[0080] like Figure 1I As shown in the previous reference Figure 1H At the end of the described processing stage, the gate dielectric structure 126 may be formed to substantially cover the gate dielectric structure 126 exposed in the additional opening 124 ( Figure 1H ) in the third isolation material 122, the gate structure 120, and the side surfaces (eg, sidewalls) of the second isolation material 112. The gate dielectric structure 126 may be formed in the additional opening 124 ( Figure 1H ) is directly horizontally adjacent to the side surfaces (e.g., sidewalls) of the third isolation material 122, the gate structure 120, and the second isolation material 112 at the horizontal boundary of the gate structure 120. In addition, the gate dielectric structure 126 may be formed to extend vertically (i.e., in the Z direction) substantially completely through the additional opening 124 ( Figure 1HFor example, each of the gate dielectric structures 126 may vertically extend from an upper surface of the third isolation material 122 to an upper surface of one of the lower contact structures 110 .

[0081] The gate dielectric structure 126 may be formed of and include at least one dielectric material, such as one or more of: at least one oxide dielectric material (e.g., SiO x 、AlO x , one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass), at least one nitride dielectric material (e.g., SiN y ), at least one high-K dielectric material (e.g., zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and for example hafnium silicon oxide (HfSi x O y ) and at least one low-K dielectric material (e.g., silicon oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y ), hydrogenated silicon oxycarbide (SiC x O y H z ) and silicon oxycarbonitride (SiO x C z N y ) in one or more of the above. In some embodiments, the gate dielectric structure 126 is made of SiO x (e.g., SiO2) is formed and contains the SiO x .

[0082] The gate dielectric structures 126 may each be substantially uniform, or one or more (e.g., each) of the gate dielectric structures 126 may be non-uniform. If an individual gate dielectric structure 126 is non-uniform, the amount of one or more elements included in the gate dielectric structure 126 may change gradually (e.g., abruptly) or may change continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of the gate dielectric structure 126. In some embodiments, each of the gate dielectric structures 126 is substantially uniform. In additional embodiments, one or more of the gate dielectric structures 126 is non-uniform. One or more of the gate dielectric structures 126 may, for example, each be formed from and include a stack of at least two different dielectric materials.

[0083] The gate dielectric structures 126 may each be formed to have a desired horizontal dimension. As a non-limiting example, one or more (eg, each) of the gate structures 120 may each be formed to have a desired horizontal dimension. Figure 1H ) has a horizontal width in one or more directions extending horizontally inward from the horizontal boundary of the gate structure 120 (e.g., in the X direction), and the width is in the range of about 2 nm to about 20 nm, for example, about 2 nm to about 15 nm, or about 2 nm to about 10 nm. In some embodiments, the horizontal width of each of the gate structures 120 is formed to be in the range of about 2 nm to about 10 nm. In addition, as Figure 1I As shown in FIG. 1 , each of the gate dielectric structures 126 may have a plurality of openings 124 ( Figure 1H ) have essentially the same vertical height H4.

[0084] Although the gate dielectric structure 126 has been described herein as being Figure 1I By way of non-limiting example, as previously discussed, in additional embodiments, the gate dielectric structure 126 is formed during the processing stages described above, but the present disclosure is not limited thereto. Figure 1F The gate dielectric structure 126 may be formed, for example, to be horizontally disposed above the sacrificial pillar structure 116 ( Figure 1F ) and the gate structure 120. In such embodiments, the gate dielectric structure 126 may terminate vertically at an upper vertical boundary (eg, an upper surface) of the second isolation material 112, rather than as Figure 1I 110. In other words, the gate dielectric structure 126 may not be formed to extend vertically through the second isolation material 112. For example, the gate dielectric structure 126 may be formed to extend vertically from the sacrificial pillar structure 116 ( Figure 1F ) extends vertically to the upper surface of the second isolation material 112. In addition, in such embodiments, due to the previously mentioned Figure 1F The formation of the gate dielectric structure 126 during the described processing stages may affect the horizontal position of the gate dielectric structure 126 and the gate structure 120 and / or the sacrificial pillar structure 116 ( Figure 1F ) (and thus the additional opening 124 ( Figure 1H )'s horizontal size can be modified.

[0085] Still refer to Figure 1I , the channel structure 128 may be formed to substantially cover the inner side surface (e.g., inner sidewall) of the gate dielectric structure 126. The channel structure 128 may be formed to be directly horizontally adjacent to the inner side surface (e.g., inner sidewall) of the gate dielectric structure 126. In addition, the channel structure 128 may be formed to extend vertically (i.e., in the Z direction) substantially completely through the additional opening 124 ( Figure 1H For example, each of the channel structures 128 may vertically extend from an upper surface of the third isolation material 122 to an upper surface of one of the lower contact structures 110 , respectively.

[0086] The channel structures 128 may each be formed to have a desired shape. Figure 1I As shown in FIG. 1 , in some embodiments, the trench structures 128 are each configured such that the dielectric filling structure 130 extends vertically (ie, in the Z direction) only partially (eg, less than completely) through the additional openings 124 ( Figure 1H ). For example, for each of the channel structures 128, one of the dielectric filling structures 130 may be horizontally interposed between different horizontal portions of the channel structure 128 and may vertically terminate on the channel structure 128. The lower surface of the channel structure 128 may be in physical contact with the upper surface of the lower contact structure 110, and the lower surface of the dielectric filling structure 130 may be in physical contact with the horizontally extending surface of the channel structure 128. In additional embodiments, the channel structures 128 are each configured such that the dielectric filling structure 130 extends vertically (i.e., in the Z direction) substantially completely through the additional opening 124 ( Figure 1H For example, for each of the trench structures 128, one of the dielectric filling structures 130 may be horizontally interposed between different horizontal portions of the trench structure 128, from the upper surface of the third isolation material 122 to the upper surface of one of the lower contact structures 110. The lower surface of the trench structure 128 may be in physical contact with the upper surface of the lower contact structure 110, and the lower surface of the dielectric filling structure 130 may also be in physical contact with the upper surface of the lower contact structure 110.

[0087] The channel structure 128 may be formed of and include at least one oxide semiconducting material having a band gap greater than that of polysilicon, such as a band gap greater than 1.65 electron volts (eV). For example, the channel structure 128 may be formed of and include one or more of the following: Zn x Sn y O、In x Zn y O, Zn x O、In x Ga y Zn z O、In x Ga y Si z O、In x W y O、In x O, Sn x O、Tix O, Zn x ON z Mg x Zn y O, Zr x In y Zn z O、Hf x In y Zn z O, Sn x In y Zn z O、Al x Sn y In z Zn a O、Si x In y Zn z O、Al x Zn y Sn z O.Ga x Zn y Sn z O, Zr x Zn y Sn z O, and other similar materials. A chemical formula containing at least one of the above "x", "y", "z" and "a" (e.g., Zn x Sn y O、In x Zn y O、In x Ga y Zn z O、In x W y O、In x Ga y Si z O、Al x Sn y In z Zn a O) represents a composite material containing an average ratio of "x" atoms of one element, "y" atoms of another element (if present), "z" atoms of an additional element (if present), and "d" atoms of another element (if present) for each atom of oxygen (O) throughout one or more regions thereof. Since the chemical formula represents relative atomic ratios rather than strict chemical structures, the channel structure 128 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", "z", and "a" may be integers or non-integers. In some embodiments, the channel structure 128 is composed of In x Ga y Znz O is formed and contains the In x Ga y Zn z O.

[0088] The oxide semiconductive material of the channel structure 128 may be formed to have a different (e.g., greater, lesser) atomic concentration of one or more elements (e.g., one or more metals, oxygen) than the oxide semiconductive material of the lower contact structure 110. By way of non-limiting example, the channel structure 128 may be formed to have an atomic concentration of one or more metals (e.g., one or more of In, Sn, Zn, Ga, Mg, Ti, Al, Hf, and Zr) and / or metalloids (e.g., Si) relative to the late of the lower contact structure 110 and an increased atomic concentration of oxygen. In other words, the channel structure 128 may be formed to be less metal and richer in oxygen than the lower contact structure 110. In some embodiments, such as where the lower contact structure 110 is formed to include an In-containing oxide semiconductor material (e.g., In x Ga y Zn z O、In x In the embodiment of FIG), the channel structure 128 may be formed to include a reduced In atomic concentration and / or an increased O atomic concentration compared to the lower contact structure 110.

[0089] The channel structures 128 may be respectively substantially uniform, or the channel structures 128 may be respectively non-uniform. If the channel structures 128 are respectively non-uniform, the amount of one or more elements contained in the individual channel structures 128 may change gradually (e.g., abruptly), or may change continuously (e.g., gradually, such as linearly, parabolically) throughout the different regions of the channel structures 128. In some embodiments, the channel structures 128 are respectively substantially uniform. In additional embodiments, the channel structures 128 are respectively non-uniform. In some embodiments, the channel structures 128 respectively contain substantially the same elements in all of their different regions, but at least one region in the individual channel structures 128 contains an atomic concentration of the one or more elements that is different from at least one other region in the channel structures 128. By way of non-limiting example, the individual channel structures 128 may be composed of a non-uniform form of In x Ga y Zn z O is formed and contains the In x Ga y Zn zO, such that each region of the channel structure 128 includes In, Ga, Zn, and O, but the atomic concentration of one or more of In, Ga, Zn, and O (e.g., In and / or O) in at least one region is different (e.g., In is relatively higher and / or O is relatively lower) from the atomic concentration of one or more of In, Ga, Zn, and O (e.g., In and / or O) in at least one other region. In additional embodiments, the channel structure 128 includes different elements in different regions thereof. Individual channel structures 128 may, for example, include a stack (e.g., a laminate) of two or more (e.g., two, three, or more than three) different oxide semiconductor materials.

[0090] The channel structures 128 may each be formed to have a desired horizontal dimension. As a non-limiting example, one or more (e.g., each) of the channel structures 128 may each be formed to have a horizontal width in one or more directions (e.g., in the X direction) extending horizontally inward from the inner horizontal boundary (e.g., the inner side surface) of the respective gate dielectric structure 126, the width being in the range of about 5 nm to about 30 nm. Figure 1I As shown in FIG. 1 , each of the channel structures 128 may have a plurality of channels corresponding to the additional openings 124 ( Figure 1H ) have essentially the same vertical height H4.

[0091] Continue to refer Figure 1I , the dielectric fill structure 130 may be formed to substantially fill the additional opening 124 ( Figure 1H ) that is not occupied by the gate dielectric structure 126 and the channel structure 128. The dielectric filling structure 130 may be formed to substantially cover the inner side surface (eg, inner sidewall) of the channel structure 128. The dielectric filling structure 130 may be formed to be directly horizontally adjacent to the inner side surface (eg, inner sidewall) of the channel structure 128. Figure 1I , the dielectric fill structure 130 can be formed to extend vertically (i.e., in the Z direction) from an upper vertical boundary (e.g., an upper surface) of the third isolation material 122 toward an upper vertical boundary (e.g., an upper surface) of the lower contact structure 110. The dielectric fill structure 130 can enhance the structural stability and reliability of the channel structure 128 (and thus the vertical transistor including the channel structure 128), and can also facilitate forming an upper contact structure having a relatively large contact surface area for contacting the channel structure 128 (compared to conventional upper contact structure configurations), as described in further detail below.

[0092] The dielectric filling structure 130 may be formed of and include at least one dielectric material having a different etching selectivity from the channel structure 128, the gate dielectric structure 126, and the third isolation material 122. For example, the dielectric filling structure 130 may be selectively etched relative to the channel structure 128, the gate dielectric structure 126, and the third isolation material 122 during a common (e.g., collective, mutual) exposure to a selected etchant. The dielectric filling structure 130 may be formed of and include, for example, one or more of the following: at least one dielectric oxide material (e.g., yttrium oxide (YO2)); x ), SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x One or more of ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y The material composition of the dielectric fill structure 130 may be different from the material composition of the third isolation material 122 and the gate dielectric structure 126, and may be substantially the same as or different from the material composition of the second isolation material 112. In some embodiments, for example, where one or more of the third isolation material 122 and the gate dielectric structure 126 are made of SiO x (e.g., SiO2) is formed and contains the SiO x In some embodiments, the dielectric filling structure 130 is respectively composed of SiN y (eg, Si3N4) is formed and contains the SiN y In additional embodiments, the dielectric filling structure 130 is respectively composed of YO x (e.g., yttrium (III) oxide (Y2O3)) is formed and contains the YO x .

[0093] The dielectric fill structures 130 may each be substantially uniform, or one or more (e.g., each) of the dielectric fill structures 130 may be non-uniform. If an individual dielectric fill structure 130 is non-uniform, the amount of one or more elements included in the dielectric fill structure 130 may vary gradually (e.g., abruptly) or may vary continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of the dielectric fill structure 130. In some embodiments, each of the dielectric fill structures 130 is substantially uniform. In additional embodiments, one or more of the dielectric fill structures 130 is non-uniform. One or more of the dielectric fill structures 130 may, for example, each be formed from and include a stack of at least two different dielectric materials.

[0094] The gate dielectric structure 126, the channel structure 128, and the dielectric fill structure 130 may be formed using conventional processes (e.g., conventional deposition processes such as one or more of ALD, CVD, and PVD; conventional material removal processes such as one or more of anisotropic etching and CMP) and conventional processing equipment not described in detail herein.

[0095] Next reference Figure 1J , the dielectric filling structure 130 may be vertically recessed relative to the channel structure 128, the gate dielectric structure 126, and the third isolation material 122 (for example, the upper portion of the dielectric filling structure 130 may be removed); the upper contact material 132 may be formed to fill the resulting recess and cover the upper surface of the channel structure 128, the gate dielectric structure 126, and the third isolation material 122; and the upper conductive material 134 may be formed on or above the upper contact material 132.

[0096] like Figure 1J As shown in FIG, the recessed upper surface 131 of the dielectric fill structure 130 may be vertically offset from the upper surfaces of the channel structure 128, the gate dielectric structure 126, and the third isolation material 122 by a vertical height H5 (e.g., vertically deeper), the height having a magnitude in the range of 5 nanometers (nm) to about 100 nm. The recessed upper surface 131 of the dielectric fill structure 130 may be vertically positioned (e.g., in the Z direction) below, at, or above the upper surface of the gate structure 120. In some embodiments, the recessed upper surface 131 of the dielectric fill structure 130 is formed to be substantially coplanar with the upper surface of the gate structure 120. In additional embodiments, the recessed upper surface 131 of the dielectric fill structure 130 is formed to be vertically positioned below the upper surface of the gate structure 120.

[0097] Continue to refer Figure 1J, the upper contact material 132 may be formed to substantially fill the recess created by the selective removal of the upper portion of the dielectric fill structure 130. For example, Figure 1J , the upper contact material 132 may be formed to include: a first portion 132A (e.g., a vertically protruding portion) that vertically extends (e.g., in the Z direction) into the recess and substantially fills the recess; and a second portion 132B that is integral and continuous with the first portion 132A and horizontally extends (e.g., in the X and Y directions) across the upper surface of the channel structure 128, the gate dielectric structure 126, and the third isolation material 122 outside the recess. Figure 1J As depicted in , the upper contact material 132 can have a non-planar lower vertical boundary and a substantially planar upper vertical boundary.

[0098] The first portion 132A of the upper contact material 132 may substantially cover the recessed upper surface 131 of the dielectric fill structure 130 and the upper portion of the inner side surface of the channel structure 128. The first portion 132A of the upper contact material 132 may be formed to be directly vertically adjacent to (e.g., vertically located above) the recessed upper surface 131 of the dielectric fill structure 130 and directly horizontally adjacent to (e.g., horizontally located above) the upper portion of the inner side surface of the channel structure 128. In addition, the second portion 132B of the upper contact material 132 may substantially cover the upper surfaces of the channel structure 128, the gate dielectric structure 126, and the third isolation material 122. The second portion 132B of the upper contact material 132 may be formed to be directly vertically adjacent to (e.g., vertically located above) the upper surfaces of the channel structure 128, the gate dielectric structure 126, and the third isolation material 122.

[0099] like Figure 1J , the first portion 132A of the upper contact material 132 can be formed to have substantially the same vertical height H5 as the recess formed by selectively removing the upper portion of the dielectric fill structure 130. Additionally, the second portion 132B of the upper contact material 132 can have a desired vertical height H6. By way of non-limiting example, the vertical height H6 of the second portion 132B of the upper contact material 132 can be in a range from about 5 nm to about 50 nm.

[0100] The upper contact material 132 (including the first portion 132A and the second portion 132B thereof) may be formed of and include at least one oxide semiconductive material. For example, the upper contact material 132 may be formed of and include one or more of the following: Zn x Sn y O、In x Zn y O, Znx O、In x Ga y Zn z O、In x Ga y Si z O、In x W y O、In x O, Sn x O、Ti x O, Zn x ON z Mg x Zn y O, Zr x In y Zn z O、Hf x In y Zn z O, Sn x In y Zn z O、Al x Sn y In z Zn a O、Si x In y Zn z O、Al x Zn y Sn z O.Ga x Zn y Sn z O, Zr x Zn y Sn z O, and other similar materials. A chemical formula containing at least one of the above "x", "y", "z" and "a" (e.g., Zn x Sn y O、In x Zn y O、In x Ga y Zn z O、In x W y O、In x Ga y Si z O、Al x Sn y In z Zn aThe upper contact material 132 may be a stoichiometric compound or compounds and may be a non-stoichiometric compound or compounds. In some embodiments, the upper contact material 132 is composed of In x Ga y Zn z O and In x O (e.g., indium (III) oxide, In2O3) is formed and includes the one or more.

[0101] The oxide semiconductive material of the upper contact material 132 may be formed to have a different (e.g., greater, lesser) atomic concentration of one or more elements (e.g., one or more metals, oxygen) than the oxide semiconductive material of the channel structure 128. By way of non-limiting example, the upper contact material 132 may be formed to have an increased atomic concentration of one or more metals (e.g., one or more of In, Sn, Zn, Ga, Mg, Ti, Al, and Zr) and / or metalloids (e.g., Si) and a reduced atomic concentration of oxygen relative to the channel structure 128. In other words, the upper contact material 132 may be formed to be rich in metal and low in oxygen relative to the channel structure 128. In some embodiments, such as embodiments in which the channel structure 128 is formed to include an In-containing oxide semiconductor material, the upper contact material 132 may be formed to include an increased In atomic concentration and / or a reduced oxygen atomic concentration relative to the channel structure 128.

[0102] The material composition of the upper contact material 132 may be different from the material composition of the lower contact structure 110 (and thus from the lower contact material 108 ( Figure 1C ) material composition) or the material composition of the upper contact material 132 may be substantially the same as the material composition of the lower contact structure 110 (and thus the lower contact material 108 ( Figure 1C In some embodiments, the material composition of the upper contact material 132 is substantially the same as the material composition of the lower contact structure 110 .

[0103] The upper contact material 132 may be substantially uniform, or the upper contact material 132 may be non-uniform. If the upper contact material 132 is non-uniform, the amount of one or more elements included in the upper contact material 132 may change gradually (e.g., abruptly) or may change continuously (e.g., gradually, such as linearly or parabolically) throughout different regions of the upper contact material 132. In some embodiments, the upper contact material 132 is substantially uniform. In additional embodiments, the upper contact material 132 is non-uniform. Relatively vertically higher (e.g., in the Z direction) regions of the upper contact material 132 may, for example, be relatively metal-rich (e.g., In-rich) and oxygen-poor compared to relatively vertically lower regions of the upper contact material 132. In some embodiments, the upper contact material 132 comprises substantially the same elements in all of its different vertical regions, but at least one relatively vertically higher region of the upper contact material 132 comprises a different atomic concentration of one or more elements than at least one relatively vertically lower region of the upper contact material 132. By way of non-limiting example, the upper contact material 132 may comprise a non-uniform form of In x Ga y Zn z O, such that each vertical region of the upper contact material 132 includes In, Ga, Zn, and O, but the atomic concentration of one or more of In, Ga, Zn, and O (e.g., In and / or O) in at least one relatively vertically higher region is different (e.g., In is relatively higher and / or O is relatively lower) than the atomic concentration of one or more of In, Ga, Zn, and O (e.g., In and / or O) in at least one relatively vertically lower region. In additional embodiments, the upper contact material 132 includes a different element in at least one of its different vertical regions than in at least one other of its different vertical regions. The upper contact material 132 may, for example, comprise a stack (e.g., a laminate) of two or more (e.g., two, three, or more than three) different oxide semiconductor materials. In some such embodiments, a first oxide semiconductor material positioned relatively vertically higher (e.g., in the Z direction) within the upper contact material 132 may be metal-rich (e.g., In-rich) and / or oxygen-reduced compared to a second oxide semiconductor material positioned relatively vertically lower within the upper contact material 132.

[0104] Still refer to Figure 1J, upper conductive material 134 may be formed on or over an upper surface of upper contact material 132 . The upper conductive material 134 may be formed of and include at least one conductive material, such as one or more of: at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al); at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co and Ni and Fe-based alloy, Al-based alloy, Cu-based alloy, magnesium (Mg)-based alloy, Ti-based alloy, steel, low carbon steel, stainless steel); at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe); and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). The material composition of the upper conductive material 134 may be substantially the same as the material composition of the lower conductive structure 104, or the material composition of the upper conductive material 134 may be different from the material composition of the lower conductive structure 104. In some embodiments, the upper conductive material 134 is formed of and includes W.

[0105] The upper conductive material 134 may be substantially uniform, or the upper conductive material 134 may be non-uniform. If the upper conductive material 134 is non-uniform, the amount of one or more elements included in the upper conductive material 134 may change gradually (e.g., abruptly) or may change continuously (e.g., gradually, such as linearly or parabolically) throughout different portions of the upper conductive material 134. In some embodiments, the upper conductive material 134 is substantially uniform. In other embodiments, the upper conductive material 134 is non-uniform. The upper conductive material 134 may, for example, be formed from and include a stack (e.g., lamination) of at least two different conductive materials.

[0106] The dielectric fill structure 130 may be vertically recessed, and the upper contact material 132 and the upper conductive material 134 may be formed using conventional processes not described in detail herein. By way of non-limiting example, the dielectric fill structure 130 may be vertically recessed, and the upper contact material 132 and the upper conductive material 134 may be formed using conventional processes not described in detail herein. Figure 1IThe described processing stage is followed by treating the microelectronic device structure 100 (e.g., by a spin coating process, a spray coating process, a dip coating process, a vapor coating process, and a soaking process) with at least one etchant (e.g., at least one wet etchant) formulated to selectively remove exposed portions of the dielectric fill structure 130 without substantially removing exposed portions of the channel structure 128, the gate dielectric structure 126, and the third isolation material 122 to selectively remove upper portions of the dielectric fill structure 130. Thereafter, upper contact material 132 and a conductive material may be formed by one or more conventional deposition processes (e.g., one or more of ALD, CVD, and PVD).

[0107] Next reference Figure 1K , segments (e.g., regions, portions) of upper contact material 132 and upper conductive material 134 may be removed to form upper contact structure 136 and upper conductive structure 138, respectively. Upper contact structure 136 may include first portion 136A corresponding to first portion 132A of upper contact material 132, and second portion 136B corresponding to an additional segment of second portion 132B of upper contact material 132 remaining after the material removal process. Second portion 136B of upper contact structure 136 may be integral and continuous with first portion 136A of upper contact structure 136. Additionally, upper conductive structure 138 contacts (e.g., physically contacts, electrically contacts) upper contact structure 136 and corresponds to an additional segment of upper conductive material 134 remaining after the material removal process.

[0108] like Figure 1K , the first portion 136A of the upper contact structure 136 can be positioned directly vertically adjacent to (e.g., vertically above) the recessed upper surface 131 of the dielectric fill structure 130, and directly horizontally adjacent to (e.g., horizontally above) the upper portion of the inner side surface of the channel structure 128. Additionally, the second portion 136B of the upper contact structure 136 can cover (e.g., substantially cover) and contact (e.g., physically contact, electrically contact) at least the upper surface of the channel structure 128. The second portion 136B of the upper contact structure 136 can be formed to have desired horizontal dimensions (e.g., in the X direction and in the Y direction). Figure 1K , in some embodiments, the second portion 136B of the upper contact structure 136 covers and physically contacts the upper surfaces of the channel structure 128 and the gate dielectric structure 126. In additional embodiments, the second portion 136B of the upper contact structure 136 covers and physically contacts the upper surfaces of the channel structure 128 and the gate dielectric structure 126, as well as a portion of the upper surface of the third isolation material 122.

[0109] The first portion 136A of each upper contact structure 136 can enhance the surface area of ​​the upper contact structure 136 that contacts one of the channel structures 128 relative to conventional upper contact structure configurations that do not include the first portion 136A (e.g., conventional configurations in which the upper contact structure presents a substantially planar lower surface that contacts only the upper surface of the channel structure). The relatively enhanced contact surface area of ​​the upper contact structures 136 can improve the electrical on-state characteristics of a device (e.g., a transistor) that includes the upper contact structures 136 relative to conventional device (e.g., a conventional transistor) configurations that do not include the upper contact structures 136.

[0110] Continue to refer Figure 1K , the gate structures 120, gate dielectric structures 126, channel structures 128, dielectric fill structures 130, lower contact structures 110, and upper contact structures 136 (including first and second portions 136A and 136B thereof) of the microelectronic device structure 100 may form a plurality of vertical transistors 140 (e.g., vertical thin film transistors (TFTs)). The vertical transistors 140 may, for example, be used as driver transistors (e.g., string driver transistors) for a microelectronic device including the microelectronic device structure 100, as described in further detail. Each of the vertical transistors 140 may respectively include a lower contact structure 110, at least one gate structure 120, a gate dielectric structure 126, a channel structure 128, a dielectric fill structure 130, and an upper contact structure 136. As previously described with reference to Figure 1F As described, depending on the configuration of the gate structure 120 , the vertical transistors 140 may each have a “dual gate” design, a “single gate” design, a “triple gate” design, or a “gate all wrapped” design.

[0111] Still refer to Figure 1K The upper conductive structure 138 can be formed to have a desired geometry (e.g., shape, size). The geometry of the upper conductive structure 138 depends, at least in part, on the desired function of the upper conductive structure 138. In some embodiments, the upper conductive structure 138 serves as a conductive routing structure (e.g., metallization hierarchy) for control logic circuitry (e.g., complementary metal oxide semiconductor (CMOS) circuitry) for a control logic device (e.g., a string driver) that includes the vertical transistor 140.

[0112] The upper contact material 132 ( Figure 1J ) and upper conductive material 134 ( Figure 1J ) forms an upper contact structure 136 and.

[0113] Therefore, according to an embodiment of the present disclosure, a method for forming a microelectronic device includes forming a lower contact structure comprising a first oxide semiconducting material on a conductive structure extending vertically through a first isolation material. A second isolation material is formed on the first isolation material and the lower contact structure. A gate structure is formed on the second isolation material. A channel structure is formed horizontally adjacent to the gate structure and vertically extending through the second isolation material to the lower contact structure. The channel structure comprises a second oxide semiconducting material. A dielectric structure is formed horizontally adjacent to the channel structure and has an upper surface that is vertically recessed relative to an upper surface of the channel structure. An upper contact structure comprising a third oxide semiconducting material is formed on the channel structure and the dielectric structure.

[0114] In addition, according to an additional embodiment of the present disclosure, a transistor includes a lower contact structure, a channel structure, a dielectric fill structure, and an upper contact structure. The lower contact structure includes a first oxide semiconducting material. The channel structure is in physical contact with the lower contact structure and includes a second oxide semiconducting material, wherein the atomic concentration of one or more metals in the second oxide semiconducting material is lower than the atomic concentration of the one or more metals in the first oxide semiconducting material. The dielectric fill structure is in physical contact with the inner surface of the channel structure and has an upper surface that is vertically recessed relative to the upper surface of the channel structure. The upper contact structure includes a third oxide semiconducting material, wherein the atomic concentration of the one or more metals in the third oxide semiconducting material is relatively higher than the atomic concentration of the one or more metals in the channel structure. The upper contact structure includes a first portion in physical contact with the upper surface of the dielectric fill structure and the inner surface of the channel structure, and a second portion in physical contact with the upper surface of the channel structure.

[0115] The microelectronic device structure according to the embodiment of the present disclosure (for example, in the previous reference Figure 1K The microelectronic device structure 100 after the described processing stages may be included in a microelectronic device (eg, a memory device such as a 3D NAND flash memory device) of the present disclosure. For example, Figure 2 A simplified partial cross-sectional view of a microelectronic device 201 including a microelectronic device structure 200 is shown. The microelectronic device structure 200 may be substantially similar to that previously described with reference to FIG. Figure 1K The microelectronic device structure 100 after the described processing stages. Figure 2 and the associated description below, with reference to the previous Figures 1A to 1K Functionally similar features (eg, structures, materials, regions) of one or more of the features of the described microelectronic device structure 100 are referred to by like reference numerals incremented by 100. To avoid repetition, not Figure 2 All features presented in the are described in detail herein. Specifically, unless otherwise described below, Figure 2 In the previous reference Figures 1A to 1K Features indicated by reference numerals that are incremented by 100 with respect to one or more described features in the present disclosure will be understood to be substantially similar to, and formed in substantially the same manner as, previously described features.

[0116] like Figure 2 As shown in FIG. 2 , the microelectronic device structure 200 of the microelectronic device 201 (including the previously referenced Figures 1A to 1K One or more of the components described herein (e.g., in the Z direction) may vertically overlie (e.g., in the Z direction) a stacked structure 242 of the microelectronic device 201 and be operatively associated therewith. The stacked structure 242 includes a vertically alternating (e.g., in the Z direction) sequence of conductive structures 244 (e.g., access line plates, word line plates) and insulating structures 246 arranged in layers 248. In addition, as Figure 2 , the stacked structure 242 includes a memory array region 242A and a stepped region 242B horizontally adjacent (e.g., in the X-direction) to the memory array region 242A. As described in further detail below, the microelectronic device 201 further includes additional components (e.g., features, structures, devices) within the horizontal boundaries of the different regions of the stacked structure 242 (e.g., the memory array region 242A and the stepped region 242B).

[0117] The layers 248 of the stacked structure 242 of the microelectronic device 201 can each include at least one of the conductive structures 244 vertically adjacent to at least one of the insulating structures 246. The stacked structure 242 can include a desired number of layers 248. For example, the stacked structure 242 can include greater than or equal to eight (8) layers 248 of conductive structures 244 and insulating structures 246, greater than or equal to sixteen (16) layers 248, greater than or equal to thirty-two (32) layers 248, greater than or equal to sixty-four (64) layers 248, greater than or equal to one hundred and twenty-eight (128) layers 248, or greater than or equal to two hundred and fifty-six (256) layers 248.

[0118] The conductive structure 244 of the layer 248 of the stacked structure 242 may be formed of and include at least one conductive material, such as one or more of: at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al); at least one alloy (e.g., Co-based alloy, Fe-based alloy, Ni-based alloy, Fe and Ni-based alloy, Co and Ni-based alloy, Fe and Co-based alloy, Co and Ni and Fe-based alloy, Al-based alloy, Cu-based alloy, magnesium (Mg)-based alloy, Ti-based alloy, steel, low carbon steel, stainless steel); at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe); and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide). In some embodiments, the conductive structures 244 are formed of and include a metallic material (e.g., a metal such as W; an alloy). In additional embodiments, the conductive structures 244 are formed of and include conductively doped polysilicon. Each of the conductive structures 244 may be substantially uniform, or one or more of the conductive structures 244 may be substantially non-uniform. In some embodiments, each of the conductive structures 244 of the stacked structure 242 is substantially uniform. In additional embodiments, at least one (e.g., each) of the conductive structures 244 of the stacked structure 242 is non-uniform. Individual conductive structures 244 may, for example, be formed of and include a stack of at least two different conductive materials. The conductive structures 244 of each of the layers 248 of the stacked structure 242 may each be substantially planar and may each have a desired thickness.

[0119] The insulating structure 246 of the layer 248 of the stacked structure 242 may be formed of and include at least one dielectric material, such as one or more of: at least one dielectric oxide material (e.g., SiO x , phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlO x , HfO x 、NbO x 、TiO x 、ZrO x 、TaO x and MgO x One or more of ), at least one dielectric nitride material (e.g., SiN y ), at least one dielectric oxynitride material (e.g., SiO x N y), and at least one dielectric carbon oxynitride material (e.g., SiO x C z N y ). In some embodiments, the insulating structure 246 is formed of and includes SiO2. Each of the insulating structures 246 may be substantially uniform, or one or more of the insulating structures 246 may be substantially non-uniform. In some embodiments, each of the insulating structures 246 of the stacked structure 242 is substantially uniform. In additional embodiments, at least one (e.g., each) of the insulating structures 246 of the stacked structure 242 is non-uniform. Individual insulating structures 246 may, for example, be formed from and include a stack of at least two different dielectric materials. The insulating structures 246 of each of the layers 248 of the stacked structure 242 may each be substantially planar and may each have a desired thickness.

[0120] At least one lower conductive structure 244 of the stacked structure 242 can serve as at least one lower select gate (e.g., at least one source-side select gate (SGS)) of the microelectronic device 201. In some embodiments, a single (e.g., only one) conductive structure 244 of the vertically lowermost layer 248 of the stacked structure 242 serves as a lower select gate (e.g., SGS) of the microelectronic device 201. Additionally, an upper conductive structure 244 of the stacked structure 242 can serve as an upper select gate (e.g., drain-side select gate (SGD)) of the microelectronic device 201. In some embodiments, a horizontally adjacent (e.g., in the Y direction) conductive structure 244 of the vertically uppermost layer 248 of the stacked structure 242 serves as an upper select gate (e.g., SGD) of the microelectronic device 201.

[0121] Still refer to Figure 2Within the horizontal boundaries of the memory array region 242A of the stacked structure 242 (e.g., in the X and Y directions), the microelectronic device 201 may include pillar structures 254 extending vertically through the stacked structure 242. Each of the pillar structures 254 may include a semiconductive pillar (e.g., a polysilicon pillar, a silicon germanium pillar) at least partially surrounded by one or more charge storage structures (e.g., a charge collection structure, such as a charge collection structure comprising an oxide-nitride-oxide ("ONO") material; a floating gate structure). The intersection of the pillar structures 254 and the conductive structures 244 of the layer 248 of the stacked structure 242 may define vertically extending memory cell strings 256 coupled in series with each other within the memory array region 242A of the stacked structure 242. In some embodiments, the memory cells 256 formed at the intersection of the conductive structures 244 and the pillar structures 254 within each layer 248 of the stacked structure 242 comprise so-called "MONOS" (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cell 256 comprises a so-called "TANOS" (Tantalum Nitride-Aluminum Oxide-Nitride-Oxide-Semiconductor) memory cell, or a so-called "BETANOS" (Band / Barrier Engineered TANOS) memory cell, each of which is a subset of a MONOS memory cell. In other embodiments, the memory cell 256 comprises a so-called "floating gate" memory cell, which includes a floating gate (e.g., a metal floating gate) as a charge storage structure. The floating gate can be horizontally interposed between the pillar structures 254 of the different layers 248 of the stacked structure 242 and the central structure of the conductive structure 244. The microelectronic device 201 can include any desired number and distribution of pillar structures 254 within the memory array region 242A of the stacked structure 242.

[0122] The microelectronic device 201 may further include a digit line 262 (e.g., a data line, a bit line) vertically overlying the stack structure 242 and at least one source structure 260 (e.g., a source line, a source plate) vertically below the stack structure 242. The pillar structure 254 may extend vertically between the digit line 262 and the source structure 260. The digit line 262 and the source structure 260 may each be formed of and include at least one conductive material, such as one or more of: at least one metal (e.g., W, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Cu, Ag, Au, Al); at least one alloy (e.g., Co-based alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co, Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, mild steel, stainless steel); at least one conductively doped semiconductor material (e.g., conductively doped polysilicon, conductively doped Ge, conductively doped SiGe); and at least one conductive metal-containing material (e.g., conductive metal nitride, conductive metal silicide, conductive metal carbide, conductive metal oxide).

[0123] Continue to refer Figure 2 , within the horizontal boundaries of the stepped region 242B of the stacked structure 242, the stacked structure 242 may include at least one stepped structure 250. The stepped structure 250 includes steps 252 that are at least partially defined by the horizontal ends (e.g., in the X direction) of the layer 248. The steps 252 of the stepped structure 250 may serve as contact areas to electrically couple the conductive structure 244 of the layer 248 of the stacked structure 242 to other components (e.g., features, structures, devices) of the microelectronic device 201, as described in further detail below. The stepped structure 250 may include a desired number of steps 252. In addition, as Figure 2 , in some embodiments, the steps 252 of each of the stepped structures 250 are arranged in order such that the steps 252 that are directly horizontally adjacent to each other (e.g., in the X-direction) correspond to the layers 248 of the stacked structures 242 that are directly vertically adjacent to each other (e.g., in the Z-direction). In additional embodiments, the steps 252 of the stepped structures 250 are arranged in a disordered manner such that at least some of the steps 252 of the stepped structures 250 that are directly horizontally adjacent to each other (e.g., in the X-direction) correspond to the layers 248 of the stacked structures 242 that are not directly vertically adjacent to each other (e.g., in the Z-direction).

[0124] Still refer to Figure 2, the microelectronic device 201 may further include a lower conductive structure 204 that physically and electrically contacts at least some (e.g., each) of the steps 252 of the stepped structure 250 of the stacked structure 242 to provide electrical access to the conductive structures 244 of the stacked structure 242. The lower conductive structure 204 may be coupled to the conductive structures 244 of the layer 248 of the stacked structure 242 at the steps 252 of the stepped structure 250. The lower conductive structure 204 may correspond to the lower conductive structure 204 previously described herein with reference to Figure 1A The lower conductive structure 104 is described. Figure 2 As shown in FIG. 1 , the lower conductive structure 204 may be in physical contact with the conductive structure 244 at the step 252 of the staircase structure 250 and extend vertically upward therefrom (e.g., in the positive Z direction) to the lower contact structure 210 of the vertical transistor 240 (wherein the vertical transistor 240 including the features thereof corresponds to the previously described embodiment of the present invention). Figure 1K vertical transistor 140 as described above).

[0125] Microelectronic device 201 may further include a first isolation material 202 on or above stacked structure 242, a second isolation material 212 on or above first isolation material 202, and a third isolation material 222 on or above second isolation material 212. First isolation material 202, second isolation material 212, and third isolation material 222 may correspond to the aforementioned reference numerals. Figures 1A to 1K The first isolation material 102, the second isolation material 112 and the third isolation material 122 are described. Figure 2 , the first isolation material 202 may be vertically interposed (e.g., in the Z direction) between the stack structure 242 and the second isolation material 212. The first isolation material 202 may substantially cover the stepped structure 250 within the stepped region 242B of the stack structure 242 and may substantially surround the side surfaces (e.g., sidewalls) of the lower conductive structure 204 on the steps 252 of the stepped structure 250. The first isolation material 202 may present a substantially planar upper vertical boundary and a substantially non-planar lower vertical boundary that is complementary to the surface shape of at least the stack structure 242 (including the stepped structure 250) thereunder.

[0126] like Figure 2As shown in FIG, vertical transistor 240 (including its lower contact structure 210, gate structure 220, gate dielectric structure 226, channel structure 228, dielectric fill structure 230, and upper contact structure 236) can be vertically located (e.g., in the Z direction) above and at least partially (e.g., substantially) within the horizontal boundaries (e.g., in the X and Y directions) of step region 242B of stacked structure 242. Vertical transistor 240 and upper conductive structure 238 can, for example, be used as part of a driver assembly (e.g., a string driver assembly) for microelectronic device 201. As described in further detail below, vertical transistor 240 can, for example, be used as a driver transistor (e.g., a string driver transistor) for microelectronic device 201. Vertical transistor 240 can be electrically coupled to conductive structure 244 of stacked structure 242 by means of lower conductive structure 204.

[0127] although Figure 2 The vertical transistors 240 of the microelectronic device 201 are depicted as being within the horizontal boundaries (e.g., in the X direction, in the Y direction) of the stepped region 242B of the stacked structure 242 of the microelectronic device 201, but one or more portions of the vertical transistors 240 may be located outside the horizontal boundaries of the stepped region 242B of the stacked structure 242 of the microelectronic device 201. For example, one or more (e.g., all, less than all) of the vertical transistors 240 may be located outside the horizontal boundaries of the stepped region 242B of the stacked structure 242. In such embodiments, the vertical transistors 240 may be located relative to the horizontal boundaries of the stepped region 242B. Figure 2 The geometric configuration depicted in the figure is modified to facilitate electrical connection between the one or more vertical transistors 240 and one or more conductive structures 244 of the stacked structure 242 by modifying the geometric configuration of the lower conductive structure 204 and the upper conductive structure 238 connected (e.g., physically connected, electrically connected) to one or more of the vertical transistors 240.

[0128] Therefore, according to an embodiment of the present disclosure, a microelectronic device includes a first conductive structure, a first contact structure, a channel structure, a second contact structure, a second conductive structure, a conductive gate structure, a gate, and a dielectric structure. The first conductive structure extends vertically through a first isolation material. The first contact structure is on the first conductive structure. Each of the first contact structures comprises an oxide semiconducting material. The channel structure is on the first contact structure and extends vertically through a second isolation material on the first isolation material and a third isolation material on the second isolation material. Each of the channel structures comprises an additional oxide semiconducting material having a relatively lower metal concentration and a relatively higher oxygen concentration than the metal concentration and oxygen concentration in the oxide semiconducting material. The second contact structure is on the channel structure. Each of the second contact structures comprises the oxide semiconducting material. The second conductive structure is on the second contact structure. The conductive gate structure is on the second isolation material and horizontally adjacent to the channel structure. The gate dielectric structure is horizontally interposed between the channel structure and the conductive gate structure.

[0129] Furthermore, according to an additional embodiment of the present disclosure, a memory device includes a stacked structure, a stepped structure, a conductive pillar structure, a string driver transistor, and a string of memory cells. The stacked structure includes a vertically alternating sequence of conductive structures and insulating structures arranged in layers. The stepped structure is within the stacked structure and has a step including an edge of the layer. The conductive structure is on the step of the stepped structure. The string driver transistor vertically overlies the stepped structure. Each of the string driver transistors includes a first contact structure, a channel structure, a second contact structure, a gate dielectric structure, and a gate electrode. The first contact structure is on one of the conductive structures and includes a first indium-containing oxide semiconducting material. The channel structure is on the first contact structure and includes a second indium-containing oxide semiconducting material having less indium than the first indium-containing oxide semiconducting material. The second contact structure is on the channel structure and includes a third indium-containing oxide semiconducting material having more indium than the second indium-containing oxide semiconducting material. The gate dielectric structure is horizontally adjacent to an outer sidewall of the channel structure. The gate electrode is horizontally adjacent to an outer sidewall of the gate dielectric structure. The string of memory cells extends vertically through the stacked structure.

[0130] The microelectronic device structure according to the embodiment of the present disclosure (for example, the previously referenced Figure 1K The microelectronic device structure 100 described above and the microelectronic device (eg, previously described with reference to Figure 2 The microelectronic device 201 described herein may be used in embodiments of the electronic system of the present disclosure. For example, Figure 3is a block diagram of an exemplary electronic system 300 according to an embodiment of the present disclosure. The electronic system 300 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a tablet computer with Wi-Fi or cellular capabilities (e.g., or Tablet computers), electronic books, navigation devices, etc. The electronic system 300 includes at least one memory device 302. The memory device 302 may include, for example, a microelectronic device structure previously described herein (e.g., previously referenced Figure 1K The microelectronic device structure 100 described above and the microelectronic device (eg, previously described with reference to Figure 2 The electronic system 300 may further include at least one electronic signal processing device 304 (often referred to as a "microprocessor"). The electronic signal processing device 304 may optionally include a microelectronic device structure (e.g., as previously described with reference to FIG. Figure 1K The microelectronic device structure 100 described above and the microelectronic device (eg, previously described with reference to Figure 2 Although the memory device 302 and the electronic signal processing device 304 are depicted as Figure 3 304, but in additional embodiments, a single (e.g., only one) memory / processor device having the functionality of the memory device 302 and the electronic signal processor device 304 is included in the electronic system 300. In such embodiments, the memory / processor device may include a microelectronic device structure previously described herein (e.g., previously described with reference to FIG. Figure 1K The microelectronic device structure 100 described above and the microelectronic device (eg, previously described with reference to Figure 2 The electronic system 300 may further include one or more input devices 306 for inputting information into the electronic system 300 by a user, such as a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel. The electronic system 300 may further include one or more output devices 308 for outputting information (e.g., visual or audio output) to the user, such as a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device 306 and the output device 308 may include a single touch screen device that can be used to input information to the electronic system 300 and output visual information to the user. The input device 306 and the output device 308 may be in electrical communication with one or more of the memory device 302 and the electronic signal processor device 304.

[0131] Therefore, according to an embodiment of the present disclosure, an electronic system includes an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device includes a stacked structure, a memory cell string, a conductive pillar structure, and a transistor. The stacked structure has a layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure. The stacked structure includes: a stepped region including a stepped structure having a step including a horizontal end of the layer; and a memory array region horizontally adjacent to the stepped region. The memory cell string is within the memory array region of the stacked structure. The conductive pillar structure is on the step of the stepped structure. The transistor vertically overlaps and is within the horizontal boundary of the stepped region of the stacked structure. Each of the transistors includes a lower contact structure, a channel structure, a dielectric structure, an upper contact structure, a gate dielectric structure, and a gate electrode. The lower contact structure is electrically coupled to one of the conductive pillar structures and includes indium and oxygen. The trench structure is above the lower contact structure and includes less indium and more oxygen than the lower contact structure. The dielectric structure is directly adjacent to a sidewall of the trench structure and has an upper surface that is recessed relative to the trench structure. The upper contact structure is above the trench structure and the dielectric structure and includes more indium and less oxygen than the trench structure. The gate dielectric structure is directly adjacent to an additional sidewall of the trench structure. The gate electrode is directly adjacent to a sidewall of the gate dielectric structure.

[0132] The structures, devices, and systems of the present disclosure advantageously facilitate one or more of improved simplicity of assembly, greater packaging density, and enhanced miniaturization compared to conventional structures, conventional devices, and conventional systems. The methods and structures of the present disclosure facilitate the formation of devices (e.g., transistors, microelectronic devices, memory devices) and systems (e.g., electronic systems) that have one or more of the following: enhanced performance, improved on-state current characteristics, more components, less component congestion, smaller horizontal size, increased efficiency, enhanced reliability, and enhanced durability compared to conventional devices (e.g., conventional transistors, conventional microelectronic devices, conventional memory devices) and conventional systems (e.g., conventional electronic systems).

[0133] Non-limiting example embodiments may include:

[0134] Embodiment 1: A transistor, comprising: a lower contact structure comprising a first oxide semiconducting material; a channel structure, which is in physical contact with the lower contact structure and comprises a second oxide semiconducting material, the atomic concentration of one or more metals in the second oxide semiconducting material being lower than the atomic concentration of the one or more metals in the first oxide semiconducting material; a dielectric filling structure, which is in physical contact with the inner surface of the channel structure and has an upper surface that is vertically recessed relative to the upper surface of the channel structure; and an upper contact structure comprising a third oxide semiconducting material, the atomic concentration of the one or more metals in the third oxide semiconducting material being higher than the atomic concentration of the one or more metals in the channel structure, the upper contact structure comprising: a first portion, which is in physical contact with the upper surface of the dielectric filling structure and the inner surface of the channel structure; and a second portion, which is in physical contact with the upper surface of the channel structure.

[0135] Embodiment 2: The transistor according to embodiment 1 further comprises: a gate dielectric structure in physical contact with an outer side surface of the channel structure; and at least one gate electrode in physical contact with at least one outer side surface of the gate dielectric structure.

[0136] Embodiment 3: A transistor according to any one of Embodiments 1 and 2, wherein: the first oxide semiconductive material includes a first atomic concentration of indium; the second oxide semiconductive material includes a second atomic concentration of indium that is less than the first atomic concentration of indium; and the third oxide semiconductive material includes a third atomic concentration of indium that is greater than the second atomic concentration of indium.

[0137] Embodiment 4: The transistor of Embodiment 3, wherein the first oxide semiconducting material, the second oxide semiconducting material, and the third oxide semiconducting material each comprise indium gallium zinc oxide.

[0138] Embodiment 5: The transistor of Embodiment 3, wherein: the first oxide semiconducting material comprises indium oxide; the second oxide semiconducting material comprises indium gallium zinc oxide; and the third oxide semiconducting material comprises additional indium oxide.

[0139] Embodiment 6: The transistor of Embodiment 3, wherein the first atomic concentration of indium is substantially equal to the third atomic concentration of indium.

[0140] Embodiment 7: The transistor of Embodiment 3, wherein the lower contact structure and the upper contact structure are each non-uniform due to an amount of the one or more metals increasing within the lower contact structure and the upper contact structure in a direction extending away from the channel structure.

[0141] Embodiment 8: The transistor of Embodiment 3, wherein the lower contact structure and the upper contact structure are each substantially uniform.

[0142] Embodiment 9: The transistor of Embodiment 3, wherein the first portion of the upper contact structure extends vertically from and is integral and continuous with the second portion of the upper contact structure.

[0143] Embodiment 10: A microelectronic device comprising: a first conductive structure extending vertically through a first isolation material; a first contact structure on the first conductive structure, each of the first contact structures comprising an oxide semiconductive material; a channel structure on the first contact structure and extending vertically through a second isolation material on the first isolation material and a third isolation material on the second isolation material, each of the channel structures comprising an additional oxide semiconductive material having a relatively smaller metal concentration and a relatively larger oxygen concentration than the metal concentration and oxygen concentration in the oxide semiconductive material; a second contact structure on the channel structure, each of the second contact structures comprising the oxide semiconductive material; a second conductive structure on the second contact structure; a conductive gate structure on the second isolation material and horizontally adjacent to the channel structure; and a gate dielectric structure horizontally inserted between the channel structure and the conductive gate structure.

[0144] Embodiment 11: The microelectronic device of Embodiment 10, further comprising a dielectric structure directly horizontally adjacent to the channel structure and having an upper surface recessed relative to the channel structure, the second contact structure being in physical contact with the dielectric structure and the channel structure.

[0145] Embodiment 12: The microelectronic device of Embodiment 11, wherein for each of the trench structures, one of the dielectric structures is horizontally interposed between different portions of the trench structures.

[0146] Embodiment 13: A microelectronic device according to embodiment 11, wherein the second contact structure includes: a lower portion, which is on the upper surface of the dielectric structure and in physical contact with the side surface of the channel structure; and an upper portion, which is integral and continuous with the lower portion and is on the upper surface of the channel structure.

[0147] Embodiment 14: The microelectronic device of any one of Embodiments 10 to 13, wherein the second isolation material has a different material composition than the first isolation material and the third isolation material.

[0148] Embodiment 15: The microelectronic device of any one of Embodiments 10 to 14, wherein the first contact structure, the channel structure, and the second contact structure each include indium, the first contact structure and the second contact structure being enriched in indium compared to the channel structure.

[0149] Embodiment 16: A method for forming a microelectronic device, comprising: forming a lower contact structure comprising a first oxide semiconductive material on a conductive structure extending vertically through a first isolation material; forming a second isolation material on the first isolation material and the lower contact structure; forming a gate structure on the second isolation material; forming a channel structure horizontally adjacent to the gate structure and extending vertically through the second isolation material to the lower contact structure, the channel structure comprising a second oxide semiconductive material; forming a dielectric structure horizontally adjacent to the channel structure, the dielectric structure having an upper surface vertically recessed relative to an upper surface of the channel structure; and forming an upper contact structure comprising a third oxide semiconductive material on the channel structure and the dielectric structure.

[0150] Embodiment 17: The method of embodiment 16, wherein forming a gate structure comprises: forming a sacrificial material on the second isolation material; patterning the sacrificial material to form a sacrificial structure at least partially within the horizontal boundary of the lower contact structure; and forming the gate structure to be horizontally adjacent to the sacrificial structure.

[0151] Embodiment 18: A method according to embodiment 17, wherein forming a channel structure includes: forming a third isolation material on the second isolation material that horizontally surrounds the gate structure and the sacrificial structure; selectively removing the sacrificial structure and a portion of the second isolation material vertically located thereunder to form an opening, wherein the opening is horizontally adjacent to the gate structure and vertically extends through the third isolation material and the second isolation material to reach the upper surface of the lower contact structure; and forming the channel structure within the opening and on the upper surface of the lower contact structure.

[0152] Embodiment 19: The method of Embodiment 18, further comprising forming a gate dielectric structure within the opening and horizontally interposed between the gate structure and the channel structure.

[0153] Embodiment 20: The method according to embodiments 18 and 19, wherein forming the dielectric structure comprises: filling the portion of the opening not occupied by the channel structure with a dielectric material; and selectively removing an upper portion of the dielectric material to form a recess horizontally adjacent to the upper portion of the channel structure.

[0154] Example 21: A method according to Example 20, wherein forming an upper contact structure includes: forming the third oxide semiconductive material to fill the recess and cover the upper surface of the channel structure and the third isolation material outside the recess; and removing a portion of the third oxide semiconductive material on the third isolation material.

[0155] Embodiment 22: A method according to any one of embodiments 16 to 21, wherein: forming the channel structure includes forming the second oxide semiconductive material of the channel structure to be less indium than the indium in the first oxide semiconductive material of the lower contact structure; and forming the upper contact structure includes forming the third oxide semiconductive material of the upper contact structure to be rich in indium compared to the indium in the second oxide semiconductive material of the channel structure.

[0156] Embodiment 23: A memory device comprising: a stacked structure comprising a vertically alternating sequence of conductive structures and insulating structures arranged in layers; a stepped structure within the stacked structure and having steps including edges of the layers; a conductive pillar structure on the steps of the stepped structure; a string driver transistor vertically covering the stepped structure, each of the string driver transistors comprising: a first contact structure on one of the conductive pillar structures and comprising a first indium-containing oxide semiconducting material; a channel structure on the first contact structure and comprising a second indium-containing oxide semiconducting material having less indium than the first indium-containing oxide semiconducting material; a second contact structure on the channel structure and comprising a third indium-containing oxide semiconducting material having more indium than the second indium-containing oxide semiconducting material; a gate dielectric structure horizontally adjacent to an outer sidewall of the channel structure; and a gate electrode horizontally adjacent to an outer sidewall of the gate dielectric structure; and a memory cell string extending vertically through the stacked structure.

[0157] Embodiment 24: A memory device according to embodiment 23, wherein each of the string driver transistors further includes a dielectric structure directly horizontally adjacent to an inner sidewall of the channel structure, the dielectric structure having an upper surface that is recessed relative to an upper surface of the channel structure and directly vertically adjacent to the second contact structure.

[0158] Embodiment 25: An electronic system comprising: an input device; an output device; a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device and comprising: a stacked structure having a layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, the stacked structure comprising: a stepped region including a stepped structure having a step including a horizontal end of the layer; and a memory array region horizontally adjacent to the stepped region; a memory cell string within the memory array region of the stacked structure; a conductive pillar structure on the step of the stepped structure; and a transistor vertically covering At and within the horizontal boundary of the stepped region of the stacked structure, the transistors each include: a lower contact structure electrically coupled to one of the conductive pillar structures and including indium and oxygen; a channel structure on the lower contact structure and including less indium and more oxygen than the lower contact structure; a dielectric structure directly adjacent to the sidewalls of the channel structure and having an upper surface recessed relative to the channel structure; an upper contact structure on the channel structure and the dielectric structure and including more indium and less oxygen than the channel structure; a gate dielectric structure directly adjacent to an additional sidewall of the channel structure; and a gate electrode directly adjacent to the sidewalls of the gate dielectric structure.

[0159] While the present disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, the present disclosure is not limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the scope of the following claims, as well as their legal equivalents.

Claims

1. A transistor comprising: a lower contact structure comprising a first oxide semiconducting material having a first atomic concentration of indium; a channel structure in physical contact with the lower contact structure and comprising a second oxide semiconductive material having a second atomic concentration of indium less than the first atomic concentration of indium; a dielectric filling structure in physical contact with an inner side surface of the trench structure and having an upper surface vertically recessed relative to an upper surface of the trench structure; as well as an upper contact structure comprising a third oxide semiconductive material having a third atomic concentration of indium greater than the second atomic concentration of indium, the amount of indium in each of the upper contact structure and the lower contact structure being non-uniform and increasing in a direction extending away from the channel structure, the upper contact structure comprising: a first portion in physical contact with the upper surface of the dielectric fill structure and the inner side surface of the trench structure; as well as A second portion is in physical contact with the upper surface of the channel structure.

2. The transistor according to claim 1, comprising: a gate dielectric structure in physical contact with an outer surface of the channel structure; as well as At least one gate electrode is in physical contact with at least one outer side surface of the gate dielectric structure. 3 . The transistor of claim 1 , wherein the first oxide semiconducting material, the second oxide semiconducting material, and the third oxide semiconducting material each comprise indium gallium zinc oxide.

4. The transistor according to claim 1, wherein: The first oxide semiconductive material includes indium oxide; The second oxide semiconducting material comprises indium gallium zinc oxide; and The third oxide semiconductive material includes indium oxide.

5. The transistor of claim 1, wherein the first atomic concentration of indium is substantially equal to the third atomic concentration of indium. 6 . The transistor of claim 1 , wherein the first portion of the upper contact structure extends vertically from and is integral and continuous with the second portion of the upper contact structure.

7. A microelectronic device comprising: a first conductive structure extending vertically through the first isolation material; first contact structures on the first conductive structure, the first contact structures each comprising a first oxide semiconductive material having a first atomic concentration of indium; a channel structure on the first contact structure and extending vertically through a second isolation material on the first isolation material and a third isolation material on the second isolation material, each of the channel structures comprising a second oxide semiconductive material having a relatively greater oxygen concentration than the first oxide semiconductive material and a second atomic concentration of indium that is less than the first atomic concentration of indium; a second contact structure on the channel structure, each of the second contact structures comprising a third oxide semiconductive material having a third atomic concentration of indium greater than the second atomic concentration of indium, an amount of indium in each of the second contact structure and the first contact structure being non-uniform and increasing in a direction extending away from the channel structure; a second conductive structure on the second contact structure; a conductive gate structure on the second isolation material and horizontally adjacent to the channel structure; as well as A gate dielectric structure is horizontally interposed between the channel structure and the conductive gate structure.

8. The microelectronic device of claim 7, comprising a dielectric structure directly horizontally adjacent to the channel structure and having an upper surface recessed relative to the channel structure, the second contact structure being in physical contact with both the dielectric structure and the channel structure. 9 . The microelectronic device of claim 8 , wherein for each of the trench structures, one of the dielectric structures is horizontally interposed between different portions of the trench structure.

10. The microelectronic device according to claim 8, wherein the second contact structure comprises: a lower portion on an upper surface of the dielectric structure and in physical contact with a side surface of the channel structure; as well as An upper portion is integral with and continuous with the lower portion and is on an upper surface of the channel structure.

11. The microelectronic device of claim 7, wherein the second isolation material has a different material composition than the first isolation material and the third isolation material.

12. A method of forming a microelectronic device, comprising: forming a lower contact structure comprising a first oxide semiconductive material having a first atomic concentration of indium on the conductive structure extending vertically through the first isolation material; forming a second isolation material on the first isolation material and the lower contact structure; forming a gate structure on the second isolation material; forming a channel structure horizontally adjacent to the gate structure and extending vertically through the second isolation material to the lower contact structure, the channel structure comprising a second oxide semiconductive material having a second atomic concentration of indium less than the first atomic concentration of indium; forming a dielectric structure horizontally adjacent to the trench structure, the dielectric structure having an upper surface vertically recessed relative to an upper surface of the trench structure; as well as An upper contact structure including a third oxide semiconductive material is formed on the channel structure and the dielectric structure, the third oxide semiconductive material having a third atomic concentration of indium greater than the second atomic concentration of indium, the amount of indium in each of the upper contact structure and the lower contact structure being non-uniform and increasing in a direction extending away from the channel structure.

13. The method according to claim 12, wherein forming the gate structure comprises: forming a sacrificial material on the second isolation material; patterning the sacrificial material to form a sacrificial structure at least partially within a horizontal boundary of the lower contact structure; as well as The gate structure is formed to be horizontally adjacent to the sacrificial structure.

14. The method according to claim 13, wherein forming the channel structure comprises: forming a third isolation material on the second isolation material to horizontally surround the gate structure and the sacrificial structure; selectively removing the sacrificial structure and a portion of the second isolation material vertically thereunder to form an opening, the opening being horizontally adjacent to the gate structure and vertically extending through the third isolation material and the second isolation material to an upper surface of the lower contact structure; as well as The trench structure is formed within the opening and on the upper surface of the lower contact structure.

15. The method of claim 14, comprising forming a gate dielectric structure within the opening and horizontally interposed between the gate structure and the channel structure.

16. The method of claim 14, wherein forming a dielectric structure comprises: filling the portion of the opening not occupied by the trench structure with a dielectric material; as well as An upper portion of the dielectric material is selectively removed to form a recess horizontally adjacent to the upper portion of the trench structure.

17. The method of claim 16, wherein forming the upper contact structure comprises: forming the third oxide semiconductive material to fill the recess and cover an upper surface of the channel structure and the third isolation material outside the recess; as well as A portion of the third oxide semiconductive material on the third isolation material is removed.

18. The method of claim 12, wherein: forming the channel structure includes forming the second oxide semiconducting material of the channel structure to have less indium than the first oxide semiconducting material of the lower contact structure; and Forming an upper contact structure includes forming the third oxide semiconducting material of the upper contact structure to have more indium than the second oxide semiconducting material of the channel structure.

19. A memory device comprising: a stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in layers; a stepped structure within the stacked structure and having a step including an edge of the layer; a conductive pillar structure, which is on the step of the stepped structure; string driver transistors vertically covering the ladder structure, each of the string driver transistors comprising: a first contact structure on one of the conductive pillar structures and comprising a first indium-containing oxide semiconductive material having a first atomic concentration of indium; a channel structure on the first contact structure and comprising a second indium-containing oxide semiconducting material having a second atomic concentration of indium less than the first atomic concentration of indium; a second contact structure on the channel structure and comprising a third indium-containing oxide semiconductive material, the third indium-containing oxide semiconductive material having a third atomic concentration of indium greater than the second atomic concentration of indium, the amount of indium in each of the first and second contact structures being non-uniform and increasing in a direction extending away from the channel structure; a gate dielectric structure horizontally adjacent to an outer sidewall of the channel structure; and a gate electrode horizontally adjacent to an outer sidewall of the gate dielectric structure; and A memory cell string extends vertically through the stacked structure.

20. The memory device of claim 19, wherein each of the string driver transistors includes a dielectric structure directly horizontally adjacent to an inner sidewall of the channel structure, the dielectric structure having an upper surface that is recessed relative to an upper surface of the channel structure and directly vertically adjacent to the second contact structure.

21. An electronic system comprising: input device; output device; a processor device operatively coupled to the input device and the output device; as well as a memory device operatively coupled to the processor device and comprising: A stacked structure having a layer including a conductive structure and an insulating structure vertically adjacent to the conductive structure, the stacked structure comprising: a stepped region comprising a stepped structure having steps including horizontal ends of the layers; and a memory array region horizontally adjacent to the staircase region; a memory cell string within the memory array region of the stacked structure; a conductive pillar structure on the step of the stepped structure; and transistors vertically covering and within a horizontal boundary of the stepped region of the stacked structure, each of the transistors comprising: a lower contact structure electrically coupled to one of the conductive pillar structures and comprising indium and oxygen, the lower contact structure having a first atomic concentration of indium; a channel structure on the lower contact structure, the channel structure having more oxygen than the lower contact structure and having a second atomic concentration of indium less than the first atomic concentration of indium; a dielectric structure directly adjacent to a sidewall of the trench structure and having an upper surface that is recessed relative to the trench structure; an upper contact structure over the trench structure and the dielectric structure, the upper contact structure having less oxygen than the trench structure and a third atomic concentration of indium greater than the second atomic concentration of indium, the amount of indium in each of the upper contact structure and the lower contact structure being non-uniform and increasing in a direction extending away from the trench structure; a gate dielectric structure directly adjacent to a sidewall of the channel structure; and A gate electrode is directly adjacent to a sidewall of the gate dielectric structure.

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