Method for removing barrier layer

Abstract

The present invention discloses a method for removing a barrier layer from a metal interconnect on a silicon wafer. Removing a single-layer ruthenium barrier layer includes: an oxidation step, in which the single-layer ruthenium barrier layer is oxidized into a ruthenium oxide layer using an electrochemical anodic oxidation process; an oxide layer etching step, in which the ruthenium oxide layer is etched with an etching solution to remove the ruthenium oxide layer. The present invention also provides a method for removing a barrier layer from a metal interconnect on a silicon wafer, which is used in structures with process nodes of 10nm and below. The structure includes a substrate, a dielectric layer, a barrier layer, and a metal layer. The dielectric layer is deposited on the substrate, a recessed region is formed in the dielectric layer, the barrier layer is deposited on the dielectric layer, and the metal layer is deposited on the barrier layer. The metal layer is a copper layer, and the barrier layer is a single-layer ruthenium metal layer. The method includes: a thinning step, in which the metal layer is thinned; a removal step, in which the metal layer is removed; an oxidation step, in which the barrier layer is oxidized using an electrochemical anodic oxidation process; and an oxide layer etching step, in which the oxidized barrier layer is etched.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly, to the field of semiconductor manufacturing technology. Background Art

[0002] As integrated circuit (IC) feature sizes gradually shrink to below 14nm, current development focuses on manufacturing technologies for process nodes at and below 10nm. At these nodes, in the back-end-of-line (BEOL) interconnect process, the traditional Ta / TaN double-layer barrier structure encounters problems such as a sharp increase in interconnect resistance and uneven copper seed layer deposition when used on copper interconnects.

[0003] To overcome these issues, ruthenium (Ru), due to its excellent electrochemical properties, has been chosen as a barrier layer for copper interconnects in next-generation IC manufacturing. Compared to Ta and TaN, Ru has lower resistivity and excellent adhesion to copper. Furthermore, copper can be deposited evenly and easily on a ruthenium layer.

[0004] The barrier layer lies between the metal layer and the dielectric layer. During the manufacturing process, portions of the barrier layer need to be removed while others remain. Because the barrier layer is typically covered by a metal layer, the metal layer must be removed first, followed by the barrier layer. Grinding and etching processes are the primary methods used to remove material layers in semiconductor manufacturing.

[0005] Chemical mechanical polishing (CMP) is the most commonly used polishing process, widely used to remove excess material layers and create a flat surface for the next metallization layer. CMP primarily removes material through mechanical pressure, so it has no specific requirements for the material's chemical properties. CMP can be applied to remove metal layers or barrier layers, including a variety of metals such as Cu, Ta, TaN, and Ru. For ruthenium, oxidizing agents such as H2O2 in the polishing slurry can produce ruthenium oxide, which is then polished away. Because the CMP process relies on mechanical pressure, the wafer is pressed against the polishing pad using downward force. The wafer is subjected to significant pressure during polishing, which can easily cause defects such as scratches, metal corrosion wear, and even stress fragmentation. At process nodes below 10nm, the density of IC structures on the wafer increases significantly, and the wafer's ability to withstand mechanical stress decreases. The mechanical pressure of CMP can cause greater damage to the wafer and IC structures. Furthermore, the CMP polishing process consumes large amounts of consumables such as polishing slurry and polishing pads, making the process costly.

[0006] To address the issue of mechanical stress, stress-free polishing (SFP) technology has been developed. SFP is a process for electrolytically polishing metal. Through an electrochemical reaction, the metal is oxidized into metal ions that enter the polishing solution, thereby removing the metal from the wafer surface. SFP is commonly used for polishing copper and is often used to remove metal layers. The SFP process primarily relies on electrochemical reactions to remove metal layers. The advantage of SFP is that no external force is applied to the wafer during the process, avoiding common CMP defects such as scratches, metal corrosion and wear. In addition, the polishing solution used in SFP can be recycled, significantly reducing process costs.

[0007] Because barrier layer materials, such as Ta, TaN, and Ru, are generally chemically stable and react weakly with most chemicals, with only specific chemical agents exhibiting high reaction rates, SFP is rarely used for direct barrier layer removal. Besides CMP, chemical etching is often used for barrier layer removal. HF is the most commonly used etchant for barrier layer removal, as it has a good etch rate for both Ta and TaN.

[0008] However, when the barrier layer is made of ruthenium metal, the situation changes. This is because ruthenium metal is very stable and its reaction rate with the commonly used SFP electrolyte (phosphoric acid) and HF is very low. Experimental data show that:

[0009] When the ruthenium metal Ru is used as an electrolyte with a mass fraction of 30% to 70% phosphoric acid and an applied current of 5A, the removal amount within a 60s cycle is 3.2 angstroms.

[0010] When HF with a mass fraction of 0.01% to 0.4% is used as an etchant, the amount of metal ruthenium Ru removed within a 60s cycle is 2.6 angstroms.

[0011] Both SFP electrolyte and HF have low etching rates for ruthenium metal, failing to meet process requirements. Developing a new etchant suitable for Ru would require a long time from R&D to mass production, failing to meet demand in the short term. Therefore, improving Ru removal efficiency from a process perspective is a more practical option. Summary of the Invention

[0012] The present invention provides a method for removing a metal ruthenium barrier layer.

[0013] According to one embodiment of the present invention, a method for removing a barrier layer of a metal interconnect on a silicon wafer is provided, which is used for process nodes of 10 nm and below and is used to remove a single-layer metal ruthenium barrier layer deposited between a dielectric layer and a copper layer. The method comprises:

[0014] an oxidation step of oxidizing the single-layer metal ruthenium barrier layer into a ruthenium oxide layer, wherein the oxidation step uses an electrochemical anodic oxidation process to oxidize the metal ruthenium barrier layer;

[0015] The oxide layer etching step uses an etching solution to etch the ruthenium oxide layer to remove the ruthenium oxide layer.

[0016] In one embodiment, the electrochemical anodization process performs electrochemical anodization from the center to the edge of the silicon wafer through a cathode nozzle, or performs electrochemical anodization from the edge to the center of the silicon wafer. The electrolyte used in the electrochemical anodization process is phosphoric acid with a mass fraction of 30% to 70%, and the applied current is 0A to 5A.

[0017] In one embodiment, the etching solution used in the oxide layer etching step is HF with a mass fraction of 0.01% to 1wt%, and the etching rate ratio of the etching solution to the ruthenium oxide layer and the dielectric layer is greater than 0.62:1.

[0018] According to one embodiment of the present invention, a method for removing a barrier layer of a metal interconnect on a silicon wafer is provided. The method is used in a structure with a process node of 10 nm or below. The structure includes a substrate, a dielectric layer, a barrier layer, and a metal layer. The dielectric layer is deposited on the substrate, a recessed region is formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, and the metal layer is deposited on the barrier layer. The metal layer is a copper layer, and the barrier layer is a single-layer ruthenium metal layer. The method includes:

[0019] a thinning step of thinning the metal layer, removing most of the metal layer and leaving a continuous metal layer on the surface of the barrier layer;

[0020] a removing step of removing the metal layer on the non-recessed area to expose the barrier layer, and retaining a reserved thickness of the metal layer on the recessed area;

[0021] an oxidation step of oxidizing the single-layer metal ruthenium barrier layer on the non-recessed area into a ruthenium oxide layer, while removing the metal layer remaining on the recessed area, wherein the oxidation step uses an electrochemical anodization process;

[0022] In the oxide layer etching step, the ruthenium oxide layer on the non-recessed area is etched with an etching solution to remove the ruthenium oxide layer, so that the recessed area and the non-recessed area have a flat surface after etching.

[0023] In one embodiment, during the thinning step, a continuous metal layer with a thickness of 500-1000 angstroms is left on the surface of the barrier layer, wherein the thickness of the metal layer on the recessed area is greater than that on the non-recessed area.

[0024] In one embodiment, the electrochemical anodization process performs electrochemical anodization from the center to the edge of the silicon wafer through a cathode nozzle, or performs electrochemical anodization from the edge to the center of the silicon wafer. The electrolyte used in the electrochemical anodization process is phosphoric acid with a mass fraction of 30% to 70%, and the applied current is 0A to 5A.

[0025] In one embodiment, the electrolyte used in the electrochemical anodization process removes the copper layer while oxidizing the metallic ruthenium barrier layer, wherein:

[0026] (Oxidation rate of metal ruthenium / removal rate of copper) = (thickness of metal ruthenium barrier layer / reserved thickness of copper layer on recessed area).

[0027] In one embodiment, the etching solution used in the oxide layer etching step is HF with a mass fraction of 0.01% to 1wt%, and the etching rate ratio of the etching solution to the ruthenium oxide layer and the dielectric layer is greater than 0.62:1.

[0028] According to one embodiment of the present invention, a method for removing a barrier layer of a metal interconnect on a silicon wafer is provided. The method is used in a structure with a process node of 10 nm or below. The structure includes a substrate, a dielectric layer, a barrier layer, and a metal layer. The dielectric layer is deposited on the substrate, a recessed region is formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, and the metal layer is deposited on the barrier layer. The metal layer is a copper layer, and the barrier layer is a single-layer ruthenium metal layer. The method includes:

[0029] Using CMP to thin the metal layer to a thickness below 2000 angstroms while maintaining a continuous metal layer;

[0030] Using an electrochemical anodic oxidation process to remove the metal layer on the non-recessed area and oxidize the single-layer metal ruthenium barrier layer on the non-recessed area into a ruthenium oxide layer;

[0031] The ruthenium oxide layer on the non-recessed area is etched with an etching solution to remove the ruthenium oxide layer, so that the recessed area and the non-recessed area have flat surfaces after etching.

[0032] According to one embodiment of the present invention, a method for removing a barrier layer of a metal interconnect on a silicon wafer is provided. The method is used in a structure with a process node of 10 nm or below. The structure includes a substrate, a dielectric layer, a barrier layer, and a metal layer. The dielectric layer is deposited on the substrate, a recessed region is formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, and the metal layer is deposited on the barrier layer. The metal layer is a copper layer, and the barrier layer is a single-layer ruthenium metal layer. The method includes:

[0033] Using CMP to remove all the metal layers on the non-recessed area until the barrier layer is exposed;

[0034] The single-layer metal ruthenium barrier layer on the non-recessed area is oxidized into a ruthenium oxide layer by an electrochemical anodic oxidation process;

[0035] The ruthenium oxide layer on the non-recessed area is etched with an etching solution to remove the ruthenium oxide layer, so that the recessed area and the non-recessed area have flat surfaces after etching.

[0036] The barrier layer removal method of the present invention employs an oxidation-first, then etching approach, effectively addressing the issue of low ruthenium metal removal efficiency. The reaction rate of the oxidized ruthenium oxide with HF meets process requirements. Furthermore, by adjusting the HF concentration, the removal selectivity of the barrier layer and dielectric layer can be adjusted. The present invention utilizes electrochemical anodic oxidation, such as the SFP process, to achieve oxidation of ruthenium metal, resulting in a highly efficient and cost-effective overall process. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A flow chart of a method for removing a barrier layer of a metal interconnect on a silicon wafer according to an embodiment of the present invention is disclosed.

[0038] Figure 2 Revealed Figure 1 The embodiment shown is directed to the removal effect of metallic ruthenium.

[0039] Figure 3a and Figure 3b Revealed Figure 1 Comparison diagram before and after implementation of the embodiment shown.

[0040] Figure 4 A flow chart of a method for removing a barrier layer of a metal interconnection on a silicon wafer according to another embodiment of the present invention is disclosed.

[0041] Figure 5a 、 5b , 5c and 5d reveal Figure 4 The implementation process of the embodiment shown.

[0042] Figure 6a Schematic diagram of electrochemical anodization from the center to the edge of a silicon wafer through a cathode showerhead.

[0043] Figure 6b Schematic diagram of electrochemical anodization from the edge to the center of a silicon wafer through a cathode showerhead. DETAILED DESCRIPTION

[0044] First reference Figure 1 As shown, Figure 1 A flow chart of a method for removing a barrier layer of a metal interconnect on a silicon wafer according to an embodiment of the present invention is disclosed. Figure 1The method for removing a barrier layer from a metal interconnect on a silicon wafer can be considered a laboratory verification method to verify the removal performance of a ruthenium metal layer. This barrier layer removal method is used for process nodes of 10nm and below, and is used to remove a single layer of ruthenium metal barrier layer deposited between a dielectric layer and a copper layer. The method includes:

[0045] S101, oxidation step. In the oxidation step, the monolayer metal ruthenium barrier layer is oxidized to form a ruthenium oxide layer. The oxidation step uses an electrochemical anodization process to oxidize the metal ruthenium barrier layer. In one embodiment, the electrochemical anodization process uses a cathode showerhead to perform electrochemical anodization from the center to the edge of the silicon wafer, or from the edge to the center of the silicon wafer. Figure 6a and Figure 6b A schematic diagram of the process of performing electrochemical anodization is disclosed. Figure 6a This is a schematic diagram of electrochemical anodization from the center to the edge of the silicon wafer through the cathode nozzle. Figure 6b This is a schematic diagram of electrochemical anodization from the edge to the center of a silicon wafer using a cathode showerhead. There is no difference in the effectiveness of different process directions, and the specific process direction can be selected based on the matching process and other practical needs. In one embodiment, the electrochemical anodization process used in the oxidation step is SFP. The electrolyte used in the electrochemical anodization process (SFP) is phosphoric acid with a mass fraction of 30% to 70%, and the applied current is 0A to 5A.

[0046] S102, oxide layer etching step. In the oxide layer etching step, the ruthenium oxide layer is etched with an etchant to remove the ruthenium oxide layer. In one embodiment, the etchant used in the oxide layer etching step is 0.01% to 1% by weight of HF, and the etch rate ratio of the etchant for the ruthenium oxide layer to the dielectric layer is greater than 0.62:1.

[0047] In a specific example of this barrier layer removal method, the oxidation step is implemented using an SFP electrochemical process, the electrolyte is phosphoric acid with a mass fraction (wt%) of 30% to 70%, the applied current is 5A, and the duration is 60s. The etchant used in the oxide layer etching step of this example is HF with a mass fraction (wt%) of 0.3%, and the etching time is 60s. The initial thickness of the metal ruthenium layer on the wafer surface is 2000 angstroms. After the metal ruthenium is oxidized to ruthenium oxide by the oxidation action of the SFP electrochemical process, the HF has a high etching rate for the ruthenium oxide. After a 60-second oxidation step and a 60-second etching step, the removal amount is 1393.7 angstroms. This removal efficiency can meet the removal rate requirements of the actual process.

[0048] Combine Figure 2 、 Figure 3a and Figure 3b, discloses another specific example of the method for removing the barrier layer. In this specific example, the SFP oxidation parameters are optimized by controlling the current or voltage and the movement rate to obtain different removal thickness and removal rate morphologies. One embodiment is: the applied current range is 0A to 5A, and the current is given different values ​​at different positions of the wafer movement; the wafer moves at a given movement speed at different positions, and the movement speed range in this embodiment is 2.01-4.0mm / s. This method is used to process a wafer with a metal ruthenium Ru layer on the entire surface, and then it is etched for 20s using a 0.1wt% HF solution and post-cleaned. The removal amount of the Ru layer is measured, and the results are as follows Figure 2 Reference Figure 2 The overall profile of the Ru layer removal is relatively flat. The average removal under this condition is calculated to be 183.4 angstroms, and the uniformity (NU) is 5.99%, which meets the process requirements. Figure 2 In the figure, the horizontal axis R represents the distance from the wafer center in mm, and the vertical axis Ra represents the measured thickness removed in angstroms. SEM analysis of a slice of the wafer at a specific location, such as a 90mm radius, reveals a flat and smooth surface of the ruthenium layer, with a calculated removal thickness of 183 angstroms. Figure 3a and Figure 3b The SEM analysis photos of the slices before and after the oxidation and etching processes are respectively disclosed. It should be noted that due to the requirements of the slice process, Figure 3a and Figure 3b The photos shown are not from the same wafer. However, the wafer structure is highly consistent, and even if they are different wafers, they are still of great reference value as a basis for comparison. Figure 3a As shown in Figure 2, before the process is implemented, the position of the Ru layer reference plane is at 226nm. Figure 3b As shown, after the process is implemented, the position of the Ru layer reference plane is at 207.7 nm, and the amount of Ru layer removed is calculated to be 183 angstroms.

[0049] In addition, under the condition that HF ​​can completely remove the ruthenium oxide layer oxidized by the SFP electrochemical process, the relationship between the average removal amount of the Ru layer and the SFP process time is as follows:

[0050] Ra(Ru)=3.1732t-28.6(Angstroms)

[0051] Where: Ra(Ru) is the removal amount of the Ru layer; t is the SFP process time.

[0052] The amount of Ru layer removed here refers to the amount of Ru removed by HF etching after the Ru layer undergoes SFP oxidation. The thickness of the Ru layer is calculated based on the original Ru layer (before the SFP process). This formula considers the thickness of the Ru layer before and after the process, not the thickness of the ruthenium oxide layer during the process.

[0053] In one embodiment, the removal selectivity of the ruthenium oxide layer and the dielectric layer SiO2 can be adjusted by adjusting the HF concentration, that is, the mass fraction (wt%) of HF: under the same SFP oxidation method and HF etching time, the HF concentration is selected to be 1wt% and 0.1wt%, respectively, and SFP oxidation + HF treatment is performed on the metal Ru and the dielectric layer SiO2, respectively, and the etching amount and selectivity are calculated.

[0054] It has been calculated that when the HF concentration is 1wt%, the etching selectivity ratio of the ruthenium oxide layer (herein referred to as RuO) and SiO2 is R(RuO) / R(SiO2)=0.62:1; when the HF concentration is 0.1wt%, the etching selectivity ratio of the ruthenium oxide layer and SiO2 is R(RuO) / R(SiO2)=18.42:1.

[0055] While ensuring that Ru oxidized by SFP is completely etched away, appropriately reducing the HF concentration can improve the etching selectivity between the ruthenium oxide layer and SiO2. Experimental testing has shown that when the HF concentration is ≤0.4wt%, the selectivity ratio can reach over 5:1. Therefore, in one embodiment, the HF concentration range can be selected between 0.01% and 1wt% to achieve an etch rate ratio of greater than 0.62:1 between the ruthenium oxide layer and the dielectric layer. In another embodiment, the HF concentration range can be selected between 0.01wt% and 0.4wt% to achieve an etch rate ratio of greater than 5:1 between the ruthenium oxide layer and the dielectric layer.

[0056] In addition, through experiments, it is found that when the etching time is constant, the etching amount of HF on SiO2 conforms to the following formula:

[0057] Ra(SiO2)=16171*C(HF)+17.343(Angstroms)

[0058] Where C refers to the concentration (mass fraction) of HF.

[0059] refer to Figure 4 As shown, Figure 4 A flow chart of a method for removing a barrier layer of a metal interconnection on a silicon wafer according to another embodiment of the present invention is disclosed. Figure 4 The method for removing the barrier layer of the metal interconnection on the silicon wafer can be considered as a field-implemented process method that can be used for mass production. Figure 5a 、 5b, 5c and 5d reveal Figure 4 The method for removing the barrier layer of the metal interconnection on the silicon wafer is used in the structure of the process node of 10nm and below. Figure 5a The structure used in the method for removing the barrier layer is disclosed. The structure includes a substrate 501, a dielectric layer 502, a barrier layer 503, and a metal layer 504. The dielectric layer 502 is deposited on the substrate 501, and a recessed area 505 is formed in the dielectric layer. The recessed area 505 is a hole or groove. The barrier layer 503 is deposited on the dielectric layer 502, and the metal layer 504 is deposited on the barrier layer 503. The metal layer is a copper (Cu) layer, and the barrier layer is a single layer of ruthenium (Ru). The method for removing the barrier layer includes:

[0060] S401, thinning step, thinning the metal layer, removing most of the metal layer and leaving a continuous metal layer 504 on the surface of the barrier layer 503. In one embodiment, in the thinning step, the thickness of the continuous metal layer 504 left on the surface of the barrier layer 503 is 500-1000 angstroms, wherein the thickness of the metal layer on the recessed area is greater than the metal layer on the non-recessed area. The thinning step can be performed by CMP process or SPF process. The structure after the thinning step is as follows Figure 5b As shown, a thicker metal layer is retained on the recessed area, while only a thinner metal layer is retained on the non-recessed area.

[0061] S402, a removal step, removing the metal layer on the non-recessed area to expose the barrier layer, while retaining a reserved thickness of the metal layer on the recessed area. In the removal step, all metal layers on the non-recessed area will be removed, but a certain thickness of metal layer will be retained on the recessed area. The purpose of retaining the metal layer is to continue using the SFP process in the next oxidation step. The SFP process will etch the copper layer while oxidizing the ruthenium metal. In order to avoid excessive etching of the metal layer in the recessed area during the oxidation step, it is necessary to retain a certain thickness of metal layer on the recessed area. The removal step is usually performed using the SFP process.

[0062] S403: Oxidation step: oxidizing the single-layer metal ruthenium barrier layer on the non-recessed area into a ruthenium oxide layer, while removing the metal layer remaining on the recessed area. The oxidation step utilizes an electrochemical anodization process to oxidize the metal ruthenium barrier layer into the ruthenium oxide layer. In one embodiment, the electrochemical anodization process uses a cathode showerhead to perform electrochemical anodization from the center to the edge of the silicon wafer, or from the edge to the center of the silicon wafer. Figure 6a and Figure 6b A schematic diagram of the process of performing electrochemical anodization is disclosed. Figure 6a This is a schematic diagram of electrochemical anodization from the center to the edge of the silicon wafer through the cathode nozzle. Figure 6bIt is a schematic diagram of electrochemical anodization from the edge to the center of the silicon wafer through a cathode nozzle. There is no difference in effect between different process directions, and the specific process direction can be selected according to the matching process and other actual needs. In one embodiment, the electrochemical anodization process used in the oxidation step is SFP, and the electrolyte used in the electrochemical anodization process (SFP) is phosphoric acid with a mass fraction of 30% to 70%, and the applied current is 0A to 5A. The parameters of the SFP used in the oxidation step are different from those of the SFP used in the removal step. The removal step mainly considers the effective etching of the copper layer, while the oxidation step needs to consider both the oxidation of metallic ruthenium and the etching of metallic copper. The electrolyte used in the SFP electrochemical process in the oxidation step removes the copper layer while oxidizing the metallic ruthenium barrier layer, wherein:

[0063] (Oxidation rate of metal ruthenium / removal rate of copper) = (thickness of metal ruthenium barrier layer / reserved thickness of copper layer on recessed area).

[0064] In one embodiment, the SFP electrolyte is phosphoric acid with a mass fraction (wt%) of 30% to 70%, the applied current is 5A, and the duration is 60s. The polishing amount of the metal layer Cu is 1052.6 angstroms. It is calculated that under the same SFP electrochemical treatment conditions, the ratio of Ru oxidation amount to Cu polishing amount is about 0.17:1. Correspondingly, the ratio of the reserved thickness of the copper layer on the recessed area to the thickness of the barrier layer Ru in step S402 is 1:0.17. The structure after the oxidation step is as follows Figure 5c As shown, the copper layer on the non-recessed area is removed, and the copper layer 504 remains in the recessed area 505. The metal ruthenium layer on the non-recessed area is oxidized to a ruthenium oxide layer 506. The metal ruthenium layer 503 continues to remain on the sidewalls of the recessed area 505.

[0065] S404, oxide layer etching step, using an etching solution to etch the ruthenium oxide layer on the non-recessed area, remove the ruthenium oxide layer, so that the recessed area and the non-recessed area have a flat surface after etching. In one embodiment, the etching solution used in the oxide layer etching step is HF with a mass fraction of 0.01% to 1wt%, and the etching rate ratio of the etching solution to the ruthenium oxide layer and the dielectric layer is greater than 0.62:1. As described above, appropriately reducing the HF concentration can improve the etching selectivity of the ruthenium oxide layer and SiO2. Therefore, in another embodiment, the HF concentration range can be selected between 0.01wt% and 0.4wt% to make the etching rate ratio of the ruthenium oxide layer and the dielectric layer greater than 5:1. The structure after the oxide layer etching step is as follows Figure 5dAs shown, the ruthenium oxide layer on the non-recessed area is removed, and the copper layer 504 remains in the recessed area 505. The metal ruthenium layer 503 continues to remain as a single-layer barrier layer on the sidewalls of the recessed area 505. After etching, the recessed area and the non-recessed area have a flat surface.

[0066] The following describes an embodiment of the present invention, which is also a specific implementation process of a method for removing a barrier layer from a metal interconnect on a silicon wafer. This method is used in a structure with a process node of 10nm or below. The structure includes a substrate, a dielectric layer, a barrier layer, and a metal layer. The dielectric layer is deposited on the substrate, a recessed region is formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, and the metal layer is deposited on the barrier layer. The metal layer is a copper layer, and the barrier layer is a single layer of ruthenium. This method shares the same basic concept as the aforementioned method, but differs in some process details. The method includes:

[0067] The metal layer is thinned by CMP until the thickness is below 2000 angstroms while maintaining the metal layer continuous. This method retains a relatively large amount of metal layer, approximately 2000 angstroms, when the metal layer is thinned by CMP.

[0068] The metal layer on the non-recessed area is removed by an electrochemical anodization process, and the single-layer metal ruthenium barrier layer on the non-recessed area is oxidized into a ruthenium oxide layer. This method is equivalent to using an electrochemical anodization process to complete the removal step and the oxidation step.

[0069] The ruthenium oxide layer on the non-recessed area is etched with an etching solution to remove the ruthenium oxide layer so that the recessed area and the non-recessed area have a flat surface after etching. This step is the same as the oxide layer etching step in the above method.

[0070] The following describes an embodiment of the present invention, which is also a specific implementation process of a method for removing a barrier layer from a metal interconnect on a silicon wafer. This method is used in a structure with a process node of 10nm or below. The structure includes a substrate, a dielectric layer, a barrier layer, and a metal layer. The dielectric layer is deposited on the substrate, a recessed region is formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, and the metal layer is deposited on the barrier layer. The metal layer is a copper layer, and the barrier layer is a single layer of ruthenium. This method shares the same basic concept as the aforementioned method, but differs in some process details. The method includes:

[0071] CMP is used to completely remove the metal layer in the non-recessed area until the barrier layer is exposed. In this method, CMP is directly used to remove the entire metal layer. This is equivalent to combining the thinning and removal steps and completing them with CMP.

[0072] The electrochemical anodic oxidation process is used to oxidize the single-layer metal ruthenium barrier layer on the non-recessed area into a ruthenium oxide layer, which is equivalent to completing the oxidation step by the electrochemical anodic oxidation process.

[0073] The ruthenium oxide layer on the non-recessed area is etched with an etching solution to remove the ruthenium oxide layer so that the recessed area and the non-recessed area have a flat surface after etching. This step is the same as the oxide layer etching step in the above method.

[0074] The barrier layer removal method of the present invention employs an oxidation-first, then etching approach, effectively addressing the issue of low ruthenium metal removal efficiency. The reaction rate of the oxidized ruthenium oxide with HF meets process requirements. Furthermore, by adjusting the HF concentration, the removal selectivity of the barrier layer and dielectric layer can be adjusted. The present invention utilizes electrochemical anodic oxidation, such as the SFP process, to achieve oxidation of ruthenium metal, resulting in a highly efficient and cost-effective overall process.

[0075] It should also be noted that the embodiments listed above are only specific embodiments of the present invention. Obviously, the present invention is not limited to the above embodiments, and similar changes or modifications made therewith are directly derived from the contents disclosed by those skilled in the art or can be easily associated with them, and should all fall within the scope of protection of the present invention. The above embodiments are provided to those familiar with the art to implement or use the present invention, and those familiar with the art can make various modifications or changes to the above embodiments without departing from the inventive concept of the present invention. Therefore, the scope of protection of the present invention is not limited by the above embodiments, but should be the maximum scope of the innovative features mentioned in the claims.

Claims

1. A method for removing a barrier layer of a metal interconnect on a silicon wafer, characterized in that: For process nodes of 10nm and below, the method is used to remove a single-layer metal ruthenium barrier layer deposited between a dielectric layer and a copper layer, comprising: an oxidation step of oxidizing the single-layer metal ruthenium barrier layer into a ruthenium oxide layer, wherein the oxidation step uses an electrochemical anodic oxidation process to oxidize the metal ruthenium barrier layer; an oxide layer etching step, etching the ruthenium oxide layer with an etching solution to remove the ruthenium oxide layer; The etching solution used in the oxide layer etching step is HF with a mass fraction of 0.01% to 1wt%, the etching rate ratio of the etching solution to the ruthenium oxide layer and the dielectric layer is greater than 0.62:1, and the dielectric layer material is SiO2.

2. The method for removing a barrier layer of a metal interconnection on a silicon wafer according to claim 1, wherein: The electrochemical anodizing process performs electrochemical anodizing from the center to the edge of the silicon wafer, or from the edge to the center of the silicon wafer, through a cathode nozzle. The electrolyte used in the electrochemical anodizing process is phosphoric acid with a mass fraction of 30% to 70%, and the applied current is 0A to 5A.

3. A method for removing a barrier layer of a metal interconnect on a silicon wafer, characterized in that: For use in a structure of a process node of 10nm or below, the structure includes a substrate, a dielectric layer, a barrier layer, and a metal layer, wherein the dielectric layer is deposited on the substrate, a recessed region is formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, and the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer and the barrier layer is a single-layer ruthenium metal layer. The method includes: a thinning step of thinning the metal layer, removing most of the metal layer and leaving a continuous metal layer on the surface of the barrier layer; a removing step of removing the metal layer on the non-recessed area to expose the barrier layer, and retaining a reserved thickness of the metal layer on the recessed area; an oxidation step of oxidizing the single-layer metal ruthenium barrier layer on the non-recessed area into a ruthenium oxide layer, while removing the metal layer remaining on the recessed area, wherein the oxidation step uses an electrochemical anodization process; an oxide layer etching step, wherein the ruthenium oxide layer on the non-recessed area is etched with an etching solution to remove the ruthenium oxide layer so that the recessed area and the non-recessed area have a flat surface after etching; The etching solution used in the oxide layer etching step is HF with a mass fraction of 0.01% to 1wt%, the etching rate ratio of the etching solution to the ruthenium oxide layer and the dielectric layer is greater than 0.62:1, and the dielectric layer material is SiO2.

4. The method for removing a barrier layer of a metal interconnection on a silicon wafer according to claim 3, wherein: During the thinning step, a continuous metal layer with a thickness of 500-1000 angstroms is left on the surface of the barrier layer, wherein the thickness of the metal layer on the recessed area is greater than that on the non-recessed area.

5. The method for removing a barrier layer of a metal interconnection on a silicon wafer according to claim 3, wherein: The electrochemical anodizing process performs electrochemical anodizing from the center to the edge of the silicon wafer, or from the edge to the center of the silicon wafer, through a cathode nozzle. The electrolyte used in the electrochemical anodizing process is phosphoric acid with a mass fraction of 30% to 70%, and the applied current is 0A to 5A.

6. The method for removing a barrier layer of a metal interconnection on a silicon wafer according to claim 5, wherein: The electrolyte used in the electrochemical anodization process simultaneously removes the copper layer while oxidizing the metallic ruthenium barrier layer, wherein: (Oxidation rate of metal ruthenium / removal rate of copper) = (thickness of metal ruthenium barrier layer / reserved thickness of copper layer on recessed area).

7. A method for removing a barrier layer of a metal interconnect on a silicon wafer, characterized in that: For use in a structure of a process node of 10nm or below, the structure includes a substrate, a dielectric layer, a barrier layer, and a metal layer, wherein the dielectric layer is deposited on the substrate, a recessed region is formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, and the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer and the barrier layer is a single-layer ruthenium metal layer. The method includes: Using CMP to thin the metal layer to a thickness below 2000 angstroms while maintaining a continuous metal layer; Using an electrochemical anodic oxidation process to remove the metal layer on the non-recessed area and oxidize the single-layer metal ruthenium barrier layer on the non-recessed area into a ruthenium oxide layer; Etching the ruthenium oxide layer on the non-recessed area with an etching solution to remove the ruthenium oxide layer, so that the recessed area and the non-recessed area have a flat surface after etching; The etching solution used is HF with a mass fraction of 0.01% to 1wt%, the etching rate ratio of the etching solution to the ruthenium oxide layer and the dielectric layer is greater than 0.62:1, and the dielectric layer material is SiO2.

8. A method for removing a barrier layer of a metal interconnect on a silicon wafer, characterized in that: For use in a structure of a process node of 10nm or below, the structure includes a substrate, a dielectric layer, a barrier layer, and a metal layer, wherein the dielectric layer is deposited on the substrate, a recessed region is formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, and the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer and the barrier layer is a single-layer ruthenium metal layer. The method includes: Using CMP to remove all the metal layers on the non-recessed area until the barrier layer is exposed; The single-layer metal ruthenium barrier layer on the non-recessed area is oxidized into a ruthenium oxide layer by an electrochemical anodic oxidation process; Etching the ruthenium oxide layer on the non-recessed area with an etching solution to remove the ruthenium oxide layer, so that the recessed area and the non-recessed area have a flat surface after etching; The etching solution used is HF with a mass fraction of 0.01% to 1wt%, the etching rate ratio of the etching solution to the ruthenium oxide layer and the dielectric layer is greater than 0.62:1, and the dielectric layer material is SiO2.

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