Method for manufacturing semiconductor chip and laser

Abstract

This application discloses a method for fabricating a semiconductor chip and a laser. The method comprises: providing an epitaxial wafer with a preliminary zinc diffusion pattern; depositing a strained layer on at least a portion of the epitaxial wafer's surface to blue-shift the semiconductor chip's emission spectrum, wherein at least a portion of the surface comprises a window region; heating the epitaxial wafer and the strained layer to enhance zinc diffusion in the window region; wherein the film strain of the strained layer after heating is greater than the film strain before heating. By employing this method, the present application can accelerate zinc diffusion, improve production efficiency, and enhance resistance to catastrophic optical mirror damage.

Description

Technical Field

[0001] The present application relates to the field of laser technology, and in particular to a method for manufacturing a semiconductor chip and a laser. Background Art

[0002] The research focuses of semiconductor lasers include increasing optical output power, improving reliability and service life, and catastrophic optical damage (COD) is an important factor affecting the maximum output power and reliability of semiconductor lasers.

[0003] At present, the mainstream method used to improve the COD threshold is to reduce the light absorption of the cavity surface. The basic approach is to increase the band gap width of the cavity surface area, which is often called the window structure. The specific implementation methods include the following: First, epitaxial regrowth, after etching the material near the cavity surface, a wide band gap material is re-grown epitaxially to form a transparent window for output light and reduce light absorption. The disadvantage is that the process is more complicated and the cost is higher, and it may lead to poor crystal quality at the connection part and reduced device efficiency, thereby affecting the performance of the device; second, quantum well intermixing, since each layer of the epitaxial wafer is a metastable interface, the quantum well component atoms in the cavity surface area will diffuse with each other through quantum intermixing technology, thereby increasing the band gap width of the corresponding non-window area.

[0004] However, the existing problem with zinc atom diffusion to increase the band gap width in the window region is that although it takes a very short time (about 30 minutes) for zinc atoms to diffuse into the quantum well layer, since the thickness of the quantum well layer is about 10nm, it takes 1 to 3 hours to complete the atomic mixing by zinc induction alone. Therefore, the total doping time is long, which is not conducive to process production. In addition, doping needs to be carried out in a high-temperature environment. Long-term high-temperature treatment will increase the lateral or vertical diffusion of zinc, seriously affecting the atomic purity of the active area and reducing the luminous efficiency of the laser. Summary of the Invention

[0005] The present application provides a method for manufacturing a semiconductor chip and a laser, which can accelerate the diffusion of zinc, improve production efficiency, and enhance the ability to resist catastrophic optical mirror damage.

[0006] To solve the above technical problems, the technical solution adopted in this application is: to provide a method for manufacturing a semiconductor chip, the method comprising: providing an epitaxial wafer with preliminary zinc diffusion; depositing a strain layer on at least a portion of the surface of the epitaxial wafer to cause the emission spectrum of the semiconductor chip to blue-shift, wherein at least a portion of the surface includes a window area; heating the epitaxial wafer and the strain layer to enhance the diffusion of zinc in the window area; wherein, after heating, the film strain of the strain layer is greater than the film strain before heating.

[0007] In order to solve the above technical problems, the technical solution adopted in this application is: to provide a laser, which includes a semiconductor chip, and the semiconductor chip is a semiconductor chip manufactured by the above manufacturing method.

[0008] Through the above scheme, the beneficial effects of the present application are: a strained layer that can increase the diffusion of zinc atoms is deposited on the epitaxial wafer, and the diffusion of zinc atoms is accelerated by heating the epitaxial wafer and the strained layer. Since the strained layer can undergo film strain at high temperature, and the film strain can accelerate the diffusion of zinc atoms, the diffusion time of zinc atoms can be shortened, which helps to improve production efficiency. Moreover, since the band gap of the window area becomes larger after diffusion, the light emission wavelength of the semiconductor chip is blue-shifted, which can further improve the COD resistance of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0010] Figure 1 This is a flow chart of an embodiment of a method for manufacturing a semiconductor chip provided by the present application;

[0011] Figure 2 yes Figure 1 A schematic structural diagram of a semiconductor chip in the embodiment shown;

[0012] Figure 3 yes Figure 1 A schematic diagram of the process for performing preliminary zinc diffusion in the embodiment shown;

[0013] Figure 4 yes Figure 3 A schematic structural diagram corresponding to step 22 in the embodiment shown;

[0014] Figure 5 yes Figure 3 A schematic structural diagram corresponding to step 23 in the embodiment shown;

[0015] Figure 6 yes Figure 1 A schematic structural diagram corresponding to step 12 in the embodiment shown;

[0016] Figure 7 yes Figure 1 Another structural diagram corresponding to step 12 in the embodiment shown;

[0017] Figure 8 yes Figure 1Another structural diagram corresponding to step 12 in the embodiment shown;

[0018] Figure 9 yes Figure 1 A schematic diagram of the wavelength of the semiconductor chip during the manufacturing process in the embodiment shown;

[0019] Figure 10 It is a structural schematic diagram of an embodiment of a laser provided in this application. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0021] Please refer to Figures 1 to 3 , Figure 1 FIG. 1 is a flow chart of an embodiment of a method for manufacturing a semiconductor chip provided by the present application, the method comprising:

[0022] Step 11: Providing an epitaxial wafer with preliminary zinc diffusion.

[0023] like Figure 2 As shown, the epitaxial wafer 11 includes an N-type substrate 111, an N-type cladding layer 112, a first waveguide layer 113, a quantum well layer 114, a second waveguide layer 115, a P-type cladding layer 116, and a P-type contact layer 117, which are arranged in sequence. The materials of the N-type cladding layer 112 and the P-type cladding layer 116 can be N-type aluminum indium phosphide and P-type aluminum indium phosphide, respectively. The material of the quantum well layer 114 can be gallium indium phosphide. The material of the P-type contact layer 117 can be P-type gallium arsenide. The materials of the first waveguide layer 112 and the second waveguide layer 115 can be aluminum gallium indium phosphide.

[0024] In order to diffuse zinc atoms into the epitaxial wafer 11, the prepared epitaxial wafer 11 can be used to diffuse zinc atoms into the epitaxial wafer 11 by ion implantation, atomic doping or diffusion, or the epitaxial wafer 11 with zinc atoms diffused therein can be directly manufactured. Specifically, an N-type substrate 111 can be provided first, and then an N-type cladding layer 112, a first waveguide layer 113, a quantum well layer 114, a second waveguide layer 115, a P-type cladding layer 116 and a P-type contact layer 117 can be epitaxially grown on the N-type substrate 111 in sequence to form the epitaxial wafer 11. The material of the N-type substrate 111 can be N-type gallium arsenide, which can play a supporting role.

[0025] It should be noted that the preparation of epitaxial wafers can adopt relatively mature processes in the industry, which will not be described here.

[0026] Step 12: Depositing a strained layer on at least a portion of the surface of the epitaxial wafer to cause a blue shift in the emission spectrum of the semiconductor chip.

[0027] At least part of the surface includes a window area, which is an area where the band gap width needs to be increased and is generally arranged at the light-emitting end of the semiconductor chip; Figure 2 As shown, after the epitaxial wafer 11 is formed, in order to further enhance zinc diffusion, a strained layer 12 may be first deposited on at least a portion of the surface of the epitaxial wafer 11 using plasma enhanced chemical vapor deposition (PECVD). The thickness of the strained layer 12 may be 450 to 550 nm, and the material of the strained layer 12 may include silicon dioxide or silicon nitride.

[0028] Since the strained layer 12 that can increase the diffusion of zinc atoms is deposited in the window area where the band gap width needs to be increased, the strained layer 12 undergoes thin film strain at high temperature. The thin film strain can accelerate the mixing of zinc atoms in the window area. Therefore, after the optimal deposition process of the strained layer 12 is completed, the emission wavelength can be blue-shifted, so that the band gap of the window area is widened, thereby improving the COD resistance of the semiconductor chip cavity surface; specifically, impurities are diffused into the active layer near the end face of the semiconductor chip to form a disordered area, and this is used as the window area. The window area is irradiated with excitation light, and the wavelength of the photoluminescence of the window area is measured. The difference between the wavelength of the photoluminescence generated when the light irradiates the active layer without the window area and the wavelength of the photoluminescence of the window area is defined as the blue shift. The COD level of the product is predicted based on the blue shift at each stage of the process. The larger the blue shift, the more obvious the improvement in the COD resistance of the semiconductor chip.

[0029] Step 13: Heat the epitaxial wafer and the strained layer to enhance the diffusion of zinc in the window region.

[0030] Although a certain amount of zinc atoms diffuse during the deposition of the strained layer 12, complete diffusion and mixing of the active layer has not yet been achieved. Therefore, in order to achieve faster and complete diffusion of the zinc atoms, the epitaxial wafer 11 deposited with the strained layer 12 can be heated. Specifically, due to the difference in thermal expansion coefficients between the strained layer 12 and the epitaxial wafer 11, the film strain of the strained layer 12 is increased by heating the composite structure of the semiconductor chip (including the epitaxial wafer 11 and the strained layer 12), so that the film strain of the strained layer 12 after heating is greater than the film strain before heating. The film strain can accelerate the diffusion of zinc atoms in the active layer of the window area, thereby maximizing process time savings. In addition, due to the rapid induction of the film strain, atomic mixing of the active layer in the window area can be completed in a short time, which can further reduce the ineffective lateral and longitudinal diffusion of zinc atoms during the heating process, thereby reducing the impact of zinc impurities on luminous efficiency.

[0031] This embodiment provides a novel processing technology, in which a strained layer 12 is plated on at least a portion of the surface of the epitaxial wafer 11. The strained layer 12 can accelerate the zinc-induced atomic mixing in the window area, reduce the preparation time of the semiconductor chip, and improve production efficiency. In addition, due to the blue shift of the emission wavelength, the COD resistance of the semiconductor chip can be improved.

[0032] The following is a description of a specific embodiment. In a specific embodiment, Figure 3 As shown, steps 21-24 may be used to perform preliminary diffusion of zinc before depositing the strained layer 12, as shown below:

[0033] Step 21: Prepare an undoped epitaxial wafer.

[0034] The epitaxial wafer specifically includes an N-type substrate 111 , an N-type cladding layer 112 , a first waveguide layer 113 , a quantum well layer 114 , a second waveguide layer 115 , a P-type cladding layer 116 and a P-type contact layer 117 .

[0035] Furthermore, the N-type substrate 111 is an N-type GaAs single crystal; the N-type cap layer 112 is an N-type non-doped Al that matches the N-type GaAs. x In 1-x P, with a thickness of 500 to 5000 nm; the first waveguide layer 113 is N-type non-doped (Al y Ga 1-y ) x In 1-x P, with a thickness of 50 to 250 nm; the quantum well layer 114 is Ga z In 1-z P, its thickness is 2 to 200 nm, and the lasing wavelength is 620 to 670 nm; the second waveguide layer 115 is P-type (Al y Ga 1-y ) x In 1-x P, its thickness is 50 ~ 250nm; P-type cap layer 116 is P-type Al x In 1-x P, with a thickness of 500 to 5000 nm; the P-type contact layer 117 is P-type non-doped GaAs, with a thickness of 100 to 500 nm.

[0036] Step 22: Form a mask layer on the non-window area of ​​the epitaxial wafer.

[0037] like Figure 4 As shown, after the epitaxial wafer 11 is formed, a mask layer 13 may be formed in the window region. The material of the mask layer 13 may be silicon nitride, and the thickness thereof may be 250 nm.

[0038] Step 23: forming an active layer and a silicon dioxide layer in sequence on the mask layer and the epitaxial wafer not covered by the mask layer, and heating them at a preset temperature or performing rapid thermal annealing for a preset time.

[0039] like Figure 5 As shown, after the mask layer 13 is formed, an active layer 14 can be formed on the entire surface of the current structure, and then a silicon dioxide layer 15 can be formed on the active layer 14. The materials of the active layer 14 include silicon dioxide and zinc oxide. The thickness of the active layer 14 can be 150 to 250 nm, for example, 200 nm. The preset temperature can be 580 to 620° C., and the preset time can be 25 to 30 minutes. For example, the zinc atoms can be initially diffused by heating in a furnace at 600° C. or by RTA (Rapid Thermal Annealing) for 30 minutes.

[0040] Specifically, in order to accelerate the diffusion of zinc atoms, the fabricated structure (including the epitaxial wafer 11, the mask layer 13, the active layer 14 and the silicon dioxide layer 15) can be heat treated to complete the initial zinc diffusion process. Due to the rapid diffusivity of zinc atoms, zinc atoms can diffuse into the epitaxial wafer 11 through the window area, thereby increasing the band gap width of the non-window area. However, since this diffusion cannot allow the zinc atoms to completely enter the quantum well layer 114 in a relatively short time, a second zinc diffusion is required, that is, depositing the strained layer 12 to further diffuse the zinc atoms so that the zinc atoms can fully enter the quantum well layer 114.

[0041] Step 24: The silicon dioxide layer, the active layer, and the mask layer are removed in sequence to form an epitaxial structure with preliminary zinc diffusion.

[0042] After heating, the mask layer 13 , the active layer 14 and the silicon dioxide layer 15 are removed to obtain the epitaxial structure 11 ′ after preliminary diffusion. At this time, the zinc atoms in the epitaxial structure 11 ′ have not entered the quantum well layer 114 or have not completely entered the quantum well layer 114 .

[0043] In a specific embodiment, the Figure 3 The initial zinc diffusion is performed in the manner shown, and then the strained layer 12 is deposited on the entire surface of the epitaxial structure 11 ', as shown in FIG. Figure 6As shown, the thickness of the strained layer 12 can be 500 nm. By heating the epitaxial structure 11' on which the strained layer 12 is deposited, the complete diffusion of zinc atoms is achieved. Specifically, due to the difference in thermal expansion coefficients between the strained layer 12 and the epitaxial structure 11', heating the composite structure of the semiconductor chip (including the epitaxial structure 11' and the strained layer 12) increases the film strain of the strained layer 12, so that the film strain of the strained layer 12 after heating is greater than the film strain before heating. The film strain can accelerate the diffusion of zinc atoms in the active layer of the window region, thereby maximizing process time savings. In addition, due to the rapid induction of the film strain, atomic mixing in the active layer of the window region can be completed in a short time, which can further reduce the ineffective lateral and longitudinal diffusion of zinc atoms during the heating process, thereby reducing the impact of zinc impurities on luminous efficiency.

[0044] Compared with the existing technology, the accumulation layer (including the mask layer 13, the active layer 14 and the silicon dioxide layer 15) is removed after the initial diffusion, and a strain layer 12 is deposited to increase the diffusion of zinc atoms, thereby improving the COD resistance of the semiconductor chip cavity surface. On the basis of further reducing the mixing time of zinc atoms, the impact of zinc on the luminous efficiency of the semiconductor chip can be minimized.

[0045] In another specific embodiment, Figure 7 As shown, Figure 6 The embodiment shown differs in that a strained layer 12 is deposited on at least a portion of the epitaxial wafer surface corresponding to the window region. Specifically, the strained layer 12 is deposited on the surface corresponding to the window region where initial zinc diffusion occurs. In this embodiment, by depositing the strained layer 12 in the window region of the epitaxial structure 11', the heating process increases the diffusion of zinc atoms in the active layer in the window region, thereby increasing the disorder of the active layer and thereby increasing the band gap width.

[0046] In the above embodiments, in the preparation process of the epitaxial wafer, a layer structure undoped material process is adopted. Of course, it can be understood that the epitaxial wafer of the present application can also be directly prepared by pre-doping the epitaxial structure 11' with zinc atoms. The specific process flow is that in the preparation process of the epitaxial wafer, the P-type cover layer 116 is zinc-doped. Doping can increase the leakage of electrons and provide photoelectric conversion efficiency. However, the doped zinc atoms exist in the non-window area. In order to increase the mixing of zinc atoms in the window area in the quantum well layer 114, a strained layer 12 is deposited in the area where the band gap width needs to be increased, so that the zinc atoms in the P-type cover layer 116 can diffuse quickly and achieve sufficient mixing of atoms in the window area.

[0047] Furthermore, an N-type cladding layer 112, a first waveguide layer 113, a quantum well layer 114, a second waveguide layer 115, and a P-type cladding layer 116 may be epitaxially grown in sequence on an N-type substrate 111. Zinc may then be doped into the second waveguide layer 115 and the P-type cladding layer 116 to obtain a new second waveguide layer 115′ and a new P-type cladding layer 116′ having doped characteristics, and a P-type contact layer 117 may be formed on the new P-type cladding layer 116′. Figure 8 As shown, a strained layer 12 is then deposited on at least a portion of the window region on the P-type contact layer 117 .

[0048] Furthermore, in this embodiment, the N-type substrate 111 is an N-type GaAs single crystal; the N-type cap layer 112 is an N-type non-doped Al2O3 that matches the N-type GaAs. x In 1-x P, with a thickness of 500 to 5000 nm; the first waveguide layer 113 is N-type non-doped (Al y Ga 1-y ) x In 1-x P, with a thickness of 50 to 250 nm; the quantum well layer 114 is Ga z In 1-z P, its thickness is 2 to 200 nm, and the lasing wavelength is 620 to 670 nm; the second waveguide layer 115 is P-type (Al y Ga 1-y ) x In 1-x P, with a thickness of 50 to 250 nm. The new second waveguide layer 115' contains a doping material, which is Zn with a doping concentration of 5×10 17 cm -3 ; New P-type cap layer 116 'is P-type Al x In 1-x P, its thickness is 500-5000nm, the new P-type cap layer 116' has a doping material, the doping material is Zn, and the doping concentration is 3×10 18 cm -3 ; The P-type contact layer 117 is P-type non-doped GaAs, and its thickness is 100 to 500 nm.

[0049] Compared to the prior art, the new second waveguide layer 115' and the new P-type cladding layer 116' have been doped with zinc atoms. A strained layer 12 is deposited in the window region where the bandgap width needs to be increased to increase the diffusion of zinc atoms. Since the strained layer 12 undergoes film strain at high temperatures, the film strain can accelerate the mixing of zinc atoms in the window region, thereby improving the COD resistance of the semiconductor chip cavity surface.

[0050] For high-power semiconductor chips, the wavelength blue shift effect can be used to create a wide bandgap window area, which can reduce the absorption of light on the cavity surface. Therefore, the wavelength blue shift is also used to judge the anti-COD ability of the semiconductor chip to a certain extent. The difference between the wavelength of the photoluminescence emitted when the laser irradiates the active layer without disorder (no impurity diffusion) and the wavelength of the photoluminescence with the window area is defined as the blue shift amount. After summarizing the test data of different samples, we can get Figure 9 The relationship shown.

[0051] Figure 9 The figure shows the blue shift of the wavelength of the semiconductor chip during the preparation process of this embodiment. Curves ①, ②, and ③ correspond to semiconductor chips with the same structure, but with some manufacturing conditions changed. Curve ① is the wavelength distribution of the window region measured when the semiconductor chip is not subjected to zinc diffusion treatment. Curve ② is the wavelength distribution of the window region measured after the semiconductor chip undergoes a preliminary short-time zinc diffusion. At this time, there is a wavelength blue shift of about 10 to 15 nm compared to curve ①, indicating that the band gap of the window region of the semiconductor chip has widened and it has a certain COD resistance. Curve ③ is the wavelength distribution of the window region measured after the semiconductor chip is added with the strain layer 12 and thermal strain treatment. At this time, there is a wavelength blue shift of about 25 to 30 nm compared to curve 1, indicating that the COD resistance of the semiconductor chip is significantly improved. In summary, in the same group of samples, the shorter the photoluminescence wavelength, the higher the COD level. This can be explained by the fact that the disordering treatment of the window region widens the band gap, thereby reducing the light absorbed near the end face of the resonant cavity.

[0052] exist Figure 9 In the equation, if the COD level is recorded as Pcod (mW) and the photoluminescence wavelength in the window area is recorded as λ, then Pcod and λ have a linear proportional relationship, that is:

[0053] Pcod=f*λ

[0054] In the above formula, f is a linear function.

[0055] As can be seen from the above, by selecting the wavelength λ of photoluminescence from semiconductor chips with Pcod and using this value as an indicator, the COD level at the time of window region formation can be used to identify the quality of semiconductor chips. Furthermore, by measuring the wavelength λ of photoluminescence from the window region, high-reliability semiconductor chips that are resistant to COD degradation due to the window region can be manufactured with low variability and high yield.

[0056] Further references Figure 9The window area photoluminescence curves of samples with the same semiconductor structure but different process technologies show that in a semiconductor chip with an active layer having a lasing wavelength of 590nm-630nm, by making a semiconductor chip with a window area so that the photoluminescence wavelength is below 600nm, a semiconductor chip can be obtained in which the COD level is improved at least due to the effect of the window area.

[0057] See also Figure 10 , Figure 10 2 is a schematic structural diagram of an embodiment of a laser provided in the present application. The laser 20 includes a semiconductor chip 21. The semiconductor chip 21 is a semiconductor chip manufactured by the manufacturing method in the above embodiment.

[0058] The semiconductor chip 21 of this embodiment is manufactured by accelerating the diffusion of zinc atoms in the window region, which can improve the COD resistance of the cavity surface of the semiconductor chip 21.

[0059] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor chip, characterized in that: include: Providing an epitaxial wafer having a preliminary zinc diffusion; Depositing a strained layer on at least a portion of the surface of the epitaxial wafer to cause a blue shift in the emission spectrum of the semiconductor chip, wherein the at least a portion of the surface includes a window region; heating the epitaxial wafer and the strained layer to enhance the diffusion of zinc in the window region; Wherein, the film strain of the strained layer after heating is greater than the film strain before heating.

2. The method for manufacturing a semiconductor chip according to claim 1, wherein: Before the step of depositing a strained layer on at least a portion of the surface of the epitaxial wafer, the method includes: preparing undoped epitaxial wafers; forming a mask layer on a non-window area of ​​the epitaxial wafer; forming an active layer and a silicon dioxide layer in sequence on the mask layer and the epitaxial wafer not covered by the mask layer, and heating at a preset temperature or performing rapid thermal annealing for a preset time; Wherein, the material of the active layer includes silicon dioxide and zinc oxide.

3. The method for manufacturing a semiconductor chip according to claim 2, wherein: The method further comprises: heating the epitaxial wafer, the mask layer, the active layer, and the silicon dioxide layer to perform preliminary zinc diffusion; The silicon dioxide layer, the active layer and the mask layer are removed in sequence to form an epitaxial structure with preliminary zinc diffusion.

4. The method for manufacturing a semiconductor chip according to claim 2, wherein: The preset temperature is 580-620° C., the preset time is 25-30 minutes, the thickness of the active layer is 150-250 nm, the thickness of the strained layer is 450-550 nm, and the material of the strained layer includes silicon dioxide or silicon nitride.

5. The method for manufacturing a semiconductor chip according to claim 1, wherein: The strain layer is deposited on at least a portion of the window area by using a plasma enhanced chemical vapor deposition method.

6. The method for manufacturing a semiconductor chip according to claim 1, wherein: The step of providing an epitaxial wafer with preliminary zinc diffusion comprises: Providing an N-type substrate; An N-type cladding layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a P-type cladding layer and a P-type contact layer are epitaxially grown in sequence on the N-type substrate to form the epitaxial wafer.

7. The method for manufacturing a semiconductor chip according to claim 6, wherein: The step of sequentially epitaxially growing an N-type cladding layer, a first waveguide layer, a quantum well layer, a second waveguide layer, a P-type cladding layer, and a P-type contact layer on the N-type substrate to form the epitaxial wafer comprises: epitaxially growing the N-type cladding layer, the first waveguide layer, the quantum well layer, the second waveguide layer, and the P-type cladding layer in sequence on the N-type substrate; Zinc is doped into the second waveguide layer and the P-type cladding layer to obtain a new second waveguide layer and a new P-type cladding layer, and the P-type contact layer is formed on the new P-type cladding layer.

8. The method for manufacturing a semiconductor chip according to claim 6, wherein: The materials of the N-type substrate, the N-type cover layer, the quantum well layer, the P-type cover layer and the P-type contact layer are N-type gallium arsenide, N-type aluminum indium phosphide, gallium indium phosphide, P-type aluminum indium phosphide and P-type gallium arsenide, respectively, and the material of the first waveguide layer and the second waveguide layer is aluminum gallium indium phosphide.

9. The method for manufacturing a semiconductor chip according to claim 8, wherein: The thickness of the N-type cladding layer is 500~5000nm; the thickness of the first waveguide layer is 50~250nm; the thickness of the quantum well layer is 2~200nm; the thickness of the second waveguide layer is 50~250nm; the thickness of the P-type cladding layer is 500~5000nm; and the thickness of the P-type contact layer is 100~500nm.

10. A laser, characterized in that: The laser comprises a semiconductor chip, and the semiconductor chip is a semiconductor chip manufactured by the manufacturing method according to any one of claims 1 to 9.

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