Phase shifter with bidirectional amplification

Abstract

An apparatus is disclosed for bi-directional amplification with phase shifting. In an example implementation, an apparatus includes a phase shifter having a bi-directional amplifier. The bi-directional amplifier includes a first transistor (T1) coupled between a first positive node (606-1P) and a second negative node (606-2M), a second transistor (T2) coupled between a first negative node (606-1M) and a second positive node (606-2P), a third transistor (T3) coupled between the first positive node (606-1P) and the second negative node (606-2M), and a fourth transistor (T4) coupled between the first negative node (606-1M) and the second positive node (606-2P). The bi-directional amplifier also includes a fifth transistor (T5) coupled between the first positive node (606-1P) and the second positive node (606-2P), a sixth transistor (T6) coupled between the first negative node (606-1M) and the second negative node (606-2M), a seventh transistor (T7) coupled between the first positive node (606-1P) and the second positive node (606-2P), and an eighth transistor (T8) coupled between the first negative node (606-1M) and the second negative node (606-2M).

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Utility Model Application No. 16 / 835,177, filed March 30, 2020, which in turn claims priority to U.S. Provisional Application No. 62 / 843,191, filed May 3, 2019, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to wireless communication with electronic devices, and more specifically to implementing a phase shifter with a bidirectional amplifier. Background Technology

[0004] Electronic devices include traditional computing devices such as desktop computers, laptops, smartphones, wearable devices like smartwatches, and internet servers. However, electronic devices also include other types of computing devices, such as personal voice assistants, thermostats and other sensors or automatic controllers, robots, automotive electronics, devices embedded in other machines (such as refrigerators and industrial tools), and Internet of Things (IoT) devices. These diverse electronic devices provide services related to productivity, communication, social interaction, security, safety, remote management, entertainment, transportation, and information dissemination. Therefore, electronic devices play a crucial role in many aspects of modern society.

[0005] In today's interconnected world, many services provided by electronic devices rely at least in part on electronic communications. For example, electronic communications include communication that uses wireless or wired signals exchanged between two or more different electronic devices, transmitted over one or more networks (e.g., the Internet, Wi-Fi networks, or cellular networks). Therefore, electronic communications involve both wireless and wired transmission and reception. To conduct this type of electronic communication, electronic devices use transceivers, such as wireless transceivers.

[0006] Therefore, electronic communication can be achieved by transmitting signals between two wireless transceivers at two different electronic devices. For example, using a wireless transmitter, a smartphone can transmit wireless signals over the air to a base station as part of uplink communication to support mobile services. Using a wireless receiver, a smartphone can receive wireless signals from a base station over the air as part of downlink communication to enable mobile services. Mobile services using smartphones can include phone and video calls, social media interaction, messaging, watching movies, sharing videos, performing searches, obtaining map information or navigation instructions, finding friends, location-based services, transferring money, and obtaining other services (such as ride-hailing).

[0007] To provide these and other types of services, electronic devices typically use wireless transceivers to transmit wireless signals according to some wireless standard. Examples of wireless standards include 4G cellular standards and the IEEE 802.11b or 802.11g Wi-Fi standards, both of which are now used in smartphones and other connected devices. These wireless standards achieve certain wireless communication speeds. Nevertheless, efforts to achieve faster wireless networks by creating newer wireless standards are ongoing. For example, next-generation cellular networks and advanced Wi-Fi networks promise significantly higher bandwidth, lower latency, and access to additional electromagnetic (EM) spectrum. In short, this means that exciting new wireless services can be provided to users, such as safer self-driving cars, augmented reality (AR) and other mixed reality (MR) imaging, mobile 4K video streaming, ubiquitous sensors to ensure people's safety and more efficient use of natural resources, real-time speech translation, and more.

[0008] To make these new, faster wireless technologies more widely available, a multitude of wireless devices, beyond smartphones and other traditional computing devices, will be deployed—sometimes referred to as the “Internet of Things” (IoT). With the advent of the IoT, tens of billions, even trillions, of devices are expected to connect to the internet, compared to the wireless devices used today. These IoT devices can include small, inexpensive, and low-power devices such as sensors and tracking tags. To support next-generation wireless technologies, IoT devices and electronic devices will typically operate according to 5G cellular standards and newer Wi-Fi standards. Compared to devices operating according to older wireless standards, these devices will communicate with signals using a wider range of frequencies located at higher frequencies in the EM spectrum. For example, many newer devices are expected to operate at millimeter-wave (mmWave) frequencies (e.g., frequencies between at least 24 and 300 GHz) and single-digit GHz frequencies.

[0009] To meet these business expectations and overcome the associated technical hurdles, the physical components enabling wireless communication under these constraints are expected to operate efficiently at mmWave frequencies. One component facilitating electronic communication is the wireless interface device, which may include a wireless transceiver and a radio frequency front-end (RFFE). Unfortunately, wireless interface devices designed for electronic devices operating according to today's Wi-Fi and 4G cellular standards are insufficient to meet the faster Wi-Fi and 5G wireless standards of the future, which are expected to accommodate higher frequencies, consider stricter latency requirements, and meet more stringent financial constraints.

[0010] Therefore, to facilitate the widespread deployment of newer cellular and faster Wi-Fi technologies, as well as electronic devices capable of providing new capabilities and services, wireless interface devices designed to handle mmWave frequencies will be deployed. Consequently, electrical engineers and other electronic device designers are working to develop new wireless interface devices to realize the promises of 5G, faster Wi-Fi, and other higher-frequency technologies. Summary of the Invention

[0011] Newer cellular standards (e.g., 5G) and newer Wi-Fi standards (e.g., Beamforming aims to establish broadband capabilities at higher electromagnetic (EM) frequencies. These higher EM frequencies include frequencies in the gigahertz (GHz) range, such as frequencies with corresponding millimeter wavelengths (e.g., mmWave frequencies between at least 24 and 300 GHz). To facilitate wireless communication at mmWave frequencies, some electronic devices use signal beamforming. Signal beamforming requires the use of an antenna array to aim or guide the signal beam in the desired direction. Guiding the signal beam from the source device to the destination device reduces the amount of transmit power required to reach the destination device. Furthermore, beamforming allows signals to propagate over much greater distances compared to omnidirectional transmission, including transmission at mmWave frequencies.

[0012] To generate a signal beam, multiple antenna elements of an antenna array transmit or receive different versions of a wireless signal, such as versions with different delays or phase shifts. In some device architectures, corresponding component chains are associated with each antenna element of the antenna array to generate a corresponding version of the wireless signal. Therefore, the individual physical components of each component chain are reproduced for each antenna element. A single electronic device can include many antenna elements, such as 4, 6, 12, 16, or more distributed across multiple antenna arrays. Therefore, the negative impact of any particular physical component as part of a component chain (e.g., the size occupied by the individual physical component) is multiplied by the number of antenna elements included in the electronic device.

[0013] An example of an individual physical component that can be included in each component chain is a phase shifter. A phase shifter can adjust the phase of a wireless signal version relative to other versions of the signal to enable beamforming for mmWave and other wireless communication frequencies. Phase shifters can be constructed using, for example, signal phase generators and vector modulators. In some implementations, a signal phase generator converts a signal having one phase corresponding to one signal component into a split signal having at least two phases corresponding to at least two components of the signal. In some scenarios, the two phases of the split signal are separated by ninety degrees (90°), for example by having 0° and 90° phases. Such a split signal can be described as having in-phase (I) and quadrature (Q) signal components.

[0014] In operation, as part of the phase shifting process, the vector modulator can adjust the amplitude of each signal component of the split signal. In a single-ended environment, the vector modulator can modulate two signal components, which can correspond to 0° and 90° phase of the split signal. In a differential environment, the vector modulator can modulate four signal components, which can correspond to 0°, 90°, 180°, and 270° phase of the split signal. The vector modulator of the phase shifter can be implemented as an amplifier for adjusting the relative amplitude of the components of the split signal. After recombinating the adjusted components of the split signal, relative amplitude adjustment can effectively change the phase of a given component chain of signals flowing through a given antenna element to support beamsteering operation.

[0015] Typically, amplifiers can be implemented as unidirectional or bidirectional amplifiers. Since the component chain acts on both the transmitted and received signals simultaneously, the unidirectional amplifier deployed as a vector modulator for a phase shifter is repeated at each phase shifter. This repetition occurs at each component chain of each antenna element in each antenna array of the electronic device. Therefore, by using bidirectional amplifiers for each phase shifter's vector modulator in the electronic device, the total number of amplifiers used by the device's phase shifters can be reduced by fifty percent. This space reduction provides cost savings.

[0016] Some bidirectional amplifiers use both active and passive components. Passive components (e.g., inductors) occupy a large area of ​​the radio frequency (RF) integrated circuit (IC) (RFIC). This larger RFIC size increases cost and results in a larger device. Furthermore, phase-shifting operation can be sensitive to phase and impedance variations induced by the amplifier in a vector modulator. Providing constant phase and impedance performance at different gain factors is particularly challenging, and amplifiers use multiple gain factors to provide different phase shifts for vector modulator-based phase shifters.

[0017] To address one or more of these issues, some of the described implementations include a phase shifter employing a bidirectional variable gain amplifier (VGA) as part of a bidirectional active vector modulator. The described bidirectional VGA can maintain phase and input / output (I / O) impedance during gain changes used to modulate the signal components of a split signal, such as I and Q components. Example bidirectional VGAs also include built-in symbol switching capability to extend the phase offset range from 0–180° to 0–360°. The described bidirectional VGA also offers the opportunity that the size of the transistors used to amplify the transmitted signal can be determined independently of the transistors used to amplify the received signal. Determining the transistor sizes independently for at least partially separate signal transmission and reception paths allows noise figure and linearity performance to be optimized separately for transmission and reception operations.

[0018] In the example implementation, the bidirectional VGA for the vector modulator used for the phase shifter includes multiple bidirectional amplifiers, each capable of generating different amplification amounts to achieve gain programmability. In some implementations, each bidirectional amplifier includes a first set of transistors for one signal propagation direction and different unidirectional amplification circuitry for the other signal propagation direction. In other implementations, each bidirectional amplifier includes a first set of transistors and a second set of transistors, with each corresponding transistor set arranged to amplify either the transmitted or received signal. Thus, the first and second transistor sets together form the bidirectional amplifiers of the bidirectional VGA. Different bidirectional amplifiers corresponding to different amplification amounts can be activated or deactivated to establish a target gain for the VGA, where different gain amounts of the VGA correspond to different phase offsets of the associated phase shifter. In some cases, each transistor set includes multiple pairs of transistors (e.g., four differential transistor pairs per set, with two sets per differential bidirectional amplifier, each set containing 16 transistors).

[0019] Within a given transistor group, at least two differential transistor pairs are cross-coupled to each other. Therefore, the output terminals of the first transistor pair have opposite differential polarizations relative to the output terminals of the second transistor pair. In other words, the positive and negative output configurations of the first transistor pair are reversed relative to the positive and negative output configurations of the second transistor pair. For four transistor pairs in a given transistor group, two transistor pairs with the first differential output polarity can be enabled at a first time, allowing a version of the signal with a given amplification to pass through without phase inversion. The other two transistor pairs with the second differential output polarity can be enabled at a second time, allowing a version of the signal with a 180-degree phase change (or phase inversion) at a given amplification to pass through, providing built-in symbol switching capability. In some cases, each respective differential transistor pair can be individually enabled or disabled by a corresponding enabling device (e.g., a switch or a variable current source). If enabled, the differential transistor pair accepts at least one direct current (DC) and amplifies at least one signal component, for example, using a common-source (CS) or common-drain (CD) configuration for each transistor.

[0020] The phase of the signal propagated through the VGA and the VGA's I / O impedance remain substantially constant across gain. This is because the cross-coupling present in each transistor group, and because the same number of transistor pairs are enabled and disabled in each bidirectional amplifier for different operating modes, reduces the likelihood of phase and I / O impedance variations across different gain amounts. Operating modes can include a "normal active" amplification mode, a 180-degree or "reverse active" amplification mode for sign switching, and an inactive or "inactive" amplification mode. In inactive amplification mode, the specific bidirectional amplifier for the VGA does not provide amplitude adjustment.

[0021] Furthermore, the drain-gate parasitic capacitance of each transistor in multiple transistor pairs is essentially neutralized by cross-coupling present within each transistor group of each bidirectional amplifier. Therefore, each transistor group, one for transmission and one for reception, can have transistors whose dimensions are independently determined relative to the transistors in other transistor groups within a given bidirectional amplifier to accommodate different target parameters for transmission and reception performance. In these ways, the described bidirectional phase shifter can be implemented using a bidirectional VGA that provides sign switching across different gain amounts as well as substantially constant phase and I / O impedance. Furthermore, the bidirectional VGA enables custom transistor sizes for both the transmission and reception signal paths.

[0022] In one example, an apparatus for phase shifting a signal is disclosed. The apparatus includes a phase shifter. The phase shifter includes a first positive node, a first negative node, a second positive node, a second negative node, and a bidirectional amplifier. The bidirectional amplifier includes a first transistor coupled between the first positive node and the second negative node, a second transistor coupled between the first negative node and the second positive node, a third transistor coupled between the first positive node and the second negative node, and a fourth transistor coupled between the first negative node and the second positive node. The bidirectional amplifier also includes a fifth transistor coupled between the first positive node and the second positive node, a sixth transistor coupled between the first negative node and the second negative node, a seventh transistor coupled between the first positive node and the second positive node, and an eighth transistor coupled between the first negative node and the second negative node.

[0023] In an example, an apparatus for phase shifting a signal is disclosed. The apparatus includes a phase shifter. The phase shifter includes a first differential interface, a second differential interface, and a bidirectional amplifier. The bidirectional amplifier includes a first transistor pair having an input and an output, wherein the input of the first transistor pair is coupled to the first differential interface. The bidirectional amplifier also includes a second transistor pair having an input and an output, wherein the input of the second transistor pair is coupled to the first differential interface. The bidirectional amplifier includes a third transistor pair having an input and an output, wherein the input of the third transistor pair is coupled to the first differential interface. The bidirectional amplifier includes a fourth transistor pair having an input and an output, wherein the input of the fourth transistor pair is coupled to the first differential interface. The bidirectional amplifier also includes a first polarity means for coupling the outputs of the first transistor pair and the second transistor pair to the second differential interface. The bidirectional amplifier also includes a second polarity means for coupling the outputs of the third transistor pair and the fourth transistor pair to the second differential interface.

[0024] In an example, a method for operating a phase shifter with bidirectional amplification is disclosed. The method includes generating at least one phase of a signal. The method also includes modulating the amplitude of a component of the signal corresponding to the at least one phase. Modulation includes amplifying the component of the signal according to an activity mode. Amplifying the component of the signal according to the activity mode includes enabling a first transistor pair and a second transistor pair. The first and second transistor pairs are coupled to a first interface and are coupled to a second interface via a first polarity. Amplifying the component of the signal according to the activity mode also includes disabling a third transistor pair and a fourth transistor pair. The third and fourth transistor pairs are coupled to the first interface and are coupled to the second interface via a second polarity opposite to the first polarity.

[0025] In an example, an apparatus for phase-shifting a signal is disclosed. The apparatus includes a phase shifter. The phase shifter includes a signal phase generator and at least one bidirectional amplifier coupled to the signal phase generator. The bidirectional amplifier includes a first interface, a second interface, a first transistor group, and a second transistor group. The first transistor group is coupled between the first interface and the second interface. The first transistor group includes four transistor pairs configured to amplify a first signal propagating from the first interface to the second interface. The second transistor group is coupled between the first interface and the second interface. The second transistor group includes four transistor pairs configured to amplify a second signal propagating from the second interface to the first interface. Attached Figure Description

[0026] Figure 1 An example environment is shown that includes an electronic device with a wireless interface device having a radio frequency (RF) front end, which includes at least one phase shifter with a vector modulator.

[0027] Figure 2 An antenna array coupled to an example wireless interface device is shown, the wireless interface device including a communication processor and an RF front end having at least one phase shifter.

[0028] Figure 3-1 An antenna array coupled to an example RF front end is shown, which includes multiple component chains, each of which includes a phase shifter.

[0029] Figure 3-2 An antenna element coupled to an example portion of a component chain is shown, the component chain including a phase shifter that can operate bidirectionally.

[0030] Figure 4-1 This is a block diagram showing an example phase shifter that includes a signal phase generator, a vector modulator, and multiple ports.

[0031] Figure 4-2 This is an operational diagram illustrating an example phase shifter that includes a signal phase generator, a vector modulator, and multiple baluns. Multiple phases of multiple example signal components are depicted using a phasor diagram.

[0032] Figure 5 This is a schematic diagram of an example phase shifter including a signal phase generator and a vector modulator, the vector modulator including at least one variable gain amplifier (VGA).

[0033] Figure 6 This is a schematic diagram showing an example VGA that includes multiple bidirectional amplifiers.

[0034] Figure 7 This is a schematic diagram illustrating an example bidirectional amplifier comprising multiple transistor groups and depicting multiple signal flows.

[0035] Figure 8 This is a schematic diagram illustrating an example bidirectional amplifier comprising multiple transistor groups, each group including multiple transistor pairs.

[0036] Figure 9 This is a circuit diagram showing an example bidirectional amplifier that includes multiple transistor pairs and multiple groups of enabled devices.

[0037] Figure 10-1 This is a circuit diagram showing an example bidirectional amplifier implemented with an example enabling device and an example power distribution network.

[0038] Figure 10-2 This is a circuit diagram showing an example bidirectional amplifier and depicting several example operational aspects.

[0039] Figure 10-3 This is a circuit diagram showing an example bidirectional amplifier implemented with other example enabling devices and another example power distribution network.

[0040] Figure 11-1 This is a circuit diagram showing an example operating configuration of a bidirectional amplifier in a normal active mode for signal amplification.

[0041] Figure 11-2 This is a circuit diagram showing a bidirectional amplifier in an example operating configuration for signal amplification in an inverting active mode.

[0042] Figure 11-3 This is a circuit diagram showing a bidirectional amplifier in an example operating configuration for an inactive mode used for non-amplification.

[0043] Figure 12 This is a flowchart illustrating an example process for phase shifting with bidirectional amplification. Detailed Implementation

[0044] Compared to 4G cellular and existing Wi-Fi networks, next-generation networks (e.g., 5G cellular networks and...) Wi-Fi networks will use higher electromagnetic (EM) frequencies. These higher EM frequencies include millimeter wave (mmWave) frequencies, which can span the EM spectrum from approximately 24 to 300 GHz. Other technologies that can operate at mmWave frequencies include 5G New Radio Spectrum Sharing (5G NR-SS) and... While higher EM frequencies offer greater bandwidth and lower latency, they also present technical challenges. For example, signals transmitted at higher frequencies are attenuated by the atmosphere more quickly and therefore have a shorter inherent range at a given power level. Given this naturally shorter propagation distance, signals can be transmitted via signal beamforming, which directs the signal towards a specific target with more efficient power; this is called antenna beamforming or signal beamforming. Using antenna beamforming, a signal at a given power level can travel much farther as a signal beam compared to omnidirectional transmission.

[0045] Therefore, electronic devices operating under 5G cellular and mmWave Wi-Fi, for example, can use beamforming to direct signals to receiving devices. The wireless interface device of the electronic device is at least partially responsible for generating the signal beam for beamforming communication. To form a transmission signal beam, the wireless interface device uses an antenna array to emit multiple versions of the transmission signal, each modified relative to the others. These modifications allow the signal versions to be combined constructively and destructively during signal propagation. The signal modifications used to generate different signal versions can include amplification by different amounts or phase shifts relative to each other (e.g., delays relative to each other by different durations). A meaningful EM signal combination region generates a signal beam that can be received at a relatively long distance compared to a signal emitted without antenna beamforming. By processing different received signal versions to reconstruct the received signal beam along a certain direction, beamforming technology is used to receive communication signals in a mutually or inverse manner. Although antenna beamforming is described in part with respect to mmWave signaling herein, beamforming is also applicable to other EM frequencies.

[0046] For antenna beamforming, each signal version is typically received from or fed to the corresponding antenna elements of an electronic device's antenna array. To modify different signal versions corresponding to corresponding antenna elements in different antenna elements of the antenna array, a wireless interface device coupled to the antenna array may include a corresponding component chain among multiple component chains for each corresponding antenna element among multiple antenna elements. An electronic device may include multiple antenna arrays, each having multiple antenna elements to target signal beams from different sides of the electronic device. In some architectures, there exists a component chain associated with and coupled to each antenna element of each of the multiple antenna arrays.

[0047] Therefore, within an electronic device, antenna elements are grouped into antenna arrays that can have two to five or more elements per array. Since each electronic device can have two, three, four, or more antenna arrays, the total number of antenna elements in a single electronic device can range from four to 20 or more. For example, if an electronic device includes three antenna arrays, each with four antenna elements, the electronic device can include a dozen or more antenna elements, and thus a dozen or more corresponding component chains. Therefore, the impact of each individual physical component present in each component chain (e.g., the negative impact caused by any individual physical component) is multiplied by the number of antenna elements included in the electronic device. Examples of negative impacts include the size occupied by an individual physical component, the power usage of the component, or the loss of signal strength delivered to the signal being processed by the component. For example, as the size of the physical components increases, larger components occupy more space within the electronic device and increase the cost of the device.

[0048] An example of an individual physical component that can be included in each component chain is a phase shifter. A phase shifter can adjust the phase of a version of a wireless signal relative to other versions of the signal to enable beamforming for mmWave and other wireless communication frequencies. A phase shifter can be constructed using, for example, a signal phase generator and a vector modulator. The signal phase generator and the vector modulator are coupled to each other, and both process the version of the signal propagating through the phase shifter.

[0049] In some implementations, a signal phase generator converts a signal having a phase corresponding to one of its components into a split signal having at least two components corresponding to at least two phases of the signal. The two phases of the split signal can be separated by ninety degrees (90°), for example, by 0° and 90° phase. Such a split signal can be described as having an in-phase (I) signal component (e.g., with a 0° phase) and a quadrature (Q) signal component (e.g., with a 90° phase). The vector modulator of the phase shifter can be implemented using an amplifier that modulates the relative amplitudes of the components of the split signal. In a single-ended environment, the vector modulator can modulate two signal components, which can correspond to the 0° and 90° phases of the split signal. In a differential environment, the vector modulator can modulate four signal components, which can correspond to the 0°, 90°, 180°, and 270° phases of the split signal. After recombination of the amplitude-modulated components of the split signal, relative amplitude modulation can effectively change the phase of a given component chain of signals flowing through a given antenna element to support beam control operation.

[0050] Phase shifters can be implemented entirely or partially passively or actively. Passive phase shifters can be used to achieve approximately three-bit resolution, where the number of bits determines the granularity of the phase shift. The number of bits in a passive phase shifter is limited by the large size of the passive components that make up the passive phase shifter (e.g., resistors, capacitors, and / or inductors) and the significant attenuation caused by them. On the other hand, active phase shifters can achieve higher bit resolution to obtain finer phase shift granularity. Unlike the 45° phase shift increment limited to using a three-bit phase shifter, 22.5° and 11.25° phase shift increments can be achieved using four-bit and five-bit phase shifters, respectively. This allows for finer targeting of the signal beam when using, for example, a five-bit active phase shifter, compared to a three-bit passive phase shifter.

[0051] In some environments, active phase shifters can utilize active vector modulators that include variable gain amplifiers (VGAs). However, VGAs affect various performance characteristics of signal beamforming. Furthermore, these performance characteristics, influenced by the operation of each VGA as part of the phase shifter, can propagate along each component chain of the antenna array and thus affect the quality of the signal beam. For example, if the gain of a VGA is programmed at each of multiple component chains to adjust the phase offset, the phase or input / output (I / O) impedance (or both) of each VGA can be altered through some VGA design. When the phase or I / O impedance of a VGA changes due to VGA gain programming, the resulting signal beam may fail to provide the intended coverage area or even reach the target destination device.

[0052] Furthermore, many active vector modulators and VGAs are unidirectional, meaning that such a VGA cannot be readily used for both transmit and receive operations using a given antenna element. Therefore, this unidirectional active vector modulator is repeated at each antenna element. In other words, the transmit path includes one instance of the active vector modulator, and the receive path includes another instance. Since a single electronic device can include 4, 9, 16, or more antenna elements distributed across two, three, or more antenna arrays, repeating the unidirectional active vector modulator for each antenna element consumes a significant amount of area on one or more transceiver integrated circuit (IC) chips. Moreover, as mentioned above, some active vector modulators introduce signal phase changes with gain adjustment and / or present different I / O impedances during or after gain adjustment, which are used to change the phase offset provided by associated phase shifters. Additionally, existing bidirectional amplifiers utilize area-consuming inductors or include additional switches along the signal propagation path, which affects signal characteristics. Other bidirectional amplifiers still require size-matched transistors to amplify the signal transmitted in both the transmit and receive directions. Therefore, transistor sizes cannot be independently set for signals transmitted in opposite directions, which makes it possible to tune the performance characteristics of transmission and reception operations separately.

[0053] In contrast, some of the described implementations target phase shifters that include a signal phase generator and an active vector modulator. The active vector modulator is implemented using a bidirectional VGA. Therefore, a bidirectional phase shifter can be implemented if a bidirectional VGA is paired with a bidirectional signal phase generator. Examples of described bidirectional VGAs maintain phase and I / O impedance between adjustments for different gain amounts used to modulate the amplitudes of the signal components (e.g., I and Q signal vectors) of the split signal by different amplification values. Furthermore, the described implementation of the bidirectional VGA provides built-in symbol switching capability. This implementation also offers the opportunity that the size of the transistor used to amplify the transmitted signal can be determined independently, compared to the transistor used to amplify the received signal. Independently determining the size of the amplifying transistor allows the noise figure and linearity performance to be tuned separately for transmission and reception operations.

[0054] In the example implementation, the bidirectional VGA for the vector modulator used for the phase shifter includes multiple bidirectional amplifiers, each capable of providing a different amplification level. Each bidirectional amplifier includes a first group of transistors and a second group of transistors, and each corresponding group of transistors is arranged to amplify either the transmitted or received signal. Thus, the first and second groups of transistors together form the bidirectional amplifier of the VGA. The different bidirectional amplifiers corresponding to the different amplification levels can be activated or deactivated to establish the target gain of the VGA. As part of the associated phase shifter, the different gain amounts of the VGA correspond to the different phase offsets of the associated phase shifter. In some cases, each group of transistors includes multiple pairs of transistors (e.g., four differential transistor pairs per group, with two groups per differential bidirectional amplifier, each group containing 16 transistors).

[0055] Within a given transistor group, at least two differential transistor pairs are cross-coupled to each other. Therefore, with respect to the same differential polarization at the input terminals of both transistor pairs, the output terminals of the first transistor pair have opposite differential polarizations relative to the output terminals of the second transistor pair. In other words, the positive and negative output configurations of the first transistor pair are inverted relative to the positive and negative output configurations of the second transistor pair. For four transistor pairs in a given transistor group, two transistor pairs having the same first differential output polarity can be enabled at a first time to allow a version of the signal at a given amplification level to pass without phase inversion. The other two transistor pairs are disabled during this first time period. Another two transistor pairs having the same second differential output polarity (opposite to the first differential output polarity) can be enabled at a second time to allow a version of the signal at a given amplification level to pass with a 180-degree phase change (or phase inversion), providing built-in symbol switching capability. In some cases, each respective differential transistor pair can be individually enabled or disabled using a corresponding enabling device (e.g., a switch or a variable current source). If enabled, the differential transistors accept direct current (DC) and amplify at least one signal component, for example, by using a common-source (CS) or common-drain (CD) configuration for each transistor.

[0056] Both the phase of the propagating signal version and the I / O impedance of the bidirectional VGA can remain substantially constant across different gain adjustments. The possibility of phase and I / O impedance variations is reduced due to the cross-coupling connections in each transistor group and the same number of transistor pairs enabled for different operating modes. Operating modes can include a "normal active" amplification mode, a 180-degree or "reverse active" amplification mode, and an inactive or "inactive" amplification mode. In inactive amplification mode, the specific bidirectional amplifier of the VGA enables two transistor pairs with opposite differential output polarities without amplitude adjustment. Furthermore, the drain-gate parasitic capacitance of each transistor in the multiple transistor pairs is substantially neutralized by the cross-coupling present within each transistor group of each bidirectional amplifier. Therefore, each transistor group, one for transmission and one for reception, can have transistors with dimensions independently determined relative to the transistors in other transistor groups to accommodate different target parameters for transmission and reception performance.

[0057] As described herein, a bidirectional VGA can be formed using multiple bidirectional amplifiers, and this bidirectional VGA can be used to implement a bidirectional vector modulator with a phase shifter. This reduces the number of vector modulators included as part of an electronic device. Furthermore, a bidirectional phase shifter can be implemented if a bidirectional signal phase generator is coupled to the bidirectional vector modulator. In some implementations, each bidirectional amplifier includes four transistor pairs in a first transistor group for transmission and another four transistor pairs in a second transistor group for reception. Therefore, the transistors can be adjusted separately for transmission and reception operations. Within each group of four transistor pairs, two transistor pairs are cross-coupled relative to the other two transistor pairs from the perspective of the transistor's I / O terminals and differential polarity. In operation, different amplification modes are used separately by activating two of the four transistor pairs. In these ways, substantially constant phase and I / O impedance can be maintained across different amplification adjustments or different gain amounts in the bidirectional VGA.

[0058] Figure 1 An example environment 100 is illustrated, comprising an electronic device 102 having a wireless interface device 120, which has a radio frequency (RF) front-end 128 including at least one phase shifter 130. The phase shifter 130 includes at least one signal phase generator 132 and at least one vector modulator 134. In environment 100, the example electronic device 102 communicates with a base station 104 via a wireless link 106. Figure 1In this context, electronic device 102 is depicted as a smartphone. However, electronic device 102 can be implemented as any suitable computing or other electronic device, such as a cellular base station, broadband router, access point, user equipment or mobile phone, gaming device, navigation device, media device, laptop computer, desktop computer, tablet computer, server computer, network attached storage (NAS) device, smart appliance, vehicle-based communication system, Internet of Things (IoT) device, sensor or security device, asset tracker, fitness management device, wearable device such as smart glasses or smartwatch, wireless power device (transmitter or receiver), medical device, etc.

[0059] Base station 104 communicates with electronic device 102 via wireless link 106, which can be implemented as any suitable type of wireless link carrying communication signals. Although depicted as a base station tower of a cellular radio network, base station 104 can be represented or implemented as another device, such as a satellite, terrestrial broadcast tower, access point, peer-to-peer device, mesh network node, fiber optic line, or another electronic device as generally described above. Therefore, electronic device 102 can communicate with base station 104 or another device via wired connection, wireless connection, or a combination thereof.

[0060] Wireless link 106 extends between electronic device 102 and base station 104. Wireless link 106 may include a downlink transmitting data or control information from base station 104 to electronic device 102, and an uplink transmitting other data or control information from electronic device 102 to base station 104. Wireless link 106 may be implemented using any suitable communication protocol or standard. Examples of such protocols and standards include 3GPP standards, such as Long Term Evolution (LTE), 4G, or 5G cellular standards; IEEE 802.11 standards, such as 802.11g, ac, ax, ad, aj, or ay standards, including Wi-Fi 6; and IEEE 802.16 standards (e.g., WiMAX). TM Bluetooth TM Standards; etc. In some implementations, the wireless link 106 may be wirelessly powered, and the electronic device 102 or base station 104 may include a power supply.

[0061] As shown in the figure, electronic device 102 includes at least one application processor 108 and at least one computer-readable storage medium 110 (CRM 110). The application processor 108 may include any type of processor, such as a central processing unit (CPU) or a multi-core processor, configured to execute processor-executable instructions (e.g., code) stored in the CRM 110. The CRM 110 may include any suitable type of data storage medium, such as volatile memory (e.g., random access memory (RAM)), non-volatile memory (e.g., flash memory), optical media, magnetic media (e.g., magnetic disk or magnetic tape), etc. In the context of this disclosure, the CRM 110 is implemented to store instructions 112, data 114, and other information of electronic device 102, and therefore the CRM 110 does not include transient propagation signals or carrier waves.

[0062] Electronic device 102 may also include one or more input / output ports 116 (I / O ports 116) or at least one display 118. I / O ports 116 enable data exchange or interaction with other devices, networks, or users. I / O ports 116 may include serial ports (e.g., Universal Serial Bus (USB) ports), parallel ports, audio ports, infrared (IR) or radar ports, camera or other sensor ports, etc. Display 118 may be implemented as a display screen or projector that displays one or more graphical images generated by electronic device 102, such as a user interface associated with an operating system, program, or application. Alternatively or additionally, display 118 may be implemented as a display port or virtual interface through which graphical content of electronic device 102 can be transmitted or displayed.

[0063] Electronic device 102 also includes at least one wireless interface device 120 and at least one antenna array 122. The wireless interface device 120 provides connectivity to a corresponding network and peer devices via a wireless link, which may be configured similarly or differently from wireless link 106. Alternatively or additionally, electronic device 102 may include a wired interface device (not shown), such as an Ethernet or fiber optic transceiver, for communication over a wired local area network (LAN), intranet, or the Internet. Wireless interface device 120 can facilitate communication over any suitable type of wireless network, such as a wireless LAN (WLAN), wireless personal area network (PAN) (WPAN), peer-to-peer (P2P) network, mesh network, cellular network, wireless wide area network (WAN) (WWAN), and / or navigation network (e.g., North American Global Positioning System (GPS) or other satellite positioning systems (SPS) or Global Navigation Satellite Systems). In the context of example environment 100, electronic device 102 can bidirectionally transmit various data and control information with base station 104 via wireless interface device 120. However, electronic device 102 may additionally or alternatively communicate directly with other peer devices, alternative wireless networks, etc.

[0064] As shown, the wireless interface device 120 includes at least one communication processor 124, at least one transceiver 126, and at least one RF front-end 128 (RFFE 128). These components process data information, control information, and signals associated with transmitting information to the electronic device 102 via the antenna array 122. The communication processor 124 may be implemented as at least a portion of a system-on-a-chip (SoC), a modem baseband processor, or a baseband radio processor (BBP) that enables a digital communication interface for data, voice, messaging, or other applications of the electronic device 102. The communication processor 124 includes a digital signal processor (DSP) or one or more signal processing blocks (not shown) for encoding and modulating data for transmission and for demodulating and decoding received data. Furthermore, the communication processor 124 may also manage (e.g., control or configure) aspects or operations of the transceiver 126, the RF front-end 128, and other components of the wireless interface device 120 to implement various communication protocols or communication technologies, such as antenna beamforming.

[0065] In some cases, application processor 108 and communication processor 124 may be combined into a single module or integrated circuit (IC), such as a SoC. In any case, application processor 108 or communication processor 124 may be operatively coupled to one or more other components, such as CRM 110 or display 118, to enable control of or other interaction with other components of electronic device 102. Thus, operative coupling can enable components to perform functions together or interoperate as described herein. Communication processor 124 may also include memory (not shown separately), such as CRM 110, for storing data and processor-executable instructions (e.g., code).

[0066] Use separate illustrative boxes Figure 1 The various components shown (and other figures) can be manufactured or packaged in different discrete or integrated ways. For example, one physical module may include components of the RF front-end 128 and a portion of the transceiver 126, and another physical module may combine the communication processor 124 with the remaining components of the transceiver 126. Additionally or alternatively, at least one antenna array 122 may be co-packaged with at least some components of the RF front-end 128 as an antenna module. Furthermore, the electronic device 102 may include a plurality of such antenna modules, thereby distributing the various physical components of at least one RF front-end 128 within the internal space of the housing of the electronic device 102.

[0067] Transceiver 126 may include circuitry and logic for filtering, amplification, channelization, and frequency conversion. Frequency conversion may include up-conversion or down-conversion performed in a single conversion operation (e.g., using a direct conversion architecture) or through multiple conversion operations (e.g., using a superheterodyne architecture). Transceiver 126 may include filters, switches, amplifiers, mixers, etc., for routing and regulating signals transmitted or received via antenna array 122. Although not explicitly shown, wireless interface device 120 may also include a digital-to-analog converter (DAC) or analog-to-digital converter (ADC) for converting analog signals to digital signals. The DAC or ADC may be implemented as part of communication processor 124, part of transceiver 126, or separately from both.

[0068] The components or circuitry of transceiver 126 can be implemented in any suitable manner, such as combined transceiver logic or individually as respective transmitter and receiver entities. In some cases, transceiver 126 is implemented in multiple or different parts to achieve respective transmit and receive operations (e.g., separate transmit and receive chains are implemented separately). Transceiver 126 may also include logic that performs in-phase / quadrature (I / Q) operations, such as combining, phase correction, modulation, demodulation, etc.

[0069] Typically, RF front-end 128 includes one or more filters, switches, or amplifiers for conditioning signals received via antenna array 122 or for conditioning signals to be transmitted via antenna array 122. As shown, RF front-end 128 includes at least one phase shifter 130 (PS 130). RF front-end 128 may also include other RF sensors and components, such as peak detectors, power meters, gain control blocks, antenna tuning circuitry, N-way multiplexers, baluns, etc. Configurable components of RF front-end 128 (e.g., phase shifter 130) can be controlled by communication processor 124 to enable communication using different frequency bands or various modes employing antenna beamforming. Although phase shifter 130 is depicted as part of RF front-end 128, typically, the described implementation of phase shifter 130 can alternatively be used in another part of wireless interface device 120 (e.g., transceiver 126) or another part of electronics 102.

[0070] In an example implementation, phase shifter 130 includes at least one signal phase generator 132 and at least one vector modulator 134 coupled to each other. Signal phase generator 132 alters the number of phases of the signal, for example, by generating at least one phase to increase the number of phases. For example, signal phase generator 132 can generate in-phase (I) signal components and quadrature (Q) signal components (e.g., two phases for single-ended signaling) from in-phase signal components (e.g., one phase for single-ended signaling). Vector modulator 134 can adjust the amplitude of at least one component of the signal passing through the circuitry of vector modulator 134. This adjustment can include increasing the signal amplitude (e.g., positive amplification, amplification with a gain greater than 1, or amplification) or decreasing the signal amplitude (e.g., negative amplification, amplification with a gain between 0 and 1, or attenuation). Example implementations of signal phase generator 132 and vector modulator 134 are described below. Figure 4-1 and Figure 4-2 Begin the description.

[0071] As shown in the figure, the vector modulator 134 can be implemented using at least one variable gain amplifier 136 (VGA 136). For example, the vector modulator 134 may include a VGA 136 for the in-phase signal channel and another VGA 136 for the quadrature signal channel. The VGA 136 described herein can typically be additionally or alternatively deployed in other parts of the wireless interface device 120 or electronic device 102. The following describes... Figure 5 The description begins with an example implementation of a vector modulator 134 including at least one VGA136. (See reference...) Figure 6 Each VGA 136 may include at least one bidirectional amplifier to enable the bidirectional vector modulator 134 and support the bidirectional phase shifter 130.

[0072] In some implementations, antenna array 122 is implemented as at least one antenna array comprising a plurality of antenna elements. Therefore, as used herein, depending on the context, “antenna” can refer to at least one antenna array or at least one antenna element. To achieve antenna beamforming, corresponding phase shifters 130 are coupled to each corresponding antenna element of antenna array 122, which will be referred to below. Figure 3-1 and Figure 3-2 Describe it. See below for reference. Figure 2 Additional aspects of antenna beamforming are described for the wireless interface device 120 and the antenna array 122.

[0073] Figure 2 An example implementation of an antenna array 122 coupled to a wireless interface device 120 is shown at 200, the wireless interface device 120 including a communication processor 124 and an RF front-end 128. The example signal flow direction 202 is depicted bidirectionally. Therefore, signals can flow through the wireless interface device 120 in both directions to accommodate both transmitted and received signals. As shown, the communication processor 124 is coupled to a transceiver 126, and the transceiver 126 is coupled to the RF front-end 128, which includes at least one phase shifter 130. Although not explicitly shown, the communication processor 124 may be coupled to... Figure 1 Other components of the electronic device 102, such as application processor 108, CRM 110, or display 118.

[0074] In operation, antenna array 122 emits signals for transmission or sensing for reception of at least one wireless signal 206. Through antenna beamforming, the wireless signal 206 can include multiple signal versions and can be transmitted or received via at least one signal beam 210. Using beam control, the wireless signal 206 can thus be transmitted or received relative to at least one angle 204 to provide wireless communication directionality. For this purpose, phase shifter 130 of RF front end 128 shifts the phase of the signal version propagating through phase shifter 130, wherein the propagating signal was previously received as wireless signal 206 or targeted for transmission as wireless signal 206. Therefore, signal beam 210 can be directed to a destination device for transmission operation or to the source of wireless signal 206 for reception operation.

[0075] The phase shift of phase shifter 130 can be controlled by communication processor 124 using at least one phase control signal 208. Communication processor 124 can generate phase control signal 208 in response to beamforming parameters indicating a target degree of angle 204, phase shift, or phase delay. This control of phase shift is further described below. Alternatively, transceiver 126 can generate or provide phase control signal 208. More generally, controller 212 can generate or provide phase control signal 208. Controller 212 can be part of at least one of communication processor 124 or transceiver 126, or can be separate from both.

[0076] Figure 3-1 Generally, at 300-1, antenna array 122 is shown coupled to an example RF front-end 128, which includes multiple component chains 304-1, 304-2, 304-3, ..., 304-N, where "N" represents a positive integer (e.g., two or more for beamforming). Here, each component chain 304 includes at least one phase shifter 130 (PS 130). Antenna array 122 includes multiple antenna elements 302-1, 302-2, 302-3, ..., 302-N, where "N" represents a positive integer (e.g., two or more for beamforming). Each corresponding antenna element 302 (AE 302) of the multiple antenna elements 302-1, ..., 302-N is coupled to the corresponding component chain 304 of the multiple component chains 304-1, ..., 304-N. For example, the first component chain 304-1 is coupled to the first antenna element 302-1, and the second component chain 304-2 is coupled to the second antenna element 302-2.

[0077] In the example implementation, each of the multiple component chains 304 304-1, ..., 304-N is coupled to at least one signal coupler 306. The signal coupler 306 can function as a combiner / splitter. For example, the signal coupler 306 can combine multiple signal versions received from the multiple component chains 304-1, ..., 304-N into a combined signal for receive operations. The signal coupler 306 can also separate the signal into multiple signal versions and provide these versions to the multiple component chains 304-1, ..., 304-N for transmit operations. Although a single four-to-one signal coupler 306 is explicitly shown, multiple signal couplers can be implemented instead. For example, for N=4, two two-to-one (2-to-1) signal couplers (e.g., such as...) Figure 3-2 (As shown in the middle part) can be coupled to multiple component chains 304-1, ..., 304-N.

[0078] As explicitly shown for the first component chain 304-1, each corresponding component chain 304 includes a phase shifter 130, an amplifier 310, and at least one other component 308. However, a given component chain 304 may include more, fewer, or different components. The signal flow direction 202 along each component chain 304 can be bidirectional, as indicated by the double-headed arrow. As shown, these physical components of the corresponding component chain 304 are coupled together in series between the signal coupler 306 and the corresponding antenna element 302 of the antenna array 122. Another component 308 is closest to the signal coupler 306, and the amplifier 310 is closest to the antenna element 302. Thus, the phase shifter 130 is coupled between the other component 308 and the amplifier 310. However, the order of these physical components along a given component chain 304 may be different.

[0079] Amplifier 310 can be implemented in different ways. For example, amplifier 310 can be implemented as a power amplifier 310-1 (PA) for transmission operation (PA 310-1) or a low-noise amplifier 310-2 (LNA) for reception operation (LNA 310-2). Another component 308 can be implemented as a filter, another amplifier, a mixer, etc. Thus, phase shifter 130 can provide a phase-shifted signal to PA 310-1 for amplification and forwarding to the corresponding antenna element 302 for emission from there. Phase shifter 130 can additionally or alternatively accept the amplified signal from LNA 310-2 for phase shifting and then forwarding to other components 308, or, in the absence of other components 308, for "direct" forwarding to signal coupler 306.

[0080] In the example operation, each corresponding component chain 304 adjusts or conditions the signal propagating between the signal coupler 306 and the corresponding antenna element 302. Therefore, each corresponding component chain 304 modifies the signal version to produce a corresponding signal version with a different corresponding phase or amplitude suitable for supplying to or receiving from the corresponding antenna element 302 to support beam control operation. For this purpose, the phase shifter 130 can perform phase shifting operation based on the phase control signal 208 as described herein.

[0081] exist Figure 3-1 In the diagram, signal 324 is depicted with respect to component chain 304-1. Signal 324 can propagate along component chain 304-1 between signal coupler 306 and antenna element 302-1. Each signal 324 can represent wireless signal 206. Figure 2One version of this signal. Other versions of this signal can propagate through other component chains. As shown by the dashed appearance of the arrow representing signal 324, signal 324 can be implemented as a bidirectional signal, a unidirectional signal, or a combination thereof as it passes through different parts of component chain 304-1. See below for further details. Figure 3-2 Describes the implementation of the bidirectional signal 324 during propagation across phase shifter 130.

[0082] Figure 3-2 Overall, the circuit 300-2 shows coupling to component chain 304 (e.g., Figure 3-1 The example portion of the antenna element 302 includes a component chain 304 comprising a bidirectionally operable phase shifter 130. As shown, the phase shifter 130 includes multiple ports: a first port 352-1 and a second port 352-2. The phase shifter 130 is coupled to a signal coupler 306 via the first port 352-1 and to an amplifier 310 via the second port 352-2. However, the orientation of the phase shifter 130 can be reversed, such that the first port 352-1 is positioned closer to the antenna element 302 and the second port 352-2 couples the phase shifter 130 to the signal coupler 306. Although not explicitly shown, another phase shifter 130 can be coupled to the illustrated signal coupler 306, which... Figure 3-2 It is depicted as a two-to-one (2-to-1) signal coupler. In addition, another 2-to-1 signal coupler 306 and two additional phase shifters can be deployed to serve the antenna array 122 with four antenna elements.

[0083] Switch 356 switchesably couples phase shifter 130 to amplifier 310. As shown, switch 356 is implemented using a single-pole double-throw switch. Therefore, switch 356 includes a pole coupled to the second port 352-2 of phase shifter 130 and two throws: a top throw and a bottom throw. Switch 356 can selectively connect the second port 352-2 of phase shifter 130 to the input of PA 310-1 via the top throw or to the output of LNA 310-2 via the bottom throw. However, switch 356 can be implemented differently.

[0084] The output of PA 310-1 is coupled to antenna element 302. The input of LNA 310-2 is coupled to antenna element 302 via switch 358. Switch 360 can couple the input of LNA 310-2 to ground. Figure 3-2 As shown, switches 358 and 360 are in the open and closed states, respectively, to enable transmission operation. To enable reception operation, switch 358 can be closed, and switch 360 can be open. However, different numbers or arrangements of switches can be implemented to couple various physical components of the component chain to each other or to the antenna element 302.

[0085] In some implementations, the bidirectional signal 324 passes through the phase shifter 130. The bidirectional signal 324 propagates between the signal coupler 306 and the switch 356 via the phase shifter 130. Therefore, the phase shifter 130 can be used for both transmission and reception operations. An example implementation of a bidirectional phase shifter with a bidirectional vector modulator is described below based on a bidirectional VGA including one or more bidirectional amplifiers. Figure 3-2 The diagram also depicts a unidirectional signal propagating between switch 356 and antenna element 302. Specifically, the unidirectional transmission signal 324-1 propagates from switch 356 to antenna element 302 while passing through PA 310-1. On the other hand, the unidirectional reception signal 324-2 propagates from antenna element 302 to switch 356 while passing through LNA 310-2.

[0086] Figure 4-1 This is a block diagram 400-1 illustrating an example phase shifter 130, which includes a signal phase generator 132, a vector modulator 134, and multiple ports. The multiple ports include a first port 352-1 (P1) and a second port 352-2 (P2). As shown, the first port 352-1 is coupled to the signal phase generator 132, and the second port 352-2 is coupled to the vector modulator 134. However, these couplings to the ports can be interchanged, for example, such that the vector modulator 134 is coupled closer to the first port 352-1 than to the signal phase generator 132.

[0087] Vector modulator 134 includes at least one VGA 136 and multiple interfaces, such as a first interface 402-1 and a second interface 402-2. Vector modulator 134 is coupled to signal phase generator 132 via the first interface 402-1 and to a second port 352-2 via the second interface 402-2. Therefore, the second port 352-2 may include the second interface 402-2, or vice versa, if no other components are electrically disposed between the second interface 402-2 and the second port 352-2. Alternatively, vector modulator 134 may be coupled to signal phase generator 132 via the second interface 402-2 instead of the first interface 402-1.

[0088] In example operation, signal phase generator 132 converts a first number of phases (e.g., one or two phases) of signal 324 into a second number of phases (e.g., two or four phases respectively) of signal 324. Each phase can be implemented as a signal component of signal 324 propagating through at least a portion of phase shifter 130. In particular, signal phase generator 132, in particular vector modulator 134, or phase shifter 130 can typically recombine signal components to propagate along component chain 304 (e.g., Figure 3-1Before forwarding the phase-shifted signal to another physical component, the phase-shifted signal is "converted" from a second number of phases back to a first number of phases. Therefore, the signal phase generator 132 generates one or more phases of the signal to produce a split signal with at least two signal components.

[0089] Vector modulator 134 adjusts the amplitude of at least one signal component of signal 324 based on phase control signal 208, which may be provided by controller 212. For example, by increasing or decreasing the amplitude of at least one of in-phase signal component (I signal component) or quadrature signal component (Q signal component) using vector modulator 134, phase shifter 130 can shift the phase of signal 324 while it propagates through phase shifter between first port 352-1 and second port 352-2 along either signal flow direction 202. As further described below, signal phase generator 132 can operate on the propagating signal "before" vector modulator 134 so that the signal passes through phase shifter 130 in a first direction (e.g., from first port 352-1 to second port 352-2). However, vector modulator 134 can operate on the propagating signal "before" signal phase generator 132 so that the signal passes through phase shifter 130 in an opposite second direction (e.g., from second port 352-2 to first port 352-1). This flexible operating sequence of the signal phase generator 132 relative to the vector modulator 134 facilitates bidirectional operation of the phase shifter 130.

[0090] In the example implementation, at least a portion of the phase shifter 130 operates actively rather than passively. For example, as described herein, at least the vector modulator 134 can be implemented as an active vector modulator 134. To power the active component, the phase shifter 130 is coupled to at least one power distribution network 404 (PDN 404) of the associated wireless interface device 120, such as the power distribution network for the RF front end 128 of the wireless interface device 120. The power distribution network (PDN) 404 includes at least one PDN node 408. Examples of PDN nodes 408 include a power node 408-1 and a ground node 408-2.

[0091] Power node 408-1, which may be at least a portion of the voltage rail, is coupled to a power source providing the supply voltage. An example of such a power source is a power management integrated circuit (PMIC) (not shown). Ground node 408-2 may be at least a portion of the ground plane of one or more circuits. In operation, distribution network 404 may provide a direct current (DC) 406 to the active circuitry of phase shifter 130. DC current 406 may flow from power node 408-1 to ground node 408-2. The PDN node and DC current will be referenced... Figures 10-1 to 10-3 Further description.

[0092] Figure 4-2 This is an operational diagram 400-2 illustrating an example phase shifter 130, which includes a signal phase generator 132, a vector modulator 134, and multiple baluns (B) 452-1, 452-2, and 452-3. Operational diagram 400-2 uses phasor diagrams to depict multiple phases 454-1, 454-2, ..., 454-13 and 454-14 of multiple example signal components. Each phasor diagram includes two orthogonal axes arranged within a circle and lines representing angular vectors. As indicated by the solid double-headed arrow representing signal 324, phase shifter 130 can propagate signal 324 from a first port 352-1 to a second port 352-2 or from a second port 352-2 to a first port 352-1. For clarity, the following description of an example operation of phase shifter 130 is based on the case where signal 324 passes from the first port 352-1 through phase shifter 130 to the second port 352-2.

[0093] In the example implementation, phase shifter 130 includes at least one balun 452 (B 452). Each balun 452 can convert a signal from a single-ended signal to a differential signal and vice versa. For example, a balun 452 can convert a signal with one phase (e.g., 0° phase) to a signal with two relative phases (e.g., 0° phase and 180° phase). The balun 452 can be implemented using, for example, a transformer. Figure 4-2 In this configuration, the first port 352-1 is coupled to the signal phase generator 132. The signal phase generator 132 is coupled to the vector modulator 134 via a first balun 452-1 and a second balun 452-2. The vector modulator 134 is coupled to the second port 352-2 via a third balun 452-3. In this configuration, both the first port 352-1 and the second port 352-2 provide single-ended signaling paths for signals entering or leaving the phase shifter 130. However, in other implementations, one or both ports may be modified to provide differential signaling paths. For example, the signal phase generator 132 may be designed to operate on differential signals, or the third balun 452-3 may be omitted.

[0094] In the example operation, signal 324 arrives at first port 352-1 with phase 454-1. In this example, a 45° phase is used for this signal component so that the phase angle is not obscured by the axes of the phasor diagram. Signal phase generator 132 receives the signal component with a 45° phase from first port 352-1 on its first side. Signal phase generator 132 generates one or more phases from the received signal component and provides one or more generated phases as two signal components on its second side. These two signal components of signal 324 include a phase 454-2 at 45° and another phase 454-3 at 135°.

[0095] Therefore, the two signal components on the second side of the signal phase generator 132 have a phase gap of 90°. Alternatively, using the differential signal phase generator 132, the signal phase generator 132 can generate four signal components with phases of 0°, 90°, 180°, and 270° from two signal components with phases of 0° and 180°. However, here, two baluns are used to generate the differential signal. From the signal component with a phase of 45° 454-2, the first balun 452-1 generates two signal components with phases of 45° 454-4 and 225° 454-5 (e.g., signals 180° apart). From the signal component with a phase of 135° 454-3, the second balun 452-2 generates two signal components with phases of 135° 454-6 and 315° 454-7. The four signal components supplied to the vector modulator 134 via the first balun 452-1 and the second balun 452-2 are therefore each 90° apart with a relative phase of 45°, 135°, 225°, and 315°. Thus, these four signal components can correspond to the positive in-phase signal component (I+ signal component), the positive quadrature signal component (Q+ signal component), the negative in-phase signal component (I- signal component), and the negative quadrature signal component (Q- signal component), respectively.

[0096] At any given stage of the phase-shifting process performed along phase shifter 130, the individual phases are shown and described relative to each other. Thus, phases 454-2 and 454-3 are 90° apart at this stage of phase shifter 130. For clarity, they are depicted as 45° and 135° respectively. Nevertheless, the phases at different stages can have different relationships. In other words, the 45° phase 454-1 on the first side of signal phase generator 132 can be different from the 45° phase 454-2 on the second side of signal phase generator 132.

[0097] Continuing with the example operation of phase shifter 130, vector modulator 134 receives four signal components corresponding to four phases 454-4 to 454-7. Vector modulator 134 adjusts the amplitude of one or more of these four signal components by increasing or decreasing their amplitude based on phase control signal 208. Vector modulator 134 can also allow signal components to pass through with substantially no change in their amplitude. Here, the amplitudes of the signal components corresponding to phases 454-4 and 454-5 are not changed by vector modulator 134. Therefore, vector modulator 134 generates a first signal component corresponding to phase 454-8 with an amplitude unchanged compared to phase 454-4, and a second signal component corresponding to phase 454-9 with an amplitude unchanged compared to phase 454-5.

[0098] In contrast, vector modulator 134 does modulate the amplitudes of the two other signal components. Vector modulator 134 generates a third signal component corresponding to phase 454-10 and with an amplitude increased compared to phase 454-6. Similarly, vector modulator 134 generates a fourth signal component corresponding to phase 454-11 and with an amplitude increased compared to phase 454-7. This is graphically represented by phasor arrows for phases 454-10 and 454-11 that are relatively longer than those for phases 454-6 and 454-7.

[0099] The "right-side" interface of the vector modulator 134 (e.g.) Figure 4-2 The four components at (shown) are then combined into positive-positive and negative-negative pairs, as described below, to produce a phase-adjusted differential signal. The first component corresponding to phase 454-8 and the third component corresponding to phase 454-10 are combined to produce another component corresponding to phase 454-12. This is equivalent to "recombining" the two positive components: the I+ signal component and the Q+ signal component. As shown, the phasor of phase 454-12 represents an angle of 110°. Because the amplitude of the third signal component, now at 135° phase 454-10, is greater than the amplitude of the first signal component, at 45° phase 454-8, the phase angle of the combined signal component is shifted to the 135° phase (e.g., from a 90° phase generated by two equal amplitudes at 45° and 135° phases, to the depicted 110° phase 454-12). The second component corresponding to phase 454-9 is combined with the fourth component corresponding to phase 454-11 to produce another component corresponding to phase 454-13. This is equivalent to "recombining" the two negative components: the I-signal component and the Q-signal component. As shown in the figure, the phasor of phase 454-13 represents an angle of 290°.

[0100] In this way, phase shifter 130 can use signal phase generator 132 and vector modulator 134 to shift the phases of the two differential signal components of phases 454-4 and 454-5 by a phase offset of 65° (e.g., from 45° of phase 454-4 to 110° of phase 454-12 and from 225° of phase 454-5 to 290° of phase 454-13). In this case, phase shifter 130 is coupled to another component at a second port 352-2 for single-ended signaling. Therefore, third balun 452-3 converts the differential signaling with two components of phases 454-12 and 454-13 into single-ended signaling with a phase of 110° for phase 454-14. Therefore, as signal 324 propagates from the first port 352-1 to the second port 352-2, phase shifter 130 shifts the phase of signal 324 by 65° from 45° in phase 454-1 to 110° in phase 454-14. Thus, via antenna element 302 ( Figure 3-1 and Figure 3-2 ) transmitted or received wireless signals 206 Figure 2 The phase of the version can be shifted to support beamforming operations.

[0101] The phase shifter 130 has already been described above in terms of the signal 324 traversing the depicted components from the first port 352-1 to the second port 352-2. However, the phase shifter 130 can operate bidirectionally, allowing the signal 324 to propagate from the second port 352-2 to the first port 352-1. For the bidirectional phase shifter 130, the timing sequence of signal processing between the signal phase generator 132 and the vector modulator 134 depends on whether a transmission or reception operation is occurring and which port 352 is closer to the antenna element being coupled. For example, as described above, the vector modulator 134 can operate on the propagating signal “after” the signal phase generator 132 operates on it. Additionally or alternatively, if the phase shifter 130 accepts the signal being processed at the second port 352-2 and outputs a phase shift signal at the first port 352-1, the vector modulator 134 can operate on the propagating signal “before” the signal phase generator 132 operates on it. Therefore, amplitude adjustment of the vector modulator 134 can be applied before generating one or more phases. Although not explicitly stated, the signal phase generator 132 can be implemented as two “separate” unidirectional signal phase generators to achieve the bidirectional phase shifter 130. However, in alternative environments, the phase shifter 130 can operate fully or partially in one direction.

[0102] In the RF front end 128 (e.g., Figure 3-1In this respect, the first port 3521 of the phase shifter 130 can be coupled to another component 308 and thus closer to the signal coupler 306 and transceiver 126 (e.g., Figure 2 Both. Here, the second port 352-2 of the phase shifter 130 can be coupled to the amplifier 310 and thus closer to the antenna array 122. Alternatively, the second port 352-2 can be coupled to another component 308 and thus closer to both the signal coupler 306 and the transceiver 126. Here, the first port 352-1 can be coupled to the amplifier 310 and thus closer to the antenna array 122.

[0103] In some implementations, the vector modulator 134 includes at least two VGAs. For example, a first VGA can be deployed to adjust the amplitudes of a first and a second component forming a differential signal, the first and second components corresponding to phases 454-8 and 454-9, respectively. A second VGA can be deployed to adjust the amplitudes of a third and a fourth component forming another differential signal, the third and fourth components corresponding to phases 454-10 and 454-11, respectively. (See below for reference.) Figure 5 Describe an example of this method with two VGAs. References Figure 6 The description includes an example VGA 136 with multiple bidirectional amplifiers. Reference Figures 7 to 11-3 Describe an example implementation of the bidirectional amplifier 602.

[0104] Figure 5 This is a schematic diagram illustrating an example phase shifter 130 including a signal phase generator 132 and a vector modulator 134, the vector modulator 134 including at least one variable gain amplifier 136 (VGA 136). As shown, the vector modulator 134 includes two VGAs: a first VGA 136-1 and a second VGA 136-2. The phase shifter 130 includes multiple coupling circuits 502-1, 502-2, and 502-3. As shown, each coupling circuit 502 is implemented as at least one transformer 504. Furthermore, each transformer is implemented as a balun (e.g., Figure 4-2 A balanced-to-unbalanced converter 452 is used to convert between single-ended signaling and differential signaling (e.g., between balanced and unbalanced signals). However, the coupling circuit and transformer can be implemented differently.

[0105] In the example implementation, the first port 352-1 is coupled to a signal phase generator 132. The signal phase generator 132 is coupled to a vector modulator 134 via a first coupling circuit 502-1 and a third coupling circuit 502-3. The vector modulator 134 is coupled to the second port 352-2 via a second coupling circuit 502-2. As shown, each coupling circuit 502 is implemented using a transformer 504, which is implemented as a balun with a differential side and a single-ended side. Each transformer 504 is arranged to couple the differential signal to at least one VGA 136. Therefore, each VGA 136 is configured to receive, amplify, and output the differential signal in both directions. In this example, the signal phase generator 132 and the second port 352-2 are thus coupled to the single-ended side of at least one transformer 504.

[0106] The vector modulator 134 also accepts multiple phase control signals 208-1 and 208-2, with one phase control signal 208 for each VGA 136. Therefore, each corresponding VGA 136 accepts a corresponding phase control signal 208. The first VGA 136-1 accepts the first phase control signal 208-1, and the second VGA 136-2 accepts the second phase control signal 208-2. Each corresponding VGA 136-1 and 136-2 thus performs at least one amplification operation based on the corresponding phase control signals 208-1 and 208-2. Each VGA 136 may include a bidirectional VGA 136, as referenced below. Figure 6 As stated above.

[0107] To function as a balun, each transformer 504 has a single-ended side and a differential side. In addition to the signal-bearing nodes, the single-ended side of each transformer 504 is coupled to ground node 408-2. In addition to the two differential signal-bearing nodes, the differential side of each transformer 504 is coupled to power node 408-1 via the center tap of the inductor of transformer 504. Multiple transformers may be coupled to the same ground node 408-2 or the same power node 408-1, or to different nodes of one or both of these PDN nodes. For example, transformer 504 of the first coupling circuit 502-1 is coupled to the first power node 408-11. Similarly, transformer 504 of the second coupling circuit 502-2 is coupled to the second power node 408-12, and transformer 504 of the third coupling circuit 502-3 is coupled to the third power node 408-13. As described below, each power node 408 can provide power to one or more transistors of the VGA 136 (e.g., Figure 4-1 DC current 406).

[0108] In the example operation, based on a signal having one phase, signal phase generator 132 generates a first phase 506-1 at the first coupling circuit 502-1 and a second phase 506-2 at the third coupling circuit 502-3. The single-ended signaling components of the first phase 506-1 and the second phase 506-2 can correspond, for example, to in-phase signal components (I signal components) and quadrature signal components (Q signal components), respectively. Alternatively, signal phase generator 132 can generate four phases based on one or two phases. Transformer 504 of the first coupling circuit 502-1 converts the single-ended signal component having the first phase 506-1 into a differential signal having two signal components. These two signal components at the first coupling circuit 502-1 can therefore correspond to I+ and I- signal components. Transformer 504 of the third coupling circuit 502-3 converts the single-ended signal component having the second phase 506-2 into a differential signal having two signal components. Therefore, these two signal components at the third coupling circuit 502-3 can correspond to Q+ and Q- signal components.

[0109] The first VGA 136-1 processes the two signal components received via the first coupling circuit 502-1. Therefore, the first VGA 136-1 can amplify the I+ and I- signal components based on the first phase control signal 208-1 to achieve a first gain. The second VGA 136-2 processes the two signal components received via the third coupling circuit 502-3. Therefore, the second VGA 136-2 can amplify the Q+ and Q- signal components based on the second phase control signal 208-2 to achieve a second gain. The positive and negative nodes on the differential side of the transformer 504 of the second coupling circuit 502-2 recombine these signal components on a positive-positive and negative-negative basis. The positive node combines the I+ and Q+ signal components. The negative node combines the I- and Q- signal components. However, the positive and negative nodes do not need to combine the signal components, as shown below. Figure 6 The combined positive and negative signal components are coupled to the differential side of transformer 504 in the second coupling circuit 502-2. After transformer 504 converts the positive and negative signal components into single-ended signals, the second coupling circuit 502-2 couples the single-ended signals to the second port 352-2.

[0110] An example implementation of phase shifter 130 is in Figure 4-2 and Figure 5The phase shifter 130 is shown and described above. However, the phase shifter 130 can be implemented in an alternative manner. For example, the first port 352-1 or the second port 352-2 (which may include two ports, assuming that the "or" in connectivity can be interpreted as inclusive, as described below) can be implemented as differential ports to couple to or from the phase shifter 130 and positive and negative signals. Thus, the signal phase generator 132 can be implemented as a differential signal phase generator that couples the I+ and I- signal components on one side (e.g., on the first port 3521 side) and the I+, I-, Q+, and Q- signal components on the other side (e.g., on the vector modulator 134 side). Furthermore, one or more coupling circuits can be implemented differently, including using only electrical conductors (e.g., wires). In some implementations, the balun can be moved outside the phase shifter 130 or omitted from the circuit system. For example, the baluns of the first coupling circuit 502-1 and the third coupling circuit 502-3 can be omitted by using a differential signal phase generator 132. Figure 5 (Each is implemented as a transformer 504). In some cases, this allows power to be supplied to the first VGA 136-1 and the second VGA 136-2 via the signal phase generator 132 (e.g., DC current can be routed to flow through a differential signal phase generator or a combination of two single-ended signal phase generators). As another example, the balun of the second coupling circuit 502-2 can be replaced by an inductor and two AC coupling capacitors, which are coupled together to the differential signaling path provided by the second port 352-2.

[0111] Figure 6 Schematic diagram 600 shows an example VGA 136 including multiple bidirectional amplifiers 602-1, 602-2, ..., 602-A, where “A” represents a positive integer. The value of “A” establishes the number of bidirectional amplifiers included in the VGA 136 and the bit level of the VGA 136. For example, if “A” equals five (5), the illustrated VGA 136 can provide five-bit resolution and up to 32 different combinations of amplification levels or levels from five different amplification levels. The resolution bit depth of each VGA 136 is related to the bit level of the associated phase shifter, which will be described below. Schematic diagram 600 also depicts a corresponding transformer 504 for each respective coupling circuit 502, including a first coupling circuit 502-1 with a first transformer 504 and a second coupling circuit 502-2 with a second transformer 504. Each transformer 504 may include at least one inductor 610 on each side. Figure 6 In this configuration, the transformer 504 of each coupling circuit 502 operates using differential signals; however, each transformer 504 can be modified to be implemented as follows: Figure 5The balun shown is a balanced-to-unbalanced converter.

[0112] In the example implementation, the VGA 136 is coupled between a first coupling circuit 502-1 and a second coupling circuit 502-2. Therefore, each of the plurality of bidirectional amplifiers 602-1, ..., 602-A is coupled between the first coupling circuit 502-1 and the second coupling circuit 502-2. The VGA 136 includes multiple interfaces, including a first interface 604-1 and a second interface 604-2. The first interface 604-1 is coupled to the inductor 610 of the transformer 504 of the first coupling circuit 502-1, and the second interface 604-2 is coupled to the inductor 610 of the transformer 504 of the second coupling circuit 502-2.

[0113] For differential signaling, the signal can include positive and negative signal components. The positive and negative signal components are approximately 180 degrees (180°) apart. For a circuit system supporting differential signaling, positive and negative signal paths can propagate the positive and negative signal components, respectively. Each signal path can include physical components such as passive and active circuit elements, wires, nodes, etc. Therefore, a circuit can include positive lines or positive nodes to propagate the positive signal component. Similarly, a circuit can include negative lines or negative nodes to propagate the negative signal component. Thus, a positive node represents an electrical or electromagnetic point or circuit section that can correspond to a positive signal component, and a negative node represents an electrical or electromagnetic point or circuit section that can correspond to a negative signal component.

[0114] Each interface 604 may include multiple nodes. In some implementations, each interface 604 includes a positive node and a negative node to support differential signaling. In this case, the first interface 604-1 includes a first differential interface 604-1, and the second interface 604-2 includes a second differential interface 604-2. The first interface 604-1 includes a first positive node 606-1P and a first negative node 606-1M. The second interface 604-2 includes a second positive node 606-2P and a second negative node 606-2M. The first positive node 606-1P and the first negative node 606-1M are therefore coupled to the transformer 504 of the first coupling circuit 502-1. The second positive node 606-2P and the second negative node 606-2M are therefore coupled to the transformer 504 of the second coupling circuit 502-2. Each interface 604 is coupled to each of the multiple bidirectional amplifiers 602-1, ..., 602-A. Each bidirectional amplifier 602 is therefore coupled between the first positive node 606-1P and the first negative node 606-1M and the second positive node 606-2P and the second negative node 606-2M.

[0115] Each of the multiple bidirectional amplifiers 602-1, 602-2, ..., 602-A corresponds to a corresponding amplification 612 among the multiple amplification values ​​612-1, 612-2, ..., 612-A. For example, the first bidirectional amplifier 602-1 can provide a first amplification value 612-1, and the second bidirectional amplifier 602-2 can provide a second amplification value 612-2. Therefore, each bidirectional amplifier 602 can provide a different amplification value 612. The different amplification values ​​612 can be weighted. Examples of weighting techniques include binary, thermometer encoding, logarithmic, etc. Using a binary weighting method and a five-bit VGA (e.g., "A" = 5), the weights can correspond to 1x, 2x, 4x, 8x, and 16x, which provides 32 combinations of 32 possibly different gain values ​​provided by the VGA 136. Phase shifter bits with different denominators can be used compared to the VGA gain bits. A phase shifter bit refers to the resolution of the phase shifter. For example, a five-bit phase shifter has a phase resolution of 11.25 degrees (360 / 2^5). Such a five-bit phase shifter can be implemented using a vector modulator with a 4, 5, or 6-bit VGA, depending on the amount of phase error the phase shifter can tolerate. Nevertheless, the higher the number of bits in the VGA, the higher the phase resolution that the phase shifter can typically achieve.

[0116] Different weights for the amplification 612 of each bidirectional amplifier 602 can be implemented in various ways. For example, transistors of different sizes can be used across multiple bidirectional amplifiers 602-1, ..., 602-A in each VGA 136 (e.g., transistor widths can be scaled). Additionally or alternatively, different numbers of transistors can be used across multiple bidirectional amplifiers 602-1, ..., 602-A in each VGA 136 (e.g., the number of transistors with the same width can be scaled). Other methods can be employed to achieve different amplification amounts or different amplifier weights.

[0117] Phase control signal 208 controls the gain of VGA 136. The gain of VGA 136 corresponds to a combination of multiple amplification values ​​612-1, ..., 612-A across a plurality of bidirectional amplifiers 602-1, ..., 602-A of VGA 136. Phase control signal 208 includes at least one amplification control signal 608. For example, phase control signal 208 may include a plurality of amplification control signals 608-1, 608-2, ..., 608-A. In this case, each corresponding bidirectional amplifier 602 of the plurality of bidirectional amplifiers 602-1, ..., 602-A receives and corresponds to a corresponding amplification control signal 608 of the plurality of amplification control signals 608-1, ..., 608-A. For example, a first bidirectional amplifier 602-1 is coupled to receive a first amplification control signal 608-1, and a second bidirectional amplifier 602-2 is coupled to receive a second amplification control signal 608-2.

[0118] In operation, each corresponding bidirectional amplifier 602 establishes a corresponding amplification amount 612 based on a corresponding amplification control signal 608. Therefore, each bidirectional amplifier 602 is activated or deactivated in response to the amplification control signal 608 coupled thereto. A given amplification control signal 608 may include one or more bits for participating in different operating modes, examples of which are described below. Each amplification control signal 608 corresponds to a bidirectional amplifier 602 capable of providing a corresponding amplification amount 612 (e.g., 1x, 2x, 4x, 8x, and 16x for a 5-bit VGA 136). These bidirectional amplifiers can be activated individually or in combination (e.g., only 4x activated alone or 2x and 8x activated together to obtain a total of 10x). The VGA 136 can therefore provide up to 32 different gain amounts (e.g., from none to 31x for a five-bit VGA 136) by combining the available amplification amounts from multiple amplification amounts 612-1, ..., 612-A.

[0119] This document describes example operating modes for each bidirectional amplifier 602. These operating modes include a regular active amplification mode corresponding to a given amplification amount 612 (e.g., 1x, 4x, or 16x) of a given bidirectional amplifier 602, and an inverse active amplification mode corresponding to a sign-switched version of the given amplification amount 612. These operating modes also include inactive amplification modes, where a particular bidirectional amplifier 602 does not contribute the corresponding amplification amount 612 for the amount of gain programmed for the VGA 136 (e.g., the particular bidirectional amplifier 602 is deactivated). These amplification modes will be referenced below. Figures 11-1 to 11-3 Provide a description. (See reference.) Figures 10-1 to 10-3 The circuitry system used to enable this mode is described. However, references will follow. Figures 7 to 9 Describe the general aspects of the bidirectional amplifier 602.

[0120] Figure 7 This is a schematic diagram illustrating an example bidirectional amplifier 602 comprising multiple transistor groups and depicting multiple signal flows. The bidirectional amplifier 602 corresponds to a specific amplification level 612 and operates bidirectionally as indicated by the double-headed arrows in the signal flow directions 202. The bidirectional amplifier 602 includes a first interface 604-1 and a second interface 604-2. The bidirectional amplifier 602 may include a first amplification circuit for one propagation direction and a second amplification circuit for the other propagation direction. In some cases, one of the amplification circuits is implemented by a transistor group. In other cases, both amplification circuits are implemented by corresponding transistor groups 702. (See diagram for reference...) Figure 7 As shown in the example, the bidirectional amplifier 602 includes a first transistor group 702-1 and a second transistor group 702-2.

[0121] In the example implementation, each corresponding transistor group 702 processes a signal flowing in a corresponding signal propagation direction. The first transistor group 702-1 processes a signal propagating along a first signal propagation direction 202-1 of the bidirectional signal flow direction 202. The first signal propagation direction 202-1 corresponds to a signal flowing from the first interface 604-1 to the second interface 604-2. The second transistor group 702-2 processes a signal propagating along a second signal propagation direction 202-2 of the bidirectional signal flow direction 202. The second signal propagation direction 202-2 corresponds to a signal flowing from the second interface 604-2 to the first interface 604-1. Therefore, one of the first signal propagation direction 202-1 or the second signal propagation direction 202-2 corresponds to a transmission operation, and the other signal propagation direction corresponds to a reception operation. Based on this bidirectionality, one of the first transistor group 702-1 or the second transistor group 702-2 amplifies the transmission signal for phase-shifting operations, while the other amplifies the reception signal for phase-shifting operations.

[0122] Two example signal streams in opposite directions are described. These two signal streams correspond to the first signal 704-1, represented by the dashed arrow, and the second signal 704-2, represented by the solid arrow. These two signals can collectively correspond to... Figures 3-1 to 4-2 Signal 324. The first signal 704-1 enters the bidirectional amplifier 602 via the first interface 604-1. The first signal 704-1 propagates to the "lower edge" of the first transistor group 7021 (as shown). The first transistor group 702-1 amplifies the first signal 704-1 and outputs the amplified signal at the "top edge" of the first transistor group 702-1. After amplification, the first signal 704-1 exits the bidirectional amplifier 602 via the second interface 604-2 (e.g., without passing through the second transistor group 702-2).

[0123] With respect to the relative signal propagation direction, the second signal 704-2 enters the bidirectional amplifier 602 via the second interface 604-2. The second signal 704-2 propagates to the "upper edge" of the second transistor group 702-2 (as shown). The second transistor group 702-2 amplifies the second signal 704-2 and outputs the amplified signal at the "lower edge" of the second transistor group 702-2. After amplification, the second signal 704-2 exits the bidirectional amplifier 602 interface 604-1 via the first signal (e.g., without passing through the first transistor group 702-1). Therefore, the first interface 604-1 and the second interface 604-2 of the bidirectional amplifier 602 are bidirectional. On the other hand, the first transistor group 702-1 and the second transistor group 702-2 can be implemented as a unidirectional portion of the bidirectional amplifier 602.

[0124] Figure 8 This is a schematic diagram illustrating an example bidirectional amplifier 602 comprising multiple transistor groups, each transistor group including multiple transistor pairs. A first transistor group 702-1 includes multiple transistor pairs, and a second transistor group 702-2 includes multiple transistor pairs. As shown, the bidirectional amplifier 602 includes a first interface 604-1 and a second interface 604-2. The first interface 604-1 includes a first positive node 606-1P and a first negative node 606-1M. The second interface 604-2 includes a second positive node 606-2P and a second negative node 606-2M. Therefore, the first interface 604-1 includes a first bidirectional interface 604-1, and the second interface 604-2 includes a second bidirectional interface 604-2.

[0125] In the example implementation, the bidirectional amplifier 602 includes multiple transistor pairs, such as eight (8) transistor pairs 802-1, 802-2, ..., 802-7, 802-8. In this case, each transistor group 702 includes four transistor pairs. The first transistor group 702-1 includes a first transistor pair 802-1, a second transistor pair 802-2, a third transistor pair 802-3, and a fourth transistor pair 802-4. The second transistor group 702-2 includes a fifth transistor pair 802-5, a sixth transistor pair 802-6, a seventh transistor pair 802-7, and an eighth transistor pair 802-8. Each transistor pair 802 is coupled between a first interface 604-1 and a second interface 604-2.

[0126] Each corresponding transistor pair 802 includes a corresponding input 804 and a corresponding output 806. For the first transistor group 702-1, the first transistor pair 802-1 includes an input 804-1 and an output 806-1. The second transistor pair 802-2 includes an input 804-2 and an output 806-2. The third transistor pair 802-3 includes an input 804-3 and an output 806-3. The fourth transistor pair 802-4 includes an input 804-4 and an output 806-4. The corresponding inputs 804-1, 804-2, 804-3, and 804-4 of the first transistor pair 802-1, the second transistor pair 802-2, the third transistor pair 802-3, and the fourth transistor pair 802-4 correspond to the first interface 604-1, for example, by coupling to the first positive node 606-1P and the first negative node 606-1M. The corresponding outputs 806-1, 806-2, 806-3, and 806-4 of the first transistor pair 802-1, the second transistor pair 802-2, the third transistor pair 802-3, and the fourth transistor pair 802-4 correspond to the second interface 604-2, for example, by coupling to the second positive node 606-2P and the second negative node 606-2M. Therefore, as the first signal 704-1 propagates from the first interface 604-1 to the second interface 604-2, the first signal 704-1 (e.g., also...) Figure 7 The signal can be amplified by propagating through at least one of the first transistor pair 802-1, the second transistor pair 802-2, the third transistor pair 802-3, and the fourth transistor pair 802-4. In this case, the first interface 604-1 includes a differential signaling input to the bidirectional amplifier 602, and the second interface 604-2 includes a differential signaling output to the bidirectional amplifier 602.

[0127] For the second transistor pair 702-2, the fifth transistor pair 802-5 includes an input 804-5 and an output 806-5. The sixth transistor pair 802-6 includes an input 804-6 and an output 806-6. The seventh transistor pair 802-7 includes an input 804-7 and an output 806-7. The eighth transistor pair 802-8 includes an input 804-8 and an output 806-8. The corresponding inputs 804-5, 804-6, 804-7, and 804-8 of the fifth transistor pair 802-5, the sixth transistor pair 802-6, the seventh transistor pair 802-7, and the eighth transistor pair 802-8 correspond to the second interface 604-2, for example, by coupling to the second positive node 606-2P and the second negative node 606-2M. The corresponding outputs 806-5, 806-6, 806-7, and 806-8 of the fifth transistor pair 802-5, the sixth transistor pair 802-6, the seventh transistor pair 802-7, and the eighth transistor pair 802-8 correspond to the first interface 604-1, for example, by coupling to the first positive node 606-1P and the first negative node 606-1M. Therefore, as the second signal 704-2 propagates from the second interface 604-2 to the first interface 604-1, the second signal 704-2 (e.g., also...) Figure 7 It can be amplified by propagating through at least one of the fifth transistor pair 802-5, the sixth transistor pair 802-6, the seventh transistor pair 802-7, and the eighth transistor pair 802-8. In this case, the first interface 604-1 includes the differential signaling output of the bidirectional amplifier 602, and the second interface 604-2 includes the differential signaling input of the bidirectional amplifier 602.

[0128] In some implementations, half of the transistor pair in a given transistor group 702 is coupled at its output with one differential polarity, and the other half of the transistor pair in the given transistor group 702 is coupled at its output with another different differential polarity. This is in Figure 8 The image is illustrated by opposite polarity coupling 808. In this example, the first transistor pair 802-1 and the second transistor pair 802-2 are coupled to the second interface 604-2 via a first differential polarity, and the third transistor pair 802-3 and the fourth transistor pair 802-4 are coupled to the second interface 604-2 via a second differential polarity. In other words, the positive and negative output signal coupling is swapped between the first transistor pair 802-1 and the second transistor pair 802-2, compared to the positive and negative output signal coupling of the third transistor pair 802-3 and the fourth transistor pair 802-4.

[0129] Similarly, the fifth transistor pair 802-5 and the sixth transistor pair 802-6 are coupled to the first interface 604-1 via a first differential polarity, and the seventh transistor pair 802-7 and the eighth transistor pair 802-8 are coupled to the first interface 604-1 via a second differential polarity. In other words, the positive and negative output signals of the seventh transistor pair 802-7 and the eighth transistor pair 802-8 are coupled and exchanged between the fifth transistor pair 802-5 and the sixth transistor pair 802-6. As described below, the opposite polarity coupling 808 can generate an inverted or sign-swapped signal. The opposite polarity coupling 808 can also neutralize the parasitic capacitance of the transistors during operation, as described below regarding the inactive operating mode. Each individual transistor in each transistor pair 802 includes an input 804 and an output 806, such as an input terminal and an output terminal. References are made below. Figure 9 An example describing this type of terminal.

[0130] Opposite polarity coupling 808 in Figure 8 The diagram is shown symmetrically (from the depicted left and right perspectives) and described above based on two pairs of transistors of the same polarity that are adjacent to each other. However, opposite polarity coupling 808 can be implemented differently. For example, different differential output polarities can be implemented using alternating pairs of transistors that are adjacent to each other. Therefore, the differential output polarities of multiple transistor pairs in a given transistor group 702 can be... Figure 8 or Figure 9 The order may differ from that shown or described herein.

[0131] Figure 9 This is a circuit diagram illustrating an example bidirectional amplifier 602 comprising multiple transistor pairs and multiple groups of enabled devices. Figure 8 compared to, Figure 9 Each transistor pair 802 is explicitly shown as including two transistors for differential implementation. As shown, the bidirectional amplifier 602 includes a first negative node 606-1M, a first positive node 606-1P, a second positive node 606-2P, and a second negative node 606-2M. Figure 9 It also includes a first enabled device group 906-1 and a second enabled device group 906-2. Each enabled device group 906 includes multiple enabled devices. Each enabled device 902 (ED 902) is coupled to a PDN node 408 and a transistor pair 802. An example of opposite polarity coupling 808 is also depicted with dashed lines.

[0132] In the example implementation, the first transistor group 702-1 and the second transistor group 702-2 ( Figure 7 and Figure 8 Each of the eight transistors in the array comprises four transistor pairs. Therefore, Figure 9The bidirectional amplifier 602 includes 16 transistors. The first transistor pair 802-1 includes transistor T1 and transistor T2. The second transistor pair 802-2 includes transistor T3 and transistor T4. The third transistor pair 802-3 includes transistor T5 and transistor T6. The fourth transistor pair 802-4 includes transistor T7 and transistor T8. The fifth transistor pair 802-5 includes transistor T9 and transistor T10. The sixth transistor pair 802-6 includes transistor T11 and transistor T12. The seventh transistor pair 802-7 includes transistor T13 and transistor T14. The eighth transistor pair 802-8 includes transistor T15 and transistor T16.

[0133] Each transistor (T#) in Figure 9 The transistor is shown as a metal-oxide-semiconductor (MOS) field-effect transistor (FET). However, each transistor in each pair of transistors 802 can be implemented using a different type of transistor, such as another type of FET (e.g., a junction FET (JFET)), a bipolar junction transistor (BJT), etc. FETs can be implemented using either n-channel or p-channel methods. Therefore, each transistor in the bidirectional amplifier 602 can be implemented as an n-channel MOS field-effect transistor (FET) (nMOSFET) or a p-channel MOS field-effect transistor (FET) (pMOSFET). For FET implementations, each transistor includes a gate terminal and one or more channel terminals. As used herein, the one or more channel terminals may include a source terminal and a drain terminal.

[0134] Each transistor includes an input 804 and an output 806. Figure 8 Each of them). For Figure 9Each transistor in the array has a gate terminal corresponding to input 804 and a channel terminal corresponding to output 806. Each node 606 is coupled to the gate terminals of multiple transistors among the sixteen transistors T1 to T16. More specifically, four differential nodes are AC coupled to the gate terminals of transistors T1 to T16 via at least one coupling capacitor. As shown, the first negative node 606-1M is AC coupled to the first transistor pair 802-1, the second transistor pair 802-2, the third transistor pair 802-3, and the fourth transistor pair 802-4 via the first negative capacitor 904-1M. The first positive node 606-1P is AC coupled to the first transistor pair 802-1, the second transistor pair 802-2, the third transistor pair 802-3, and the fourth transistor pair 802-4 via the first positive capacitor 904-1P. The second positive node 606-2P is AC coupled to the fifth transistor pair 802-5, the sixth transistor pair 802-6, the seventh transistor pair 802-7, and the eighth transistor pair 802-8 via the second positive capacitor 904-2P. The second negative node 606-2M is AC coupled to the fifth transistor pair 802-5, the sixth transistor pair 802-6, the seventh transistor pair 802-7, and the eighth transistor pair 802-8 via the second negative capacitor 904-2M. In contrast, the output of each transistor pair 802 is DC coupled to the positive and negative nodes to provide power with a DC current flowing through each respective enabled device 902, as described below.

[0135] As shown in the figure, the first transistor T1 is coupled between the first positive node 606-1P and the second negative node 606-2M. The second transistor T2 is coupled between the first negative node 606-1M and the second positive node 606-2P. The third transistor T3 is coupled between the first positive node 606-1P and the second negative node 606-2M. The fourth transistor T4 is coupled between the first negative node 606-1M and the second positive node 606-2P. The fifth transistor T5 is coupled between the first positive node 606-1P and the second positive node 606-2P. The sixth transistor T6 is coupled between the first negative node 606-1M and the second negative node 606-2M. The seventh transistor T7 is coupled between the first positive node 606-1P and the second positive node 606-2P. The eighth transistor T8 is coupled between the first negative node 606-1M and the second negative node 606-2M.

[0136] Furthermore, the ninth transistor T9 is coupled between the second positive node 606-2P and the first positive node 606-1P. The tenth transistor T10 is coupled between the second negative node 606-2M and the first negative node 606-1M. The eleventh transistor T11 is coupled between the second positive node 606-2P and the first positive node 606-1P. The twelfth transistor T12 is coupled between the second negative node 606-2M and the first negative node 606-1M. The thirteenth transistor T13 is coupled between the second positive node 606-2P and the first negative node 606-1M. The fourteenth transistor T14 is coupled between the second negative node 606-2M and the first positive node 606-1P. The fifteenth transistor T15 is coupled between the second positive node 606-2P and the first negative node 606-1M. The sixteenth transistor T16 is coupled between the second negative node 606-2M and the first positive node 606-1P.

[0137] In some implementations, each of the following transistors—first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8—approximately has a first size. Each of the following transistors—ninth transistor T9, tenth transistor T10, eleventh transistor T11, twelfth transistor T12, thirteenth transistor T13, fourteenth transistor T14, fifteenth transistor T15, and sixteenth transistor T16—approximately has a second size. The first size can be significantly different from the second size. For example, based on the process technology used to manufacture the bidirectional amplifier 602, the first size can be constructed to be a different size than the second size. In some cases, the second size can be at least 20% larger than the first size. This makes transistors that amplify signals propagating in one direction (e.g., for transmission operations) different from transistors that amplify signals propagating in the other direction (e.g., for reception operations).

[0138] Transistor size can be related to, for example, the physical dimensions of the transistor or how much current the transistor can handle. For instance, transistor size can be determined at least in part by the channel width. Alternatively, transistor size can be determined at least in part by the channel length. Furthermore, transistor size can be determined at least in part by the number of fins in a FinFET transistor. The number of fins is also referred to herein as the effective channel width. Transistor size can also correspond to a combination of two or more of the following: channel width, channel length, effective channel width, etc.

[0139] Two differential interfaces 604 (e.g., Figure 7 and Figure 8Each of the transistors 602 operates as an input to one transistor group 702 and as an output to another transistor group 702. Regarding the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8, the first positive node 606-1P and the first negative node 606-1P include a first bidirectional amplifier 602 relative to the first signal propagation direction 202-1 (e.g., Figure 7 The differential signaling input of the second positive node 606-2P and the second negative node 606-2M includes a bidirectional amplifier 602 relative to the first transistor group 702-1 (e.g., Figure 7 and Figure 8 The first differential signaling output of the first signal propagation direction 202-1. Regarding the ninth transistor T9, tenth transistor T10, eleventh transistor T11, twelfth transistor T12, thirteenth transistor T13, fourteenth transistor T14, fifteenth transistor T15, and sixteenth transistor T16, the second positive node 606-2P and the second negative node 606-2M include a bidirectional amplifier 602 with respect to the second differential signaling input of the second signal propagation direction 202-2. The first positive node 606-1P and the first negative node 606-1M include a bidirectional amplifier 602 with respect to the second transistor group 702-2 (e.g., Figure 7 and Figure 8 The second differential signaling output of the second signal propagation direction 202-2.

[0140] In some implementations, each enabled device group 906 includes four enabled devices. The first enabled device group 906-1 includes a first enabled device 902-1, a second enabled device 902-2, a third enabled device 902-3, and a fourth enabled device 902-4. The second enabled device group 906-2 includes a fifth enabled device 902-5, a sixth enabled device 902-6, a seventh enabled device 902-7, and an eighth enabled device 902-8. Each corresponding enabled device 902 is coupled between a corresponding transistor pair 802 and the PDN node 408. See the following reference... Figures 10-1 to 10-3 Depending on the transistor type, each PDN node 408 may include a power node 408-1 or a ground node 408-2.

[0141] Specifically, the first enabling device 902-1 is coupled between the first transistor pair 802-1 and the PDN node 408. The second enabling device 902-2 is coupled between the second transistor pair 802-2 and the PDN node 408. The third enabling device 902-3 is coupled between the third transistor pair 802-3 and the PDN node 408. The fourth enabling device 902-4 is coupled between the fourth transistor pair 802-4 and the PDN node 408. The fifth enabling device 902-5 is coupled between the fifth transistor pair 802-5 and the PDN node 408. The sixth enabling device 902-6 is coupled between the sixth transistor pair 802-6 and the PDN node 408. The seventh enabling device 902-7 is coupled between the seventh transistor pair 802-7 and the PDN node 408. The eighth enabling device 902-8 is coupled between the eighth transistor pair 802-8 and the PDN node 408. Between the two first transistor groups 702-1 and the second transistor group 702-2, the PDN node 408 can be the same or different.

[0142] As described above, various transistor pairs can be arranged to have opposite polarity coupling 808 between two or more different transistor pairs, as described below. On the input side, each transistor pair 802 of a given transistor group 702 is coupled to interface 604 in a similar manner. On the other hand, on the output side, each transistor pair 802 of a given transistor group 702 is coupled to another interface 604 in one of two different ways. Referring to the first transistor group 702-1 (e.g.) Figure 7 and Figure 8 As shown), the first transistor T1, the third transistor T3, the fifth transistor T5, and the seventh transistor T7 (e.g., four positive transistors) are each coupled to the first positive node 606-1P via their respective gate terminals. The second transistor T2, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 (e.g., four negative transistors) are each coupled to the first negative node 606-1M via their respective gate terminals. Therefore, these four transistor pairs of eight transistors T1 to T8 from 802-1 to 802-4 are coupled to the first positive node 606-1P and the first negative node 606-1M in the same manner on the input side of the first transistor group 702-1.

[0143] However, the eight transistors T1 to T8 of the four transistor pairs 802-1 to 802-4 are coupled to the second positive node 606-2P and the second negative node 606-2M in different ways on the output side of the first transistor group 702-1. The first transistor T1 and the third transistor T3 are coupled to the second negative node 606-2M via their respective channel terminals. The second transistor T2 and the fourth transistors T2 and T4 are coupled to the second positive node 606-2P via their respective channel terminals. Conversely, the fifth transistor T5 and the seventh transistors T5 and T7 are coupled to the second positive node 606-2P via their respective channel terminals. Furthermore, the sixth transistor T6 and the eighth transistors T6 and T8 are coupled to the second negative node 606-2M via their respective channel terminals. In other words, for the third transistor pair 802-3 and the fourth transistor pair 802-4, the positive input is coupled to the positive output, and the negative input is coupled to the negative output. For the first transistor pair 802-1 and the second transistor pair 802-2, the differential polarity is reversed, with the positive input coupled to the negative output and the negative input coupled to the positive output. This opposite polarity coupling 808 is utilized in some operating modes described below.

[0144] Figure 10-1 This is a circuit diagram illustrating an example bidirectional amplifier 602, including an example enabling device and an example power distribution network implementation. Figure 10-1 In the example shown, each of the 16 transistors T in pairs 802-1, ..., 802-8 is implemented using an n-type MOSFET (nMOSFET). In the illustrated example, each enable device 902 is implemented using an enable transistor. The first enable device 902-1 includes a first enable transistor, and the second enable device 902-2 includes a second enable transistor. The third enable device 902-3 includes a third enable transistor. The fourth enable device 902-4 includes a fourth enable transistor. Furthermore, the fifth enable device 902-5 includes a fifth enable transistor, and the sixth enable device 902-6 includes a sixth enable transistor. The seventh enable device 902-7 includes a seventh enable transistor. The eighth enable device 902-8 includes an eighth enable transistor.

[0145] Each corresponding enable device 902 is coupled between the corresponding transistor pair 802 and the ground node 408-2. Here, each enable transistor of each enable device 902 is implemented using an n-type MOSFET (nMOSFET). The drain terminal of each enable transistor of each enable device 902 is coupled to the source terminals of the two transistors in each transistor pair 802. The source terminal of each enable transistor is coupled to the ground node 408-2.

[0146] The gate terminal of each enable transistor in each corresponding enable device 902 is coupled to a corresponding enable signal 1002 (EN 1002). The gate terminal of the enable transistor of the first enable device 902-1 receives the first enable signal 1002-1 (EN1). The gate terminal of the enable transistor of the second enable device 902-2 receives the second enable signal 1002-2 (EN2). The gate terminal of the enable transistor of the third enable device 902-3 receives the third enable signal 1002-3 (EN3). The gate terminal of the enable transistor of the fourth enable device 902-4 receives the fourth enable signal 1002-4 (EN4). The gate terminal of the enable transistor of the fifth enable device 902-5 receives the fifth enable signal 1002-5 (EN5). The gate terminal of the enable transistor of the sixth enable device 902-6 receives the sixth enable signal 1002-6 (EN6). The gate terminal of the enable transistor of the seventh enable device 902-7 receives the seventh enable signal 1002-7 (EN7). The gate terminal of the enable transistor of the eighth enable device 902-8 receives the eighth enable signal 1002-8 (EN8).

[0147] In the example operation, each corresponding enable signal 1002 can enable or disable the corresponding transistor pair 802 using the corresponding enable device 902. If the enable transistor of the enable device 902 is turned on, a DC current flows through both transistors of the corresponding transistor pair 802. This DC current enables the transistor pair 802. To turn on the nMOSFET transistor, the enable signal 1002 is driven to a high voltage level. To turn off the nMOSFET enable transistor of the given enable device 902 and prevent the DC current from flowing through the two transistors of the corresponding transistor pair 802, the enable signal 1002 is driven to a low voltage level. Example aspects of the DC current and enable signal 1002 are referenced below. Figure 10-2 Describe it.

[0148] Figure 10-2 This is a circuit diagram illustrating an example bidirectional amplifier 602 and depicting several example operational aspects. These example operational aspects include enabling or disabling transistor pairs, generating DC current, and establishing a DC voltage bias. For clarity, a first transistor group 702-1 is shown. Figure 7 and Figure 8 The transistors in the bidirectional amplifier 602 are shown, but the transistors in the second transistor group 702-2 are omitted. As shown, the bidirectional amplifier 602 includes a bias voltage circuit system 1004, receives an amplification control signal 608, and includes two DC currents: DC current 406 and DC current 1006 flowing through each of the depicted transistor pairs 802-1 to 802-4.

[0149] In the example implementation, eight transistors T1-T8 are DC biased so that the transistors can amplify AC signals (e.g., Figure 7 and Figure 8 The first signal 704-1). For this purpose, the bias voltage circuit system 1004 is DC coupled to the gate terminal of each of the eight transistors T1-T8. The first positive bias voltage circuit system 1004-1P includes a resistor R and couples the bias voltage (Vbias) to the gate terminals of the first transistor T1, the third transistor T3, the fifth transistor T5, and the seventh transistor T7. The first negative bias voltage circuit system 1004-1M includes another resistor R and couples the bias voltage (Vbias) to the gate terminals of the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8. Although not shown, the second positive bias voltage circuit system and the second negative bias voltage circuit system can be coupled to four transistor pairs of the second transistor group 702-2 to DC bias its eight transistors.

[0150] Amplify control signal 608 (e.g., also Figure 6 This controls the amplification of the bidirectional amplifier 602. For example... Figure 10-2 As shown, the amplification control signal 608 includes multiple enable signals, such as multiple enable signals 1002-1 to 1002-4 for at least four transistor pairs 802-1 to 802-4. The amplification control signal 608 may additionally or alternatively include multiple enable signals 1002-5 to 1002-8 (e.g., Figure 10-1 and Figure 10-3 Therefore, the amplification control signal 608 may include multiple bits, such as four or eight bits. Each corresponding enable signal 1002 controls the flow of the corresponding DC current 1006 through the corresponding transistor 802.

[0151] In the example operation, DC current 406 flows from the first power supply node 408-11 to the ground node 408-2. DC current 406 can be distributed across the two conductors used for the differential path. DC current 406 flows through the center tap of inductor 610 (which can be, for example,...). Figure 5 and Figure 6(A portion of the transformer shown) flows through the second positive node 606-2P and the second negative node 606-2M. The DC current 406 is divided into up to four DC currents, including a first DC current 1006-1 (DC I), a second DC current 1006-2, a third DC current 1006-3, and a fourth DC current 1006-4. The first DC current 1006-1 flows through the first transistor pair 802-1 and the enable transistor of the first enable device 902-1 to ground 408-2. The second DC current 1006-2 flows through the second transistor pair 802-2 and the enable transistor of the second enable device 902-2 to ground 408-2. The third DC current 1006-3 flows through the third transistor pair 802-3 and the enable transistor of the third enable device 902-3 to ground 408-2. The fourth DC current 1006-4 flows through the fourth transistor pair 802-4 and the enable transistor of the fourth enable device 902-4 to ground 408-2. See below for reference. Figures 11-1 to 11-3 As stated, for some implementations, depending on the operating mode used, the two DC currents flow at any given time. Therefore, the DC current 406 can be split into two DC currents, such as a first DC current 1006-1 and a second DC current 1006-2.

[0152] These DC currents and DC bias voltages place the eight transistors T1T8 in a state in which each transistor can selectively amplify the first AC signal 704-1 (e.g., in response to multiple enable signals 1002-1 to 1002-4 of the amplification control signal 608). Figure 7 and Figure 8 The eight transistors T9-T16 of the second transistor group 702-2 can similarly operate to selectively amplify the AC second signal 704-2 in response to the multiple enable signals 1002-5 to 1002-8 of the amplification control signal 608. Figure 10-1 and Figure 10-2 Transistors T1-T16 are described as having an n-channel. However, a p-channel MOSFET can be used instead, and this is referenced... Figure 10-3 Describe it.

[0153] Figure 10-3 This is a circuit diagram illustrating an example bidirectional amplifier 602 implemented with other example enabling devices 902-1, ..., 902-8 and another example power distribution network. Figure 10-3In the example, the 16 transistors T1-T16 of the eight transistor pairs 802-1, ..., 802-8 and the eight enable transistors of the eight enable devices 902-1, ..., 902-8 are implemented using at least one p-type MOSFET (pMOSFET). To accommodate the p-type transistors, each corresponding enable transistor of the eight enable devices 902-1, ..., 902-8 is coupled between the corresponding transistor pair 802 of the eight transistor pairs 802-1, ..., 802-8 and at least one power node 408-1. To further enable operational tuning between the two transistor groups (e.g., for transmit and receive operations), four enable devices 902-1 to 902-4 may be coupled to a first power node 408-11, and four enable devices 902-5 to 902-8 may be coupled to a second power node 408-12.

[0154] DC current can flow by turning on the p-type MOSFET of each enable transistor in each enable device 902. Therefore, each enable signal 1002 is driven to a low voltage to turn on the corresponding pMOSFET. To allow DC current 406 (e.g., Figure 4-1 and Figure 10-2 The transformer 504 has at least one inductor 610 capable of flowing (e.g., Figure 6 and Figure 10-2 The inductor 610 is coupled to at least one ground node 408-2 (not explicitly shown) via the center tap. In example operation, up to four separate DC currents (e.g., similar to...) Figure 10-2 The DC currents 1006-1 to 1006-4 can flow from the first power node 408-11 through each of the four enabled devices 902-1 to 902-4 and through each of the four transistor pairs 802-1 to 802-4. These individual DC currents are combined at the outputs of the enabled transistor pairs 802-1 to 802-4 to form DC current 406. This DC current 406 flows through the second positive node 606-2P and the second negative node 606-2M and through the inductor 610 of the transformer 504 to reach the ground node 408-2. See below for reference. Figures 11-1 to 11-3 As stated above, for some implementations, depending on the operating mode employed, the two DC currents flow at any given time. Therefore, the two DC currents (e.g., the first DC current 1006-1 and the second DC current 1006-2) can be combined to form a DC current 406.

[0155] A given bidirectional amplifier 602 can participate in at least three different operating modes as part of a VGA 136, which forms part of the vector modulator 134 of a phase shifter 130. Example operating modes include an active mode, an inverted active mode, and an inactive mode. A “normal” active amplification mode corresponds to a specific amplification value 612 of the given bidirectional amplifier 602. An inverted active amplification mode corresponds to a sign-switched version of the specific amplification value 612 of the given bidirectional amplifier 602. An inactive amplification mode causes amplification of the given bidirectional amplifier 602 to be disabled. Inactive mode indicates that the bidirectional amplifier 602 does not contribute the corresponding amplification value 612 to the amount of gain programmed for the VGA 136. (Active amplification mode reference...) Figure 11-1 Describe the reverse active amplification mode. Figure 11-2 Describe the inactive zoom mode. (Refer to the inactive zoom mode.) Figure 11-3 Describe it.

[0156] In each amplification mode, two transistor pairs of a given transistor group 702 are enabled, while the other two transistor pairs of the same transistor group 702 are disabled. Four transistor pairs of another transistor group 702, used for signals propagating in the opposite direction, are also disabled. Therefore, for each amplification mode, two transistor pairs are enabled and two transistor pairs are disabled along a specific signal flow path. This allows the VGA 136 to maintain substantially constant impedance and phase as the gain is programmed, because the total number of active transistor pairs enabled across the VGA 136 remains constant for each gain level. For example, for the four bidirectional amplifiers in the VGA 136, for each programmed gain level along a specific signal propagation direction, eight transistor pairs are enabled and eight transistor pairs are disabled.

[0157] exist Figures 11-1 to 11-3 In each of these, enabled transistors are shown with solid lines, while disabled transistors are shown with dashed lines. Example voltage values ​​for the eight enable signals 1002-1, ..., 1002-8 are shown with "1" representing a high voltage value and "0" representing a low voltage value. For illustrative purposes only, the example amplification mode is shown in... Figures 11-1 to 11-3 The following describes the operation of an example bidirectional amplifier 602, which is depicted in the figure and described below in terms of nMOSFET. Furthermore, the operation of the example bidirectional amplifier 602 is described for transistors T1-T8 of the first transistor group 702-1, wherein the first signal 704-1 ( Figure 7 and Figure 8 Both signals propagate from the first interface 604-1 to the second interface 604-2. Nevertheless, these principles also apply to the operation of transistors T9 and T16 in the second transistor group 702-2, where the second signal 704-2 propagates from the second interface 604-2 to the first interface 604-1.

[0158] Figure 11-1This is a circuit diagram showing a bidirectional amplifier 602 in an example operating configuration 1100-1 for signal amplification in a regular active amplification mode. In the regular active amplification mode, the bidirectional amplifier 602 amplifies the differential signal by a corresponding amplification factor 612 without changing the sign of the differential signal. In operating configuration 1100-1, the first transistor pair 802-1 and the second transistor pair 802-2 are enabled, but the third transistor pair 802-3 and the fourth transistor pair 802-4 are disabled. The fifth transistor pairs 802-5 through the eighth transistor pairs 802-8 are also disabled.

[0159] In the example implementation, to enable the first transistor pair 802-1, the first enable signal 1002-1 turns on the enable transistor of the first enabling device 902-1 with a high voltage (“1”). To enable the second transistor pair 802-2, the second enable signal 1002-2 turns on the enable transistor of the second enabling device 902-2 with a high voltage (“1”). The third transistor pair 802-3 and the fourth transistor pair 802-4 are turned off with low voltages (“0”) on the third enable signal 1002-3 and the fourth enable signal 1002-4, respectively. Therefore, the DC current 1006 (e.g., Figure 10-2 A current 1006 can flow through each of the first transistor pair 802-1 and the second transistor pair 802-2, but no apparent DC current 1006 can flow through either the third transistor pair 802-3 or the fourth transistor pair 802-4.

[0160] Therefore, the differential first signal 704-1 entering the bidirectional amplifier 602 at the first negative node 606-1M and the first positive node 606-1P is amplified by the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4. Here, the positive portion of the input signal provided at the gate terminal of a given transistor is provided as the negative portion of the output signal at the drain terminal of the transistor. For example, the gate terminal of the first transistor T1 is coupled to the first positive node 606-1P, and the drain terminal of the first transistor T1 is coupled to the second negative node 606-2M. However, this results in a non-inverting amplified signal at the second interface 604-2 because the transistor T1 is implemented in a common-source (CS) amplifier configuration, which "naturally" or "automatically" inverts the amplified signal. By swapping the polarity of the differential amplifier formed by each transistor pair 802-1 and 802-2 between its input and output nodes, the amplified signal forwarded at the second positive node 606-2P and the second negative node 606-2M is not inverted.

[0161] Figure 11-2This is a circuit diagram showing a bidirectional amplifier 602 in an example operating configuration 1100-2 for signal amplification in inverted active mode. In inverted active amplification mode, the bidirectional amplifier 602 amplifies the differential signal by a corresponding amplification factor 612 and also changes the sign of the differential signal (e.g., inverting the polarity of the positive and negative portions of the differential signal). In operating configuration 1100-2, the third transistor pair 802-3 and the fourth transistor pair 802-4 are enabled, but the first transistor pair 802-1 and the second transistor pair 802-2 are disabled. The fifth transistor pairs 802-5 through the eighth transistor pairs 802-8 are also disabled.

[0162] In the example implementation, to enable the third transistor pair 802-3, the third enable signal 1002-3 turns on the enable transistor of the third enabling device 902-3 with a high voltage (“1”). To enable the fourth transistor pair 802-4, the fourth enable signal 1002-4 turns on the enable transistor of the fourth enabling device 902-4 with a high voltage (“1”). The first transistor pair 802-1 and the second transistor pair 802-2 are turned off with low voltages (“0”) on the first enable signal 1002-1 and the second enable signal 1002-2, respectively. Therefore, the DC current 1006 (e.g., Figure 10-2 A current 1006 can flow through each of the third transistor pair 802-3 and the fourth transistor pair 802-4, but no apparent DC current 1006 can flow through either the first transistor pair 802-1 or the second transistor pair 802-2.

[0163] Therefore, the differential first signal 704-1 entering the bidirectional amplifier 602 at the first negative node 606-1M and the first positive node 606-1P is amplified by the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. Here, the positive portion of the differential signal input at the gate terminal of a given transistor is provided as the positive portion of the output signal at the drain terminal of the transistor. For example, the gate terminal of the fifth transistor T5 is coupled to the first positive node 606-1P, and the drain terminal of the fifth transistor T5 is coupled to the second positive node 606-2P. However, this results in an inverted amplified signal at the second interface 604-2 because transistor T5 is implemented in a common-source (CS) amplifier configuration, which inverts the signal during normal operation. By not swapping the positive and negative portions of the differential signal supplied to the differential amplifier formed by each transistor pair 802-3 and 802-4 between their input and output nodes, the amplified signal forwarded at the second positive node 606-2P and the second negative node 606-2M for operation configuration 1100-2 is inverted. Therefore, by inverting the amplified signal components (e.g., I or Q signal components), bidirectional amplifier 602 can achieve sign switching to extend the phase shift range of phase shifter 130.

[0164] Figure 11-3 This is a circuit diagram showing a bidirectional amplifier 602 in an example operating configuration 1100-3 for inactive, non-amplification mode. In inactive amplification mode, the bidirectional amplifier 602 does not amplify the differential signal corresponding to the amplification factor 612. In other words, if participating in inactive operation mode (or disengaging from amplification), the bidirectional amplifier 602 does not contribute to the total gain of the VGA 136. In operating configuration 1100-3, the second transistor pair 802-2 and the third transistor pair 802-3 are enabled, but the first transistor pair 802-1 and the fourth transistor pair 802-4 are disabled. The fifth transistor pairs 802-5 through the eighth transistor pairs 802-8 are also disabled.

[0165] In the example implementation, to enable the second transistor pair 802-2, the second enable signal 1002-2 turns on the enable transistor of the second enabling device 902-2 with a high voltage (“1”). To enable the third transistor pair 802-3, the third enable signal 1002-3 turns on the enable transistor of the third enabling device 902-3 with a high voltage (“1”). The first transistor pair 802-1 and the fourth transistor pair 802-4 are turned off with low voltages (“0”) on the first enable signal 1002-1 and the fourth enable signal 1002-4, respectively. Therefore, the DC current 1006 (e.g., Figure 10-2 A current 1006 can flow through each of the second transistor pair 802-2 and the third transistor pair 802-3, but no apparent DC current 1006 can flow through either the first transistor pair 802-1 or the fourth transistor pair 802-4.

[0166] Although DC current 1006 flows through each of the second transistor pair 802-2 and the third transistor pair 802-3, the bidirectional amplifier 602 does not perform amplification in operating configuration 1100-3. Instead, the AC current from the first differential signal 704-1 circulates through the transistors of the second transistor pair 802-2 and the third transistor pair 802-3. For example, the positive portion of the first signal 704-1 (e.g., from the first positive node 606-1P) can increase the current at the drain of the third transistor T3 at the second negative node 606-2M. During this time, the negative portion of the first signal 704-1 (e.g., from the first negative node 606-1M) is decreasing the current at the drain of the sixth transistor T6 at the second negative node 606-2M, which absorbs the current supplied by the third transistor T3. This results in the two currents from the third transistor T3 and the sixth transistor T6 circulating in a manner that effectively cancels each other out. The fourth transistor T4 and the fifth transistor T5 undergo similar current cycling, which effectively cancels out any current changes at the second positive node 606-2P. Therefore, in operating configuration 1100-3, the bidirectional amplifier 602 does not contribute a significant amplification 612 to the total gain of the VGA136.

[0167] In some implementations, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 each have approximately the same size (e.g., to a certain extent, using a given process fabrication technology). In some cases, each transistor within the first transistor group 702-1 is built or designed to have the same size, but each size may still vary due to manufacturing tolerances. In other cases, the size of each transistor is within 5-10% of the size of the other transistors within the given transistor group. Furthermore, the gate-to-drain capacitance (Cgd) of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 is substantially the same as each other within the capabilities of the fabrication process. Based on each transistor having approximately the same size and the output coupling from the transistor to the second positive node 606-2P and the second negative node 606-2M, the gate-to-drain capacitances of the first transistor T1 through the eighth transistor T8 substantially neutralize the combined parasitic capacitance of the first transistor group 702-1. Similar to how the AC current circulates internally, the gate-to-drain capacitances of certain transistor pairs operate in opposite directions to cancel each other out. For example, when charge is built up on the gate-to-drain capacitance of the third transistor T3 due to a portion of the differential signal, the charge is dissipated on the gate-to-drain capacitance of the sixth transistor T6 by another portion of the differential signal with opposite polarities.

[0168] The bidirectional amplifier 602 can therefore be selectively operated in one of a plurality of operating modes based on the amplification control signal 608. These operating modes may include a first active mode (e.g., non-inverting active amplification mode), a second active mode (e.g., inverting active amplification mode), and an inactive mode (e.g., non-amplification mode). Each of the three operating modes is described above with two specific transistor pairs of the four transistor pairs in each transistor group 702 enabled and two other transistor pairs disabled. However, in addition to those described above and in… Figures 11-1 to 11-3 In addition to the example depicted, other implementations may have alternative transistor pairs that are enabled or disabled.

[0169] In other words, the four transistor pairs can be arranged with different input or output coupling polarities relative to each transistor pair. For example, for Figure 11-1In this active mode, the second transistor pair 802-2 and the third transistor pair 802-3 can be enabled, while the two "external" (as shown) transistor pairs (e.g., the first transistor pair 802-1 and the fourth transistor pair 802-4) are disabled. To implement this example, the second transistor pair 802-2 and the third transistor pair 802-3 are connected between the first differential interface 604-1 and the second differential interface 604-2, so that the signal amplified by these two transistor pairs is not inverted. Furthermore, the first transistor pair 802-1 and the fourth transistor pair 802-4 are connected between the first differential interface 604-1 and the second differential interface 604-2, so that the amplified signal is inverted, as described above for... Figure 11-2 The third transistor pair and the fourth transistor pair are described. As another example, for Figure 11-3 In non-amplification mode, any two transistor pairs with opposite differential polarity coupling can be enabled, while the other two transistor pairs are disabled. Two transistor pairs with opposite differential polarity coupling that allow AC current to circulate within the bidirectional amplifier 602 do not need to be positioned adjacent to each other on the IC substrate or electrically coupled adjacently.

[0170] Figure 12 This is a flowchart illustrating an example process 1200 for a phase shift with bidirectional amplification. Process 1200 is described in the form of a set of blocks 1202-1208 specifying the operations that can be performed. However, the operations are not necessarily limited to... Figure 12 The operations shown or described herein may be implemented in an alternative order or in a fully or partially overlapping manner. Furthermore, more, fewer, and / or different operations may be implemented to perform process 1200 or an alternative process. The operations represented by the illustrated blocks of process 1200 may be performed by transceiver 126 or RF front end 128 in conjunction with communication processor 124 or controller 212 (e.g., Figure 2 and Figure 4-1 More specifically, the operation of process 1200 can be performed by phase shifter 130.

[0171] In block 1202, at least one phase of the signal is generated. For example, phase shifter 130 can generate at least one phase 506 of signal 324. For example, signal phase generator 132 can generate at least one phase 454-3 of signal 324 based on phase 454-1 of signal 324.

[0172] In block 1204, the amplitude of a component of the modulated signal is specified. This component corresponds to at least one phase of the signal, and modulation involves amplifying the component of the signal according to an activity mode. For example, phase shifter 130 can modulate the amplitude of a component of signal 324, where the signal component corresponds to at least one phase 506. Phase shifter 130 can amplify the component of signal 324 according to the activity mode of vector modulator 134.

[0173] Vector modulator 134 can perform amplitude modulation of components of signal 324, for example, by increasing the amplitude of a component corresponding to at least one phase 454-3, wherein the at least one phase 454-3 may include at least one of signal components corresponding to phases 454-10 or 454-11. Vector modulator 134 may include at least one VGA 136, which includes one or more bidirectional amplifiers 602-1 to 602-A. The bidirectional amplifier 602 may be configured to use... Figure 11-1 The operation configuration 1100-1 establishes an active mode to amplify the components of signal 324. Enabling the active mode using operation configuration 1100-1 may include enabling and disabling certain transistor pairs of bidirectional amplifier 602. This enabling and disabling of certain transistor pairs is described with reference to reference boxes 1206 and 1208.

[0174] In block 1206, a first transistor pair and a second transistor pair are enabled. The first transistor pair and the second transistor pair are coupled to a first interface, and are coupled to a second interface via a first polarity. For example, a bidirectional amplifier 602 may enable a first transistor pair 802-1 and a second transistor pair 802-2. The first transistor pair 802-1 and the second transistor pair 802-2 are coupled to a first interface 604-1, and are coupled to the second interface 604-2 via a first polarity. In some cases, the first interface 604-1 includes a first differential interface 604-1, which includes a first positive node 606-1P and a first negative node 606-1M; the second interface 604-2 includes a second differential interface 604-1, which includes a second positive node 606-2P and a second negative node 606-2M. The first polarity can correspond to the first differential coupling, wherein the positive and negative signaling outputs are not swapped relative to the positive and negative signaling inputs of each transistor pair 802 of the first transistor pair 802-1 and the second transistor pair 802-2, as shown in operation configuration 1100-1.

[0175] In block 1208, the third and fourth transistor pairs are disabled. The third and fourth transistor pairs are coupled to a first interface and are coupled to a second interface via a second polarity opposite to the first polarity. For example, bidirectional amplifier 602 can disable the third transistor pair 802-3 and the fourth transistor pair 802-4. The third transistor pair 802-3 and the fourth transistor pair 802-4 are coupled to a first interface 604-1 and are coupled to a second interface 604-2 via a second polarity. Here, the second polarity is opposite to the first polarity by swapping the corresponding positive and negative portions of the differential signaling. For example, the second polarity can correspond to a second differential coupling, where the positive and negative signaling outputs are swapped relative to the positive and negative signaling inputs of each transistor pair 802 of the third transistor pair 802-3 and the fourth transistor pair 802-4, as shown in operation configuration 1100-1. This exchange or non-exchange of positive and negative signaling outputs relative to positive and negative signaling inputs can be made depending on whether the amplifier inherently inverts the signal (e.g., a common-source amplifier) ​​or not inherently inverts the signal (e.g., a common-gate amplifier).

[0176] The terms “first,” “second,” “third,” and other number-related indicators are used herein to identify or distinguish similar or related items in a given context—such as a particular implementation, a given circuit, a single drawing, or a claim. Therefore, a first item in one context may differ from a first item in another. For example, an item identified as a “first transistor pair” in one context may be identified as a “second transistor pair” in another context, or may be arranged differently relative to other transistor pairs in various contexts.

[0177] Unless the context otherwise requires, the use of the word “or” herein can be interpreted as the use of an inclusive “or”, or a term that allows the inclusion or application of one or more items linked by the word “or” (e.g., the phrase “A or B” can be interpreted as allowing only “A”, only “B”, or both “A” and “B”). Furthermore, items represented in the accompanying drawings and terms discussed herein may refer to one or more items or terms, and therefore reference may be made interchangeably to single or multiple forms of items and terms in this written description. Finally, while the subject matter has been described in language specific to structural features or methodological operations, the scope of the invention is provided by the claims. Therefore, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations described above, but includes, not necessarily limited to, the organization of arrangement features or the order of performing operations.

Claims

1. An apparatus comprising: Phase shifter, including: First positive node; First negative node; Second positive node; The second negative node; and A bidirectional amplifier, including: A first transistor is coupled between the first positive node and the second negative node, wherein the gate terminal of the first transistor is coupled to the first positive node, and the drain terminal of the first transistor is coupled to the second negative node; A second transistor is coupled between the first negative node and the second positive node, wherein the gate terminal of the second transistor is coupled to the first negative node, and the drain terminal of the second transistor is coupled to the second positive node; A third transistor is coupled between the first positive node and the second negative node, wherein the gate terminal of the third transistor is coupled to the first positive node and the drain terminal of the third transistor is coupled to the second negative node; A fourth transistor is coupled between the first negative node and the second positive node, wherein the gate terminal of the fourth transistor is coupled to the first negative node and the drain terminal of the fourth transistor is coupled to the second positive node; A fifth transistor is coupled between the first positive node and the second positive node, wherein the gate terminal of the fifth transistor is coupled to the first positive node, and the drain terminal of the fifth transistor is coupled to the second positive node; A sixth transistor is coupled between the first negative node and the second negative node, wherein the gate terminal of the sixth transistor is coupled to the first negative node and the drain terminal of the sixth transistor is coupled to the second negative node; A seventh transistor, coupled between the first positive node and the second positive node, wherein the gate terminal of the seventh transistor is coupled to the first positive node, and the drain terminal of the seventh transistor is coupled to the second positive node; and An eighth transistor is coupled between the first negative node and the second negative node, wherein the gate terminal of the eighth transistor is coupled to the first negative node and the drain terminal of the eighth transistor is coupled to the second negative node.

2. The apparatus of claim 1, wherein the bidirectional amplifier further comprises: The ninth transistor is coupled between the second positive node and the first positive node; The tenth transistor is coupled between the second negative node and the first negative node; The eleventh transistor is coupled between the second positive node and the first positive node; The twelfth transistor is coupled between the second negative node and the first negative node; The thirteenth transistor is coupled between the second positive node and the first negative node; The fourteenth transistor is coupled between the second negative node and the first positive node; The fifteenth transistor is coupled between the second positive node and the first negative node; as well as The sixteenth transistor is coupled between the second negative node and the first positive node.

3. The apparatus according to claim 2, wherein: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor each have approximately a first size; The ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, and sixteenth transistors each approximately have a second size; and The first dimension is substantially different from the second dimension.

4. The apparatus of claim 3, wherein the first dimension and the second dimension correspond to at least one of the following: channel width, channel length, or effective channel width.

5. The apparatus according to claim 2, wherein: For the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor: The first positive node and the first negative node include a first differential signaling input of the bidirectional amplifier relative to the first signal propagation direction; and The second positive node and the second negative node include the first differential signaling output of the bidirectional amplifier relative to the propagation direction of the first signal; as well as For the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, and the sixteenth transistor: The second positive node and the second negative node include the second differential signaling input of the bidirectional amplifier relative to the second signal propagation direction; and The first positive node and the first negative node include the second differential signaling output of the bidirectional amplifier relative to the direction of propagation of the second signal.

6. The apparatus of claim 1, wherein the phase shifter is configured to propagate an in-phase signal component (I signal component) through the bidirectional amplifier and between: Including the first differential interface between the first positive node and the first negative node; and The second differential interface includes the second positive node and the second negative node.

7. The apparatus of claim 1, wherein the bidirectional amplifier further comprises: A first positive bias circuit system is coupled to the gate terminal of the first transistor, the gate terminal of the third transistor, the gate terminal of the fifth transistor, and the gate terminal of the seventh transistor; as well as A first negative bias circuit system is coupled to the gate terminal of the second transistor, the gate terminal of the fourth transistor, the gate terminal of the sixth transistor, and the gate terminal of the eighth transistor.

8. The apparatus according to claim 1, wherein: The first positive node and the first negative node include the differential signaling input of the bidirectional amplifier; and The second positive node and the second negative node include the differential signaling output of the bidirectional amplifier.

9. The apparatus of claim 1, wherein the bidirectional amplifier further comprises: A first positive capacitor is coupled between the first positive node and the following: the first transistor, the third transistor, the fifth transistor, and the seventh transistor; as well as A first negative capacitor is coupled between the first negative node and the following: the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor.

10. The apparatus according to claim 9, further comprising: At least one distribution network (PDN) node (PDN node), wherein: The first transistor, the third transistor, the sixth transistor, and the eighth transistor are DC coupled to the at least one PDN node via the second negative node; and The second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are DC coupled to the at least one PDN node via the second positive node.

11. The apparatus of claim 1, wherein the bidirectional amplifier further comprises: The first enabled device, coupled to: The first transistor is connected to at least one power distribution network (PDN) node (PDN node); as well as Between the second transistor and the at least one PDN node; The second enabled device is coupled to: Between the third transistor and the at least one PDN node; and Between the fourth transistor and the at least one PDN node; The third enabled device is coupled to: Between the fifth transistor and the at least one PDN node; and Between the sixth transistor and the at least one PDN node; And the fourth enabling device, coupled to: Between the seventh transistor and the at least one PDN node; and The eighth transistor is between the at least one PDN node.

12. The apparatus according to claim 11, wherein: The first enabling device is configured to allow or prevent a first direct current (DC) current from flowing through the first transistor and the second transistor; The second enabling device is configured to allow or prevent the second DC current from flowing through the third transistor and the fourth transistor; The third enabling device is configured to allow or prevent the third DC current from flowing through the fifth transistor and the sixth transistor; as well as The fourth enabling device is configured to allow or prevent the fourth DC current from flowing through the seventh transistor and the eighth transistor.

13. The apparatus according to claim 12, wherein: The first enabling device includes a first enabling transistor; The second enabling device includes a second enabling transistor; The third enabling device includes a third enabling transistor; and The fourth enabling device includes a fourth enabling transistor.

14. The apparatus according to claim 11, wherein: The at least one PDN node includes a grounding node; and Each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor includes a corresponding n-channel metal-oxide-semiconductor (MOS) field-effect transistor (FET) (nMOSFET).

15. The apparatus according to claim 11, wherein: The at least one PDN node includes at least one power node; and Each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor includes a corresponding p-channel metal-oxide-semiconductor (MOS) field-effect transistor (FET) (pMOSFET).

16. The apparatus of claim 11, wherein the bidirectional amplifier is configured to be in an active or inactive mode based on at least one of the first enabling device, the second enabling device, the third enabling device, or the fourth enabling device that allows at least one direct current (DC) to flow.

17. The apparatus according to claim 16, wherein: The activity mode includes a first activity mode; and The bidirectional amplifier is configured to be in an active mode based on the first enable device and the second enable device, which together enable the at least one DC current to flow through the first transistor, the second transistor, the third transistor, and the fourth transistor.

18. The apparatus according to claim 17, wherein: The activity mode includes the first activity mode and the second activity mode; and The bidirectional amplifier is configured to be in the second active mode based on the third and fourth enable devices, which together enable the at least one DC current to flow through the fifth, sixth, seventh, and eighth transistors.

19. The apparatus of claim 18, wherein the bidirectional amplifier is configured to output a differential signal having a polarity that is reversed relative to operation in the first active mode and in response to operation in the second active mode.

20. The apparatus of claim 17, wherein the bidirectional amplifier is configured to be in the first active mode based on the third enable device and the fourth enable device, the third enable device and the fourth enable device jointly preventing the at least one DC current from flowing through the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor.

21. The apparatus of claim 16, wherein the bidirectional amplifier is configured to be in the inactive mode based on the second enable device and the third enable device, the second enable device and the third enable device together enabling the at least one DC current to flow through the third transistor, the fourth transistor, the fifth transistor and the sixth transistor.

22. The apparatus of claim 21, wherein the bidirectional amplifier is configured to be in the inactive mode based on the first enable device and the fourth enable device, the first enable device and the fourth enable device jointly preventing the at least one DC current from flowing through the first transistor, the second transistor, the seventh transistor and the eighth transistor.

23. The apparatus according to claim 16, wherein: The bidirectional amplifier is configured to be in the inactive mode based on two of the following enable devices: the first enable device, the second enable device, the third enable device, or the fourth enable device. These two enable devices collectively allow at least one DC current to flow through four of the following transistors: the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor. Each of the four transistors is coupled to at least one of the two enable devices. Two of the four transistors are coupled to the second positive node and the second negative node, which have a first polarity; and Two of the four transistors are coupled to the second positive node and the second negative node, which have a second polarity different from the first polarity.

24. The apparatus according to claim 1, wherein: The bidirectional amplifier includes a first bidirectional amplifier corresponding to the first amplification amount; and The phase shifter includes a variable gain amplifier (VGA), which includes a first bidirectional amplifier and a second bidirectional amplifier corresponding to a second amplification amount, which is different from the first amplification amount.

25. The apparatus of claim 24, wherein the transistors of the first bidirectional amplifier and the second bidirectional amplifier have different weighting factors such that the first amplification and the second amplification are different.

26. The apparatus of claim 25, wherein the transistor of the first bidirectional amplifier has a different size compared to the transistor of the second bidirectional amplifier.

27. The apparatus of claim 24, wherein the phase shifter comprises: Signal phase generator; as well as A vector modulator coupled to the signal phase generator, the vector modulator including the VGA.

28. The apparatus of claim 27, wherein the signal phase generator is configured to generate a first signal component having a first phase and a second signal component having a second phase, the first phase and the second phase being 90 degrees (90°) apart.

29. The apparatus according to claim 27, wherein: The VGA includes a first VGA associated with a first phase of the signal; The vector modulator includes a second VGA associated with a second phase of the signal; The first VGA is coupled to the signal phase generator via the first transformer; and The second VGA is coupled to the signal phase generator via the second transformer.

30. The apparatus of claim 27, further comprising: Signal coupler; Power amplifier; as well as Low noise amplifier The phase shifter is switchably coupled to: Between the signal coupler and the power amplifier; or Between the signal coupler and the low-noise amplifier.

31. The apparatus according to claim 1, further comprising: An antenna array comprising a plurality of antenna elements, at least one of the plurality of antenna elements being coupled to the phase shifter; as well as A wireless interface device coupled to the antenna array, the wireless interface device including the phase shifter and configured to use the bidirectional amplifier of the phase shifter to guide wireless signals transmitted via the antenna array.

32. The apparatus of claim 31, further comprising: Display screen; as well as A processor, operatively coupled to the display screen and the wireless interface device, is configured to display one or more graphic images on the display screen based on the wireless signal guided by the wireless interface device using the bidirectional amplifier of the phase shifter.

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