Method for accessing a memory module

Abstract

A method for accessing a memory module is provided. The method includes encoding a first portion of burst length of first data to generate first parity information and a first cyclic redundancy code, encoding a second portion of burst length of second data to generate second parity information and a second cyclic redundancy code, writing the first data and the second data to a first memory device, and writing the first parity information, the first cyclic redundancy code, the second parity information, and the second cyclic redundancy code to a second memory device and a third memory device.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0063537, filed May 27, 2020, in the Korean Intellectual Property Office, the subject matter of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the inventive concept relate to semiconductor devices. More specifically, embodiments of the inventive concept relate to methods for accessing a semiconductor memory module supporting error correction functionality. BACKGROUND

[0003] Memory devices are typically configured to store data received from an external host device and provide the stored data in response to subsequent requests from the external host device. When data is stored to and / or retrieved from a memory device, one or more errors can occur. Such error data, if not detected and corrected, can result in system errors in the external host device. To prevent system errors of this nature, the external host device can include one or more error detection / correction functions capable of detecting one or more errors in data retrieved from the memory device and correcting the detected one or more errors.

[0004] As the one or more error detection / correction functions included in the external host device improve, the probability of one or more system errors related to error data decreases. Unfortunately, improved and emerging error detection / correction functions typically require substantial computing system resources (e.g., computing cycles, processor run time, data storage capacity, and / or data communication bandwidth, etc.). SUMMARY

[0005] Embodiments of the inventive concept provide a method for accessing a semiconductor memory module supporting improved one or more error correction functions.

[0006] According to one embodiment, a method for accessing a memory module includes encoding a first portion of burst length of first data to generate a first parity and a first cyclic redundancy code, encoding a second portion of burst length of second data to generate a second parity and a second cyclic redundancy code, writing the first data and the second data to a first memory device, and writing the first parity, the first cyclic redundancy code, the second parity, and the second cyclic redundancy code to a second memory device and a third memory device, wherein the first portion of burst length and the second portion of burst length form a burst length.

[0007] According to one embodiment, a method for accessing a memory module includes storing data in a first memory device, storing a first error correction code in a second memory device and a third memory device, and replacing at least a portion of at least one memory device among the first memory device with at least a portion of the second memory device when an error occurs in the at least one memory device.

[0008] According to one embodiment, a method for accessing a memory module includes performing a first training on a first memory device, a second memory device, and a third memory device in response to a power-on of the memory module, storing first data in the second memory device and remaining memory devices among the first memory devices except for a first failed memory device and storing a first error correction code in the third memory device when the first failed memory device is detected among the first memory devices after the first training is completed in the first training, and storing the first data in the first memory device and storing a second error correction code in the second memory device and the third memory device when no first failed memory device is detected among the first memory devices in the first training after the first training is completed. BRIEF DESCRIPTION OF DRAWINGS

[0009] The above and other objects and features of the inventive concept will become apparent from a detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram illustrating a computing system according to an embodiment of the inventive concept.

[0011] Figure 2 is a block diagram illustrating a memory device according to an embodiment of the inventive concept.

[0012] Figure 3 is a block diagram illustrating a memory bank according to an embodiment of the inventive concept.

[0013] Figure 4 is a conceptual diagram illustrating a portion of a memory cell array of Figure 3

[0014] Figure 5 is a block diagram illustrating another example of a memory bank having a structure for supporting error-independent coverage or sections independent of each other for row-dependent errors.

[0015] Figure 6 is a conceptual diagram illustrating an example of a memory cell array of Figure 5

[0016] ​​Figure 7 This is a block diagram illustrating another example of a storage body with a structure for supporting mutually independent, error-independent coverage or sections for row-related errors.

[0017] Figure 8 It is shown Figure 7 A conceptual diagram of a portion of a memory cell array.

[0018] Figure 9 This is a conceptual diagram illustrating an example where a data block corresponding to data provides coverage unrelated to two or more errors.

[0019] Figure 10 This is a conceptual diagram illustrating an example in which a data block corresponding to cyclic redundancy code and parity provides coverage independent of two or more errors.

[0020] Figure 11 This is a conceptual diagram illustrating another example of a data block of a first memory device, representing a channel (e.g., the first channel of a memory module).

[0021] Figure 12 This is a flowchart illustrating, in one example, a method of operating a computing system according to an embodiment of an inventive concept.

[0022] Figure 13 This is a conceptual diagram illustrating an example of a computing device recovering a memory device at the location of a fault when an error occurs within a coverage area.

[0023] Figure 14 This is a flowchart illustrating, in one example, a method of operating a computing system according to an embodiment of the inventive concept, wherein the computing system restores coverage with a first type of fault that has occurred for the first time using coverage of a memory device for ECC.

[0024] Figure 15 This is a conceptual diagram illustrating an example of the first type of replacement being performed.

[0025] Figure 16 This is a conceptual diagram illustrating an example of recovering a memory device that has experienced a second Type 1 failure.

[0026] Figure 17 This is a flowchart illustrating, in one example, a method of operating a computing system according to an embodiment of the inventive concept, wherein the computing system restores coverage of a memory device with ECC coverage that has a second occurrence of a first type of fault.

[0027] Figure 18 This is a conceptual diagram illustrating an example of performing the first type of replacement a second time.

[0028] Figure 19 This is a conceptual diagram illustrating another example of a computing device recovering a memory device where a fault occurred when an error occurs in a data block.

[0029] Figure 20 This is a flowchart illustrating, in one example, a method of operating a computing system according to an embodiment of the inventive concept, wherein the computing system restores coverage with a second type of fault using coverage of a memory device for ECC.

[0030] Figure 21 This is a conceptual diagram illustrating an example of performing a second type of replacement.

[0031] Figure 22 This is a flowchart illustrating, in one example, a method of operating a computing system according to an embodiment of the inventive concept, wherein the computing system performs training of a memory module.

[0032] Figure 23 This is a conceptual diagram illustrating an example of the storage space of a first memory device. Detailed Implementation

[0033] Specific embodiments of the inventive concept will now be described in some additional detail with reference to the accompanying drawings.

[0034] Figure 1 This is a block diagram illustrating a computing system 1000 according to an embodiment of the inventive concept. Here, the computing system 1000 typically includes a memory module 1100 and an external host device 1200.

[0035] The memory module 1100 may include a driver 1110, a first memory device (e.g., memory devices 1121 to 1125 and 1131 to 1135), a second memory device (e.g., memory devices 1126 to 1130 and 1136 to 1140), a driver connector 1150, first memory connectors 1161 to 1165, second memory connectors 1166 to 1170, a power management circuit 1180, and a power connector 1190.

[0036] Driver 1110 can be configured to communicate various signals (e.g., at least one of data signals, address signals, instruction signals, command signals, control signals, clock signals, etc.) with external host device 1200 via driver connector 1150. For example, driver 1110 can receive command CMD, address ADDR, and clock signal CK from external host device 1200. Driver 1110 can communicate control signal CTRL with external host device 1200. (See example...) Figure 2 ).

[0037] The driver 1110 can receive a one-way control signal from the external host device 1200 and respond to the external host device 1200 with at least one of a two-way control signal and a one-way control signal.

[0038] The driver 1110 can transmit commands CMD and addresses ADDR to the first memory devices 1121 to 1125 and 1131 to 1135 via the first channel CH1. The driver 1110 can also transmit control signals received from the external host device 1200 to the first memory devices 1121 to 1125 and 1131 to 1135 via the first channel CH1.

[0039] In response to a command received from the external host device 1200, the driver 1110 can transmit control signals received from the first memory devices 1121 to 1125 and 1131 to 1135 to the external host device 1200 via the first channel CH1. The control signal CTRL communicated by the driver 1110 to the external host device 1200 may be the same as, partially the same as, or different from the control signals communicated by the driver 1110 to the first memory devices 1121 to 1125 and 1131 to 1135.

[0040] In a similar manner, driver 1110 can communicate with second memory devices 1126 to 1130 and 1136 to 1140 via second channel CH2.

[0041] In some embodiments, driver 1110 may be a register clock driver (RCD) (such as a register clock driver defined by an application technology standard associated with a Dual In-line Memory Module (DIMM). In a particular embodiment, driver 1110 may be an RCD defined in relation to a Dual Data Rate Generation 5 Synchronous Dynamic Random Access Memory (DDR5 SRAM) DIMM.

[0042] The first memory devices 1121 to 1125 and 1131 to 1135 can communicate with the external host device 1200 via the first memory connectors 1161 to 1165. For example, the first memory devices 1121 to 1125 and 1131 to 1135 can communicate with the external host device 1200 the data signal DQ and the data strobe signal DQS. (See example) Figure 2 ).

[0043] The second memory devices 1126 to 1130 and 1136 to 1140 can communicate with the external host device 1200 via the second memory connectors 1166 to 1170. For example, the second memory devices 1126 to 1130 and 1136 to 1140 can communicate with the external host device 1200 the data signal DQ and the data strobe signal DQS.

[0044] In some embodiments, the first memory devices 1121 to 1125 and 1131 to 1135, and the second memory devices 1126 to 1130 and 1136 to 1140 may be DDR5 SDRAM. Furthermore, the first memory devices 1121 to 1125 and 1131 to 1135, and the second memory devices 1126 to 1130 and 1136 to 1140 may communicate with the external host device 1200 according to one or more DIMM-related technical standards (in particular, the DDR5 SDRAM DIMM standard).

[0045] Depending on the nature of one or more requests received from the external host device 1200, the first memory devices 1121 to 1125 and 1131 to 1135, and the second memory devices 1126 to 1130 and 1136 to 1140 may simultaneously receive and / or write the received data signal DQ. Depending on the nature of one or more requests received from the external host device 1200, the first memory devices 1121 to 1125 and 1131 to 1135, and the second memory devices 1126 to 1130 and 1136 to 1140 may simultaneously read the data signal DQ and / or write the read data signal DQ.

[0046] In response to one or more specific requests from external host device 1200, first memory devices 1121 to 1125 and 1131 to 1135 and / or second memory devices 1126 to 1130 and 1136 to 1140 may sequentially receive or sequentially output data signals DQ up to multiple times, according to a defined burst length BL. For example, a burst length BL of sixteen (16) is defined in relation to the DDR5 SDRAM DIMM technology standard.

[0047] In some embodiments, the number of data signals DQ associated with DDR5 SDRAM can be practically reduced compared to certain existing memory devices (e.g., DDR4 SDRAM). For example, external host device 1200 can be configured to transmit 64-byte data signals DQ via each of the first memory connectors 1161 to 1165 and the second memory connectors 1166 to 1170. And to support compatibility with 64-byte data, the first memory devices 1121 to 1125 and 1131 to 1135, and the second memory devices 1126 to 1130 and 1136 to 1140 can be configured to communicate data using a burst length BL of 16.

[0048] Therefore, in response to a single write request or a single read request received from the external host device 1200, the first memory devices 1121 to 1125 and 1131 to 1135 and the second memory devices 1126 to 1130 and 1136 to 1140 can receive the data signal DQ 16 times consecutively, or can output the data signal DQ 16 times consecutively.

[0049] Each of the first memory connectors 1161 to 1165 and the second memory connectors 1166 to 1170 can be connected to two (2) vertically arranged memory devices. That is, each of the first memory devices 1121 to 1125 and 1131 to 1135 and the second memory devices 1126 to 1130 and 1136 to 1140 can communicate with the external host device 1200 in units of 32 bytes. Each of the first memory devices 1121 to 1125 and 1131 to 1135 and the second memory devices 1126 to 1130 and 1136 to 1140 can be a (x4) memory device that communicates four (4) data signals DQ with the external host device 1200.

[0050] The power management circuit 1180 can receive at least one external power signal from the external host device 1200 via the power connector 1190, and the power management circuit 1180 can generate various internal power signals from the at least one external power signal. For example, the power management circuit 1180 can supply one or more internal power signals to the driver 1110, the first memory devices 1121 to 1125 and 1131 to 1135, and the second memory devices 1126 to 1130 and 1136 to 1140.

[0051] In some embodiments, the power management circuit 1180 may be a power management integrated circuit (PMIC) defined according to one or more standards associated with a DDR5 SDRAM DIMM.

[0052] In some embodiments, Figure 1The memory module 1100 can be a registered DIMM (RDIMM), an unbuffered DIMM (UDIMM), a load-reduced DIMM (LRDIMM), a fully buffered DIMM (FBDIMM), etc.

[0053] Those skilled in the art will recognize that, regardless of the specific configuration, the memory module 1100 can be designed or modified in design to conform to one or more technical standards (such as one or more technical standards associated with RDIMM). Specific modifications may result in changes, additions, and / or removals of one or more components defined by one or more technical standards.

[0054] exist Figure 1 In the illustrated example, the external host device 1200 may include a processor 1210, a power supply 1220, a host power management circuitry 1230, and a device driver 1240. The processor 1210 may include a general-purpose processor (such as a central processing unit (CPU)) and a dedicated processor (such as an application processor (AP), a graphics processing unit (GPU), a neuromorphic processor (NP), or a neuromorphic processor).

[0055] Processor 1210 may include memory controller 1211. Memory controller 1211 may control memory module 1100 and may communicate with memory module 1100. Communication with external host device 1200 of data and one or more signals, as described with reference to memory module 1100, may be performed at least in part by memory controller 1211.

[0056] The memory controller 1211 may include error correction circuitry 1212, which may be configured to generate error correction codes (ECCs). When the memory controller 1211 writes data DT to the memory module 1100, the memory controller 1211 may generate various ECCs that can be used to detect and / or correct one or more data errors in the data DT.

[0057] The memory controller 1211 can write data DT to first memory devices 1121 to 1124 and 1131 to 1134 (hereinafter, "first memory devices 1121 to 1124 and 1131 to 1134 for data") which are part of first memory devices 1121 to 1125 and 1131 to 1135, and can also write ECC to the remaining memory devices 1125 and 1135 (hereinafter, "first memory devices 1125 and 1135 for ECC") which are part of the first memory devices 1121 to 1125 and 1131 to 1135.

[0058] The memory controller 1211 can write data DT to second memory devices 1127 to 1130 and 1137 to 1140, which are part of second memory devices 1126 to 1130 and 1136 to 1140 (hereinafter, "second memory devices 1127 to 1130 and 1137 to 1140 for data"), and can also write ECC to the remaining memory devices 1126 and 1136, which are part of second memory devices 1126 to 1130 and 1136 to 1140 (hereinafter, "second memory devices 1126 and 1136 for ECC").

[0059] In some embodiments, ECC may include a cyclic redundancy code "C" for detecting one or more errors and parity information "P" for correcting the detected one or more errors. (See example) Figure 11 The memory controller 1211 can read data DT and ECC from the memory module 1100 and perform error detection and / or correction (hereinafter, detection / correction).

[0060] The power supply 1220 of the external host device 1200 can generate one or more external power signals to drive the computing system 1000. In this regard, one or more external power signals can be provided to the host power management circuit 1230, and the host power management circuit 1230 can generate one or more internal power signals required to drive the external host device 1200. Here, the host power management circuit 1230 can be a PMIC designed and manufactured to meet the requirements of the computing system located in the external host device 1200. The host power management circuit 1230 can supply one or more internal power signals to the components of the processor 1210 and the external host device 1200.

[0061] Device driver 1240 can control various auxiliary devices under the control of processor 1210. For example, device driver 1240 can be connected to various devices (such as storage devices, modems, and user interface devices) and can arbitrate communication between various devices and processor 1210.

[0062] The number of first memory devices 1121 to 1125 and 1131 to 1135 and the number of second memory devices 1126 to 1130 and 1136 to 1140 may vary according to the design and are not limited to the examples shown herein.

[0063] Figure 2 This is a block diagram illustrating a memory device 100 according to an embodiment of the inventive concept. Here, the memory device 100 may correspond to the previously mentioned... Figure 1The first memory devices 1121 to 1125 and 1131 to 1135 and / or one of the second memory devices 1126 to 1130 and 1136 to 1140 are described. In some embodiments, the first memory devices 1121 to 1125 and 1131 to 1135 and the second memory devices 1126 to 1130 and 1136 to 1140 may have the same structure and may perform substantially the same one or more operations.

[0064] Reference Figure 1 and Figure 2 The memory device 100 may include a first memory bank group BG1 and a second memory bank group BG2. Each of the first memory bank group BG1 and the second memory bank group BG2 may include a first memory bank BANK1 to a fourth memory bank BANK4. The first memory banks BANK1 to the fourth memory bank BANK4 of the first memory bank group BG1 and the second memory bank group BG2 may have the same structure and may perform the same operation.

[0065] Each of the first storage bank BANK1 to the fourth storage bank BANK4 may include multiple memory units. The memory units may be used to store data DT or ECC transmitted from the external host device 1200.

[0066] The memory device 100 may further include peripheral circuitry 110. Peripheral circuitry 110 can communicate with an external host device 1200 via control signal CTRL. Peripheral circuitry 110 can receive commands CMD, address ADDR, and clock signal CK from the external host device 1200. Peripheral circuitry 110 can select the memory bank indicated by address ADDR from the first memory bank BANK1 to the fourth memory bank BANK4 of the first memory bank group BG1 and the second memory bank group BG2.

[0067] Peripheral circuitry 110 can control a selected memory bank, causing an operation (e.g., a write operation or a read operation) to be performed on a memory cell indicated by address ADDR from the selected memory bank's memory cells, guided by command CMD. Peripheral circuitry 110 can communicate with external host device 1200 the data signal DQ and the data strobe signal DQS. The data strobe signal DQS can be used to transmit timing signals to latch the data signal DQ.

[0068] The peripheral circuitry 110 may include input and output circuitry 120 configured to exchange data signals DQ and DQS with an external host device 1200. The peripheral circuitry 110 may also include control logic 130 configured to control the selected memory bank in response to commands CMD, address ADDR, clock signal CK, and control signal CTRL.

[0069] The number of memory groups and the number of memory cells can vary depending on the design, and the scope of the inventive concept is not limited to the examples shown.

[0070] Figure 3 A storage unit 200 according to an embodiment of the inventive concept is shown. Here, the storage unit 200 may correspond to the previously mentioned... Figure 2 The first storage bank BANK1 to BANK4 of the first storage bank group BG1 and / or the first storage bank BANK1 to BANK4 of the second storage bank group BG2.

[0071] Reference Figure 1 to Figure 3 The memory bank 200 may include a memory cell array 210, a row decoder 220, a first bit line sense amplifier (BLSA) 240, a second bit line sense amplifier 250, and a column decoder 260.

[0072] The memory cell array 210 may include memory cells arranged along the row and column directions. The memory cell array 210 may include a zeroth (0th) region R0 to a fifteenth (15th) region R15. Regions 0 to 15 may correspond to a defined burst length BL (e.g., 2, 4, 8, 16, 32, etc.). For example, assuming a burst length BL of 8, the number of regions in the memory cell array 210 may be 8; assuming a burst length BL of 32, the number of regions in the memory cell array 210 may be 32.

[0073] The row decoder 220 can be connected to memory cells in a row via word lines WL1 to WLn (where 'n' is a positive integer). The row decoder 220 can receive the row address RA of address ADDR and can select one of the first word lines WL1 to the nth word line WLn in response to the row address RA. For example, the row decoder 220 can apply an activation voltage (e.g., a positive voltage) to the selected word line.

[0074] The first bit line sense amplifier 240 and the second bit line sense amplifier 250 can be connected to memory cells in the column via bit lines. The bit lines connected to the first bit line sense amplifier 240 can be different from the bit lines connected to the second bit line sense amplifier 250. For example, the first bit line sense amplifier 240 can be connected to even-numbered (or odd-numbered) bit lines along the row direction, and the second bit line sense amplifier 250 can be connected to odd-numbered (or even-numbered) bit lines along the row direction.

[0075] The first bit-line sense amplifier 240 and the second bit-line sense amplifier 250 can apply voltage to the bit line or sense the voltage of the bit line. By adjusting or sensing the voltage of the bit line, the first bit-line sense amplifier 240 and the second bit-line sense amplifier 250 can perform write or read operations on the memory cell of the selected row.

[0076] Column decoder 260 can receive column address CA of address ADDR. Column decoder 260 can electrically connect a portion of the bit line to peripheral circuitry 110 in response to column address CA. In some embodiments, column decoder 260 can output data DT or ECC corresponding to burst length BL of 16 by sequentially selecting regions 0 to 15 R15 and outputting data read from memory cells of the thus selected regions.

[0077] An example is shown where memory cell array 210 includes regions 0 through 15, R15. However, memory cell array 210 may include multiple subarrays, and each subarray may include regions 0 through 15, R15. During a write or read operation, one of the multiple subarrays may be selected, and the write or read operation may be performed in regions 0 through 15, R15, of the selected subarray in units of burst length BL.

[0078] about Figure 3 The column decoder 260 is assumed to be located within memory bank 200. However, the column decoder 260 may alternatively be included in peripheral circuitry 110. When the column decoder 260 is included in peripheral circuitry 110, the column decoder 260 can control the input and / or output of data DT or ECC associated with one of the memory banks selected from the first memory bank BANK1 through the fourth memory bank BANK4 of the first memory bank group BG1 and the second memory bank group BG2. That is, the column decoder 260 can be used collectively for the first memory bank BANK1 through the fourth memory bank BANK4 of the first memory bank group BG1 and the second memory bank group BG2.

[0079] Figure 4 It is partially shown Figure 3 A conceptual diagram of the memory cell array 210. (Refer to...) Figure 1 , Figure 2 , Figure 3 and Figure 4 The memory cell array 210 may include memory cells MC (each indicated by a circle). Memory cells MC can be connected to a sub-word line driver SD via sub-word lines SWL. The sub-word line driver SD can be connected to word lines (e.g., third word lines WL3 through sixth word lines WL6).

[0080] Regions 0 (R0) to 15 (R15) can each correspond to a burst length BL of 16. For example, as... Figure 4 As shown, the sixth region R6 to the ninth region R9 can correspond to the sixth burst length BL6 to the ninth burst length BL9, respectively.

[0081] In the seventh region R7, the memory cell MC corresponding to the fourth word line WL4 and the sixth word line WL6 can be connected to the sub-word line placed to the left of the corresponding sub-word line driver SD. The memory cell MC corresponding to the third word line WL3 and the fifth word line WL5 can be connected to the sub-word line placed to the right of the corresponding sub-word line driver SD.

[0082] During write and / or read operations, at least one (or line) of sub-word line drivers SD (or sub-word lines SWL) connected to a selected word line can be selected. Write and / or read operations can be performed on memory cells MC connected to a sub-word line SWL, or on memory cells MC connected to at least one selected sub-word line SWL connected to at least one selected sub-word line driver SD.

[0083] In some embodiments, a decoding line may also be provided for selecting at least one of the sub-word line drivers SD connected to at least one of the selected word lines or sub-word lines. The decoding line may be controlled by the line decoder 220 based on the line address RA. Here, for clarity, the decoding line has been omitted.

[0084] Therefore, the sub-word line drivers SD connected to the third word line WL3 to the sixth word line SW6 can be sequentially positioned to the left and right of the sixth region R6 along the column direction. Similarly, in each of the 0th region R0 to the 5th region R5 and the 7th region R7 to the 15th region R15, the sub-word line drivers SD can be sequentially positioned to the left and right of the corresponding region along the column direction.

[0085] In some embodiments, subword line drivers SD can be configured independently of each other in the 7th region R7 and the 8th region R8, which correspond to the 7th burst length BL7 and the 8th burst length BL8, respectively. That is, the subword line SWL of the 7th region R7 can be driven independently of the subword line SWL of the 8th region R8.

[0086] One or more errors occurring in any of the subword line driver SDs associated with region 0 through region 7 (R7) will not affect regions 8 through 15 (R15). Similarly, one or more errors occurring in any of the subword line driver SDs associated with region 8 through region 15 (R15) will not affect regions 0 through 7 (R7).

[0087] Therefore, regions R0 to R7 and R8 to R15 can be segments that are independent of each other for one or more row-related errors. Thus, burst lengths BL0 to BL7 and BL8 to BL15 of a data block can be error-independent.

[0088] In each of regions 0 through 15 (R15), the first bit line sensing amplifier 240 can be connected to an even-numbered bit line. In each of regions 0 through 15 (R15), the second bit line sensing amplifier 250 can be connected to an odd-numbered bit line.

[0089] In some embodiments, four (4) memory cells MC can be connected to a subword line SWL. The memory cells MC connected to a subword line SWL can be written to or read from simultaneously. The four (4) memory cells MC connected to a subword line SWL can each correspond to four data signals DQ.

[0090] In some embodiments, multiple memory cell groups may be connected to a subword line SWL. Each of the multiple memory cell groups may include a memory cell MC (e.g., four (4) memory cells MC) corresponding to a data signal DQ that is simultaneously received or output by the memory device 100.

[0091] During a write or read operation, one of multiple memory cell groups connected to a subword line (SWL) can be selected. A write or read operation can then be performed on a memory cell within the selected memory cell group.

[0092] Figure 5 This is a block diagram illustrating another example of a memory bank 300 with a structure that supports error-independent coverage or independent sections for one or more row-related errors. (See also...) Figure 1 , Figure 2 and Figure 5 The storage unit 300 may include a memory cell array 310, a first row decoder 320, a second row decoder 330, a first bit line sensing amplifier 340, a second bit line sensing amplifier 350, and a column decoder 360.

[0093] Here, apart from configuring the first row decoder 320 and the second row decoder 330, the structure and operation of the storage bank 300 can be the same as... Figure 3 The structure and operation of the storage unit 200 are the same.

[0094] The first-line decoder 320 can be connected to word lines 11 through 1n (WL11 to WL1n). Word lines 11 through 1n (WL1n) can be connected to the storage units of regions 0 (R0) through 7 (R7). The second-line decoder 330 can be connected to word lines 21 through 2n (WL2n). Word lines 21 through 2n (WL2n) can be connected to the storage units of regions 8 (R8) through 15 (R15).

[0095] Figure 6 It is partially shown Figure 5 A conceptual diagram of the memory cell array 310. (Refer to...) Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown by the thick dashed lines, word lines 13 (WL13) to 16 (WL16) and word lines 23 (WL23) to 26 (WL26) can be electrically and physically separated between region 7 (R7) and region 8 (R8). Therefore, the sub-word line drivers SD in regions 7 (R7) and 8 (R8) do not share the same space.

[0096] Lines WL11 (11th digit) to WL1n (1nth digit) may pass through the first segment including region R0 to region R7 (7th digit), but may not pass through the second segment including region R8 to region R15 (15th digit). Lines WL21 (21st digit) to WL2n (2nth digit) may pass through the second segment including region R8 to region R15 (15th digit), but may not pass through the first segment including region R0 to region R7 (7th digit).

[0097] For reference Figure 3 and Figure 4 The above and in relation to Figure 5 and Figure 6 In the context of the described structure, errors in the subword line driver SD belonging to the first segment, which includes regions R0 to R7, will not affect regions R8 to R15 of the second segment. Furthermore, errors in the subword line driver SD within regions R8 to R15 will not affect regions R0 to R7.

[0098] Furthermore, faults occurring at word line 11 (WL11) to word line 1n (WL1n) will not affect regions 8 (R8) to 15 (R15). Faults occurring at word line 21 (WL21) to word line 2n (WL2n) will not affect regions 0 (R0) to 7 (R7). Therefore, error-independent coverage can be provided for faults at word line levels as well as faults at sub-word line driver levels.

[0099] Furthermore, a fault in the first line decoder 320 will not affect a fault in the second line decoder 330, and a fault in the second line decoder 330 will not affect a fault in the first line decoder 320. Therefore, error-independent coverage can be provided for faults in the line decoder levels.

[0100] Figure 7 This is a block diagram illustrating another example of a memory bank 400 with a structure that supports error-independent coverage or independent sections for row-related errors. (See also...) Figure 1 , Figure 2 and Figure 7 The memory bank 400 may include a memory cell array 410, a row decoder 420, a first bit line sense amplifier 440, a second bit line sense amplifier 450, and a column decoder 460.

[0101] Here, apart from the fact that the number of word lines WL1 to WL2n connected to the line decoder 420 has been doubled, the structure and operation of the memory bank 400 can be compared with... Figure 3 The structure and operation of the storage unit 200 are the same.

[0102] Figure 8 It is shown Figure 7 A conceptual diagram of an example memory cell array 410. (Refer to...) Figure 1 , Figure 2 , Figure 7 and Figure 8 The first word line WL1 to the 2n word line WL2n can be sequentially connected to the memory cells of the first segment including the 0th region R0 to the 7th region R7 and the second segment including the 8th region R8 to the 15th region R15.

[0103] In some embodiments, odd-numbered word lines, including the fifth word line WL5, the seventh word line WL7, and the ninth word line WL9, can be connected to a memory cell comprising a first segment comprising regions R0 to R7. Here, odd-numbered word lines can pass through a second segment to reach the first segment. Even-numbered word lines, including the sixth word line WL6, the eighth word line WL8, and the crosshair WL10, can be connected to a memory cell comprising a second segment comprising regions R8 to R15.

[0104] For reference Figure 3 and Figure 4 The above and in relation to Figure 7 and Figure 8In the context of the described structure, errors in the sub-word line driver SD belonging to the first segment, which includes regions R0 to R7 (region 0), will not affect regions R8 to R15 (region 15) of the second segment. Furthermore, errors in the sub-word line driver SD belonging to the second segment, which includes regions R8 to R15 (region 15), will not affect regions R0 to R7 (region 0) of the first segment.

[0105] Furthermore, faults (i.e., errors) occurring at odd-numbered word lines will not affect regions 8 (R8) through 15 (R15). Faults (i.e., errors) occurring at even-numbered word lines will not affect regions 0 (R0) through 7 (R7). Therefore, error-independent coverage can also be provided for faults at word line levels as well as faults at sub-word line driver levels.

[0106] Figure 9 This is a conceptual diagram illustrating an example of how a data block corresponding to data DT provides coverage independent of two or more errors. (Common Reference) Figure 1 to Figure 9 Each of the first memory bank BANK1 to the fourth memory bank BANK4 of the first memory bank group BG1 and the second memory bank group BG2 of the memory device 100 can be implemented as Figure 3 and Figure 4 Storage 200, Figure 5 and Figure 6 storage 300 or Figure 7 and Figure 8 400 storage units.

[0107] The memory device 100 can simultaneously receive or output first data signals DQ1 to fourth data signals DQ4. The memory device 100 can continuously receive or output first data signals DQ1 to fourth data signals DQ4 up to a number of times corresponding to the number of burst lengths BL0 to BL15 (i.e., 16). Therefore, a data block, which serves as the unit for exchanging data DT between the memory device 100 and the external host device 1200, can be formed from 64 bits.

[0108] Here, it is assumed that memory module 1100 includes eight (8) first memory devices 1121 to 1124 and 1131 to 1134 for data and eight (8) second memory devices 1127 to 1130 and 1137 to 1140 for data. Therefore, memory module 1100 can exchange data DT with external host device 1200 in units of 1024 bits.

[0109] Here, the term "coverage" refers to a subset of data blocks, each data block being a unit in which the memory device 100 exchanges data DT with the external host device 1200. For example, burst lengths 0 through 7 (BL7) can constitute a first coverage, and burst lengths 8 through 15 (BL15) can constitute a second coverage, wherein the first coverage includes first data DT1 and the second coverage includes second data DT2.

[0110] Errors occurring in the first coverage area do not affect the second coverage area and are not affected by the second coverage area. Errors occurring in the second coverage area do not affect the first coverage area and are not affected by the first coverage area. Therefore, the first and second coverage areas can be error-independent coverage areas. The memory device 100 can provide two or more error-independent coverage areas for a burst length BL of 16.

[0111] In other words, an error in the first data DT1 stored in the first coverage area will not be associated with an error in the second data DT2 stored in the second coverage area. Similarly, an error in the second data DT2 stored in the second coverage area will not be associated with an error in the first data DT1 stored in the first coverage area.

[0112] For reference Figure 4 , Figure 6 and Figure 8 The regions R0 to R15, corresponding to burst lengths BL0 to BL15 respectively, are arranged along the row direction. Therefore, two or more error-independent coverage areas can correspond to two or more segments that are independent of each other for row-related errors. Here, the term "segment" can refer to a subset of the memory cell array 210, and each segment can include two or more regions from region R0 to region R15.

[0113] Figure 10 This is a conceptual diagram showing the data block corresponding to the cyclic redundancy code "C" and parity information "P," regardless of the coverage provided for two or more errors. See reference... Figure 9 The 0th burst length BL0 to the 7th burst length BL7 constitute a first coverage area, and the 8th burst length BL8 to the 15th burst length BL15 constitute a second coverage area. (See common reference) Figure 1 to Figure 10The data blocks in the first memory devices 1121 to 1124 and 1131 to 1134 for data can be data blocks for data (e.g., data blocks for storing payload data), and the data blocks in the second memory devices 1125 and 1135 for ECC can be data blocks for ECC (e.g., data blocks for storing cyclic redundancy code "C" and parity information "P"). When the data blocks for data provide two or more error-independent coverages, the external host device 1200 can independently perform error correction encoding / decoding on the two or more coverages.

[0114] Error correction coding can be used to generate cyclic redundancy code "C" and parity information "P" from data DT during a write operation. Error correction decoding can be used during a read operation to detect one or more errors in data DT using the cyclic redundancy code "C" and to correct the detected errors using the parity information "P".

[0115] In some embodiments, a data block for ECC may include a first cyclic redundancy code C1 and a first parity information P1 for a first coverage area of ​​the data block, and a second cyclic redundancy code C2 and a second parity information P2 for a second coverage area of ​​the data block.

[0116] In some embodiments, the ECC data block corresponding to one of the first memory devices 1125 and 1135 for ECC in the first channel CH1 may include a first cyclic redundancy code C1 and a second cyclic redundancy code C2 corresponding to the data block for data in the first channel CH1, and the ECC data block corresponding to the other of the first memory devices 1125 and 1135 for ECC in the first channel CH1 may include a first parity information P1 and a second parity information P2 corresponding to the data block for data in the first channel CH1.

[0117] The ECC data block corresponding to one of the second memory devices 1126 and 1136 for ECC in the second channel CH2 may include a first cyclic redundancy code C1 and a second cyclic redundancy code C2 corresponding to the data block for data in the second channel CH2, and the ECC data block corresponding to the other of the second memory devices 1126 and 1136 for ECC in the second channel CH2 may include a first parity information P1 and a second parity information P2 corresponding to the data block for data in the second channel CH2.

[0118] Figure 11This is a conceptual diagram illustrating another example of data blocks for the first memory devices 1121 to 1125 and 1131 to 1135 of a channel (e.g., the first channel CH1) of memory module 1100. Except for the corresponding locations where the data blocks are placed, the data blocks for the second memory devices 1126 to 1130 and 1136 to 1140 of the second channel CH2 can be referenced... Figure 11 The data blocks described are the same.

[0119] Common Reference Figure 1 to Figure 11 Each of the data blocks belonging to the first memory devices 1121 to 1124 and 1131 to 1134 for data may include first data DT1 for each of the first coverage areas 1121a to 1124a and 1131a to 1134a and second data DT2 for each of the second coverage areas 1121b to 1124b and 1131b to 1134b.

[0120] The first coverage area 1125a and the second coverage area 1125b of the data block for ECC in the first memory device 1125 for ECC may include first parity information P1 and second parity information P2 corresponding to the first data DT1 of the first coverage areas 1121a to 1124a and 1131a to 1134a and the second data DT2 of the second coverage areas 1121b to 1124b and 1131b to 1134b, respectively.

[0121] The first coverage area 1135a and the second coverage area 1135b of the data block for ECC in the first memory device 1135 for ECC may include a first cyclic redundancy code C1 and a second cyclic redundancy code C2 corresponding to the first data DT1 of the first coverage areas 1121a to 1124a and 1131a to 1134a and the second data DT2 of the second coverage areas 1121b to 1124b and 1131b to 1134b, respectively.

[0122] Using the data blocks shown, the memory controller 1211 can write data to or read data from the locations corresponding to address ADDR in the first memory devices 1121 to 1125 and 1131 to 1135.

[0123] The first coverage ranges 1121a to 1124a and 1131a to 1134a are error-independent and can therefore be considered as different memories from the second coverage ranges 1121b to 1124b and 1131b to 1134b. Therefore, the range over which the memory controller 1211 performs error correction encoding / decoding can be reduced.

[0124] Therefore, when the memory controller 1211 intends to maintain error correction performance, the amount of required cyclic redundancy code and parity information can be reduced accordingly. For example, when the amount of data in the error-related coverage is equal to the total amount of data in the two (2) error-independent coverages, the amount of ECC required to maintain the same error correction performance can be halved in the two error-independent coverages.

[0125] like Figure 11 As shown, with Figure 8 Compared to the previous example, the amount of cyclic redundancy code and the amount of parity information can remain equal. Therefore, the error correction performance of the memory controller 1211 can be improved. When Figure 1 When the memory module 1100 is implemented as a general memory device that includes coverage that does not support error-independent coverage, the RAS (Reliability, Availability, Maintainability) coverage of the memory module 1100 may be a single device data correction (SDDC).

[0126] In other words, as referenced Figure 1 to Figure 11 In the case where the memory module 1100 includes first memory devices 1121 to 1125 and 1131 to 1135 and second memory devices 1126 to 1130 and 1136 to 1140 that are error-independent of each other, the RSA coverage for the error-independent coverage of the memory module 1100 can support more error correction capabilities than SDDC.

[0127] Because the data block is implemented using two error-independent coverages (e.g., because the memory cell is divided into two segments that are independent of each other for row-related errors), the error correction capability of memory module 1100 can be improved. An example of two coverages or two segments is described, but the number of coverages or segments is not limited. As the number of coverages or segments increases, the error correction capability of memory module 1100 can be improved.

[0128] exist Figure 11 An example of performing error correction coding / decoding on an error-independent coverage basis is shown. However, even with error-independent coverage provided, memory controller 1211 can also perform error correction coding / decoding on a data block basis. That is, a data block of the first memory devices 1125 and 1135 for ECC may include eight (8) "cyclic redundancy codes" and eight (8) "parity information".

[0129] Figure 12 This is an overview of an example targeting Figure 1 A flowchart illustrating the operation method of the computing system 1000. (Refer to...) Figure 1 ,Figure 11 and Figure 12 The memory controller 1211 can perform error correction coding on the first data DT1 corresponding to the first part (e.g., half) burst length to generate a first cyclic redundancy code C1 and a first parity check information P1 (S110).

[0130] The memory controller 1211 can perform error correction coding on the second data DT2 corresponding to the second part (e.g., half) burst length to generate a second cyclic redundancy code C2 and a second parity check information P2 (S120).

[0131] The memory controller 1211 can write first data DT1 and second data DT2, which correspond to the first burst length and the second burst length, respectively, into the first memory device (e.g., the first memory devices 1121 to 1124 and 1131 to 1134 for data) (S130).

[0132] The memory controller 1211 can write the first cyclic redundancy code C1, the second cyclic redundancy code C2, the first parity information P1, and the second parity information P2 into the second memory device and the third memory device (e.g., the first memory devices 1125 and 1135 for ECC) (S140).

[0133] Here, the aforementioned steps can be performed during a write operation, during which data is written to the first memory devices 1121 to 1125 and 1131 to 1135 using the first channel CH1. Then, the memory controller 1211 can perform the same type of write operation on the second memory devices 1126 to 1130 and 1136 to 1140 using the second channel CH2. Here, the first write operation and the second write operation associated with the first channel CH1 and the second channel CH2, respectively, can be performed simultaneously and in parallel (e.g., at least partially overlapping in time).

[0134] Figure 13 It is shown that Figure 1 The computing system 1000 can perform a recovery operation (i.e., "recovery") on a faulty memory device, and is a conceptual diagram assuming an error has occurred within a certain coverage area. (See also...) Figure 1 and Figure 13 A fault occurring within a coverage area can be termed a "Type I fault." Therefore, Figure 13 The example can be understood as recovery from a first-type fault.

[0135] In some embodiments, a fault may occur in a first coverage area 1131a of a first memory device 1131, which is one of the first memory devices 1121 to 1124 and 1131 to 1134 for data. The memory controller 1211 may (using, for example, memory mapping) map out the first coverage area 1131a of the first memory device 1131 in which the fault occurs.

[0136] As indicated by the first arrow A1, the memory controller 1211 can select one of the first memory devices 1125 and 1135 for ECC, and can replace the mapped coverage with a coverage of the selected first memory device 1135 for ECC.

[0137] Figure 14 This example outlines recovery after a Type I fault in a memory device used for ECC. Figure 1 A flowchart of the coverage method in the computing system 1000. (Refer to...) Figure 1 , Figure 13 and Figure 14 The memory controller 1211 can read third data from the first memory device (e.g., first memory devices 1121 to 1124 and 1131 to 1134 for data) and can read fourth data from the second and third memory devices (e.g., first memory devices 1125 and 1135 for ECC) (S210).

[0138] The memory controller 1211 can use a portion of the fourth data (e.g., the first cyclic redundancy code C1 and the first parity information P1) to perform error correction decoding (S220) on the data in the third data that corresponds to the burst length of the first portion (e.g., half) of the third data (e.g., the first data DT1).

[0139] The memory controller 1211 can use the remaining portion of the fourth data (e.g., the second cyclic redundancy code C2 and the second parity information P2) to perform error correction decoding (S230) on the data in the third data that corresponds to the burst length of the second portion (e.g., half) of the third data.

[0140] The memory controller 1211 can determine whether a first type of replacement is needed. The first type of replacement can be replacing the coverage of a data block for data with the coverage of a data block for ECC (S240).

[0141] In some embodiments, when reading a data block from memory module 1100 using a specific address ADDR, if errors repeatedly occur within the coverage area of ​​the data block corresponding to the specific location, it can be determined that a fault exists in the memory device corresponding to the specific address ADDR and the coverage area where the error occurred. When a fault is determined to exist within a coverage area, it can be determined that a first type of replacement is required.

[0142] When it is determined that no first type of replacement is needed (S240 = No), the process ends. However, when it is determined that a first type of replacement is needed (S240 = Yes), the memory controller 1211 may allocate a coverage area corresponding to a first portion of the burst length of the second memory device (e.g., the first memory device for ECC selected from the first memory devices 1125 and 1135 for ECC) (S250).

[0143] Figure 15 This is a conceptual diagram illustrating an example of the first type of replacement being performed. (See reference...) Figure 1 , Figure 13 and Figure 15 When the memory controller 1211 accesses the first memory devices 1121 to 1125 and 1131 to 1135 based on the identified faulty address ADDR, the memory controller 1211 can... Figure 15 The data block access memory module 1100 is shown in the figure.

[0144] The first coverage area 1135a of the selected first memory device 1135 for ECC can alternatively transmit the first data DT1 to be written into the memory module 1100 via the mapped coverage area 1131a. That is, the first data DT1 can be written to a portion corresponding to a first burst length (e.g., the first half of the burst length) of the storage space corresponding to address ADDR and belonging to the selected first memory device 1135 for ECC.

[0145] The second coverage area 1135b of the selected data block for the first memory device 1135 for ECC can be retained in a reserved state. That is, data may not be written to the portion corresponding to the second burst length of the storage space (e.g., the latter half of the burst length), which corresponds to address ADDR and belongs to the selected first memory device 1135 for ECC.

[0146] The first coverage area 1125a of the unselected data block for the first memory device 1125 used for ECC may include a first cyclic redundancy code C1 and a second cyclic redundancy code C2. The second coverage area 1125b of the unselected data block for the first memory device 1125 used for ECC may include first parity information P1 and second parity information P2.

[0147] The first cyclic redundancy code C1, the second cyclic redundancy code C2, the first parity check information P1, and the second parity check information P2 can be written into the storage space of the first memory device 1125, which corresponds to the address ADDR and belongs to the unselected ECC device.

[0148] and Figure 13 Compared to data blocks, Figure 15 The number of the first cyclic redundancy code C1, the second cyclic redundancy code C2, the first parity information P1, and the second parity information P2 will be halved. As mentioned above, because the amount of ECC supporting RAS coverage is halved based on error-independent coverage, the data block corresponding to address ADDR after replacement can support SDDC's RAS coverage for error-independent coverage.

[0149] Figure 16 This is a conceptual diagram illustrating an example of recovering a memory device that has experienced a second Type 1 fault. (Refer to...) Figure 1 , Figure 15 and Figure 16 The fault may occur in a first coverage area 1132a of the first memory device 1132, which is another of the first memory devices 1121 to 1124 and 1131 to 1134 used for data. The memory controller 1211 can map the first coverage area 1132a of the first memory device 1132 where the fault occurred from the memory map.

[0150] As indicated by the second arrow A2, the memory controller 1211 may replace the mapped coverage with the reserved coverage of the first memory device 1135 for ECC, which includes the reserved coverage.

[0151] Figure 17 This is an example that outlines the use of Figure 1 A flowchart of a recovery method for a computing system 1000 is provided, wherein coverage of a first-type fault that occurs a second time is recovered using coverage of a memory device used for ECC. (Refer to...) Figure 1 , Figure 16 and Figure 17The memory controller 1211 can read the fifth data from the first memory device (e.g., the first memory devices 1121 to 1124 and 1131 to 1134 for data), read the sixth data from the second memory device (e.g., the selected first memory device 1135 for ECC), and read the seventh data from the third memory device (e.g., the unselected first memory device 1125 for ECC) (S310).

[0152] The memory controller 1211 can use a portion of the 7th data (e.g., the first cyclic redundancy code C1 and the first parity information P1) to perform error correction decoding (S320) on the data corresponding to the first partial burst length of the 5th and 6th data. For example, the memory controller 1211 can use the first cyclic redundancy code C1 and the first parity information P1 to perform error correction decoding on the first data DT1. Then, the memory controller 1211 can use the remaining portion of the 7th data (e.g., the second cyclic redundancy code C2 and the second parity information P2) to perform error correction decoding on the data corresponding to the second partial burst length of the 5th data (S330). For example, the memory controller 1211 can use the second cyclic redundancy code C2 and the second parity information P2 to perform error correction decoding on the second data DT2. In one example, the size of each of the first parity check information P1 and the second parity check information P2 corresponding to the 7th data is smaller than the size of each of the first parity check information P1 corresponding to the first data DT1 and the second parity check information P2 corresponding to the second data DT2, and the size of each of the first cyclic redundancy code C1 and the cyclic redundancy code C2 corresponding to the 7th data is smaller than the size of each of the first cyclic redundancy code C1 corresponding to the first data DT1 and the second cyclic redundancy code C2 corresponding to the second data DT2.

[0153] The memory controller 1211 can determine whether a first type of replacement is needed (S340). When reading a data block from the memory module 1100 using a specific address ADDR, if an error repeatedly occurs within the coverage area of ​​the data block corresponding to the specific location, it can be determined that a fault exists in the memory device corresponding to the specific address ADDR and the coverage area where the error occurred. When a fault is determined to exist within a coverage area, it can be determined that a first type of replacement is needed.

[0154] When it is determined that the first type of replacement is not needed (S340 = No), the process ends. However, when it is determined that the first type of replacement is needed (S340 = Yes), the memory controller 1211 can allocate a coverage area of ​​the second memory device (e.g., a second memory device for the selected ECC) corresponding to the second part of the burst length for the data (S350).

[0155] Figure 18 This is a conceptual diagram illustrating an example of a second execution of the first type of replacement. (See reference...) Figure 1 , Figure 16 and Figure 18 When the memory controller 1211 accesses the first memory devices 1121 to 1125 and 1131 to 1135 based on the identified faulty address ADDR, the memory controller 1211 can... Figure 18 The data block access memory module 1100 is shown in the figure.

[0156] The second coverage area 1135b of the selected data block for the first memory device 1135 for ECC can alternatively transmit the first data DT1 to be written into the memory module 1100 via the mapped coverage area 1132a. That is, the first data DT1 can be written to a portion of the memory space corresponding to address ADDR and belonging to the selected first memory device 1135 for ECC, for example, corresponding to the second burst length.

[0157] The first coverage area 1125a of the unselected data block for the first memory device 1125 used for ECC may include a first cyclic redundancy code C1 and a second cyclic redundancy code C2. The second coverage area 1125b of the unselected data block for the first memory device 1125 used for ECC may include first parity information P1 and second parity information P2.

[0158] For reference Figure 15 As described, after replacement, the data block corresponding to address ADDR can support the RAS coverage of SDDC for error-independent coverage.

[0159] For reference Figure 13 to Figure 15 As described, when a Type I fault first occurs in the memory space corresponding to a specific address ADDR, the memory module 1100 can support the RAS coverage of the SDDC based on error-independent coverage and can support recovery.

[0160] For reference Figure 16 to Figure 18 As described, when a first-type fault occurs a second time in the memory space corresponding to a specific address ADDR, the memory module 1100 can support the RAS coverage of the SDDC based on the error-independent coverage and can support recovery.

[0161] Subsequently, even if the first type of fault occurs for the third time in the memory space corresponding to a specific address ADDR, the memory module 1100 can support the RAS coverage of the SDDC based on the error-independent coverage and can support error correction.

[0162] Regarding references Figure 13 to Figure 18The described embodiments, with reference to the data blocks of the first memory devices 1121 to 1125 and 1131 to 1135 of the first channel CH1, illustrate examples of performing fault detection, replacement, recovery, and error correction. However, this description can also be applied to... Figure 13 to Figure 18 The embodiments and the second memory devices 1126 to 1130 and 1136 to 1140 of the second channel CH2.

[0163] Figure 19 This indicates what happens when an error occurs in a data block. Figure 1 A conceptual diagram illustrating another example of a computing system recovering a failed memory device. (See also...) Figure 1 and Figure 19 A failure occurring within a data block can be a type II failure. Figure 19 The example shown illustrates the first occurrence of the second type of failure.

[0164] In other words, the fault may occur in a data block of the first memory device 1131, which is one of the first memory devices 1121 to 1124 and 1131 to 1134 used for data. The memory controller 1211 can map the faulty data block of the first memory device 1131 from the memory map.

[0165] As indicated by the third arrow A3, the memory controller 1211 can select one of the first memory devices 1125 and 1135 for ECC, and the data block of the selected first memory device 1135 for ECC can replace the mapped data block.

[0166] Figure 20 This is shown in an example. Figure 1 A flowchart illustrating a method for recovering coverage with a second type of fault using the coverage of a memory device for ECC in a computing system 1000. (Refer to...) Figure 1 , Figure 19 and Figure 20 The memory controller 1211 can read third data from the first memory device (e.g., first memory devices 1121 to 1124 and 1131 to 1134 for data) and read fourth data from the second and third memory devices (e.g., first memory devices 1125 and 1135 for ECC) (S410).

[0167] The memory controller 1211 can use a portion of the fourth data (e.g., the first cyclic redundancy code C1 and the first parity information P1) to perform error correction decoding (S420) on the data in the third data that corresponds to the first part of the burst length (e.g., the first data DT1).

[0168] The memory controller 1211 can use the remaining part of the fourth data (e.g., the second cyclic redundancy code C2 and the second parity information P2) to perform error correction decoding on the data in the third data that corresponds to the second part of the burst length (e.g., the second data DT2).

[0169] Then, the memory controller 1211 can determine whether a second type of replacement is needed (S440). The second type of replacement can be replacing a data block for data with a data block for ECC.

[0170] If, when reading a data block from memory module 1100 using a specific address ADDR, an error repeatedly occurs in the data block corresponding to a specific location, it can be determined that a fault exists in the memory device corresponding to the specific address ADDR and the data block where the error occurred. When a fault is determined in a data block, it can be determined that a second type of replacement is required.

[0171] When it is determined that a second type of replacement is not needed (S440 = No), the process ends. However, when it is determined that a second type of replacement is needed (S440 = Yes), the memory controller 1211 may allocate a second memory device for the data (e.g., the first memory device for ECC selected from the first memory devices 1125 and 1135 for ECC) (S450).

[0172] Figure 21 This is a conceptual diagram illustrating an example of performing a second type of replacement. (See reference...) Figure 1 , Figure 19 and Figure 21 When the memory controller 1211 accesses the first memory devices 1121 to 1125 and 1131 to 1135 based on the identified faulty address ADDR, the memory controller 1211 can... Figure 21 The data block access memory module 1100 is shown in the figure.

[0173] The selected data block for the first memory device 1135 for ECC can alternatively transfer the first data DT1 and the second data DT2 to be written into the memory module 1100 via the data block of the mapped first memory device 1131. That is, the first data DT1 and the second data DT2 can be written into the memory space corresponding to the address ADDR and belonging to the selected first memory device 1135 for ECC.

[0174] The first coverage area 1125a of the unselected data block for the first memory device 1125 used for ECC may include a first cyclic redundancy code C1 and a second cyclic redundancy code C2. The second coverage area 1125b of the unselected data block for the first memory device 1125 used for ECC may include first parity information P1 and second parity information P2.

[0175] The first cyclic redundancy code C1, the second cyclic redundancy code C2, the first parity check information P1, and the second parity check information P2 can be written into the storage space of the first memory device 1125 for ECC that corresponds to address ADDR and belongs to the unselected memory device 1125.

[0176] For reference Figure 15 and Figure 18 As described, after replacement, the data block corresponding to address ADDR can support SDDC's RAS coverage for error-independent coverage.

[0177] In relation to Figure 19 to Figure 21 In the described embodiments, examples of performing fault detection, replacement, recovery, and error correction are described with reference to the data blocks of the first memory devices 1121 to 1125 and 1131 to 1135 of the first channel CH1. However, this description can also be applied to the second memory devices 1126 to 1130 and 1136 to 1140 of the second channel CH2.

[0178] Figure 22 It is outlined in an example. Figure 1 A flowchart illustrating the method for training the memory module 1100 in the computing system 1000. (Refer to...) Figure 1 and Figure 22 When the computing system 1000 is powered on (S510), the memory controller 1211 can identify the isolated x4 memory modules and the burst length BL (S520). For example, the memory controller 1211 can receive information from the serial presence detection (SPD) of the memory module 1100 and can identify the isolated x4 memory modules and the burst length BL.

[0179] An isolated x4 memory module can be a memory module that supports [reference] Figure 3 to Figure 8 The described burst length BL refers to two or more error-independent coverage areas (e.g., coverage areas for row-related errors that are error-independent of each other) and is based on a memory device that receives or outputs data DT or ECC via four data signals (x4).

[0180] Then, the memory controller 1211 can begin training (S530). Here, training may include calibrating the transmission and reception timing of the data signal DQ and the data strobe signal DQS.

[0181] The memory controller 1211 can determine whether a device fault is detected (S540). For example, a device fault can be detected when training of at least one of the first memory devices 1121 to the second memory devices 1140 fails.

[0182] When a device malfunction is detected (S540 = Yes), the memory controller 1211 can perform a second type of replacement (S550). For example, as shown in the reference... Figure 19 to Figure 21 The memory controller 1211 can map a fault in the entire memory device. The memory controller 1211 can replace all data blocks of the faulty memory device with a data block from one of the memory devices used for ECC.

[0183] However, when no device malfunction is detected (S540 = No), the memory controller 1211 can complete the training (S560). In one embodiment, mapping and replacement can be performed to make them distinguishable from each other. For example, mapping can be performed during training. Replacement can be performed after training is complete.

[0184] In one example, in response to power-on of a memory module comprising a first memory device, a second memory device, and a third memory device, a first training can be performed on the first memory device, the second memory device, and the third memory device. When a first faulty memory device is detected in the first memory device during the first training, after the first training is completed, the first data is stored in the second memory device and the remaining memory devices in the first memory device excluding the first faulty memory device, and a first error correction code is stored in the third memory device. When no first faulty memory device is detected in the first memory device during the first training, after the first training is completed, the first data is stored in the first memory device, and a second error correction code is stored in the second memory device and the third memory device.

[0185] Optionally, in response to power-on of the memory module, which also includes a fourth, fifth, and sixth memory devices, a second training is performed on the fourth, fifth, and sixth memory devices. When a second faulty memory device is detected in the fourth memory device during the second training, after the second training is completed, the second data is stored in the fifth memory device and the remaining memory devices in the fourth memory device excluding the second faulty memory device, and a third error correction code is stored in the sixth memory device. When no second faulty memory device is detected in the fourth memory device during the second training, after the second training is completed, the second data is stored in the fourth memory device, and a fourth error correction code is stored in the fifth and sixth memory devices.

[0186] As described above, the memory module 1100 according to an embodiment of the inventive concept can support recovery from device malfunctions caused by training failures.

[0187] Figure 23 This is a conceptual diagram illustrating an example of the storage space for the first memory devices 1121 to 1125 and 1131 to 1135. (Refer to...) Figure 1 and Figure 23 Each of the storage spaces in the first memory devices 1121 to 1125 and 1131 to 1135 can correspond to multiple data blocks. Figure 23 In the first memory devices 1121 to 1125 and 1131 to 1135, the storage spaces are marked by thick-lined rectangles, and the data blocks corresponding to the burst length BL and the data signal DQ are marked by thin-lined rectangles.

[0188] Each data block can be implemented using two or more independent coverage areas, as indicated by thin dashed lines. The memory controller 1211 can access the storage space of the first memory devices 1121 to 1125 and 1131 to 1135 in units of data blocks. In some embodiments, the data blocks accessed when the memory controller 1211 accesses (e.g., writes or reads) the storage space of the first memory devices 1121 to 1125 and 1131 to 1135 are marked by thick dashed lines. The data blocks marked by thick dashed lines can correspond to... Figure 11 The data block shown in the image.

[0189] In each of the storage spaces of the first memory devices 1121 to 1125 and 1131 to 1135, replacement can be performed on a block-by-block basis. For example, the first storage space in the storage space of the first memory device 1121 may be normal, and the second storage space in the storage space of the first memory device 1121 may be faulty. When the memory controller 1211 accesses the first storage space of the first memory device 1121, the data block of the first memory device 1121 may include, for example, Figure 11 The first data DT1 and the second data DT2 are shown in the figure.

[0190] When the memory controller 1211 accesses the second storage space of the first memory device 1121, it can be referred to as follows. Figure 15 or Figure 21 One of the data blocks covered by the replacement first memory device 1121.

[0191] Reference Figure 23 The described embodiments can also be applied to the second memory devices 1126 to 1130 and 1136 to 1140 of the second channel CH2.

[0192] In the above embodiments, the location of the data block containing the cyclic redundancy code "C" and parity information "P" was described. However, the location of the cyclic redundancy code "C" and parity information "P" is not limited to the above examples. The order or shape of the cyclic redundancy code "C" and parity information "P" placed in the data block can be randomly determined based on the needs of the external host device 1200.

[0193] In the above embodiments, the terms "first," "second," "third," etc., are used to describe components according to the inventive concept. However, the terms "first," "second," "third," etc., can be used to distinguish components from each other without limiting the inventive concept. For example, the terms "first," "second," "third," etc., do not imply any form of sequential or numerical meaning.

[0194] In the above embodiments, blocks are used to describe components according to embodiments of the inventive concept. These blocks can be implemented using various hardware devices (such as integrated circuits, application-specific integrated circuits (ASCIs), field-programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs), firmware driven in the hardware devices), software (such as applications), or a combination of hardware devices and software. Furthermore, blocks may include circuits implemented using semiconductor elements in integrated circuits or circuits registered as intellectual property (IP).

[0195] According to the inventive concept, the memory device of a semiconductor memory module may include two or more coverages that are accessed in units of data blocks and are error-independent of each other. A method is provided for accessing a semiconductor memory module that supports improved error correction functionality by using data blocks for ECC as backup space for data blocks.

[0196] Although the inventive concept has been described with reference to certain embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the scope of the inventive concept set forth in the claims.

Claims

1. A method for accessing a memory module comprising a plurality of first memory devices, a second memory device, and a third memory device, the method comprising: encoding first data of a first partial burst length to generate first parity information and a first cyclic redundancy code; encoding second data of a second partial burst length to generate second parity information and a second cyclic redundancy code; writing the first data and the second data to the plurality of first memory devices; and writing the first parity information, the first cyclic redundancy code, the second parity information, and the second cyclic redundancy code to the second memory device and the third memory device, wherein the first partial burst length and the second partial burst length form a burst length, wherein each of the plurality of first memory devices, the second memory device, and the third memory device provides a coverage range independent of two or more errors corresponding to the first partial burst length and the second partial burst length for the burst length. The burst length is 16.

2. The method of claim 1, wherein, The first partial burst length is 8 and the second partial burst length is 8.

3. The method of claim 2, wherein, 4. The method of any one of claims 1 to 3, the method further comprising: receiving third data corresponding to the burst length from the plurality of first memory devices; receiving fourth data corresponding to the burst length from the second memory device and the third memory device; decoding a portion of the third data corresponding to the first partial burst length using a portion of the fourth data; and decoding a remaining portion of the third data corresponding to the second partial burst length using a remaining portion of the fourth data.

5. The method of claim 4, the method further comprising: allocating a first region of the second memory device corresponding to the first partial burst length in response to a determination that a first type of replacement is needed. The determination that the first type of replacement is needed is made when an error is detected in a first memory device among the plurality of first memory devices associated with decoding of the portion of the third data and decoding of the remaining portion of the third data and the error is detected a plurality of times at a same location of the first memory device.

6. The method of claim 5, wherein, 7. The method of claim 5, the method further comprising: encoding fifth data of a third partial burst length to generate third parity information and a third cyclic redundancy code; encoding sixth data of a fourth partial burst length to generate fourth parity information and a fourth cyclic redundancy code; writing the fifth data and the sixth data to the plurality of first memory devices and the second memory device; and writing the third parity information, the third cyclic redundancy code, the fourth parity information, and the fourth cyclic redundancy code to the third memory device. each of the third parity information and the fourth parity information is smaller in size than each of the first parity information and the second parity information, and each of the third cyclic redundancy code and the fourth cyclic redundancy code is smaller in size than each of the first cyclic redundancy code and the second cyclic redundancy code.

8. The method of claim 7, wherein, 9. The method of claim 7, the method further comprising: ​ ​ receiving seventh data corresponding to a burst length from the plurality of first memory devices; receiving eighth data corresponding to a first partial burst length from the second memory device; receiving ninth data corresponding to a burst length from the third memory device; decoding a portion of the seventh data corresponding to the first partial burst length and the eighth data using a portion of the ninth data; and decoding a remaining portion of the seventh data corresponding to a second partial burst length using a remaining portion of the ninth data.

10. The method of claim 9, further comprising: allocating a second region of the second memory device corresponding to the second partial burst length in response to a determination that a second type of replacement is needed. the determination that the second type of replacement is needed is made when, after allocating a first region of the second memory device corresponding to the second partial burst length, an error is detected in a first memory device among the plurality of first memory devices in one of decoding a portion of the seventh data corresponding to the first partial burst length and decoding a remaining portion of the seventh data corresponding to the second partial burst length and the error is detected multiple times at the same location in the first memory device.

11. The method of claim 10, wherein, 12. The method of claim 4, further comprising: allocating a first region of the second memory device corresponding to the first partial burst length and a second region of the second memory device corresponding to the second partial burst length in response to a determination that a third type of replacement is needed. the determination that the third type of replacement is needed is made when, in one of decoding a portion of the third data and decoding a remaining portion of the third data, an error is detected in a first memory device among the plurality of first memory devices and the error is detected multiple times at the same location.

13. The method of claim 12, wherein, 14. A method for accessing a memory module including a plurality of first memory devices, a second memory device, and a third memory device, the method comprising: storing data in the plurality of first memory devices; storing a first error correction code in the second memory device and the third memory device; replacing at least a portion of at least one memory device among the plurality of first memory devices with at least a portion of the second memory device when an error occurs in the at least one memory device; after replacing at least a portion of the at least one memory device with at least a portion of the second memory device, storing a second error correction code in the third memory device. the second error correction code supports at least single device data correction of the data. the second memory device and the third memory device are partial regions included in a single memory device.

15. The method of claim 14, wherein, the number of the plurality of first memory devices is 8, 16. The method of claim 14 or claim 15, wherein, each of the plurality of first memory devices, the second memory device, and the third memory device is a double data rate fifth generation synchronous dynamic random access memory, and 17. The method of claim 16, wherein, the memory module is a dual in-line memory module.

18. A method for accessing a memory module including a plurality of first memory devices, a second memory device, and a third memory device, the method comprising: ​ ​ in response to power-up of the memory module, performing first training on the plurality of first memory devices, the second memory device, and the third memory device; when, in the first training, a first faulty memory device is detected among the plurality of first memory devices, after completion of the first training, storing first data in the second memory device and remaining memory devices among the plurality of first memory devices except for the first faulty memory device, and storing a first error correction code in the third memory device; and when, in the first training, no first faulty memory device is detected among the plurality of first memory devices, after completion of the first training, storing the first data in the plurality of first memory devices, and storing a second error correction code in the second memory device and the third memory device.

19. The method of claim 18, wherein, The memory module further includes a fourth memory device, a fifth memory device, and a sixth memory device, and the method further includes: in response to power-up of the memory module, performing second training on the fourth memory device, the fifth memory device, and the sixth memory device; when, in the second training, a second faulty memory device is detected among the fourth memory device, after completion of the second training, storing second data in the fifth memory device and remaining memory devices of the fourth memory device except for the second faulty memory device, and storing a third error correction code in the sixth memory device; and when, in the second training, no second faulty memory device is detected among the fourth memory device, after completion of the second training, storing the second data in the fourth memory device, and storing a fourth error correction code in the fifth memory device and the sixth memory device.

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