Semiconductor components

Abstract

The present invention discloses a semiconductor element, comprising a substrate; a first dielectric layer, disposed on the substrate; a copper wire segment, embedded in the first dielectric layer and extending along a first direction, wherein the copper wire segment comprises a first end, which has a first side wall surface, a second side wall surface and a top surface located between the first side wall surface and the second side wall surface; a second dielectric layer, covering the first dielectric layer and the copper wire segment; and a slit opening, disposed in the second dielectric layer and extending into the first dielectric layer, thereby exposing the top surface, the first side wall surface and the second side wall surface of the copper wire segment.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an improved semiconductor element or semiconductor structure. Background Art

[0002] In the semiconductor manufacturing process below the sub-micron level, the signal transmission delay effect of the wire seriously affects the performance of electronic components. In order to alleviate this problem, the industry generally adopts low-resistance copper wires to replace traditional aluminum wires, and uses low-dielectric constant materials as intermetallic dielectric layers.

[0003] In the backend process of the dual damascene process, contaminants such as copper oxide, particles or polymers that remain after the etching step to form the opening must be removed. In the conventional cleaning step, solvents are often used to remove the contaminants. However, copper loss caused by the cleaning step may cause electrical failure and affect the manufacturing process yield.

[0004] Currently, this field of technology still lacks real-time monitoring technology that can immediately detect copper loss manufacturing process defects after the cleaning step in-line, and requires time-consuming wafer-level chip probing and failure analysis to filter out chips with poor electrical functions. Summary of the invention

[0005] The main purpose of the present invention is to provide an improved semiconductor device and semiconductor structure to solve the deficiencies and shortcomings of the prior art.

[0006] One aspect of the present invention provides a semiconductor element, comprising a substrate having a cutting path area thereon; a monitoring pattern arranged in the cutting path area, wherein the monitoring pattern comprises a copper wire segment embedded in a first dielectric layer and extending along a first direction, wherein the copper wire segment comprises a first end having a first side wall surface, a second side wall surface and a top surface located between the first side wall surface and the second side wall surface; a second dielectric layer covering the first dielectric layer and the copper wire segment; and a slit opening arranged in the second dielectric layer and extending into the first dielectric layer, thereby exposing the top surface, the first side wall surface and the second side wall surface of the copper wire segment.

[0007] According to an embodiment of the present invention, the slit opening extends along a second direction orthogonal to the first direction.

[0008] According to an embodiment of the present invention, the copper wire segment has a second end electrically coupled to an upper electrode plate of a capacitor.

[0009] According to an embodiment of the present invention, the copper wire segment has a second end which is electrically coupled to an inductor.

[0010] According to an embodiment of the present invention, the copper wire segment is a embedded copper wire.

[0011] According to an embodiment of the present invention, the first dielectric layer and the second dielectric layer include an ultra-low dielectric constant dielectric material.

[0012] According to an embodiment of the present invention, a capping layer is disposed between the first dielectric layer and the second dielectric layer.

[0013] According to an embodiment of the present invention, the capping layer includes a nitrogen-carbon doped material layer.

[0014] According to an embodiment of the present invention, the slit opening penetrates the cover layer.

[0015] According to an embodiment of the present invention, one end surface of the copper wire segment is exposed in the slit opening.

[0016] On the other hand, the present invention provides a semiconductor structure, comprising a substrate; a first dielectric layer disposed on the substrate; a copper wire segment embedded in the first dielectric layer and extending along a first direction, wherein the copper wire segment comprises a first end having a first side wall surface, a second side wall surface and a top surface located between the first side wall surface and the second side wall surface; a second dielectric layer covering the first dielectric layer and the copper wire segment; and a slit opening disposed in the second dielectric layer and extending into the first dielectric layer, thereby exposing the top surface, the first side wall surface and the second side wall surface of the copper wire segment.

[0017] According to an embodiment of the present invention, the slit opening extends along a second direction orthogonal to the first direction.

[0018] According to an embodiment of the present invention, the copper wire segment has a second end electrically coupled to an upper electrode plate of a capacitor.

[0019] According to an embodiment of the present invention, the copper wire segment has a second end which is electrically coupled to an inductor.

[0020] According to an embodiment of the present invention, the copper wire segment is a embedded copper wire.

[0021] According to an embodiment of the present invention, the first dielectric layer and the second dielectric layer include an ultra-low dielectric constant dielectric material.

[0022] According to an embodiment of the present invention, a capping layer is disposed between the first dielectric layer and the second dielectric layer.

[0023] According to an embodiment of the present invention, the capping layer includes a nitrogen-carbon doped material layer.

[0024] According to an embodiment of the present invention, the slit opening penetrates the cover layer.

[0025] According to an embodiment of the present invention, one end surface of the copper wire segment is exposed in the slit opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1 to 4 A schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0027] Figure 5 Example with stereoscopic perspective Figure 2 A schematic diagram of the monitoring pattern in the middle cutting lane area;

[0028] Figure 6 The cross-sectional view of a semiconductor structure is shown in another embodiment of the present invention.

[0029] Main component symbols

[0030] 1Semiconductor components

[0031] 100 base

[0032] 110 first dielectric layer

[0033] 112 Covering layer

[0034] 120 second dielectric layer

[0035] 130 pattern layers

[0036] 131 Silicon Oxynitride Layer

[0037] 132Titanium nitride layer

[0038] 133 Silicon Oxynitride Layer

[0039] 140 planarization layer

[0040] 150 copper layers

[0041] CR active circuit area

[0042] SL cutting area

[0043] ML copper interconnect structure

[0044] MS copper wire segment

[0045] MP monitoring pattern

[0046] E1 first end

[0047] E2 second end

[0048] CAS charge accumulation structure

[0049] PR photoresist pattern layer

[0050] PRO-1, PRO-2, PRO-3 opening

[0051] DD double inlay opening

[0052] DT Groove

[0053] DV Mesos

[0054] SO slit opening

[0055] D1 first direction

[0056] D2 Second direction

[0057] S1 first side wall

[0058] S2 Second side wall

[0059] TS top surface

[0060] ES end face DETAILED DESCRIPTION

[0061] In the following, the details will be described with reference to the accompanying drawings, which also constitute a part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0062] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0063] See also Figures 1 to 4 , which is a schematic diagram of a method for manufacturing a semiconductor element according to an embodiment of the present invention. The semiconductor element may be a silicon wafer or an integrated circuit chip. First, Figure 1 As shown, the semiconductor element 1 includes a substrate 100 having a cutting line region SL and an active circuit region CR thereon, wherein the cutting line region SL is adjacent to the active circuit region CR. The substrate 100 may be a semiconductor substrate, such as a silicon substrate, but is not limited thereto. A first dielectric layer 110, such as a low dielectric constant dielectric layer or an ultra-low dielectric constant dielectric layer, is formed on the substrate 100. A cap layer 112 is formed on the first dielectric layer 110. According to an embodiment of the present invention, the cap layer 112 may include a nitrogen-doped carbon material layer, but is not limited thereto.

[0064] According to an embodiment of the present invention, a copper interconnect structure ML is disposed in the first dielectric layer 110 in the active circuit region CR. A copper line segment MS is disposed in the first dielectric layer 110 in the scribe line region SL to form a monitoring pattern MP. Figure 1 In the embodiment, the top surfaces of the copper interconnect structure ML and the copper wire segment MS are covered by the capping layer 112. According to the embodiment of the present invention, the copper interconnect structure ML and the copper wire segment MS may be damascene copper wires.

[0065] According to the embodiment of the present invention, the copper line segment MS in the scribe line region SL includes a first end E1 and a second end E2. According to the embodiment of the present invention, the second end E2 can be electrically coupled to a charge accumulation structure CAS, such as an upper electrode plate of a capacitor or an inductor.

[0066] According to an embodiment of the present invention, a second dielectric layer 120, for example, a low-k dielectric layer or an ultra-low-k dielectric layer, is further formed on the cap layer 112. According to an embodiment of the present invention, a pattern layer 130 has been formed on the second dielectric layer 120, for example, the pattern layer 130 may include a silicon oxynitride layer 131, a titanium nitride layer 132, and a silicon oxynitride layer 133. According to an embodiment of the present invention, a planarization layer 140, for example, a silicon oxide layer or an organic dielectric layer (ODL) may be formed on the pattern layer 130.

[0067] According to an embodiment of the present invention, a photoresist pattern layer PR may be formed on the planarization layer 140. The photoresist pattern layer PR includes openings PRO-1, PRO-2, and PRO-3, wherein the openings PRO-1 and PRO-2 are located in the active circuit region CR and correspond to the underlying copper interconnect structure ML, and the opening PRO-3 is located in the scribe line region SL and corresponds to the underlying copper line segment MS.

[0068] Next, an anisotropic dry etching process is performed to etch down the photoresist pattern layer PR, the planarization layer 140, and the second dielectric layer 120 and the cap layer 112 that are not covered by the pattern layer 130, so that a dual damascene opening DD is formed in the second dielectric layer 120 in the active circuit region CR, including a trench DT and a via DV, and at the same time, a slit opening SO is formed in the second dielectric layer 120 in the scribe line region SL. According to the embodiment of the present invention, the slit opening SO penetrates the cap layer 112.

[0069] After completing the above-mentioned anisotropic dry etching process, a cleaning process can be continued to remove residual contaminants, such as copper oxide, particles or polymers. As mentioned above, solvents are often used to remove contaminants in conventional cleaning steps. However, copper loss in the via DV caused by the cleaning step may cause electrical failure and affect the yield of the manufacturing process. The present invention can realize online immediate monitoring and timely discover copper loss manufacturing process defects after the cleaning step.

[0070] Please also see Figure 5 , which is illustrated in a stereoscopic perspective Figure 2 The monitoring pattern MP in the middle cutting line area SL. Figure 2 and Figure 5 As shown, the monitoring pattern MP is arranged in the cutting line area SL, wherein the monitoring pattern MP includes a copper wire segment MS embedded in the first dielectric layer 110 and extending along a first direction D1, wherein the copper wire segment MS includes a first end E1, which has a first side wall surface S1, a second side wall surface S2 and a top surface TS located between the first side wall surface S1 and the second side wall surface S2. The second dielectric layer 120 covers the first dielectric layer 110 and the copper wire segment MS. The slit opening SO is arranged in the second dielectric layer 120 and extends into the first dielectric layer 110, thereby exposing the top surface TS, the first side wall surface S1 and the second side wall surface S2 of the copper wire segment MS. According to an embodiment of the present invention, the slit opening SO extends along a second direction D2 orthogonal to the first direction D1. According to another embodiment of the present invention, an end surface ES of the copper wire segment MS is exposed in the slit opening SO.

[0071] The main feature of the present invention is that the slit opening SO extends along a second direction D2 orthogonal to the first direction D1, so that the copper wire segment MS can expose the first side wall surface S1, the second side wall surface S2 and the top surface TS of the first end E1. This allows the copper wire segment MS to be inspected at an inclined angle through the slit opening SO in the second direction D2 during electron microscope scanning, thereby realizing online and immediate monitoring of copper loss manufacturing process defects. Moreover, by electrically coupling the second end E2 of the copper wire segment MS to the charge accumulation structure CAS, such as the upper electrode plate of a capacitor or an inductor, the monitoring sensitivity is greatly increased.

[0072] After the monitoring pattern MP in the slit opening SO is inspected by a scanning electron microscope, if no copper loss manufacturing process defect is found, the subsequent manufacturing process steps can be continued, such as Figure 3 As shown, a copper electroplating process is then performed to deposit a copper layer 150 on the entire substrate 100, and the copper layer 150 fills the dual damascene opening DD in the active circuit region CR and the slit opening SO in the scribe line region SL. Of course, before depositing the copper layer 150, a barrier layer or a copper seed layer may be deposited first, which is a well-known technique and will not be described in detail.

[0073] Then, if Figure 4 As shown, the chemical mechanical polishing (CMP) process is continued to polish away the redundant copper layer 150 and the pattern layer 130 on the second dielectric layer 120, thus completing the copper dual damascene process.

[0074] See also Figure 6 , according to another embodiment of the present invention, Figure 5 The semiconductor structure in the embodiment is not necessarily arranged in the cutting path area, but may also be arranged in the active circuit area. Figure 5 and Figure 6 As shown, the semiconductor structure includes a substrate 100; a first dielectric layer 110, disposed on the substrate 100; a copper wire segment MS, embedded in the first dielectric layer 110 and extending along a first direction D1, wherein the copper wire segment MS has a first end E1, which has a first side wall surface S1, a second side wall surface S2 and a top surface TS located between the first side wall surface S1 and the second side wall surface; a second dielectric layer 120, covering the first dielectric layer 110 and the copper wire segment MS; and a slit opening SO, disposed in the second dielectric layer 120 and extending into the first dielectric layer 110, thereby exposing the top surface TS, the first side wall surface S1 and the second side wall surface S2 of the copper wire segment MS.

[0075] According to an embodiment of the present invention, Figure 5 As shown, the slit opening SO extends along a second direction D2 that is orthogonal to the first direction D1.

[0076] According to an embodiment of the present invention, the copper wire segment MS has a second end E2, which can be electrically coupled to a charge accumulation structure CAS, such as an upper electrode plate of a capacitor or an inductor.

[0077] According to the embodiment of the present invention, the copper wire segment MS is a embedded copper wire.

[0078] According to the embodiment of the present invention, the first dielectric layer 110 and the second dielectric layer 120 include an ultra-low dielectric constant dielectric material.

[0079] According to an embodiment of the present invention, a cap layer 112 is disposed between the first dielectric layer 110 and the second dielectric layer 120. According to an embodiment of the present invention, the cap layer 112 includes a nitrogen-doped carbon material layer. According to an embodiment of the present invention, the slit opening SO penetrates the cap layer 112.

[0080] According to an embodiment of the present invention, the end surface ES of the copper wire segment MS is exposed in the slit opening SO. Figure 6As shown, the end surface ES, the first side wall surface S1, the second side wall surface S2 and the top surface TS of the copper wire segment MS are finally covered by the copper layer 150 filled in the slit opening SO. According to another embodiment of the present invention, if the end surface ES of the copper wire segment MS is not exposed, only the first side wall surface S1, the second side wall surface S2 and the top surface TS of the first end E1 of the copper wire segment MS are covered by the copper layer 150 filled in the slit opening SO.

[0081] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device comprising: a substrate having a scribe line region thereon; A monitoring pattern is arranged in the cutting path area, wherein: The monitoring pattern comprises a copper wire segment embedded in the first dielectric layer and extending along a first direction, wherein the copper wire segment comprises a first end, which has a first side wall surface, a second side wall surface, and a top surface located between the first side wall surface and the second side wall surface, and the top surface is located on a side of the first side wall surface and the second side wall surface away from the substrate; a second dielectric layer covering the first dielectric layer and the copper wire segment; a slit opening disposed in the second dielectric layer and extending into the first dielectric layer, thereby exposing the top surface, the first sidewall surface, and the second sidewall surface of the copper wire segment; and The copper layer fills the slit opening and covers the top surface, the first side wall surface and the second side wall surface of the copper line segment.

2. The semiconductor element according to claim 1, wherein The slit opening extends along a second direction orthogonal to the first direction.

3. The semiconductor element according to claim 1, wherein The copper wire segment has a second end that is electrically coupled to an upper electrode plate of the capacitor.

4. The semiconductor element according to claim 1, wherein The copper wire segment has a second end that is electrically coupled to an inductor.

5. The semiconductor device according to claim 1, wherein The copper wire segment is an inlaid copper conductor.

6. The semiconductor device according to claim 1, wherein The first dielectric layer and the second dielectric layer include ultra-low-k dielectric materials.

7. The semiconductor device according to claim 1, wherein A capping layer is disposed between the first dielectric layer and the second dielectric layer.

8. The semiconductor element according to claim 7, wherein The capping layer includes a nitrogen-carbon doped material layer.

9. The semiconductor device according to claim 7, wherein: The slit opening penetrates through the cover layer.

10. The semiconductor device according to claim 1, wherein The end surface of the copper wire segment is exposed in the slit opening.

11. A semiconductor structure comprising: substrate; A first dielectric layer is disposed on the substrate; a copper wire segment embedded in the first dielectric layer and extending along a first direction, wherein: The copper wire segment comprises a first end having a first side wall surface, a second side wall surface, and a top surface located between the first side wall surface and the second side wall surface; a second dielectric layer, covering the first dielectric layer and the copper wire segment; a slit opening, disposed in the second dielectric layer and extending into the first dielectric layer, thereby exposing the top surface, the first side wall surface, and the second side wall surface of the copper wire segment, wherein the top surface is located on a side of the first side wall surface and the second side wall surface away from the substrate; as well as The copper layer fills the slit opening and covers the top surface, the first side wall surface and the second side wall surface of the copper line segment.

12. The semiconductor structure according to claim 11, wherein: The slit opening extends along a second direction orthogonal to the first direction.

13. The semiconductor structure according to claim 11, wherein: The copper wire segment has a second end that is electrically coupled to an upper electrode plate of the capacitor.

14. The semiconductor structure according to claim 11, wherein: The copper wire segment has a second end that is electrically coupled to an inductor.

15. The semiconductor structure according to claim 11, wherein: The copper wire segment is an inlaid copper conductor.

16. The semiconductor structure according to claim 11, wherein: The first dielectric layer and the second dielectric layer include ultra-low dielectric constant dielectric material.

17. The semiconductor structure according to claim 11, wherein: A capping layer is disposed between the first dielectric layer and the second dielectric layer.

18. The semiconductor structure according to claim 17, wherein: The capping layer includes a nitrogen-carbon doped material layer.

19. The semiconductor structure according to claim 17, wherein: The slit opening penetrates through the cover layer.

20. The semiconductor structure of claim 11, wherein: One end surface of the copper wire segment is exposed in the slit opening.

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