Adaptive baseline correction for delta amplification

Abstract

Embodiments of the present disclosure relate to adaptive baseline correction for delta amplification. A data demodulation circuit device includes a sensing circuit that senses a power signal applied to a coil at a first time and a second time, and outputs an analog value representing the voltage difference between the power signal at the first time and the second time. An analog-to-digital converter digitizes the analog value output by the analog voltage differential sensing circuit to generate a digital code. A compensation circuit compares the current value of the digital code with the first value of the digital code during the time period over a period of time, and if the current value is greater than the first value, subtracts a given value from the current value of the digital code, but if the current value is less than the first value, adds the given value to the current value of the digital code. An accumulator accumulates the output of the compensation circuit, and a filter filters the output of the accumulator.

Description

Technical Field

[0001] The present disclosure relates to the field of wireless power transmission, and in particular to hardware, operating techniques for the hardware, and methods for demodulating data modulated onto wireless power transmission. Background Art

[0002] Portable electronic devices, such as smart phones, smart watches, audio output devices (earbuds, headphones), and wearable devices, rely on batteries for power rather than having wired power delivered to them via wired transmission lines and distribution systems. The batteries used in such devices are typically rechargeable, and therefore a method for charging such batteries is necessary.

[0003] Most portable electronic devices include a charging port, typically compliant with the Micro USB or USB-C standard, into which a power cord connected to a power source can be plugged to charge its battery. However, such a charging port may make it difficult to enhance the water resistance of the electronic device and may be easily damaged by repeated use. Additionally, some smaller portable electronic devices (e.g., earbuds and smartwatches) may lack the available space to provide a charging port. Furthermore, some users may find it cumbersome to plug a power cord into the charging port of an electronic device to charge the battery of the device.

[0004] Therefore, to address these issues, wireless power transmission has been developed. A typical wireless power transmission system utilizes a transmitter, formed by a transmission coil driven by time-varying power from a power source, to generate a time-varying electric field, and a receiver, formed by a receiver coil. The time-varying electric field induces an AC current in the receiver coil, which is then rectified and used to drive a load, such as a rechargeable battery.

[0005] It is desirable to enable data communication between a transmitter and a receiver, for example, to achieve a desired or safe amount of power transfer. Typically, data is transmitted from a transmitter to a receiver by modulating the frequency of the power signal flowing through a transmission coil, a technique known as frequency shift keying (FSK). Conversely, data is transmitted from a receiver to a transmitter by modulating its impedance, thereby inducing a measurable electrical change in the power signal at the transmitter coil, a technique known as amplitude shift keying (ASK).

[0006] Typically, in wireless power transfer systems, the transmitter is a single-purpose device (such as a charging pad) and the receiver (such as a smartphone) is placed on the transmitter. For such wireless power transfer along with the accompanying data transmission, well-known arrangements are suitable and efficient.

[0007] However, in some instances, it is desirable to incorporate a wireless power transceiver into a device (such as a smartphone) to allow the device to receive and transmit power wirelessly. Here, additional challenges arise with incorporating data transmission, as typical hardware for demodulating data received via ASK consumes an undesirable amount of space, which is quite limited in certain devices (such as smartphones). Furthermore, typical hardware for demodulating data received via ASK utilizes digital memory and digital filters to process data words containing a large number of bits, which increases costs.

[0008] Therefore, there is a need for further development of ASK demodulation systems, particularly for use in devices incorporating wireless power transceivers. Summary of the Invention

[0009] Disclosed herein is a wireless power transceiver comprising: a transceiver coil having a first terminal and a second terminal; a controlled switching bridge circuit having a first input and a second input coupled to the first terminal and the second terminal of the transceiver coil, the controlled switching bridge circuit also having a first output and a second output, the second output being coupled to ground; a controller configured to generate a control signal for the controlled switching bridge circuit so that the controlled switching bridge circuit generates a time-varying signal across the first input and the second input thereof in a transmitter mode; and an analog voltage differential sensing circuit configured to sense the voltage across the first input and the second output of the controlled switching bridge circuit at a first time and a second time when in the transmitter mode. an analog-to-digital converter configured to digitize the analog value output by the analog voltage differential sensing circuit to generate a digital code; a compensation circuit configured to compare, over a period of time, a current value of the digital code with a first value of the digital code during the time period, and subtract a given value from the current value of the digital code if the current value is greater than the first value, but add the given value to the current value of the digital code if the current value is less than the first value; an accumulator configured to accumulate the output of the compensation circuit; and a filter configured to filter the output of the accumulator.

[0010] The given value can be the number 1.

[0011] The filter may be a bandpass filter.

[0012] The analog voltage differential sensing circuit may include: a first switch coupled between an input and a first node, wherein the first switch is closed when a first control signal is asserted and is open otherwise; a sample / hold capacitor coupled between the first node and ground; a second switch coupled between the first node and a gain capacitor, wherein the second switch is closed when a second control signal is asserted and is open otherwise; an amplifier having a non-inverting terminal coupled to ground, an inverting terminal coupled to the gain capacitor, and an output coupled to an analog-to-digital converter; a feedback capacitor coupled between the non-inverting terminal and the output of the amplifier; and a reset switch coupled in series with the feedback capacitor, wherein the reset switch is closed when a third control signal is asserted and is open otherwise.

[0013] This article also discloses a data demodulation circuit device, including: an analog voltage differential sensing circuit, configured to sense a power signal applied to a coil at a first time and a second time, and output an analog value representing the voltage difference of the power signal at the first time and the second time; an analog-to-digital converter, configured to digitize the analog value output by the analog voltage differential sensing circuit to generate a digital code; a compensation circuit, configured to compare a current value of the digital code with a first value of the digital code during the time period within a period of time, and if the current value is greater than the first value, subtract a given value from the current value of the digital code, but if the current value is less than the first value, add the given value to the current value of the digital code; an accumulator, configured to accumulate the output of the compensation circuit; and a filter, configured to filter the output of the accumulator.

[0014] The given value can be the number 1.

[0015] The filter may be a bandpass filter.

[0016] The analog voltage differential sensing circuit may include: a first switch coupled between an input and a first node, wherein the first switch is closed when a first control signal is asserted and is open otherwise; a sample / hold capacitor coupled between the first node and ground; a second switch coupled between the first node and a gain capacitor, wherein the second switch is closed when a second control signal is asserted and is open otherwise; an amplifier having a non-inverting terminal coupled to ground, an inverting terminal coupled to the gain capacitor, and an output coupled to an analog-to-digital converter; a feedback capacitor coupled between the non-inverting terminal and the output of the amplifier; and a reset switch coupled in series with the feedback capacitor, wherein the reset switch is closed when a third control signal is asserted and is open otherwise.

[0017] The present invention also discloses a wireless power transceiver, comprising: a transceiver coil having a first terminal and a second terminal; a controlled switching bridge circuit having a first input and a second input coupled to the first terminal and the second terminal of the transceiver coil, the controlled switching bridge circuit also having a first output and a second output, the second output being coupled to ground; a voltage regulator coupled between the first output and an output node of the controlled switching bridge circuit; a power supply; a controller configured to: in a receiver mode, generate a control signal for the controlled switching bridge circuit so that the controlled switching bridge circuit rectifies a time-varying signal at its first input and second input, thereby generating a rectified output voltage across its first output and second output, and in a transmitter mode, generate a control signal for the controlled switching bridge circuit so that the controlled switching bridge circuit generates a time-varying signal from the power supply across its first input and second input; a switching circuit device configured to couple the power supply to the output node when the controller is in the receiver mode. point and ground, but when the controller is in transmitter mode, the power supply is coupled between the first output of the controlled switching bridge circuit and the ground; an analog voltage differential sensing circuit, configured to sense the power signal across the first input and the second input of the controlled switching bridge circuit at a first time and a second time when the controller is in transmitter mode, and output an analog value representing the voltage difference of the power signal at the first time and the second time; an analog-to-digital converter, configured to digitize the analog value output by the analog voltage differential sensing circuit to generate a digital code; a compensation circuit, configured to compare a current value of the digital code with a first value of the digital code during the time period over a period of time, and if the current value is greater than the first value, subtract a given value from the current value of the digital code, but if the current value is less than the first value, add the given value to the current value of the digital code; an accumulator, configured to accumulate the output of the compensation circuit; and a filter, configured to filter the output of the accumulator.

[0018] The given value can be the number 1.

[0019] The filter may be a bandpass filter.

[0020] The analog voltage differential sensing circuit may include: a first switch coupled between an input and a first node, wherein the first switch is closed when a first control signal is asserted and is open otherwise; a sample / hold capacitor coupled between the first node and ground; a second switch coupled between the first node and a gain capacitor, wherein the second switch is closed when a second control signal is asserted and is open otherwise; an amplifier having a non-inverting terminal coupled to ground, an inverting terminal coupled to the gain capacitor, and an output coupled to an analog-to-digital converter; a feedback capacitor coupled between the non-inverting terminal and the output of the amplifier; and a reset switch coupled in series with the feedback capacitor, wherein the reset switch is closed when a third control signal is asserted and is open otherwise.

[0021] The present invention also discloses a wireless power transceiver, comprising: a transceiver coil having a first terminal and a second terminal; a controlled switching bridge circuit having a first input and a second input coupled to the first terminal and the second terminal of the transceiver coil, the controlled switching bridge circuit also having a first output and a second output, the second output being coupled to ground; a controller configured to generate a control signal for the controlled switching bridge circuit so that the controlled switching bridge circuit generates a time-varying signal across its first input and second input in a transmitter mode; an analog voltage differential sensing circuit configured to sense a power signal across the first input and the second input of the controlled switching bridge circuit at a first time and a second time when in the transmitter mode, and output an analog value representing a voltage difference of the power signal at the first time and the second time; an analog-to-digital converter configured to digitize the analog value output by the analog voltage differential sensing circuit to generate a digital code, the digital code having a baseline value; and a compensation circuit configured to compensate for drift of the baseline value.

[0022] The compensation circuit may determine the presence of drift by comparing a current value of the digital code to a first value of the digital code during the time period over a period of time, and modifying the digital code based on the comparison to compensate for the drift.

[0023] The analog voltage differential sensing circuit may include: a first switch coupled between an input and a first node, wherein the first switch is closed when a first control signal is asserted and is open otherwise; a sample / hold capacitor coupled between the first node and ground; a second switch coupled between the first node and a gain capacitor, wherein the second switch is closed when a second control signal is asserted and is open otherwise; an amplifier having a non-inverting terminal coupled to ground, an inverting terminal coupled to the gain capacitor, and an output coupled to an analog-to-digital converter; a feedback capacitor coupled between the non-inverting terminal and the output of the amplifier; and a reset switch coupled in series with the feedback capacitor, wherein the reset switch is closed when a third control signal is asserted and is open otherwise.

[0024] The accumulator may be configured to accumulate the output of the compensation circuit.

[0025] The filter may be configured to filter the output of the accumulator.

[0026] Also disclosed herein is a method of operating a wireless power transceiver, comprising: operating a controlled switching bridge to generate a time-varying signal across first and second inputs thereof coupled to first and second terminals of a transceiver coil; sensing the power signal across the first and second inputs of the controlled switching bridge at a first time and a second time, and outputting an analog value representing a voltage difference between the power signal at the first time and the second time; digitizing the analog value to generate a digital code, the digital code having a baseline value; and compensating for drift of the baseline value.

[0027] The baseline value may be determined by comparing the current value of the digital code with the first value of the digital code during the time period over a period of time to determine the presence of drift and modifying the digital code based on the comparison to compensate for drift in the baseline value. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic block diagram of the wireless power transmission system disclosed in this article.

[0029] Figure 2 is with Figure 1 A schematic block diagram of a data demodulation circuit device used in conjunction with a wireless power transmission system.

[0030] Figure 3 It shows Figure 2 Diagram of the operation of the analog voltage differential sensing circuit.

[0031] Figure 4 It shows Figure 2 A diagram of the accumulator output and the data output when the data demodulation circuit apparatus operates without adaptive baseline adjustment.

[0032] Figure 5 It is an explanation Figure 2 Flowchart of the operation of the data demodulation circuit device when performing adaptive baseline adjustment.

[0033] Figure 6 It shows Figure 2 A diagram of the accumulator output when the data demodulation circuit apparatus operates with and without adaptive baseline adjustment.

[0034] Figure 7 is a diagram illustrating how over-adjustment of an adaptive baseline is possible.

[0035] Figure 8 It shows Figure 2 A diagram of the accumulator output and the filter output when the data demodulation circuit apparatus operates with adaptive baseline adjustment. DETAILED DESCRIPTION

[0036] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. Without departing from the spirit and scope of the present disclosure, the general principles described herein can be applied to embodiments and applications other than those described in detail above. The present disclosure is not intended to be limited to the embodiments shown, but rather to the widest scope consistent with the principles and features disclosed or suggested herein.

[0037] Figure 1Shown is a wireless power transfer system 10. The wireless power transfer system 10 includes a first device 11 and a second device 15. The first device 11 can be a device to be wirelessly charged, such as a charging case for a pair of wireless earbuds, and the second device 15 can be a device capable of both wireless power transmission and wireless power reception, such as a smartphone.

[0038] The first device 11 includes: a receiver coil Ls (secondary; capacitor Cs represents the capacitance of the receiver coil), in which a time-varying current is induced by a time-varying electric field; and receiver hardware 12, which rectifies, regulates, and utilizes the time-varying current induced in the receiver coil Ls to power the device 11, for example, to charge its battery.

[0039] The second device 15 includes a controlled switching bridge circuit 16 (operable as a bridge rectifier or a DC-AC inverter) coupled to the transceiver coil Lxcvr at nodes Ac1 and Ac2, where capacitor Cxcvr represents the capacitance of the transceiver coil Lxcvr. The controlled switching bridge circuit 16 includes an n-channel transistor T1 having a source coupled to node Ac1, a drain coupled to node Nin, and a gate coupled to a gate voltage G1; an n-channel transistor T2 having a source coupled to node N, a drain coupled to node Ac2, and a gate coupled to a gate voltage G2; an n-channel transistor T3 having a source coupled to node Ac2, a drain coupled to node Nin, and a gate coupled to a gate voltage G3; and an n-channel transistor T4 having a source coupled to node N, a drain coupled to node Ac1, and a gate coupled to a gate voltage G4. A storage capacitor Ctank is coupled between node Nin and node N. A voltage regulator 17 has an input coupled to node Nin and an output coupled to node Nout. A battery 18 is selectively coupled between node Nout and node N via switch SW1, and selectively coupled between node N and node Nin via switch SW2. Switches SW1 and SW2 operate out of phase with each other; when the second device 15 operates in a power reception mode as a receiver, switch SW1 is closed and switch SW2 is open, wherein circuit 16 functions as an AC-DC rectifier and a regulator for generating a regulated voltage Vreg to charge the battery; and when the second device 15 operates in a power transmission mode as a transmitter, switch SW1 is open and switch SW2 is closed, wherein circuit 16 functions as a DC-AC inverter powered by the battery. A controller 19 generates gate voltages G1 to G4 to control bridge 16 to operate in the desired rectifier / inverter mode.

[0040] When the second device 15 operates as a receiver, the controlled switching bridge circuit 16 rectifies the AC current to generate a DC current, which charges the energy storage capacitor Ctank connected to the node Nin, and the rectified voltage Vrect is formed across the energy storage capacitor Ctank. The voltage regulator 17 generates a regulated output voltage Vreg at its output node Nout, and the output voltage Vreg is provided to the battery 18, thereby charging the battery 18.

[0041] When the second device 15 operates as a transmitter, the voltage of the battery 18 is applied to the node Nin through the switch SW2 and becomes the voltage Vrect. The gate voltages G1 to G4 are then driven by the controller 19 to generate a time-varying current through the transceiver coil Lxcvr. Details of this control scheme can be found in U.S. patent application Ser. No. 16 / 669,068, filed on October 30, 2019, the contents of which are incorporated by reference in their entirety.

[0042] When the second device 15 is operating in power transmission mode, the first device 11 can transmit data to the second device 15 via amplitude shift keying (ASK) by modulating the impedance of the receiver coil Ls. The receiver coil Ls induces a measurable electrical change in the power signal at the transceiver coil Lxcvr via inductive coupling between the receiver coil Ls and the transceiver coil Lxcvr. To achieve this, the first device 11 includes a resistor Rask and a switch Sask connected in series, which are coupled in parallel with the receiver coil Ls. By switching the switch Sask between open and closed positions (by "keying" the switch Sask), the impedance of the receiver coil Ls changes, and in turn, a change is induced in the current and / or voltage of the power signal at the transceiver coil Lxcvr. By demodulating the power signal, the data transmitted from the first device 11 to the second device 15 can be recovered.

[0043] refer to Figure 2Demodulation circuitry 20 within second device 15 for demodulating and digitizing received data symbols will now be described. Demodulation circuitry 20 includes an input IN for receiving an input time-varying signal carrying data symbols encoded using amplitude shift keying (ASK). Switches S1 and S2 and capacitor Cg are connected in series between input node Ac1 and the inverting input terminal of amplifier 21. The non-inverting input terminal of amplifier 21 is coupled to ground. Switch S1 is closed when control signal PHI1 is logic high and open otherwise. Switch S2 is closed when control signal PHI2 is logic high and open otherwise. Sample / hold capacitor Csh is coupled between switches S1 and S2 and ground. Amplifier 21 has a feedback capacitor Cfb coupled between its inverting input and its output, and a reset switch S3 coupled in parallel with feedback capacitor Cfb. Switch D3 is closed when control signal PHI3 is logic high and open otherwise.

[0044] Now additionally refer to Figure 3 In operation, at time T1, when PHI1 is logic high (during which time PHI2 is logic low and PHI3 is logic high), switch S1 is closed, thereby sampling the current voltage of input signal Ac1 across sample-and-hold capacitor Csh. When PHI1 transitions back to logic low to open switch S1, and then PHI2 rises to logic high to close switch S2, the sampled voltage of input signal Ac1 is stored in capacitor Cg due to the series connection of capacitors Csh and Cg. When PHI1 goes high again at time T2 to close switch S1 (at this time, PHI2 is low, so switch S2 is closed), the current voltage of input signal Ac1 is then stored across sample-and-hold capacitor Csh. Therefore, at this point, the current voltage of input signal Ac1 is stored across capacitor Csh, and the previous voltage of input signal Ac1 is stored across capacitor Cg.

[0045] Therefore, between time T2 and T3, when PHI1 transitions to low and PHI2 transitions to high, causing switch S1 to open and switch S2 to close, charge is shared between capacitors Csh and Cg, meaning that the difference between the voltage of input signal Ac1 at time T1 and the voltage of input signal Ac1 at time T2 is stored across capacitors Csh and Cg. Additionally, between time T2 and T3, PHI3 transitions to low to open switch S3, so the difference between the voltage of input signal Ac1 at time T1 and the voltage of input signal Ac1 at time T2 is amplified by amplifier 21 to generate output voltage Vout.

[0046] The analog-to-digital converter 22 digitizes the output voltage Vout output by the amplifier 21, and the resulting digital value is added by the digital adder 23 to the value from the adaptive baseline generating circuit device 24. The output of the digital adder 23 is accumulated by the accumulator loop formed by the digital adder 25 to generate an accumulated digital value Acc, which is then filtered by the bandpass filter 26 to generate output data.

[0047] Ideally, the output Acc of the accumulator 25 changes only according to the value of the data (e.g., the difference between the voltage of the input signal Ac1 at time T1 and the voltage of the input signal Ac1 at time T2). However, problems may arise if the baseline output of the ADC 22 (the output of the ADC 22 when there is no input signal at the input Ac1) drifts due to various possible problems.

[0048] The baseline output of ADC 22 may drift, for example, due to increased leakage across switch S3 as the operating temperature rises, which in turn increases the offset of amplifier 21. This change in the offset of amplifier 21 can, in turn, change the quantization error of ADC 22. Furthermore, when the load of first device 11 changes, the power signal passing through transceiver coil Lxcvr changes, and thus the input signal Ac1 sampled by ADC 22 changes. Furthermore, changes in operating temperature can also change the power signal passing through transceiver coil Lxcvr, which can also change the input signal Ac1 sampled by ADC 22.

[0049] When the baseline drifts, the accumulated digital value Acc also drifts accordingly, which means that the slope of the accumulated digital value Acc increases too much. Figure 4 This potential problem of drifting accumulated digital value Acc is observed in ( Figure 4 (The diagram specifically illustrates an example of an upward baseline drift.) While it is possible to remove the drift from the output data as shown, data will be lost if the drift causes accumulator 25 and / or digital filter 26 to overflow. While the memory size of accumulator 25 can be increased to help prevent this, this increases cost and area consumption and, in addition, means that the memory size of digital filter 26 needs to be increased accordingly.

[0050] Therefore, the digital adder 23 and the adaptive baseline generating circuit 24 are used to adjust the baseline. Figure 5As shown in flowchart 30 of FIGURE 3, the current n-th value of the accumulated digital value Acc is compared with the first accumulated digital value Acc of the period during a period of N samples (block 31). If the difference is positive (block 32), this indicates that the baseline has drifted upward, and then the adaptive baseline generation circuit device 24 performs a correction by subtracting 1 from the output of ADC 22 to add 1 to the baseline, thereby shifting the digital waveform represented by the output of ADC 22 downward (block 33). Conversely, if the difference is negative (block 32), this indicates that the baseline has drifted downward, and then the adaptive baseline generation circuit device 24 performs a correction by adding 1 to the output of ADC 22 to subtract 1 from the baseline, thereby shifting the digital waveform represented by the output of ADC 22 upward (block 34).

[0051] This operation is used to help keep the effective baseline flat and thus keep the accumulated digital value Acc within the memory storage range of the accumulator 25 and the filter 26. These results can be Figure 6 As can be seen in FIG, the accumulated digital value Acc (using the above-mentioned adaptive baseline adjustment) remains approximately flat after sample 400 and varies with the input data, indicating that the baseline is held constant, rather than the accumulated digital value Acc constantly rising (without the above-mentioned adaptive baseline adjustment).

[0052] Note that from Figure 7 As can be seen in , the baseline may be over-adjusted because it is adjusted in increments of 1 or -1, whereas an adjustment between -1 and 1 may be appropriate. To correct this, Figure 8 As shown, a digital filter 26 is used to help further keep the baseline constant and keep the accumulated digital filter output flat.

[0053] While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art having benefit of this disclosure will appreciate that other embodiments can be conceived that do not depart from the scope of the disclosure disclosed herein. Accordingly, the scope of the present disclosure should be limited only by the appended claims.

Claims

1. A wireless power transceiver, comprising: a transceiver coil having a first terminal and a second terminal; a controlled switching bridge circuit having first and second inputs coupled to the first and second terminals of the transceiver coil, the controlled switching bridge circuit also having first and second outputs, the second output coupled to ground; a controller configured to generate a control signal for the controlled switching bridge circuit to cause the controlled switching bridge circuit to generate a time-varying signal in a transmitter mode across a first input and a second input thereof; an analog voltage differential sensing circuit configured to sense a power signal across the first input and the second input of the controlled switching bridge circuit at a first time and a second time when in the transmitter mode, and output an analog value representing a voltage difference of the power signal at the first time and the second time; an analog-to-digital converter configured to digitize the analog value output by the analog voltage differential sensing circuit to generate a digital code; a compensation circuit configured to compare, within a time period, a current value of the digital code with a first value of the digital code during the time period, and subtract a given value from the current value of the digital code if the current value is greater than the first value, and add the given value to the current value of the digital code if the current value is less than the first value; an accumulator configured to accumulate outputs of the compensation circuit; as well as A filter is configured to filter the output of the accumulator. The wireless power transceiver according to claim 1 , wherein the given value is a number 1. . The wireless power transceiver of claim 1 , wherein the filter is a bandpass filter.

4. The wireless power transceiver of claim 1 , wherein the analog voltage differential sensing circuit comprises: a first switch coupled between the input and the first node, wherein the first switch is closed when the first control signal is asserted and is open otherwise; a sample / hold capacitor coupled between the first node and ground; a second switch coupled between the first node and the gain capacitor, wherein the second switch is closed when the second control signal is asserted and is open otherwise; an amplifier having a non-inverting terminal coupled to ground, an inverting terminal coupled to the gain capacitor, and an output coupled to the analog-to-digital converter; a feedback capacitor coupled between the non-inverting terminal and an output of the amplifier; as well as A reset switch is coupled in series with the feedback capacitor, wherein the reset switch is closed when the third control signal is asserted and is open otherwise.

5. A data demodulation circuit comprising: an analog voltage differential sensing circuit configured to sense a power signal applied to the coil at a first time and a second time, and output an analog value representing a voltage difference between the power signal at the first time and the second time; an analog-to-digital converter configured to digitize the analog value output by the analog voltage differential sensing circuit to generate a digital code; a compensation circuit configured to compare, within a time period, a current value of the digital code with a first value of the digital code during the time period, and subtract a given value from the current value of the digital code if the current value is greater than the first value, and add the given value to the current value of the digital code if the current value is less than the first value; an accumulator configured to accumulate outputs of the compensation circuit; as well as A filter is configured to filter the output of the accumulator. The data demodulation circuit according to claim 5 , wherein the given value is digital 1.

7. The data demodulation circuit according to claim 5, wherein the filter is a bandpass filter.

8. The data demodulation circuit according to claim 5, wherein the analog voltage differential sensing circuit comprises: a first switch coupled between the input and the first node, wherein the first switch is closed when the first control signal is asserted and is open otherwise; a sample / hold capacitor coupled between the first node and ground; a second switch coupled between the first node and the gain capacitor, wherein the second switch is closed when the second control signal is asserted and is open otherwise; an amplifier having a non-inverting terminal coupled to ground, an inverting terminal coupled to the gain capacitor, and an output coupled to the analog-to-digital converter; a feedback capacitor coupled between the non-inverting terminal and an output of the amplifier; as well as A reset switch is coupled in series with the feedback capacitor, wherein the reset switch is closed when the third control signal is asserted and is open otherwise.

9. A wireless power transceiver comprising: a transceiver coil having a first terminal and a second terminal; a controlled switching bridge circuit having first and second inputs coupled to the first and second terminals of the transceiver coil, the controlled switching bridge circuit also having first and second outputs, the second output coupled to ground; a voltage regulator coupled between the first output and an output node of the controlled switching bridge circuit; power supply; a controller configured to: in a receiver mode, generate a control signal for the controlled switching bridge circuit to cause the controlled switching bridge circuit to rectify the time-varying signal at its first and second inputs to produce a rectified output voltage across its first and second inputs; and, in a transmitter mode, generating a control signal for the controlled switching bridge circuit to cause the controlled switching bridge circuit to generate a time-varying signal from the power supply across its first and second inputs; a switching circuit arrangement configured to couple the power supply between the output node and ground when the controller is in the receiver mode and to couple the power supply between the first output of the controlled switching bridge circuit and ground when the controller is in the transmitter mode; an analog voltage differential sensing circuit configured to sense a power signal across the first input and the second input of the controlled switching bridge circuit at a first time and a second time when the controller is in the transmitter mode, and output an analog value representing a voltage difference of the power signal at the first time and the second time; an analog-to-digital converter configured to digitize the analog value output by the analog voltage differential sensing circuit to generate a digital code; a compensation circuit configured to compare, within a time period, a current value of the digital code with a first value of the digital code during the time period, and subtract a given value from the current value of the digital code if the current value is greater than the first value, and add the given value to the current value of the digital code if the current value is less than the first value; an accumulator configured to accumulate outputs of the compensation circuit; as well as A filter is configured to filter the output of the accumulator. 10 . The wireless power transceiver of claim 9 , wherein the given value is a number 1. The wireless power transceiver of claim 9 , wherein the filter is a bandpass filter.

12. The wireless power transceiver of claim 9, wherein the analog voltage differential sensing circuit comprises: a first switch coupled between the input and the first node, wherein the first switch is closed when the first control signal is asserted and is open otherwise; a sample / hold capacitor coupled between the first node and ground; a second switch coupled between the first node and the gain capacitor, wherein the second switch is closed when the second control signal is asserted and is open otherwise; an amplifier having a non-inverting terminal coupled to ground, an inverting terminal coupled to the gain capacitor, and an output coupled to the analog-to-digital converter; a feedback capacitor coupled between the non-inverting terminal and an output of the amplifier; as well as A reset switch is coupled in series with the feedback capacitor, wherein the reset switch is closed when the third control signal is asserted and is open otherwise.

13. A wireless power transceiver, comprising: a transceiver coil having a first terminal and a second terminal; a controlled switching bridge circuit having first and second inputs coupled to the first and second terminals of the transceiver coil, the controlled switching bridge circuit also having first and second outputs, the second output coupled to ground; a controller configured to generate a control signal for the controlled switching bridge circuit to cause the controlled switching bridge circuit to generate a time-varying signal in a transmitter mode across a first input and a second input thereof; an analog voltage differential sensing circuit configured to sense a power signal across the first input and the second input of the controlled switching bridge circuit at a first time and a second time when in the transmitter mode, and output an analog value representing a voltage difference of the power signal at the first time and the second time; an analog-to-digital converter configured to digitize the analog value output by the analog voltage differential sensing circuit to generate a digital code, the digital code having a baseline value; as well as The compensation circuit is configured to compensate for drift of the baseline value.

14. The wireless power transceiver of claim 13 , wherein the compensation circuitry compensates for the drift by comparing a current value of the digital code with a first value of the digital code during a time period over a period of time to determine the presence of the drift, and modifying the digital code based on the comparison.

15. The wireless power transceiver of claim 13 , wherein the analog voltage differential sensing circuit comprises: a first switch coupled between the input and the first node, wherein the first switch is closed when the first control signal is asserted and is open otherwise; a sample / hold capacitor coupled between the first node and ground; a second switch coupled between the first node and the gain capacitor, wherein the second switch is closed when the second control signal is asserted and is open otherwise; an amplifier having a non-inverting terminal coupled to ground, an inverting terminal coupled to the gain capacitor, and an output coupled to the analog-to-digital converter; a feedback capacitor coupled between the non-inverting terminal and an output of the amplifier; as well as A reset switch is coupled in series with the feedback capacitor, wherein the reset switch is closed when the third control signal is asserted and is open otherwise.

16. The wireless power transceiver of claim 13, further comprising: an accumulator configured to accumulate outputs of the compensation circuit; as well as A filter is configured to filter the output of the accumulator.

17. A method of operating a wireless power transceiver, comprising: operating a controlled switching bridge to generate a time-varying signal in a transmitter mode across first and second inputs thereof coupled to first and second terminals of a transceiver coil; sensing a power signal across the first input and the second input of the controlled switching bridge at a first time and a second time when the controlled switching bridge is in the transmitter mode, and outputting an analog value representing a voltage difference of the power signal at the first time and the second time; digitizing the analog value to generate a digital code, the digital code having a baseline value; and compensating for drift of the baseline value; The controlled switching bridge further has a first output and a second output, the second output being coupled to ground.

18. The method of claim 17, wherein the baseline value determines the presence of the drift by comparing a current value of the digital code over a time period with a first value of the digital code during the time period, and modifying the digital code based on the comparison to compensate for the drift.

Images