Polar code encoding method, Polar code decoding method and device thereof

Abstract

The embodiment of the present application discloses a polar code encoding method, a polar code decoding method and a device thereof, which are used to reduce the complexity of encoding and decoding. The method of the embodiment of the present application includes: generating an input vector, the input vector includes T sub-blocks, the first information bit on the first sub-block is obtained by copying the second information bit on the second sub-block, wherein the first sub-block and the second sub-block are sub-blocks in the T sub-blocks, the sequence number of the first sub-block is after the sequence number of the second sub-block, and T is an integer greater than or equal to 2; polarization encoding is performed on the input vector to obtain the encoded bit.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a Polar code encoding method, a Polar code decoding method and a device thereof. Background Art

[0002] In the field of communication technology, communication equipment (such as terminal equipment, base station, etc.) can perform channel coding and decoding by means of polar codes. When the decoding end device fails to decode, the encoding end device retransmits to the decoding end device by means of hybrid automatic repeat request (HARQ) to improve system performance.

[0003] At present, the retransmission methods for HARQ mainly include incremental redundancy hybrid automatic repeat request (IR-HARQ) and incremental freezing hybrid automatic repeat request (IF-HARQ). Here, IR-HARQ is used as an example for explanation. In IR-HARQ, the information bits in the sub-blocks transmitted multiple times by the transmitting device have an information coupling relationship. Although this can improve the coding gain and decoding performance, it also increases the complexity of coding and decoding, resulting in high coding and decoding complexity. Summary of the invention

[0004] The embodiments of the present application provide a coding method, a decoding method and a device thereof, which are used to reduce the complexity of coding and decoding.

[0005] A first aspect of an embodiment of the present application provides an encoding method, the method comprising:

[0006] An input vector is generated, where the input vector includes T sub-blocks, where a first information bit on a first sub-block is obtained by copying a second information bit on a second sub-block, where the first sub-block and the second sub-block are sub-blocks in the T sub-blocks, a sequence number of the first sub-block is after a sequence number of the second sub-block, and T is an integer greater than 2 or equal to 2; and polarization coding is performed on the input vector to obtain coded bits.

[0007] In this embodiment, during the encoding process, the first information bit on the first sub-block is obtained by copying the second information bit on the second sub-block, which is equivalent to setting a coupling relationship between the information bit on the first sub-block and the information bit on the second sub-block, so that the first information bit on the first sub-block and the second information bit on the second sub-block have a verification relationship. Then, during the encoding and decoding process, encoding and decoding can be performed according to the coupling relationship between the information bit on the first sub-block and the information bit on the second sub-block, thereby reducing the complexity of encoding and decoding.

[0008] In one possible implementation, the information bit on the first sub-block is copied from the second information bit on the second sub-block according to a mapping relationship, and the mapping relationship includes a mapping relationship between a sub-channel carrying the first information bit in the first sub-block and a sub-channel carrying the second information bit in the second sub-block.

[0009] In this implementation, a method is provided to implement information bit replication through a mapping relationship between sub-channels, so as to implement an information coupling relationship between a first information bit on a first sub-block and a second information bit on a second sub-block.

[0010] In another possible implementation, the method also includes: determining the number of first information bits carried on the first sub-block according to a first code rate allocation table; then, determining the sub-channel sequence number carrying the first information bit on the first sub-block according to a preset first reliability sequence, and the first reliability sequence includes the reliability ranking of the sub-channels of the first sub-block.

[0011] In this possible implementation, a specific method for determining the number of information bits carried on each sub-block and determining the sub-channel for carrying information bits of each sub-block through the reliability sequence of the sub-channel of each sub-block are provided, and a sub-channel with higher reliability is selected for carrying information bits. This is conducive to improving the transmission performance of retransmission.

[0012] In another possible implementation, the method further includes: determining the number of information bits related to the second coupling sub-block carried by the first coupling sub-block according to the second code rate allocation table, the first coupling sub-block and the second coupling sub-block respectively include at least two sub-blocks, the first coupling sub-block is obtained by XORing the encoded bit sequences corresponding to the at least two sub-blocks, and the second coupling sub-block is obtained by XORing the encoded bit sequences corresponding to the at least two sub-blocks. Then, determining the sub-channel sequence number of the information bits related to the second coupling sub-block carried by the first coupling sub-block according to a preset second reliability sequence, the second reliability sequence including the reliability ranking of the sub-channels of the first coupling sub-block.

[0013] In this possible implementation, a method for determining the number of information bits carried on each coupling sub-block is provided, and a sub-channel carrying information bits on each coupling sub-block is determined through a reliability sequence of each coupling sub-block. The coupling sub-block includes at least two sub-blocks, and a sub-channel carrying information bits is selected from the coupling sub-block, so that the reliability of the sub-channel can be compared in a larger range, and a sub-channel with a higher reliability can be selected to carry information bits, which is conducive to improving the transmission performance of retransmission.

[0014] In another possible implementation, the method further includes: determining a subchannel sequence number carrying the first information bit on the first subblock according to a preset third reliability sequence, where the third reliability sequence includes reliability rankings of subchannels of T subblocks.

[0015] In this possible implementation, the subchannels of the T subblocks are sorted by reliability, and the corresponding subchannels on each subblock are selected to carry information bits (for example, subchannels with higher reliability on each subblock are selected), which is conducive to improving the transmission performance of retransmission.

[0016] In another possible implementation, the second sub-block includes a third sub-block, the first information bit on the first sub-block is obtained by copying the information bit on the third sub-block, the first coupling sub-block and the second coupling sub-block include the same third sub-block, and the third sub-block includes a first sub-channel; the method further includes: when the first sub-channel corresponds to multiple reliabilities, determining the reliability of the first sub-channel according to a first preset rule; wherein the first sub-channel corresponds to multiple reliabilities including: the first sub-channel corresponds to a first reliability in the first coupling sub-block, and the first sub-channel corresponds to a second reliability in the second coupling sub-block. Reliability; the first preset rule includes: when the first reliability is greater than or equal to the second reliability, the first reliability is used as the reliability of the first sub-channel; or, when the sequence number sequence of the first coupling sub-block is after the sequence number sequence of the second coupling sub-block, the first reliability is used as the reliability of the first sub-channel; or, when the first reliability is less than or equal to the second reliability, the second reliability is used as the reliability of the first sub-channel; or, when the sequence number sequence of the first coupling sub-block is before the sequence number sequence of the second coupling sub-block, the second reliability is used as the reliability of the first sub-channel.

[0017] In this possible implementation, for a subchannel on a subblock belonging to two different coupled subblocks, when the subchannel has multiple reliabilities, a specific method for determining the reliability of the subchannel is provided, which is conducive to the implementation of the solution and improves the integrity of the solution.

[0018] In another possible implementation, the second sub-block includes a fourth sub-block and a fifth sub-block, the first information bit on the first sub-block is copied from the information bit on the fourth sub-block and the information bit on the fifth sub-block, the first reliability sequence is used to indicate the reliability ranking of the sub-channels of each sub-block, the fourth sub-block includes the second sub-channel, and the fifth sub-block includes the third sub-channel; the method further includes: when the second sub-channel and the third sub-channel have the same reliability, determining the reliability of the second sub-channel and the reliability of the third sub-channel according to a second preset rule; wherein In the embodiment, the second subchannel and the third subchannel have the same reliability, which includes: the second subchannel corresponds to the third reliability in the first reliability sequence, and the third subchannel corresponds to the third reliability in the first reliability sequence; the second preset rule includes: when the sequence number sequence of the fourth subblock is after the sequence number sequence of the fifth subblock, determining that the reliability of the second subchannel is greater than the reliability of the third subchannel; or, when the sequence number sequence of the fourth subblock is before the sequence number sequence of the fifth subblock, determining that the reliability of the third subchannel is greater than the reliability of the second subchannel.

[0019] In this possible implementation, for the case where multiple sub-channels have the same reliability, a method for determining the reliability of the multiple sub-channels is provided. For example, when selecting one of the multiple sub-channels, the sub-channel with the highest reliability can be selected and information bits can be replicated. Then the reliability of the multiple sub-channels can be determined by this implementation, thereby improving the feasibility and integrity of the solution.

[0020] In another possible implementation, the second sub-block includes M sub-blocks adjacent to the first sub-block, or the second sub-block includes M sub-blocks non-adjacent to the first sub-block, where M is an integer greater than or equal to 1 and less than T-1.

[0021] In this possible implementation, the degree of information coupling between sub-blocks is configurable, and a flexible trade-off can be made based on the complexity of encoding and decoding and the performance gain; and two sub-blocks with an information coupling relationship can be adjacent or non-adjacent, which can be set according to actual needs, which is conducive to improving the transmission performance of retransmission.

[0022] In another possible implementation, the method further includes: determining M sub-blocks according to a preset mapping sequence, the first information bit on the first sub-block being directly copied from the information bits on the M sub-blocks, and the mapping sequence is used to indicate a mapping relationship between the T sub-blocks.

[0023] In this possible implementation, a specific method for determining the M sub-blocks is provided, which is implemented through a preset mapping sequence, which is conducive to the execution and implementation of the solution.

[0024] In another possible implementation, when T=8, the mapping relationship includes:

[0025] There is a mapping relationship between the first sub-block and the second sub-block;

[0026] There is a mapping relationship between the second sub-block and the third sub-block;

[0027] There is a mapping relationship between the first sub-block and the fourth sub-block;

[0028] There is a mapping relationship between the 1st sub-block and the 5th sub-block;

[0029] There is a mapping relationship between the 1st sub-block and the 6th sub-block;

[0030] There is a mapping relationship between the 1st sub-block and the 7th sub-block;

[0031] There is a mapping relationship between the 1st sub-block and the 8th sub-block;

[0032] or,

[0033] The mapping sequence of the T sub-blocks includes:

[0034] There is a mapping relationship between the first sub-block and the second sub-block;

[0035] There is a mapping relationship between the second sub-block and the third sub-block;

[0036] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0037] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0038] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0039] There is a mapping relationship between the 7th sub-block and the 8th sub-block;

[0040] or,

[0041] The mapping sequence of the T sub-blocks includes:

[0042] There is a mapping relationship between the first sub-block and the second sub-block;

[0043] There is a mapping relationship between the second sub-block and the third sub-block;

[0044] There is a mapping relationship between the 3rd sub-block and the 4th sub-block;

[0045] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0046] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0047] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0048] There is a mapping relationship between the 7th sub-block and the 8th sub-block;

[0049] or,

[0050] The mapping sequence of the T sub-blocks includes:

[0051] There is a mapping relationship between the first sub-block and the second sub-block;

[0052] There is a mapping relationship between the second sub-block and the third sub-block;

[0053] There is a mapping relationship between the first sub-block and the fourth sub-block;

[0054] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0055] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0056] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0057] There is a mapping relationship between the 7th sub-block and the 8th sub-block.

[0058] In another possible implementation manner, performing polarization coding on the input vector to obtain coded bits includes:

[0059] Performing polarization encoding on the input vector using a first generator matrix;

[0060] Among them, the first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes at least two matrix blocks distributed according to a preset position relationship, the matrix block includes multiple first generating matrix cores, the first generating matrix includes A matrix blocks, the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, and A is a positive integer.

[0061] In the implementation, a codeword coupling degree is set by a first generation matrix. Combined with the above first aspect, the embodiment of the present application provides a flexible code construction framework. In the code construction process, appropriate information coupling and codeword coupling can be set to obtain performance gains similar to IR-HARQ, providing a flexible compromise between the complexity of encoding and decoding and performance gain. A smaller information coupling degree can be set to save hardware overhead and avoid complex switching networks due to information replication processes.

[0062] In another possible implementation manner, the code length of each sub-block in the T sub-blocks is the same as the dimension of the first generator matrix kernel.

[0063] In another possible implementation manner, the positional relationship between two adjacent matrix blocks in the A matrix blocks is the same as the preset positional relationship.

[0064] In another possible implementation manner, there is an overlapping portion between the at least two matrix blocks.

[0065] In this implementation, since there is an overlapped portion between the two matrix sub-blocks, it is possible to implement a codeword coupling relationship for different sub-blocks.

[0066] In another possible implementation manner, the first diagonal line of the matrix block includes the first generation matrix kernel.

[0067] In another possible implementation, the plurality of first generation matrix cores in the matrix block are distributed in a lower triangle.

[0068] In another possible implementation, the distribution of the first generation matrix core in the matrix block is the same as the distribution of the first element in the second generation matrix core, the number of elements included in the second generation matrix core is the same as the number of matrix units included in the matrix block, and the matrix units included in the matrix block are the first generation matrix core or 0 matrix.

[0069] In the above process, since the distribution of the first generation matrix core in the matrix block is the same as the distribution of the first element in the second generation matrix core, the codeword coupling relationship between the sub-blocks is similar to the existing encoding method, so that the encoding complexity is low.

[0070] In another possible implementation manner, performing polarization coding on the input vector to obtain coded bits includes:

[0071] Performing polarization encoding on the input vector using a first generator matrix;

[0072] The first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes a first submatrix block located at the upper left corner of the second submatrix block, the second submatrix block is located at the lower right corner of the first generating matrix, the first submatrix block and the second submatrix block are the same, along the diagonal direction of the second generating matrix, the distance between the first element in the first submatrix block and the second element in the second submatrix block is u, and u is an integer greater than or equal to 1; the first generating matrix includes A second generating matrices, the A second generating matrices are distributed along the diagonal of the second generating matrix (for example, the diagonal can be the main diagonal), the first submatrix block of the b+1th second generating matrix among the A second generating matrices coincides with the second submatrix block of the bth second generating matrix, b is an integer greater than or equal to 1, and T is an integer greater than or equal to 2.

[0073] In this implementation, a codeword coupling degree is set by a first generation matrix. Combined with the third aspect above, the embodiment of the present application provides a flexible code construction framework. In the code construction process, appropriate information coupling and codeword coupling can be set to obtain performance gains similar to IR-HARQ, providing a flexible compromise between the complexity of encoding and decoding and performance gain. A smaller information coupling degree can be set to save hardware overhead and avoid complex switching networks due to information replication processes.

[0074] In another possible implementation manner, there are no overlapping elements in the first sub-matrix block and the second sub-matrix block.

[0075] In another possible implementation, the size of the second generator matrix is ​​v*v, and the elements in the second generator matrix satisfy: a i,j =a i+u,j+u , where i is an integer, j is an integer, v is a positive integer, u is an integer, 1≤i <v,1≤j<v,1<i+u≤v,1<j+u≤v。

[0076] In this possible implementation, the second generator matrix satisfies a i,j =a i+u,j+u When the second generation matrix satisfies self-similarity, the codeword coupling degree can be set by the first generation matrix. In the code construction process, appropriate information coupling degree and codeword coupling degree can be set to obtain performance gain similar to IR-HARQ, providing a flexible trade-off between the complexity of encoding and decoding and performance gain.

[0077] In another possible implementation, the elements of the second generation matrix are symmetric along the secondary diagonal of the second generation matrix. From this implementation, it can be seen that the elements of the second generation matrix are symmetric along the secondary diagonal of the second generation matrix, so that the encoding complexity is low.

[0078] In another possible implementation, A is a minimum integer that satisfies a first condition, which is that a size of the first generator matrix is ​​greater than or equal to a code length M of T sub-blocks included in the input vector.

[0079] In another possible implementation, A satisfies the following relationship:

[0080] v+(A-2)*u <M≤v+(A-1)*u;

[0081] Wherein, v is the size of the second generation matrix, M is the code length M of the T sub-blocks included in the input vector, and M is an integer greater than 1.

[0082] A second aspect of an embodiment of the present application provides a decoding method, the method comprising:

[0083] Receive bit information to be decoded, where the bit information to be decoded includes bit information of a first sub-block and bit information of a second sub-block, where the bits on the first sub-block are copied from the bits on the second sub-block, and a sequence number of the second sub-block is after a sequence number of the first sub-block; then, perform polarization decoding according to the bit information to be decoded to obtain polarization-decoded bits.

[0084] In this embodiment, since the bits on the first sub-block are obtained by copying the bits on the second sub-block, it is equivalent to setting an information coupling relationship between the bits on the first sub-block and the bits on the second sub-block, so that there is a verification relationship between the bits on the first sub-block and the bits on the second sub-block. Then, in the decoding process, decoding can be performed according to the information coupling relationship between the bits on the first sub-block and the bits on the second sub-block, thereby reducing the complexity of encoding and decoding.

[0085] In one possible implementation, the bits on the first sub-block are obtained by copying the bits on the second sub-block, including: the first information bits on the first sub-block are copied from the second information bits on the second sub-block according to a mapping relationship, and the mapping relationship includes a mapping relationship between the sub-channel carrying the first information bit in the first sub-block and the sub-channel carrying the second information bit in the second sub-block.

[0086] In this possible implementation, a method is provided for implementing information bit replication through a mapping relationship between sub-channels, so as to implement an information coupling relationship between a first information bit on a first sub-block and a second information bit on a second sub-block.

[0087] In another possible implementation, performing polarization decoding on the bit information to be decoded to obtain polarization-decoded bits includes: performing polarization decoding on the bit information to be decoded according to a first generation matrix and a mapping relationship to obtain polarization-decoded bits;

[0088] Among them, the first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes at least two matrix blocks distributed according to a preset position relationship, the matrix block includes multiple first generating matrix cores, the first generating matrix includes A matrix blocks, the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, A is a positive integer, the mapping relationship includes a mapping relationship between the sub-channel carrying the first information bit on the first sub-block and the sub-channel carrying the second information bit on the second sub-block, and T is an integer greater than or equal to 2.

[0089] In the implementation, a codeword coupling degree is set by a first generation matrix. Combined with the above-mentioned first aspect, the embodiment of the present application provides a flexible code construction framework. In the code construction process, appropriate information coupling degree and codeword coupling degree can be set to obtain performance gain similar to IR-HARQ, providing a flexible compromise between the complexity of encoding and decoding and performance gain. Accordingly, in the decoding process, polarization decoding is performed in combination with the first generation matrix and the mapping relationship.

[0090] In another possible implementation manner, the bit information to be decoded includes Q first log-likelihood ratios (LLRs), where Q is a positive integer.

[0091] In another possible implementation, the Q first LLRs include P first LLR sequences, the first LLR sequence includes at least two first LLRs, and P is an integer greater than or equal to 2; performing polarization decoding on the bit information to be decoded according to the first generation matrix and the mapping relationship to obtain the polarization-decoded bits includes: determining P second LLR sequences corresponding to the P first LLR sequences, one first LLR sequence corresponds to one sub-block, and one second LLR sequence corresponds to one sub-block; according to the P second LLR sequence LR sequence, determine to obtain a codeword decoding result of the P-th sub-block and an information decoding result of the P-th sub-block; determine the codeword decoding result of the ith sub-block and the information decoding result of the ith sub-block according to the codeword decoding result of at least one sub-block from the codeword decoding result of the i+1-th sub-block to the codeword decoding result of the P-th sub-block, the information decoding result of at least one sub-block from the information decoding result of the i+1-th sub-block to the information decoding result of the P-th sub-block, and the ith second LLR sequence, where i is an integer between 1 and P-1.

[0092] In this possible implementation, based on the code construction framework in the embodiment of the present application, during the code construction process, appropriate information coupling and codeword coupling can be set. Therefore, during the decoding process, the information decoding results and codeword decoding results of other sub-blocks can be combined to assist the information decoding of the current sub-block, thereby reducing the complexity of decoding.

[0093] In another possible implementation manner, the positional relationship between two adjacent matrix blocks in the A matrix blocks is the same as the preset positional relationship.

[0094] In another possible implementation, performing polarization decoding on the bit information to be decoded to obtain polarization-decoded bits includes: performing polarization decoding on the bit information to be decoded according to a first generation matrix and a mapping relationship to obtain polarization-decoded bits;

[0095] The first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes a first submatrix block located at the upper left corner of the second submatrix block, the second submatrix block is located at the lower right corner of the first generating matrix, the first submatrix block and the second submatrix block are the same, along the diagonal direction of the second generating matrix, the distance between the first element in the first submatrix block and the second element in the second submatrix block is u, and u is an integer greater than or equal to 1; the first generating matrix includes A second generating matrices, the A second generating matrices are distributed along the diagonal of the second generating matrix (for example, the diagonal can be the main diagonal), the first submatrix block of the b+1th second generating matrix in the A second generating matrices overlaps with the second submatrix block of the bth second generating matrix, b is an integer greater than or equal to 1, and T is an integer greater than or equal to 2; the mapping relationship includes a mapping relationship between a subchannel carrying a first information bit on the first subblock and a subchannel carrying a second information bit on the second subblock, and T is an integer greater than or equal to 2.

[0096] In the implementation, a codeword coupling degree is set by a first generation matrix. Combined with the third aspect above, the embodiment of the present application provides a flexible code construction framework. In the code construction process, appropriate information coupling degree and codeword coupling degree can be set to obtain performance gain similar to IR-HARQ, providing a flexible compromise between the complexity of encoding and decoding and performance gain. Accordingly, in the decoding process, polarization decoding is performed in combination with the first generation matrix and the mapping relationship.

[0097] A third aspect of an embodiment of the present application provides a coding device, the coding device comprising:

[0098] A generating unit, configured to generate an input vector, the input vector comprising T sub-blocks, a first information bit on a first sub-block being obtained by copying a second information bit on a second sub-block, wherein the first sub-block and the second sub-block are sub-blocks in the T sub-blocks, a sequence number of the first sub-block is subsequent to a sequence number of the second sub-block, and T is an integer greater than or equal to 2;

[0099] The encoding unit is used to perform polarization encoding on the input vector to obtain encoded bits.

[0100] In one possible implementation, the information bit on the first sub-block is copied from the second information bit on the second sub-block according to a mapping relationship, and the mapping relationship includes a mapping relationship between a sub-channel carrying the first information bit in the first sub-block and a sub-channel carrying the second information bit in the second sub-block.

[0101] In another possible implementation, the encoding device further includes a determining unit;

[0102] The determination unit is used to determine the number of first information bits carried on the first sub-block according to the first code rate allocation table; determine the sub-channel sequence number carrying the first information bit on the first sub-block according to a preset first reliability sequence, and the first reliability sequence includes the reliability ranking of the sub-channels of the first sub-block.

[0103] In another possible implementation, the encoding device further includes a determining unit;

[0104] The determination unit is used to determine the number of information bits related to the second coupling sub-block carried by the first coupling sub-block according to the second code rate allocation table, the first coupling sub-block and the second coupling sub-block respectively include at least two sub-blocks, the first coupling sub-block is obtained by XORing the encoded bit sequences corresponding to the at least two sub-blocks, and the second coupling sub-block is obtained by XORing the encoded bit sequences corresponding to the at least two sub-blocks; determine the sub-channel sequence number of the information bits related to the second coupling sub-block carried by the first coupling sub-block according to a preset second reliability sequence, and the second reliability sequence includes the reliability ranking of the sub-channels of the first coupling sub-block.

[0105] In another possible implementation, the encoding device further includes a determining unit;

[0106] The determination unit is used to determine the subchannel sequence number carrying the first information bit on the first subblock according to a preset third reliability sequence, and the third reliability sequence includes the reliability ranking of the subchannels of T subblocks.

[0107] In another possible implementation manner, the second sub-block includes a third sub-block, the first information bit on the first sub-block is obtained by copying the information bit on the third sub-block, the first coupling sub-block and the second coupling sub-block include the same third sub-block, and the third sub-block includes the first sub-channel; and the determining unit is further used to:

[0108] When the first subchannel corresponds to multiple reliabilities, determining the reliability of the first subchannel according to a first preset rule;

[0109] Among them, the first subchannel corresponds to multiple reliabilities, including: the first subchannel corresponds to a first reliability in the first coupling sub-block, and the first subchannel corresponds to a second reliability in the second coupling sub-block; the first preset rule includes: when the first reliability is greater than or equal to the second reliability, the first reliability is used as the reliability of the first sub-channel; or, when the sequence number sequence of the first coupling sub-block is after the sequence number sequence of the second coupling sub-block, the first reliability is used as the reliability of the first sub-channel; or, when the first reliability is less than or equal to the second reliability, the second reliability is used as the reliability of the first sub-channel; or, when the sequence number sequence of the first coupling sub-block is before the sequence number sequence of the second coupling sub-block, the second reliability is used as the reliability of the first sub-channel.

[0110] In another possible implementation, the second sub-block includes a fourth sub-block and a fifth sub-block, the first information bit on the first sub-block is copied from the information bit on the fourth sub-block and the information bit on the fifth sub-block, the first reliability sequence is used to indicate the reliability ranking of the sub-channels of each sub-block, the fourth sub-block includes the second sub-channel, and the fifth sub-block includes the third sub-channel; the determining unit is further used to:

[0111] When the second sub-channel and the third sub-channel have the same reliability, determining the reliability of the second sub-channel and the reliability of the third sub-channel according to a second preset rule;

[0112] Among them, the second subchannel and the third subchannel have the same reliability, which includes: the second subchannel corresponds to the third reliability in the first reliability sequence, and the third subchannel corresponds to the third reliability in the first reliability sequence; the second preset rule includes: when the sequence number sequence of the fourth subblock is after the sequence number sequence of the fifth subblock, determining that the reliability of the second subchannel is greater than the reliability of the third subchannel; or, when the sequence number sequence of the fourth subblock is before the sequence number sequence of the fifth subblock, determining that the reliability of the third subchannel is greater than the reliability of the second subchannel.

[0113] In another possible implementation, the second sub-block includes M sub-blocks adjacent to the first sub-block, or the second sub-block includes M sub-blocks non-adjacent to the first sub-block, where M is an integer greater than or equal to 1 and less than T-1.

[0114] In another possible implementation, the determining unit is further configured to:

[0115] The M sub-blocks are determined according to a preset mapping sequence, the first information bit on the first sub-block is directly copied from the information bits on the M sub-blocks, and the mapping sequence is used to indicate a mapping relationship between the T sub-blocks.

[0116] In another possible implementation, when T=8, the mapping relationship includes:

[0117] There is a mapping relationship between the first sub-block and the second sub-block;

[0118] There is a mapping relationship between the second sub-block and the third sub-block;

[0119] There is a mapping relationship between the first sub-block and the fourth sub-block;

[0120] There is a mapping relationship between the 1st sub-block and the 5th sub-block;

[0121] There is a mapping relationship between the 1st sub-block and the 6th sub-block;

[0122] There is a mapping relationship between the 1st sub-block and the 7th sub-block;

[0123] There is a mapping relationship between the 1st sub-block and the 8th sub-block;

[0124] or,

[0125] The mapping sequence of the T sub-blocks includes:

[0126] There is a mapping relationship between the first sub-block and the second sub-block;

[0127] There is a mapping relationship between the second sub-block and the third sub-block;

[0128] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0129] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0130] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0131] There is a mapping relationship between the 7th sub-block and the 8th sub-block;

[0132] or,

[0133] The mapping sequence of the T sub-blocks includes:

[0134] There is a mapping relationship between the first sub-block and the second sub-block;

[0135] There is a mapping relationship between the second sub-block and the third sub-block;

[0136] There is a mapping relationship between the 3rd sub-block and the 4th sub-block;

[0137] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0138] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0139] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0140] There is a mapping relationship between the 7th sub-block and the 8th sub-block;

[0141] or,

[0142] The mapping sequence of the T sub-blocks includes:

[0143] There is a mapping relationship between the first sub-block and the second sub-block;

[0144] There is a mapping relationship between the second sub-block and the third sub-block;

[0145] There is a mapping relationship between the first sub-block and the fourth sub-block;

[0146] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0147] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0148] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0149] There is a mapping relationship between the 7th sub-block and the 8th sub-block.

[0150] In another possible implementation, the encoding unit is specifically used for:

[0151] Performing polarization encoding on the input vector using a first generator matrix;

[0152] Among them, the first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes at least two matrix blocks distributed according to a preset position relationship, the matrix block includes multiple first generating matrix cores, the first generating matrix includes A matrix blocks, the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, and A is a positive integer.

[0153] In another possible implementation manner, the code length of each sub-block in the T sub-blocks is the same as the dimension of the first generator matrix kernel.

[0154] In another possible implementation manner, the positional relationship between two adjacent matrix blocks in the A matrix blocks is the same as the preset positional relationship.

[0155] In another possible implementation manner, there is an overlapping portion between the at least two matrix blocks.

[0156] In another possible implementation manner, the first diagonal line of the matrix block includes the first generation matrix kernel.

[0157] In another possible implementation, the plurality of first generation matrix cores in the matrix block are distributed in a lower triangle.

[0158] In another possible implementation, the distribution of the first generation matrix core in the matrix block is the same as the distribution of the first element in the second generation matrix core, the number of elements included in the second generation matrix core is the same as the number of matrix units included in the matrix block, and the matrix units included in the matrix block are the first generation matrix core or 0 matrix.

[0159] In another possible implementation, the encoding unit is specifically used for:

[0160] Performing polarization encoding on the input vector using a first generator matrix;

[0161] The first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes a first submatrix block located at the upper left corner of the second submatrix block, the second submatrix block is located at the lower right corner of the first generating matrix, the first submatrix block and the second submatrix block are the same, along the diagonal direction of the second generating matrix, the distance between the first element in the first submatrix block and the second element in the second submatrix block is u, and u is an integer greater than or equal to 1; the first generating matrix includes A second generating matrices, the A second generating matrices are distributed along the diagonal of the second generating matrix (for example, the diagonal can be the main diagonal), the first submatrix block of the b+1th second generating matrix among the A second generating matrices coincides with the second submatrix block of the bth second generating matrix, b is an integer greater than or equal to 1, and T is an integer greater than or equal to 2.

[0162] In another possible implementation manner, there are no overlapping elements in the first sub-matrix block and the second sub-matrix block.

[0163] In another possible implementation, the size of the second generator matrix is ​​v*v, and the elements in the second generator matrix satisfy: a i,j =a i+u,j+u , where i is an integer, j is an integer, v is a positive integer, u is an integer, 1≤i <v,1≤j<v,1<i+u≤v,1<j+u≤v。

[0164] In another possible implementation manner, the elements of the second generation matrix are symmetric along a secondary diagonal line of the second generation matrix.

[0165] In another possible implementation, A is a minimum integer that satisfies a first condition, which is that a size of the first generator matrix is ​​greater than or equal to a code length M of T sub-blocks included in the input vector.

[0166] In another possible implementation, A satisfies the following relationship:

[0167] v+(A-2)*u <M≤v+(A-1)*u;

[0168] Wherein, v is the size of the second generation matrix, M is the code length M of the T sub-blocks included in the input vector, and M is an integer greater than 1.

[0169] A fourth aspect of the present application provides a decoding device, the decoding device comprising:

[0170] A receiving unit, configured to receive bit information to be decoded, the bit information to be decoded comprising bit information of a first sub-block and bit information of a second sub-block, the bits on the first sub-block are copied from the bits on the second sub-block, and the sequence number of the second sub-block is subsequent to the sequence number of the first sub-block;

[0171] The decoding unit is used to perform polarization decoding according to the bit information to be decoded to obtain polarization-decoded bits.

[0172] In one possible implementation, the bits on the first sub-block are obtained by copying the bits on the second sub-block, including: the first information bits on the first sub-block are copied from the second information bits on the second sub-block according to a mapping relationship, and the mapping relationship includes a mapping relationship between the sub-channel carrying the first information bit in the first sub-block and the sub-channel carrying the second information bit in the second sub-block.

[0173] In another possible implementation, the decoding unit is specifically used for:

[0174] Performing polarization decoding on the bit information to be decoded according to the first generation matrix and the mapping relationship to obtain polarization-decoded bits;

[0175] Among them, the first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes at least two matrix blocks distributed according to a preset position relationship, the matrix block includes multiple first generating matrix cores, the first generating matrix includes A matrix blocks, the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, A is a positive integer, the mapping relationship includes a mapping relationship between the sub-channel carrying the first information bit on the first sub-block and the sub-channel carrying the second information bit on the second sub-block, and T is an integer greater than or equal to 2.

[0176] In another possible implementation manner, the bit information to be decoded includes Q first log-likelihood ratios (LLRs), where Q is a positive integer.

[0177] In another possible implementation manner, the Q first LLRs include P first LLR sequences, the first LLR sequence includes at least two first LLRs, and P is an integer greater than or equal to 2; the decoding unit is specifically configured to:

[0178] Determine P second LLR sequences corresponding to the P first LLR sequences, where one first LLR sequence corresponds to one sub-block, and one second LLR sequence corresponds to one sub-block;

[0179] Determine, according to the Pth second LLR sequence, a codeword decoding result of the Pth sub-block and an information decoding result of the Pth sub-block;

[0180] The codeword decoding result of the i-th sub-block and the information decoding result of the i-th sub-block are determined according to the codeword decoding result of at least one sub-block from the codeword decoding result of the i+1-th sub-block to the codeword decoding result of the P-th sub-block, the information decoding result of at least one sub-block from the information decoding result of the i+1-th sub-block to the information decoding result of the P-th sub-block, and the i-th second LLR sequence, where i is an integer between 1 and P-1.

[0181] In another possible implementation manner, the positional relationship between two adjacent matrix blocks in the A matrix blocks is the same as the preset positional relationship.

[0182] In another possible implementation, the decoding unit is specifically used for:

[0183] Performing polarization decoding on the bit information to be decoded according to the first generation matrix and the mapping relationship to obtain polarization-decoded bits;

[0184] The first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes a first submatrix block located at the upper left corner of the second submatrix block, the second submatrix block is located at the lower right corner of the first generating matrix, the first submatrix block and the second submatrix block are the same, along the diagonal direction of the second generating matrix, the distance between the first element in the first submatrix block and the second element in the second submatrix block is u, and u is an integer greater than or equal to 1; the first generating matrix includes A second generating matrices, the A second generating matrices are distributed along the diagonal of the second generating matrix (for example, the diagonal can be the main diagonal), the first submatrix block of the b+1th second generating matrix in the A second generating matrices overlaps with the second submatrix block of the bth second generating matrix, b is an integer greater than or equal to 1, and T is an integer greater than or equal to 2; the mapping relationship includes a mapping relationship between a subchannel carrying a first information bit on the first subblock and a subchannel carrying a second information bit on the second subblock, and T is an integer greater than or equal to 2.

[0185] A fifth aspect of an embodiment of the present application provides a coding device, comprising: a memory, a processor, and a computer program, wherein the computer program is stored in the memory, and the processor runs the computer program to execute the coding method as described in any one of the first aspects.

[0186] A sixth aspect of an embodiment of the present application provides a decoding device, comprising: a memory, a processor, and a computer program, wherein the computer program is stored in the memory, and the processor runs the computer program to execute the decoding method as described in any one of the second aspects.

[0187] A seventh aspect of an embodiment of the present application provides a storage medium, wherein the storage medium includes a computer program, and the computer program is used to implement the encoding method as described in any one of the first aspects.

[0188] An eighth aspect of the embodiments of the present application provides a storage medium, wherein the storage medium includes a computer program, and the computer program is used to implement the decoding method as described in any one of the second aspects.

[0189] A ninth aspect of the embodiments of the present application provides a coding device, which may include a communication interface and a logic circuit;

[0190] The logic circuit is used to generate an input vector, the input vector includes T sub-blocks, a first information bit on a first sub-block is obtained by copying a second information bit on a second sub-block, wherein the first sub-block and the second sub-block are sub-blocks in the T sub-blocks, a sequence number of the first sub-block is after a sequence number of the second sub-block, and T is an integer greater than or equal to 2; polarization encoding is performed on the input vector to obtain encoded bits;

[0191] The communication interface is used to output the encoded bits.

[0192] In a possible implementation, the logic circuit may also execute the encoding method described in any one of the first aspects.

[0193] A tenth aspect of the embodiments of the present application provides a decoding device, which may include an input interface and a logic circuit, wherein:

[0194] The input interface is used to receive bit information to be decoded, the bit information to be decoded includes bit information of a first sub-block and bit information of a second sub-block, the bits on the first sub-block are copied from the bits on the second sub-block, and the sequence number sequence of the second sub-block is after the sequence number sequence of the first sub-block;

[0195] The logic circuit is used to perform polarization decoding according to the bit information to be decoded to obtain polarization-decoded bits.

[0196] In a possible implementation, the logic circuit may also execute the decoding method described in any one of the second aspects.

[0197] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0198] Through the above scheme, it can be known that an input vector is generated, which includes T sub-blocks, and the first information bit on the first sub-block is obtained by copying the second information bit on the second sub-block; wherein the first sub-block and the second sub-block are sub-blocks in the T sub-blocks, the sequence number of the first sub-block is after the sequence number of the second sub-block, and T is an integer between 2 and T; and then the input vector is polarized encoded to obtain the encoded bit. It can be seen that in the encoding process, the first information bit on the first sub-block is obtained by copying the second information bit on the second sub-block, which is equivalent to setting the coupling relationship between the information bit on the first sub-block and the information bit on the second sub-block, so that the first information bit on the first sub-block and the second information bit on the second sub-block have a verification relationship. Then in the encoding and decoding process, encoding and decoding can be performed according to the coupling relationship between the information bit on the first sub-block and the information bit on the second sub-block, thereby reducing the complexity of encoding and decoding. BRIEF DESCRIPTION OF THE DRAWINGS

[0199] Figure 1 An architecture diagram of a communication system according to an embodiment of the present application;

[0200] Figure 2 A coding diagram provided in an embodiment of the present application;

[0201] Figure 3 A schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0202] Figure 4A A schematic diagram of a flow chart of the encoding method according to an embodiment of the present application;

[0203] Figure 4B This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0204] Figure 4C This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0205] Figure 4D This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0206] Figure 4E This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0207] Figure 4F This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0208] Figure 4G This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0209] Figure 4H This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0210] Fig. 4I This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0211] Figure 4J This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0212] Figure 4K This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0213] Figure 5 A schematic diagram of a matrix block according to an embodiment of the present application;

[0214] Fig. 6A A schematic diagram of a second generation matrix according to an embodiment of the present application;

[0215] Figure 6B Another schematic diagram of the second generation matrix of the embodiment of the present application;

[0216] Figure 6C Another schematic diagram of the second generation matrix of the embodiment of the present application;

[0217] Fig.6D Another schematic diagram of the second generation matrix of the embodiment of the present application;

[0218] Fig. 7A Another schematic diagram of the first generation matrix of the embodiment of the present application;

[0219] Figure 7B Another schematic diagram of the first generation matrix of the embodiment of the present application;

[0220] Figure 7C Another schematic diagram of the first generation matrix of the embodiment of the present application;

[0221] Fig. 8A A schematic diagram of a third generation matrix according to an embodiment of the present application;

[0222] Figure 8B Another schematic diagram of the third generation matrix of the embodiment of the present application;

[0223] Fig.9A This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0224] Fig. 9B This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0225] Fig. 10A Another schematic diagram of the encoding method according to the embodiment of the present application;

[0226] Fig. 10B This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0227] Fig. 10C This is another schematic diagram of a scenario of the encoding method according to an embodiment of the present application;

[0228] Fig.11A Another schematic diagram of the second generation matrix of the embodiment of the present application;

[0229] Fig. 11B Another schematic diagram of the second generation matrix of the embodiment of the present application;

[0230] Fig. 11C Another schematic diagram of the second generation matrix of the embodiment of the present application;

[0231] Fig. 12A Another schematic diagram of the second generation matrix of the embodiment of the present application;

[0232] Fig. 12B Another schematic diagram of the second generation matrix of the embodiment of the present application;

[0233] Fig.13 Another schematic diagram of the first generation matrix of the embodiment of the present application;

[0234] Fig.14 Another schematic diagram of the first generation matrix of the embodiment of the present application;

[0235] Fig.15A Another schematic diagram of the first generation matrix of the embodiment of the present application;

[0236] Fig. 15B Another schematic diagram of the first generation matrix of the embodiment of the present application;

[0237] Fig. 15C Another schematic diagram of the first generation matrix of the embodiment of the present application;

[0238] Fig.16 A schematic diagram of a flow chart of a decoding method according to an embodiment of the present application;

[0239] Fig.17A A schematic diagram of a decoding process of an embodiment of the present application;

[0240] Fig. 17B Another schematic diagram of a decoding process according to an embodiment of the present application;

[0241] Fig.18A Another schematic diagram of a decoding process according to an embodiment of the present application;

[0242] Fig.18B Another schematic diagram of a decoding process according to an embodiment of the present application;

[0243] Fig.18CAnother schematic diagram of a decoding process according to an embodiment of the present application;

[0244] Fig.18D Another schematic diagram of a decoding process according to an embodiment of the present application;

[0245] Fig.19 Another decoding performance diagram of an embodiment of the present application;

[0246] Fig. 20 Another decoding performance diagram of an embodiment of the present application;

[0247] Fig.21 Another decoding performance diagram of an embodiment of the present application;

[0248] Fig. 22 A schematic diagram of the structure of an encoding device according to an embodiment of the present application;

[0249] Fig.23 A schematic diagram of the structure of a decoding device according to an embodiment of the present application;

[0250] Fig.24 This is a schematic diagram of the structure of another encoding device according to an embodiment of the present application;

[0251] Fig.25 A schematic diagram of the structure of another decoding device according to an embodiment of the present application;

[0252] Fig.26 This is a schematic diagram of the structure of another encoding device according to an embodiment of the present application;

[0253] Fig. 27 FIG. 4 is a schematic diagram of the structure of another decoding device according to an embodiment of the present application. DETAILED DESCRIPTION

[0254] The embodiments of the present application provide a coding method, a decoding method and a device thereof, which are used to reduce the complexity of coding and decoding.

[0255] The embodiments of the present application are applied to various fields using Polar coding, such as data storage, optical network communication, wireless communication, etc. Among them, the wireless communication systems mentioned in the embodiments of the present application include but are not limited to: narrowband Internet of Things (NB-IoT), Wimax, long-term evolution (LTE), and the three major application scenarios of the new radio (NR) of the next-generation 5G mobile communication system, enhanced mobile broad band (eMBB), ultra-reliable and low-latency communication (URLLC), and massive machine-type communications (mMTC). Of course, the fields using Polar coding can also be other, and this application does not make specific restrictions on this. The embodiments of the present application are applicable to hybrid automatic repeat request (HARQ) scenarios in communication systems to adapt to channel fading and changes. In the embodiments of the present application, the information coupling relationship between some sub-blocks of the T sub-blocks in the input vector is realized by using the replication relationship of the information bits between some sub-blocks. Furthermore, some of the T sub-blocks have a codeword coupling relationship, thereby reducing the complexity of encoding and decoding while ensuring the original IR-HARQ performance.

[0256] For ease of understanding, the following Figure 1 , introducing an architecture diagram of a communication system to which an embodiment of the present application is applicable.

[0257] Figure 1 An architectural diagram of the communication system provided for this application. Figure 1 , including a sending device 101 and a receiving device 102.

[0258] Optionally, when the sending device 101 is a terminal device, the receiving device 102 is a network device. When the sending device 101 is a network device, the receiving device 102 is a terminal device.

[0259] See also Figure 1 The transmitting device 101 includes an encoder, so that the transmitting device 101 can perform polar coding and output a coded sequence. The coded sequence is transmitted to the receiving device 102 on the channel after rate matching, interleaving and modulation. The receiving device 102 includes a decoder, and the receiving device 102 can receive the signal sent by the transmitting device 101 and decode the received signal.

[0260] It should be noted that Figure 1 The architecture diagram of a communication system is merely illustrated in the form of an example, and is not intended to limit the architecture diagram of the communication system.

[0261] To facilitate understanding, the concepts involved in the embodiments of the present application are introduced below.

[0262] Terminal equipment: including but not limited to mobile station (MS), mobile terminal (MT), mobile telephone (MT), handset and portable equipment, etc., which can communicate with one or more core networks via radio access network (RAN). For example, the terminal equipment can be a mobile phone (or "cellular" phone), a computer with wireless communication function, etc. The terminal equipment can also be a portable, pocket-sized, handheld, computer-built-in or vehicle-mounted mobile device or equipment.

[0263] Network equipment: It can be an evolutionary node B (eNB or eNodeB) in the LTE system, or the network equipment can be a gNB or transmission reception point (TRP), micro base station, etc. in the 5G communication system, or the network equipment can be a relay station, access point, vehicle-mounted equipment, wearable device, and network equipment in the future evolved public land mobile network (public land mobile network, PLMN), or in a network that integrates multiple technologies, or in base stations in various other evolved networks, etc.

[0264] Polarization coding: Polarization coding can also be called polar coding. Polarization coding can be described in the following two ways:

[0265] One way: The encoding process can be represented by a generator matrix, that is,

[0266] is a row vector, N is the code length, and N is an integer greater than or equal to 1. i is the bit before encoding, and i is an integer between 1 and N. includes information bits and / or frozen bits, that is, a iIt can be an information bit or a frozen bit. The information bit is a bit used to carry information, and the information bit may include a cyclic redundancy check (CRC) bit and / or a parity check (PC) bit. The frozen bit is a padding bit, and the frozen bit may usually be 0.

[0267] G N is the generator matrix, G N is an N*N matrix, Among them, B N is an N*N transposed matrix, for example, B N It can be a bit reversal matrix. is the Kronecker product of log2(N) matrices F2. The addition and multiplication involved above are all operations on the binary Galois field. G N It is called the generator matrix kernel.

[0268] Another way: the encoding process can be represented by a coding diagram.

[0269] Next, combine Figure 2 , explain the coding diagram.

[0270] Figure 2 A coding diagram provided for the embodiment of the present application. Figure 2 , the coding code length corresponding to this coding diagram is 8. Each circle in the first column represents an information bit or a frozen bit. The first column shows a1, a2, ..., a8 as bits before coding (information bits or frozen bits), where a4, a6, a7, a8 are information bits, and a1, a2, a3, a5 are frozen bits. Each circle in the columns other than the first column represents a partial sum bit. The x1, x2, ..., x8 in the last column are the bits after coding. Each butterfly diagram (shown on the right side of the figure) represents a polarization of 2 bits, that is,

[0271] Sub-block: includes multiple information bits and / or multiple frozen bits. Optionally, all bits included in the sub-block are information bits; or, all bits included in the sub-block are frozen bits; or, some of the bits included in the sub-block are information bits and some are frozen bits.

[0272] For example, sub-block u1=(1,1,1,1,1,1,1,1), where "1" refers to the information bit and "0" refers to the frozen bit. It can be seen that all the bits included in sub-block u1 are information bits "1". Taking another example, sub-block u1=(1,0,0,0,1,1,1,0), it can be seen that u1 includes multiple information bits "1" and multiple frozen bits "0". Taking another example, sub-block u1=(0,0,0,0,0,0,0,0), it can be seen that all the bits included in sub-block u1 are frozen bits "0".

[0273] Sub-block sequence number: refers to the sequence number of the sub-blocks in order. The sequence number of the sub-block indicates the positional relationship between the sub-blocks in order. For example, Figure 3 As shown, the input vector includes the first sub-block u1, the second sub-block u2, ... and the eighth sub-block u8, that is, the sequence number of the first sub-block u1 is 1, the sequence number of the second sub-block u2 is 2, and so on. It can be understood that the sequence number of the second sub-block u2 is after the sequence number of the first sub-block u1, and the sequence number of the eighth sub-block u8 is after the second sub-block u2.

[0274] Information coupling relationship: refers to the process of encoding, when the information bits on one sub-block are directly copied from the information bits on another sub-block, then the two sub-blocks are said to have information coupling relationship. Figure 3 As shown, during the encoding process, the information bits on the second sub-block are copied from the information bits on the first sub-block, and it is said that there is an information coupling relationship between the first sub-block and the second sub-block.

[0275] Codeword coupling relationship: refers to the process of encoding, when an XOR operation is performed on the encoded bit sequences corresponding to two sub-blocks (where XOR operation is a binary representation and an addition operation is expressed in decimal. In the subsequent schematic diagrams, "+" is used to indicate the addition operation in decimal), the two sub-blocks are said to have a codeword coupling relationship. For example, Figure 3 As shown, during the encoding process, the encoded bit sequence c1 corresponding to the first sub-block is added to the encoded bit sequence c2 corresponding to the second sub-block. It can be seen that c1 and c2 have a codeword coupling relationship, which is referred to as the codeword coupling relationship between the first sub-block and the second sub-block in the following text.

[0276] A coupled sub-block includes at least two sub-blocks, and the encoded bit sequences corresponding to the at least two sub-blocks are obtained by XOR, which can be referred to as the at least two sub-blocks having a codeword coupling relationship. Figure 3As shown, during the encoding process, the encoded bit sequence c1 corresponding to the first sub-block is added to the encoded bit sequence c2 corresponding to the second sub-block. It can be seen that c1 and c2 have a codeword coupling relationship, so the first sub-block and the second sub-block can form a coupled sub-block.

[0277] The serial number sequence of the coupling sub-blocks: refers to the serial number sequence of the sub-block with the earliest serial number sequence among the at least two sub-blocks included in the coupling sub-blocks; or, refers to the serial number sequence of the sub-block with the latest serial number sequence among the at least two sub-blocks included in the coupling sub-blocks. For example, the first coupling sub-block includes the third sub-block u3 and the fourth sub-block u4, and the second coupling sub-block includes the first sub-block u1 and the second sub-block u2. The serial number sequence of the sub-block with the earliest serial number sequence is taken as the serial number sequence of the coupling sub-blocks. It can be seen that the sub-block with the earliest serial number sequence on the first coupling sub-block is the third sub-block u3; and the sub-block with the latest serial number sequence on the second coupling sub-block is the first sub-block u1. It can be seen that the serial number sequence of the third sub-block u3 is after the serial number sequence of the first sub-block u1, so the serial number sequence of the first coupling sub-block is after the serial number sequence of the second coupling sub-block, or the serial number sequence of the second coupling sub-block is before the serial number sequence of the first coupling sub-block. For example, the first coupling sub-block includes the second sub-block u2 and the third sub-block u3, and the second coupling sub-block includes the first sub-block u1 and the second sub-block u2. The sequence number of the sub-block with the last sequence number is the sequence number of the coupling sub-block. It can be seen that the sub-block with the first sequence number on the first coupling sub-block is the third sub-block u3, and the sub-block with the last sequence number on the second coupling sub-block is the second sub-block u2. It can be seen that the sequence number of the third sub-block u3 is after the sequence number of the second sub-block u2, so the sequence number of the first coupling sub-block is after the sequence number of the second coupling sub-block, or the sequence number of the second coupling sub-block is before the sequence number of the first coupling sub-block.

[0278] Information decoding result: refers to the decoding end decoding the received bit information to obtain the bit sequence before encoding.

[0279] Codeword decoding result: refers to the decoding end encoding the obtained pre-encoded bit sequence to obtain the encoded bit sequence.

[0280] It should be noted that in the embodiment of the present application, the starting coordinates in the matrix (the coordinates of the upper left corner) are taken as (1,1) for explanation. Of course, the starting coordinates in the matrix can also be (0,0), and the embodiment of the present application does not make any specific limitation on this.

[0281] See also Figure 4A , Figure 4A This is a schematic diagram of an embodiment of the encoding method of the present application. Figure 4A The method comprises:

[0282] 401. Generate an input vector.

[0283] The input vector includes T sub-blocks, a first information bit on a first sub-block of the T sub-blocks is obtained by copying a second information bit on a second sub-block of the T sub-blocks, and a sequence number of the first sub-block is after a sequence number of the second sub-block, and T is an integer greater than or equal to 2. Optionally, the first information bit is all or part of the information bit on the second sub-block.

[0284] First, the code length of each sub-block in the T sub-blocks is introduced. Optionally, the code length of each sub-block in the T sub-blocks may be the same or different.

[0285] For the case where the code lengths of the T sub-blocks are the same, for example, Figure 3 The first sub-block u1 and the second sub-block u2 are used as examples for explanation, and the same is true for other sub-blocks. For example, the first sub-block u1 = (1, 0, 0, 0, 1, 1, 1, 0), the second sub-block u2 = (1, 1, 0, 0, 0, 0, 0), where "1" refers to the information bit and "0" refers to the frozen bit. It can be seen that the code length of the first sub-block u1 is 8, and the code length of the second sub-block u2 is also 8.

[0286] For the case where the code lengths of the T sub-blocks are different. Figure 3 The first sub-block u1 and the second sub-block u2 are used as examples for explanation, and the same is true for other sub-blocks. The first sub-block u1 = (1, 0, 0, 0, 1, 1, 1, 0), the second sub-block u2 = (1, 0, 0, 0, 0, 0), where "1" refers to the information bit and "0" refers to the frozen bit. It can be seen that the code length of the first sub-block u1 is 8, and the code length of the second sub-block u2 is also 6. The code lengths of the first sub-block u1 and the second sub-block u2 are different.

[0287] In the subsequent embodiments or implementations, the case where the code length of each sub-block in the T sub-blocks is the same is taken as an example for description.

[0288] For example, Figure 3Taking the coding scenario shown as an example, the first sub-block is the first sub-block u1, and the second sub-block is the second sub-block u2, that is, the second sub-block u2 is after the first sub-block u1. The first information bit on the second sub-block u2 is copied from the second information bit on the first sub-block u1. It should be noted that the second sub-block u2 can carry frozen bits or new information bits on other sub-channels except for the first information bit, and this application does not limit it. In subsequent embodiments or implementation methods, only the example of the first sub-block carrying frozen bits on other sub-channels except for the first information bit is used for explanation, and the first information bit carried on the first sub-block is referred to as the information bit carried on the first sub-block, and the second information bit carried on the second sub-block is referred to as the information bit carried on the second sub-block.

[0289] The sequence number of the first sub-block is after the sequence number of the second sub-block. Optionally, the second sub-block is M sub-blocks adjacent to the first sub-block, or the second sub-block is M sub-blocks non-adjacent to the first sub-block, where M is an integer greater than or equal to 1 and less than T-1.

[0290] The information bits on the first sub-block are directly copied from the information bits on the M sub-blocks.

[0291] First, combine Figure 3 and Figure 4B An example is given for the case where the second sub-block is M sub-blocks adjacent to the first sub-block:

[0292] Example 1: See Figure 3 ,Depend on Figure 3 As can be seen from the input vector shown, starting from the second sub-block, the information bits on the sub-block are copied from the information bits on the previous sub-block adjacent to the sub-block. In this implementation, the second sub-block is a sub-block adjacent to the first sub-block. For example, the first sub-block is u2 and the second sub-block is u1.

[0293] Example 2: Please refer to Figure 4B ,Depend on Figure 4B From the input vector shown, it can be seen that starting from the third sub-block, the information bits on the sub-block are copied from the information bits of the first two or more sub-blocks adjacent to the sub-block. In this implementation, the second sub-block is one or more sub-blocks adjacent to the first sub-block. For example, the first sub-block is u3, and the second sub-blocks are u1 and u2.

[0294] Combine the following Figure 4C An example is given for the case where the second sub-block is M sub-blocks that are non-adjacent to the first sub-block:

[0295] Example 3: See Figure 4C ,Depend on Figure 4CIt can be seen from the input vector shown that the information bit on the 5th sub-block is copied from the information bit on the 3rd sub-block. In this implementation, the second sub-block is a sub-block that is non-adjacent to the first sub-block. For example, the first sub-block is u5 and the second sub-block is u3.

[0296] In a possible implementation, the information bits on the first sub-block are copied from the information bits on the second sub-block on the T sub-blocks according to a mapping relationship. The mapping relationship includes a mapping relationship between a sub-channel carrying information bits on the first sub-block and a sub-channel carrying information bits on the second sub-block.

[0297] The following takes the first subblock as the second subblock u2 and the second subblock as the first subblock u1 as an example to introduce the information bit replication process. When polarization coding is performed on each subblock in the input vector, if the code length of each subblock is N, then each subblock corresponds to N subchannels. Figure 4D As shown, the first sub-block u1 = (1, 0, 0, 0, 1, 1, 1, 0), and the second sub-block u2 = (1, 1, 0, 0, 0, 0, 0). The mapping relationship includes u 1子信道6 with u 2子信道1 The mapping relationship between 1子信道7 and u 2子信道2 The mapping relationship between them.

[0298] Then, through this mapping relationship, the information bit 1 transmitted on the subchannel 6 of the first subblock u1 is copied, and the information bit 1 is used as the information bit on the subchannel 1 of the second subblock u2; the information bit 2 of the subchannel 7 in the first subblock u1 is copied, and the information bit 2 is used as the information bit on the subchannel 2 of the second subblock u2. Figure 4D As described above, subchannel 1 and subchannel 2 of the second subblock u2 carry information bit "1" from subchannel 6 and subchannel 7 of the first subblock u1, and subchannel 3 to subchannel 8 of the second subblock u2 carry frozen bit "0".

[0299] The above shows that the mapping relationship includes u 1子信道6 with u 2子信道1 The mapping relationship between 1子信道7 and u 2子信道2 An example of a mapping relationship between Figure 3 The first sub-block u1 and the second sub-block u2 in the scene shown. Figure 3 As shown, the input vector includes 8 sub-blocks, and the mapping relationship includes the mapping relationship of the sub-channels of the 8 sub-blocks. The above is only to introduce the mapping relationship provided by the present application by taking the mapping relationship of the sub-channels of the first sub-block u1 and the sub-channels of the second sub-block u2 as an example. The mapping relationship between the sub-channels of other sub-blocks is similar and will not be repeated here.

[0300] The T sub-blocks include sub-blocks for initial transmission and sub-blocks for retransmission. Figure 3 As shown, the first sub-block u1 is a sub-block for initial transmission, and the second sub-block u2 to the eighth sub-block u8 are sub-blocks for retransmission.

[0301] The following describes the process of establishing the mapping relationship provided by the embodiment of the present application, and takes the process of establishing the mapping relationship between the subchannel on the first subblock and the subchannel on the second subblock as an example for explanation. Since the reliability of the subchannel on the subblock should be considered during the retransmission process to improve the transmission performance. For example, the replicated information bits are preferentially transmitted on the subchannel with higher reliability on the subblock used for retransmission. Therefore, the mapping relationship can be established according to the reliability of the subchannel on the subblock used for retransmission.

[0302] The mapping relationship between the sub-channels of the first sub-block and the sub-channels of the second sub-block is introduced below in conjunction with steps 1 to 4.

[0303] Step 1: Determine the second sub-block.

[0304] The sequence number of the second sub-block is after the sequence number of the first sub-block. Optionally, the second sub-block is M sub-blocks adjacent to the first sub-block, or the second sub-block is M sub-blocks non-adjacent to the first sub-block. For details, please refer to the relevant description above.

[0305] Optionally, the M sub-blocks are determined according to a preset mapping sequence, and the information bits on the first sub-block are directly copied from the information bits on the M sub-blocks. The preset mapping sequence is used to indicate a mapping relationship between the T sub-blocks.

[0306] For example, Figure 4D As shown, the first sub-block u1 = (1, 0, 0, 0, 1, 1, 1, 0), and the second sub-block u2 = (1, 1, 0, 0, 0, 0, 0). 1子信道6 The information bit "1" on the second sub-block u2 is u 2子信道1 The information bit "1" on the first sub-block u1 is copied. 1子信道7 The information bit "1" on the second sub-block is u2. 2子信道2 It is obtained by copying the information bit "1" on the first sub-block u1 and the information bit on the second sub-block u2. It can be known that the information bit on the first sub-block u1 and the information bit on the second sub-block u2 have a copy relationship, so it can be understood that there is a mapping relationship between the first sub-block u1 and the second sub-block u2.

[0307] Several possible mapping sequences are shown below, where T is 8.

[0308] Example 1: The mapping sequence includes the following parts or a combination of the following parts:

[0309] There is a mapping relationship between the first sub-block and the second sub-block;

[0310] There is a mapping relationship between the second sub-block and the third sub-block;

[0311] There is a mapping relationship between the first sub-block and the fourth sub-block;

[0312] There is a mapping relationship between the 1st sub-block and the 5th sub-block;

[0313] There is a mapping relationship between the 1st sub-block and the 6th sub-block;

[0314] There is a mapping relationship between the 1st sub-block and the 7th sub-block;

[0315] There is a mapping relationship between the 1st sub-block and the 8th sub-block.

[0316] Optionally, the mapping sequence of Example 1 can also be expressed as the following parts or a combination of the following parts:

[0317]

[0318]

[0319]

[0320]

[0321]

[0322]

[0323]

[0324]

[0325]

[0326]

[0327]

[0328]

[0329]

[0330] Among them, u j Refers to the j-th sub-block, where j is an integer greater than or equal to 1 and less than or equal to 8. It means that there is a mapping relationship between two sub-blocks.

[0331] Example 2: The mapping includes the following parts or a combination of the following parts:

[0332] There is a mapping relationship between the first sub-block and the second sub-block;

[0333] There is a mapping relationship between the second sub-block and the third sub-block;

[0334] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0335] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0336] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0337] There is a mapping relationship between the 7th sub-block and the 8th sub-block.

[0338] Optionally, the mapping sequence of Example 2 can also be expressed as the following parts or a combination of the following parts:

[0339]

[0340]

[0341]

[0342]

[0343]

[0344]

[0345]

[0346]

[0347]

[0348]

[0349]

[0350] Among them, u j Refers to the j-th sub-block, where j is an integer greater than or equal to 1 and less than or equal to 8. It means that there is a mapping relationship between two sub-blocks.

[0351] Example 3: The mapping includes the following parts or a combination of the following parts:

[0352] There is a mapping relationship between the first sub-block and the second sub-block;

[0353] There is a mapping relationship between the second sub-block and the third sub-block;

[0354] There is a mapping relationship between the 3rd sub-block and the 4th sub-block;

[0355] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0356] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0357] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0358] There is a mapping relationship between the 7th sub-block and the 8th sub-block.

[0359] Optionally, the mapping sequence of Example 3 can also be expressed as the following parts or a combination of the following parts:

[0360]

[0361]

[0362]

[0363]

[0364]

[0365]

[0366]

[0367]

[0368]

[0369]

[0370]

[0371]

[0372]

[0373] Among them, u j Refers to the j-th sub-block, where j is an integer greater than or equal to 1 and less than or equal to 8. It means that there is a mapping relationship between the sub-channels of two sub-blocks.

[0374] Example 4: The mapping includes the following parts or a combination of the following parts:

[0375] There is a mapping relationship between the first sub-block and the second sub-block;

[0376] There is a mapping relationship between the second sub-block and the third sub-block;

[0377] There is a mapping relationship between the first sub-block and the fourth sub-block;

[0378] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0379] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0380] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0381] There is a mapping relationship between the 7th sub-block and the 8th sub-block.

[0382] Optionally, the mapping sequence of Example 4 can also be expressed as the following parts or a combination of the following parts:

[0383]

[0384]

[0385]

[0386]

[0387]

[0388]

[0389]

[0390]

[0391]

[0392]

[0393]

[0394]

[0395]

[0396] Among them, u j Refers to the j-th sub-block, where j is an integer greater than or equal to 1 and less than or equal to 8. It means that there is a mapping relationship between two sub-blocks.

[0397] Step 2: Determine the subchannel number that carries information bits on the first sub-block.

[0398] There are multiple ways to determine the sequence number of the sub-channel carrying the information bits on the first sub-block, which are described below with examples.

[0399] 1. Introduce implementation method 1 in combination with step 2a and step 2b.

[0400] Step 2a: Determine the number of information bits carried by the first sub-block according to the first code rate allocation table.

[0401] Two implementations of determining the number of information bits carried by the first sub-block through the first code rate allocation table are shown below.

[0402] 1. The input parameters of the first code rate allocation table are the code length M of the T sub-blocks and the code rate of the T sub-blocks, and the output parameter of the first code rate allocation table is the number K of information bits carried by each sub-block j Wherein, code length M = T*code length N of each sub-block, j is the sequence number of the sub-block, j∈{1,…,T}. In this manner, the number of information bits carried by the first sub-block can be directly determined by the first code rate allocation table.

[0403] 2. The input parameters of the first rate allocation table are the code length M of the T sub-blocks and the code rate of the T sub-blocks, and the output parameter of the first rate allocation table is the code rate R of each sub-block. j . Wherein, code length M = T*code length N of each sub-block, j is the sequence number of the sub-block, j∈{1,2,…,T}. In this way, the code rate of the first sub-block can be determined by the first code rate allocation table, and the code rate of the first sub-block is multiplied by the code length N of the first sub-block to obtain the number of information bits carried by the first sub-block.

[0404] Step 2b: Determine the subchannel sequence number of the first sub-block carrying the information bits according to the preset first reliability sequence.

[0405] Specifically, each of the T sub-blocks corresponds to N sub-channels, and the first reliability sequence includes the reliability ranking of the N sub-channels of the first sub-block. Then, the sub-channel sequence number carrying the information bit on the first sub-block can be determined according to the first reliability sequence. Two possible determination methods are shown below by way of example.

[0406] 1. Select the subchannels with top X reliability among the N subchannels of the first sub-block through the first reliability sequence, and use the subchannel numbers with top X reliability as the subchannel numbers carrying information bits on the first sub-block, where X is the number of information bits carried on the first sub-block.

[0407] For example, Figure 4D As shown, the first sub-block is u2, the second sub-block is u1, and the number of information bits carried on the first sub-block is 2. The reliability of subchannel 1 and subchannel 2 on u2 is determined to be higher than that of other subchannels through the first reliability sequence, and the sequence number of subchannel 1 and the sequence number of subchannel 2 on u2 are used as the sequence number of the subchannel carrying the first information bit.

[0408] 2. Select X subchannels with medium reliability from the N subchannels of the first sub-block through the first reliability sequence, and use the sequence numbers of the X subchannels with medium reliability as the subchannel sequence numbers of the first information bit, where X is the number of information bits carried by the first sub-block.

[0409] For example, Figure 4E As shown, the first sub-block is u2, the second sub-block is u1, and the number of information bits carried on the first sub-block is 2. It is determined through the first reliability sequence that the reliability of sub-channel 3 and the reliability of sub-channel 4 on u2 are lower than the reliability of sub-channel 1 and the reliability of sub-channel 2, but higher than the reliability of other sub-channels, and the sequence number of sub-channel 3 and the sequence number of sub-channel 4 on u2 are used as the sub-channel sequence number carrying information bits on u1.

[0410] Below are two possible representations of the first reliability sequence.

[0411] Representation 1: The first reliability sequence is: r = {r1, r2, ..., r N}. Among them, r i represents the subchannel number of the first sub-block, r i The position in the r sequence represents the subchannel r i The reliability ranking of the subchannels included in the first sub-block. In the first reliability ranking, the more forward the subchannel is, the higher the reliability of the subchannel is.

[0412] For example, assuming that the first sub-block includes 8 sub-channels, the serial numbers of the 8 sub-channels are: 1, 2, ..., 7, 8. Assuming that the reliability ranking sequence r = {4, 5, 3, 6, 7, 2, 1, 8}, it means that the reliability of the 8 sub-channels satisfies: sub-channel 4> sub-channel 5> sub-channel 3> sub-channel 6> sub-channel 7> sub-channel 2> sub-channel 1> sub-channel 8.

[0413] Representation 2: The first reliability sequence is: w = {w1, w2, ..., w N}. Among them, w i represents the reliability of the i-th subchannel of the first sub-block. i The larger the value, the greater the reliability of the ith subchannel of the first sub-block. i>w j , it means that the reliability of the i-th subchannel of the first subblock is greater than the reliability of the j-th subchannel of the first subblock.

[0414] For example, assuming that the first sub-block includes 8 sub-channels, and the reliability ranking sequence w={2.1, 3, 4.5, 5, 3.2, 2, 2.6, 7}, then the reliabilities of the 8 sub-channels are as shown in Table 1:

[0415] Table 1

[0416]

[0417] Optionally, the reliability rankings of subchannels in different subblocks may be the same or different. When the reliability rankings of subchannels in different subblocks are the same, only the subchannel reliability sequence of one subblock may be stored.

[0418] In a possible implementation, the second sub-block includes a fourth sub-block and a fifth sub-block, and the information bits on the first sub-block are copied from the information bits on the fourth sub-block and the information bits on the fifth sub-block.

[0419] In this implementation, the following situation exists: the reliability of the second subchannel of the fourth sub-block is the same as the reliability of the third subchannel of the fifth sub-block. Since the information bits of the first sub-block are copied from the information bits on the fourth sub-block and the information bits on the fifth sub-block, when the reliability of the second sub-channel is the same as the reliability of the third sub-channel, if a sub-channel is selected from the second sub-channel and the third sub-channel to copy the information bits, the problem of which sub-channel to select is faced. The following describes a method for determining the reliability of the second sub-channel and the reliability of the third sub-channel for this situation. The determination method includes:

[0420] When the second sub-channel and the third sub-channel have the same reliability, determining the reliability of the second sub-channel and the reliability of the third sub-channel according to a second preset rule;

[0421] The second subchannel and the third subchannel having the same reliability includes: the second subchannel corresponds to the third reliability in the first reliability sequence, and the third subchannel corresponds to the third reliability in the first reliability sequence.

[0422] The second preset rule includes any of the following possible implementations:

[0423] 1. When the sequence number of the fourth sub-block is after the sequence number of the fifth sub-block, it is determined that the reliability of the second sub-channel is greater than the reliability of the third sub-channel;

[0424] 2. When the sequence number of the fourth sub-block is before the sequence number of the fifth sub-block, it is determined that the reliability of the third sub-channel is greater than the reliability of the second sub-channel.

[0425] For example, Figure 4B As shown, the first sub-block is the third sub-block u3, and the second sub-block is the first sub-block u1 and the second sub-block u2. Figure 4B It can be seen that the information bits on the third sub-block u3 are copied from the information bits on the first sub-block u1 and the information bits on the second sub-block u2. When selecting the copied bits from the first sub-block u1 and the second sub-block u2, the reliability ranking of the sub-channels of the first sub-block u1 and the reliability ranking of the sub-channels of the second sub-block u2 are determined according to the first reliability sequence, and X sub-channels with larger reliability are selected, and the information bits on the X sub-channels are copied as the information bits on the third sub-block u3.

[0426] When determining the subchannel of the first subblock u1 and the subchannel of the second subblock u2, if the reliabilities of the first subchannel of the first subblock u1 and the second subchannel of the second subblock u2 are the same, the reliability of the first subchannel of the first subblock u1 with an earlier sequence number is determined to be greater than the reliability of the second subchannel of the second subblock u2; or, the reliability of the second subchannel of the second subblock u2 with a later sequence number is determined to be greater than the reliability of the first subchannel of the first subblock u1. Therefore, if a subchannel needs to be selected from the first subchannel of the first subblock u1 and the second subchannel of the second subblock u2, the subchannel with a higher reliability can be selected and the information bits of the subchannel can be copied.

[0427] 2. Implementation method 2 is introduced through steps 2c and 2d.

[0428] Step 2c: Determine the number of information bits related to the second coupling sub-block carried by the first coupling sub-block according to the second code rate allocation table.

[0429] Among them, the first coupling sub-block and the second coupling sub-block respectively include at least two sub-blocks, the first coupling sub-block is obtained by the XOR operation of the encoded bit sequences corresponding to the at least two sub-blocks, and the second coupling sub-block is obtained by the XOR operation of the encoded bit sequences corresponding to the at least two sub-blocks, that is, there is a codeword coupling relationship between the at least two sub-blocks included in the coupling sub-block.

[0430] For example, by Figure 3 It can be seen that there is a codeword coupling relationship between two adjacent sub-blocks, so the coupled sub-block includes two sub-blocks. Figure 4FAs shown, the first coupling sub-block includes the 2nd sub-block u2 and the 3rd sub-block u3, and the second coupling sub-block includes the 1st sub-block u1 and the 2nd sub-block u2; or, the first coupling sub-block includes the 3rd sub-block u3 and the 4th sub-block u4, and the second coupling sub-block includes the 1st sub-block u1 and the 2nd sub-block u2.

[0431] In this embodiment, two possible implementations of determining the number of information bits related to the second coupling sub-block by using the second code rate allocation table are shown below.

[0432] 1. The input parameters of the second code rate allocation table are the code length M of the T sub-blocks and the code rate of the T sub-blocks, and the output parameter of the second code rate allocation table is the number of information bits carried by each coupling sub-block. Among them, the code length M = T * the code length N of each sub-block. In this way, the number of information bits related to the second coupling sub-block carried by the first coupling sub-block can be directly determined by the second code rate allocation table.

[0433] 2. The input parameters of the second code rate allocation table are the code length M of the T sub-blocks and the code rate of the T sub-blocks, and the output parameter of the second code rate allocation table is the code rate of each coupled sub-block. Wherein, code length M = T * code length N of each sub-block. In this way, the code rate of the first coupled sub-block is determined by the second code rate allocation table, and the code rate of the first coupled sub-block is multiplied by the code length M' of the first coupled sub-block. Wherein, M' = the number of sub-blocks included in the coupled sub-block * the code length N of each sub-block.

[0434] For example, the first coupling subblock includes the third subblock u3 and the fourth subblock u4, and the second coupling subblock includes the first subblock u1 and the second subblock u2. Then, the number of information bits carried by the first coupling subblock is determined to be 7 and the number of information bits carried by the second coupling subblock is determined to be 3 through the second code rate allocation table.

[0435] Step 2d: Determine the subchannel sequence number of the information bit related to the second coupling subblock carried by the first coupling subblock according to a preset second reliability sequence.

[0436] The second reliability sequence includes the reliability ranking of the subchannels of the first coupling subblock. The information bits related to the second coupling subblock and carried by the first coupling subblock are obtained by copying the information bits on the second coupling subblock.

[0437] Specifically, the subchannels with top Y reliability in the subchannels of the second coupling subblock are selected through the second reliability sequence as the subchannel sequence numbers of the information bits related to the second coupling subblock; or, Y subchannels with medium reliability in the subchannels of the second coupling subblock are selected as the subchannel sequence numbers of the information bits related to the second coupling subblock. Wherein, Y is the number of information bits related to the second coupling subblock.

[0438] For example, Figure 4F As shown, the first coupling sub-block includes the third sub-block u3 and the fourth sub-block u4, and the second coupling sub-block includes the first sub-block u1 and the second sub-block u2. The first coupling sub-block includes 4 information bits, and the second coupling sub-block includes 7 information bits. Then the sequence numbers of the four sub-channels with the top four reliabilities in the first coupling sub-block are determined by the second reliability sequence, and the sequence numbers of the four sub-channels are used as the sequence numbers of the sub-channels carrying the information bits related to the second coupling sub-block.

[0439] In this embodiment, the representation method of the second reliability sequence is similar to the representation method of the first reliability sequence. For details, please refer to the introduction of the representation method of the first reliability sequence, which will not be repeated here.

[0440] It should be noted that the reliability rankings of the subchannels of different coupling subblocks may be the same or different. When the reliability rankings of the subchannels of different coupling subblocks are the same, only the reliability sequence of the subchannels of one coupling subblock may be stored. With respect to implementation method 2, the relationship between the first coupling subblock and the second coupling subblock and the first subblock and the second subblock includes the following two possible situations, which are respectively introduced below.

[0441] Case 1: the first coupling sub-block includes the first sub-block, and the second coupling sub-block includes the second sub-block.

[0442] For example, Figure 4F As shown, the first coupling sub-block includes the third sub-block u3 and the fourth sub-block u4, and the second coupling sub-block includes the first sub-block u1 and the second sub-block u2. Figure 3 As shown, since two adjacent sub-blocks have an information coupling relationship, the first sub-block is the third sub-block u3 and the second sub-block is the second sub-block u2. If the first coupling sub-block carries 3 first information bits, the second coupling sub-block carries 7 information bits. According to the second reliability sequence, the sub-channels carrying the information bits on the first coupling sub-block are determined to be two sub-channels on the third sub-block u3 and one sub-channel on the fourth sub-block u4; then, the sequence numbers of the two sub-channels on the third sub-block u3 are used as the sequence numbers of the sub-channels carrying the information bits on the third sub-block u3.

[0443] Optionally, in case 1, the second sub-block includes the third sub-block, and when the first coupling sub-block and the second coupling sub-block both include the third sub-block, the first sub-channel on the third sub-block corresponds to different reliabilities in different coupling sub-blocks, that is, the first sub-channel corresponds to multiple reliabilities. Since the information bits of the first sub-block include those copied from the information bits on the third sub-block, and when the first sub-channel corresponds to multiple reliabilities, it is necessary to determine the reliability of the first sub-channel so as to select the sub-channel for copying the information bits from the third sub-block according to the reliability. The following is an introduction to the method for determining the reliability of the first sub-channel. The determination method includes:

[0444] When the first sub-channel corresponds to multiple reliabilities, the reliability of the first sub-channel is determined according to a first preset rule.

[0445] The first sub-channel corresponds to multiple reliabilities, which includes: the first sub-channel corresponds to a first reliability in the first coupling sub-block, and the first sub-channel corresponds to a second reliability in the second coupling sub-block.

[0446] The first preset rule includes any one of the following:

[0447] When the first reliability is greater than or equal to the second reliability, taking the first reliability as the reliability of the first sub-channel;

[0448] When the sequence number of the first coupling sub-block is after the sequence number of the second coupling sub-block, the first reliability is used as the reliability of the first sub-channel;

[0449] When the first reliability is less than or equal to the second reliability, taking the second reliability as the reliability of the first sub-channel;

[0450] When the sequence number of the first coupling sub-block is before the sequence number of the second coupling sub-block, the second reliability is used as the reliability of the first sub-channel.

[0451] For example, Figure 4G As shown, the first coupling sub-block includes the second sub-block u2 and the third sub-block u3, and the second coupling sub-block includes the first sub-block u1 and the second sub-block u2. It can be seen that the first coupling sub-block and the second coupling sub-block include the same second sub-block u2. Here, the first sub-channel of the second sub-block u2 is taken as an example for explanation. When the first sub-channel corresponds to two reliabilities, the larger reliability is selected as the reliability of the first sub-channel; or, the smaller reliability is selected as the reliability of the first sub-channel; or, the reliability corresponding to the first sub-channel in the coupling sub-block with an earlier sequence number is selected as the reliability of the first sub-channel; or, the reliability corresponding to the first sub-channel in the coupling sub-block with a later sequence number is selected as the reliability of the first sub-channel.

[0452] Optionally, the second sub-block includes the sixth sub-block and the seventh sub-block, and the first information bit on the first sub-block is copied from the information bit on the sixth sub-block and the information bit on the seventh sub-block. The first coupling sub-block includes the first sub-block, the second coupling sub-block includes the third coupling sub-block and the fourth coupling sub-block, the third coupling sub-block includes the sixth sub-block, and the fourth coupling sub-block includes the seventh sub-block. Then, when the first coupling sub-block copies the information bits from the third coupling sub-block and the fourth coupling sub-block, the reliability of the sub-channel of the third coupling sub-block and the reliability of the sub-channel of the fourth coupling need to be considered.

[0453] In this implementation, the following situation exists: the reliability of the fourth subchannel of the sixth subblock is the same as the reliability of the fifth subchannel of the seventh subblock. Since the information bits of the first subblock are copied from the information bits on the sixth subblock and the information bits on the seventh subblock, when the reliability of the fourth subchannel is the same as the reliability of the fifth subchannel, if a subchannel is selected from the fourth subchannel and the fifth subchannel to copy the information bits, the problem of which subchannel to select is faced. The following describes a method for determining the reliability of the fourth subchannel and the reliability of the fifth subchannel for this situation. The determination method includes:

[0454] When the fourth subchannel and the fifth subchannel have the same reliability, determining the reliability of the fourth subchannel and the reliability of the fifth subchannel according to a third preset rule;

[0455] When the fourth sub-channel and the fifth sub-channel have the same reliability, the reliability of the fourth sub-channel and the reliability of the fifth sub-channel are determined according to a third preset rule.

[0456] The third preset rule includes any of the following possible implementations:

[0457] 1. When the sequence number of the sixth sub-block is after the sequence number of the seventh sub-block, it is determined that the reliability of the fourth sub-channel is greater than the reliability of the fifth sub-channel;

[0458] 2. When the sequence number of the sixth sub-block is before the sequence number of the seventh sub-block, it is determined that the reliability of the fifth sub-channel is greater than the reliability of the fourth sub-channel.

[0459] For example, Figure 4H As shown, there is an information coupling relationship between four adjacent sub-blocks and a codeword coupling relationship between two adjacent sub-blocks, so it can be known that the coupled sub-block includes two adjacent sub-blocks. Fig. 4IAs shown, the first coupling sub-block includes the 4th sub-block u4 and the 5th sub-block u5, the third coupling sub-block includes the 1st sub-block u1 and the 2nd sub-block u2, and the fourth coupling sub-block includes the 2nd sub-block u2 and the 3rd sub-block u3. Here, the 6th sub-block is the 1st sub-block u1, the 7th sub-block is the 3rd sub-block u3, and the 1st sub-block is the 4th sub-block u4. The information bits on the 4th sub-block u4 are copied from the 1st sub-block u1, the 2nd sub-block u2 and the 3rd sub-block u3. Therefore, when copying the information bits, the reliability of the sub-channels on the 1st sub-block u1, the 2nd sub-block u2 and the 3rd sub-block u3 needs to be considered.

[0460] However, in this implementation, the following situations exist: the reliability corresponding to the fourth subchannel of the first sub-block u1 in the second reliability sequence is the same as the reliability corresponding to the fifth sub-channel of the third sub-block u3 in the second reliability sequence, then it is determined that the reliability of the fifth sub-channel is greater than the reliability of the fourth sub-channel (that is, it is considered that the reliability corresponding to the fifth sub-channel in the fourth coupling sub-block with a later sequence number is greater), or, the reliability of the fourth sub-channel is greater than the reliability of the fifth sub-channel (that is, it is considered that the reliability corresponding to the fourth sub-channel in the third coupling sub-block with an earlier sequence number is greater).

[0461] Case 2: The first coupling sub-block includes a first sub-block and a second sub-block.

[0462] For example, the first coupled sub-block includes the first sub-block u1 and the second sub-block u2. The first sub-block is the second sub-block u2, the second sub-block is the first sub-block u1, and the information bits on the second sub-block u2 are copied from the information bits on the first sub-block u1. If the first coupled sub-block includes 3 information bits, the number of information bits carried on the first sub-block u1 is 2. Then, according to the second reliability sequence, the sub-channel with the highest reliability in the second sub-block u2 is selected as the sub-channel carrying the information bits copied from the first sub-block u1; or, the sub-channel with medium reliability in the second sub-block u2 is selected as the sub-channel carrying the information bits copied from the first sub-block u1.

[0463] 3. Introduce implementation method 3 in combination with step 2e.

[0464] Step 2e: Determine the subchannel sequence number carrying the information bits on the first sub-block according to the preset third reliability sequence.

[0465] The third reliability sequence includes the reliability ranking of the sub-channels of the T sub-blocks, and the information bits carried by the first sub-block are obtained by copying the information bits on the second sub-block.

[0466] The representation method of the third reliability sequence is similar to that of the first reliability sequence. For details, please refer to the introduction of the representation method of the first reliability sequence, which will not be repeated here.

[0467] For example, if the code length of each sub-block in the T sub-blocks is N, then the code length of the T sub-blocks is M=T*N. It can be seen that the third reliability sequence includes the reliability ranking of the M sub-channels of the T sub-blocks. The reliability ranking of the N sub-channels of the first sub-block is determined according to the third reliability sequence; then, the X sub-channels with the reliability ranking in the top X among the N sub-channels of the first sub-block are selected, and the sequence numbers of the X sub-channels are used as the sub-channel sequence numbers carrying the information bits on the first sub-block. Among them, X is the number of information bits carried on the first sub-block.

[0468] 4. Combine step 2f to introduce implementation method 4.

[0469] Step 2f: Determine the subchannel sequence number of the first sub-block that carries the information bits according to the fourth reliability sequence.

[0470] The fourth reliability sequence is obtained by calculation, and includes the reliability ranking of the sub-channels of the T sub-blocks. The generation process of the fourth reliability sequence is described below:

[0471] The reliabilities of all subchannels corresponding to the T subblocks are calculated, and the reliabilities of all subchannels are sorted in descending order to obtain a fourth reliability sequence, wherein the fourth reliability sequence includes the reliability sorting of the subchannels of the T subblocks, and the information bits carried by the first subblock are obtained by copying the information bits on the second subblock.

[0472] The representation method of the fourth reliability sequence is similar to that of the first reliability sequence. For details, please refer to the introduction of the representation method of the fourth reliability sequence, which will not be repeated here.

[0473] Since the code length of each sub-block is N, the fourth reliability sequence of the sub-channel of the T sub-blocks is N*T. The calculation of the fourth reliability sequence includes the reliability calculation within each sub-block and the reliability calculation between sub-blocks. The reliability calculation method within the sub-block is the same as the reliability calculation method within the existing polar short code.

[0474] Optionally, when the codeword coupling relationship between the sub-blocks is different, the method of calculating the reliability of the sub-channel is also different. Figure 3 and Figure 4J , a method for calculating the reliability of a subchannel is introduced through a specific example.

[0475] Depend on Figure 3 As shown in the figure, there is a codeword coupling relationship between two adjacent sub-blocks. Figure 4J , is the third reliability of the i-th sub-block, is the calculated fifth reliability of the i-th sub-block, where i is an integer between 1 and 8. f is calculated as: f(m1, m2) = φ -1 (1-(1-φ(m1))(1-φ(m2))), where

[0476] φ -1 (x) is the inverse function of φ(x).

[0477] See also Figure 4J , the fourth reliability m1 of the first sub-block is the third reliability of the first sub-block Then for m1 and Perform f operation to obtain the fourth reliability m2 of the second sub-block. Then calculate m2 and Perform f operation to obtain the fourth reliability m3 of the third sub-block, and so on until the fourth reliability of the eighth sub-block is obtained. It can be expressed as

[0478] See also Figure 4J , first determine the fifth reliability of the 8th sub-block is the fourth reliability m8 of the 8th sub-block. Then determine the fifth reliability m8 of the 7th sub-block. for The fifth reliability of the sixth sub-block is determined by adding m7. for The sum of m6 and m1 is calculated by analogy until the fifth reliability of the first sub-block is obtained. It can be expressed as:

[0479] Then, the fifth reliability of each sub-block is input into the reliability calculation module respectively, and the reliability of the sub-channel on each sub-block is calculated by the reliability calculation module respectively.

[0480] Step 3: Determine the subchannel number carrying the information bits on the second sub-block.

[0481] The following introduces step 3 in combination with the four possible implementation methods provided in step 2.

[0482] 1. Based on implementation mode 1 provided in step 2, step 3 specifically includes: selecting, according to the first reliability sequence, the sequence number of the sub-channel on the second sub-block for copying information bits of the first sub-block.

[0483] For example, the sequence numbers of X subchannels with lower reliability are selected from the subchannels carrying information bits on the second sub-block according to the first reliability sequence. Figure 4D As shown, the second sub-block is the first sub-block u1, and the sub-channels used to carry information bits on the first sub-block u1 include sub-channel 1, sub-channel 5, sub-channel 6 and sub-channel 7. For the second reliability sequence r={r1, r5, r6, r7, r2, r3, r4, r8}, sub-channel 6 and sub-channel 7 of the first sub-block u1 with lower reliability are selected as sub-channels for copying information bits of the first sub-block; or, sub-channel 5 and sub-channel 6 of the first sub-block u1 with medium reliability are selected as sub-channels for copying information bits of the first sub-block.

[0484] 2. Based on the implementation method 2 provided in step 2, step 2 specifically includes: selecting the sequence number of the subchannel on the second subblock for copying the information bits of the first subblock according to the second reliability sequence. The specific execution process of this implementation method is similar to the selection process based on the implementation method 1 provided in step 2, and please refer to the selection process based on the implementation method 1 provided in step 2 for details.

[0485] 3. Based on the implementation method 3 provided in step 2, step 2 specifically includes: selecting the sequence number of the subchannel on the second subblock for copying the information bits of the first subblock according to the third reliability sequence. The specific execution process of this implementation method is similar to the selection process based on the implementation method 1 provided in step 2, and please refer to the selection process based on the implementation method 1 provided in step 2 for details.

[0486] 4. Based on the implementation method 3 provided in step 2, step 2 specifically includes: selecting the sequence number of the subchannel on the second subblock for copying the information bits of the first subblock according to the fourth reliability sequence. The specific execution process of this implementation method is similar to the selection process based on the implementation method 1 provided in step 2, and please refer to the selection process based on the implementation method 1 provided in step 2 for details.

[0487] Step 4: Establish a mapping relationship between the sub-channel carrying information bits on the first sub-block and the sub-channel carrying information bits on the second sub-block.

[0488] Specifically, a mapping relationship between the sequence number of the subchannel carrying the information bit on the first subblock and the sequence number of the subchannel carrying the information bit on the second subblock is generated. The mapping relationship is used to determine which subchannels on the first subblock are used to place the copied information bits and from which subchannels of the second subblock the first subblock will copy the information bits carried by the first subblock.

[0489] 402. Perform polarization coding on the input vector to obtain coded bits.

[0490] In a possible implementation, polarization coding is performed on the input vector through a first generator matrix to obtain coded bits. That is, the first generator matrix can reflect the codeword coupling relationship between the T sub-blocks.

[0491] The first generation matrix is ​​generated according to the second generation matrix, the second generation matrix includes at least two matrix blocks distributed according to a preset position relationship, and the matrix block includes multiple first generation matrix cores. The first generation matrix includes A matrix blocks, and the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, and A is a positive integer.

[0492] First, we introduce the first generation matrix kernel and matrix block.

[0493] The first generator matrix kernel can be G N , the code length of each of the T sub-blocks is the same as the dimension of the first generator matrix core. N is the code length of each of the T sub-blocks, N = 2 n , n is a positive integer. In actual application, the size of N can be set according to actual needs, for example, N can be a preset value.

[0494] Combine the following Figure 4K An example of G N The construction process:

[0495] Assuming that the code length of the sub-block is 4, the dimension of the identity matrix is ​​4, such as Figure 4K As shown, the identity matrix is If it is determined by calculation that the identity matrix is ​​subjected to three circular shifts, then the identity matrix After a circular shift, we get The circular shift refers to circularly shifting the element "1" in the matrix within the row where the element "1" is located. Perform a circular shift and get And then Perform a circular shift and get The first matrix kernel For other lengths of the first matrix kernel G N The construction process of is similar and will not be explained here one by one.

[0496] The matrix block may include a first generation matrix kernel and a 0 matrix (which may be represented as 0 N ). The size of the first generation matrix core is the same as the size of the 0 matrix. For example, assuming that the size of the first generation matrix core is N*N, the size of the 0 matrix is ​​also N*N. For ease of description, hereinafter, the first generation matrix core or the 0 matrix is ​​referred to as a matrix unit.

[0497] It should be noted that, in the embodiment of the present application, the size of the matrix refers to the number of rows and columns in the matrix, and the size of the matrix can be represented by R*S (R is the number of rows of the matrix, and S is the number of columns of the matrix). When the matrix is ​​a square matrix (square matrix), the size of the matrix can be represented by the number of rows or columns. For example, when the matrix includes R rows and R columns, the size of the matrix can be represented by R*R, or by R.

[0498] Combine the following Figure 5 The matrix block is described.

[0499] Figure 5 A schematic diagram of a matrix block provided in an embodiment of the present application. Figure 5 , the matrix block includes multiple matrix units, Figure 5 Taking the number of matrix units as 16 as an example, each matrix unit includes N*N elements, for example, the elements can be 0 or 1. The matrix unit can be G N or 0 N . Assuming N is 2, then

[0500] Optionally, the first diagonal of the matrix block includes a first generator matrix kernel (G N ). The first diagonal can be the main diagonal of the matrix block. For example, see Figure 5 , the matrix unit located on the main diagonal of the matrix block is G N , such as the (1,1), (2,2), (3,3), (4,4)th matrix unit is G N .

[0501] Optionally, the plurality of first generation matrix cores in the matrix block are distributed in a triangle. Figure 5 , multiple G in the matrix block N The following triangle distribution.

[0502] Optionally, the distribution of the first generation matrix core in the matrix block is the same as the distribution of the first element in the second generation matrix core, and the first element may be 1. Distribution of elements in the second generation matrix core The number of elements in the second generator matrix core may be the same as or different from the number of elements in the first generator matrix core. For example, assuming that the second generator matrix core is Matrix blocks such as Figure 5 As shown, the matrix block G N The distribution of 1 is the same as that of 1 in the second generation matrix kernel. Correspondingly, the distribution of 0 in the matrix block N The distribution of is the same as the distribution of 0 in the second generator matrix kernel.

[0503] The matrix block is explained below through a specific example.

[0504] Example 1: Assume that the second generator matrix kernel is Then the matrix block can be The number of matrix units included in the matrix block is 2*2. N The distribution of is the same as the distribution of element 1 in the second generator matrix kernel.

[0505] Assume N = 2, then Will Substitute G into the above matrix block N , we can get the matrix block as:

[0506] Assume N = 4, then Will Substitute G into the above matrix block N , we can get the matrix block as:

[0507] Example 2: Assume that the second generator matrix kernel is Then the matrix block can be Matrix block G N The distribution of is the same as the distribution of element 1 in the second generator matrix kernel.

[0508] Assume N = 2, then Will Substitute G into the above matrix block N , we can get the matrix block as:

[0509] Example 3: Assume that the second generator matrix kernel is Then the matrix block can be The number of matrix units included in the matrix block is 2*2. N The distribution of is the same as the distribution of element 1 in the second generator matrix kernel.

[0510] Assume N = 2, then Will Substitute G into the above matrix block N , we can get the matrix block as:

[0511] Assume N = 4, then Will Substitute G into the above matrix block N , we can get the matrix block as:

[0512] Example 4: Assume that the second generator matrix kernel is Then the matrix block can be Matrix block G NThe distribution of is the same as the distribution of element 1 in the second generator matrix kernel.

[0513] Assume N = 2, then Will Substitute G into the above matrix block N , we can get the matrix block as:

[0514] The second generation matrix includes at least two matrix blocks distributed according to a preset position relationship. Optionally, the number of matrix blocks included in the second generation matrix may be 2.

[0515] Optionally, there are overlapping parts in at least two matrix blocks in the second generation matrix. For example, there are overlapping parts in every two adjacent matrix blocks in the second generation matrix, assuming that the two adjacent matrix blocks are matrix block 1 and matrix block 2, and the elements in the lower right corner area of ​​matrix block 1 overlap with the elements in the upper left corner area of ​​matrix block 2.

[0516] For example, when the second generation matrix includes two matrix blocks (respectively recorded as matrix block 1 and matrix block 2), the preset position relationship can be: matrix block 1 is located in the upper left part of the second generation matrix, matrix block 2 is located in the lower right part of the second generation matrix, and the lower right corner area of ​​matrix block 1 coincides with the upper left corner area of ​​matrix block 2.

[0517] Next, combine FIG. 6A to FIG. 6D The second generation matrix is ​​described.

[0518] Fig. 6A A schematic diagram of a second generation matrix provided in an embodiment of the present application. Figure 6B A schematic diagram of another second generation matrix provided in an embodiment of the present application. Figure 6C A schematic diagram of another second generation matrix provided in an embodiment of the present application. Fig.6D A schematic diagram of another second generation matrix provided in an embodiment of the present application.

[0519] See also Fig. 6A , the second generation matrix includes two matrix blocks, which are respectively recorded as the first matrix block and the second matrix block, and the first matrix block and the second matrix block are the same. The first matrix block is located in the upper left part of the second generation matrix, and the second matrix block is located in the lower right part of the second generation matrix. The lower right corner area of ​​the first matrix block overlaps with the upper left corner area of ​​the second matrix block, and the elements in the lower right corner area of ​​the first matrix block are distributed in the same manner as the elements in the upper left corner area of ​​the second matrix block.

[0520] See also Figure 6B The second generation matrix includes a first matrix block and a second matrix block, and the first matrix block and the second matrix block are respectively Then the second generator matrix can be The first matrix block is located at the upper left portion of the second generation matrix, and the second matrix block is located at the lower right portion of the second generation matrix. The first matrix unit in the first matrix block coincides with the second matrix unit in the second matrix block. The coordinates of the first matrix unit in the first matrix block are (2,2), and the coordinates of the second matrix unit in the second matrix block are (1,1).

[0521] See also Figure 6C The second generation matrix includes a first matrix block and a second matrix block, and the first matrix block and the second matrix block are respectively Then the second generator matrix can be The first matrix block is located in the upper left part of the second generation matrix, and the second matrix block is located in the lower right part of the second generation matrix. The four first matrix units in the first matrix block overlap with the four second matrix units in the second matrix block. The coordinates of the four first matrix units in the first matrix block are: (3,3), (3,4), (4,3), (4,4); the coordinates of the four second matrix units in the second matrix block are: (1,1), (1,2), (2,1), (2,2).

[0522] See also Fig.6D The second generation matrix includes a first matrix block and a second matrix block, and the first matrix block and the second matrix block are respectively Then the second generator matrix can be The first generation matrix block is located in the upper left part of the second generation matrix, and the second matrix block is located in the lower right part of the second generation matrix. The four first matrix units in the first matrix block overlap with the four second matrix units in the second matrix block. The coordinates of the four first matrix units in the first matrix block are: (5,5), (5,6), (6,5), (6,6); the coordinates of the four second matrix units in the second matrix block are: (1,1), (1,2), (2,1), (2,2)

[0523] It should be noted that for the convenience of description and viewing, Figure 6B-6D 0 is omitted in the figure N The annotation, that is, Figure 6B-6C The blank matrix cells are all 0 N .

[0524] The first generator matrix is ​​introduced below.

[0525] Specifically, the number A of matrix blocks included in the first generation matrix can be determined according to the second generation matrix, the size of the matrix block and the code length M of the T sub-blocks, and the first generation matrix can be generated according to the second generation matrix and the number A.

[0526] Optionally, A is a minimum integer that first satisfies a first condition, and the first condition is that the size of the first generator matrix is ​​greater than or equal to the code length M of the T sub-blocks. The first generator matrix is ​​a square matrix, and the size of the first generator matrix can be represented by the number of rows or columns included in the first generator matrix, that is, the size of the first generator matrix is ​​the number of rows or columns included in the first generator matrix.

[0527] For example, A satisfies the following relationship:

[0528] v+(A-2)*g <M≤v+(A-1)*g;

[0529] v is the size of the matrix block (the matrix block is a square matrix, and v represents the number of rows or columns of elements included in the matrix block). M is the code length of the T sub-blocks, and M is an integer greater than 1. g is the distance between two matrix blocks, and the distance between the two matrix blocks can be represented by the distance (row number difference or column number difference) between the first elements in two adjacent matrix blocks (for example, the first element can be the element with coordinates (1, 1) in the matrix block).

[0530] For example, assuming that the size v of the matrix block is 256, the code length of the T sub-blocks is 512, and the distance g between two adjacent matrix blocks is 128, then A is 3.

[0531] For example, assuming that the size v of the matrix block is 384, the code length of the T sub-blocks is 512, and the distance g between two adjacent matrix blocks is 128, then A is 2.

[0532] Combine the following 7A to 7C The first generation matrix is ​​described using a specific example.

[0533] Fig. 7A A schematic diagram of a first generation matrix provided in an embodiment of the present application. Fig. 7A The second generation matrix includes two matrix blocks, each of which includes 16 matrix units, some of which are G N , some matrix cells are 0 N The positional relationship between the two matrix blocks is as follows: Fig. 7A shown.

[0534] Assuming that the size of each matrix unit is 64 (including 64 rows and 64 columns), the size of the matrix block is 256, the distance between the two matrix blocks in the second generation matrix is ​​128, and assuming that the code length M of the T sub-blocks is 512, the first generation matrix includes 3 matrix blocks, which are respectively recorded as matrix block 1, matrix block 2 and matrix block 3. The positional relationship between every two adjacent matrix blocks in the three matrix blocks is the same as the positional relationship between the two matrix blocks in the second generation matrix. The size of the first generation matrix (the number of rows or columns included in the first generation matrix) is 512.

[0535] Figure 7B This is a schematic diagram of another first generation matrix provided in an embodiment of the present application. Figure 7B , assuming that the second generation matrix includes two matrix blocks, each matrix block includes 36 matrix units, and some matrix units are G N , some matrix cells are 0 N The positional relationship between the two matrix blocks is as follows: Figure 6B shown.

[0536] Assuming that the size of each matrix unit is 64 (including 64 rows and 64 columns), the size of the matrix block is 384, the distance between the two matrix blocks in the second generation matrix is ​​128, and assuming that the code length M of the T sub-blocks is 512, the first generation matrix includes 2 matrix blocks, which are respectively recorded as matrix block 1 and matrix block 2. The positional relationship between each two adjacent matrix blocks in the two matrix blocks is the same as the positional relationship between the two matrix blocks in the second generation matrix. The size of the first generation matrix (the number of rows or columns included in the first generation matrix) is 640.

[0537] Figure 7C A schematic diagram of another first generation matrix provided in an embodiment of the present application. Figure 7C , assuming that the second generation matrix includes two matrix blocks, each matrix block includes 4 matrix units, and some matrix units are G N , some matrix cells are 0 N The positional relationship between the two matrix blocks is as follows: Figure 7C shown.

[0538] Assuming that the size of each matrix unit is 128 (including 128 rows and 128 columns), the size of the matrix block is 256, the distance between the two matrix blocks in the second generation matrix is ​​128, and assuming that the code length M of the T sub-blocks is 1024, the first generation matrix includes 7 matrix blocks, which are respectively recorded as matrix block 1, matrix block 2, ..., matrix block 6 and matrix block 7. The positional relationship between every two adjacent matrix blocks in the 7 matrix blocks is the same as the positional relationship between the two matrix blocks in the second generation matrix. The size of the first generation matrix (the number of rows or columns included in the first generation matrix) is 1024.

[0539] It should be noted that in Figure 7A-7C In addition to G N All matrix cells outside are 0 N , for the convenience of description and viewing, 0 is omitted in the figure N The annotation, that is, Figure 7A-7C The blank matrix cells are all 0 N .

[0540] It should be noted that Figure 7A-7CThe first generation matrix is ​​merely illustrated in an exemplary form, and is not intended to be limiting. Of course, the first generation matrix may also be other, and the embodiments of the present application do not specifically limit this.

[0541] The following describes a process of performing polarization coding on an input vector by using a first generator matrix to obtain coded bits.

[0542] If the size of the first generator matrix is ​​equal to the code length M of the T sub-blocks, the input vector is polarized encoded according to the first generator matrix to obtain encoded bits. Fig. 7A The first generator matrix shown is the aforementioned Figure 4B In the first generation matrix shown in FIG. , four adjacent sub-blocks have a codeword coupling relationship. Figure 4B As shown, the input vector is multiplied by the first generator matrix to obtain the encoded bits.

[0543] If the size of the first generation matrix is ​​greater than the code length M of the T sub-blocks, the third generation matrix is ​​first determined in the first generation matrix, and the input vector is polarized encoded according to the third generation matrix to obtain the encoded bits. The third generation matrix is ​​a matrix intercepted in the upper left corner area of ​​the first generation matrix, or the third generation matrix is ​​a matrix intercepted in the lower right corner area of ​​the first generation matrix. The third generation matrix is ​​a square matrix.

[0544] Combine the following Fig. 8A and Figure 8B , the third generation matrix is ​​explained.

[0545] Fig. 8A A schematic diagram of a third generation matrix provided in an embodiment of the present application. Fig. 8A Assuming that the code length of the T sub-blocks is 512 and the size of the first generation matrix is ​​640, a matrix with a size of 512 can be intercepted at the upper left corner of the first generation matrix as the third generation matrix.

[0546] Figure 8B This is a schematic diagram of another third generation matrix provided in an embodiment of the present application. Figure 8B Assuming that the code length of the T sub-blocks is 512 and the size of the first generation matrix is ​​640, a matrix with a size of 512 can be intercepted at the lower right corner of the first generation matrix as the third generation matrix.

[0547] In one possible implementation, Figure 4A The illustrated embodiment further includes step 403 .

[0548] 403. Obtain K bits to be encoded.

[0549] The bit to be encoded is an information bit, that is, the bit to be encoded is a bit carrying specific information, and K is a positive integer.

[0550] Optionally, the second information bit on the second sub-block is an information bit in the bit to be encoded, or is an information bit obtained by copying the bit to be encoded. Then the first information bit on the first sub-block is an information bit obtained by copying the bit to be encoded; or, the first information bit on the first sub-block is an information bit obtained by copying the second information bit on the second sub-block, and the second information bit on the second sub-block is an information bit obtained by copying the bit to be encoded.

[0551] Next, pass Fig.9A and Fig. 9B Some examples in the embodiments of the present application are shown again.

[0552] See also Fig.9A , Fig.9A In the input vector, there is an information coupling relationship between adjacent sub-blocks, and there is a codeword coupling relationship between four adjacent sub-blocks. It is set that some of the T sub-blocks have an information coupling relationship and some of the T sub-blocks have a codeword coupling relationship, thereby reducing the complexity of encoding and decoding while ensuring the coding gain.

[0553] See also Fig. 9B , Fig. 9B In the input vector, there is an information coupling relationship between adjacent sub-blocks, and there is a codeword coupling relationship between the 8 sub-blocks. It is set that some of the 8 sub-blocks have an information coupling relationship, so as to reduce the complexity of encoding and decoding while ensuring the coding gain.

[0554] It can be seen that a flexible code construction framework is provided in the embodiment of the present application, and the code construction framework includes code construction, encoding process and decoding process. In the code construction process, appropriate information coupling and codeword coupling can be set to obtain performance gain similar to IR-HARQ, providing a flexible compromise between the complexity of encoding and decoding and performance gain. A smaller information coupling can be set to save hardware overhead and avoid complex switching networks due to information replication processes.

[0555] In the embodiment of the present application, the maximum mother code length supported by the hardware resources (e.g., decoder chip) has certain limitations, for example, Nmax=1024 or Nmax=512 or Nmax=256. Often, a larger codeword coupling degree can bring better performance gain. Therefore, it is necessary to compromise between encoding and decoding complexity and performance gain.

[0556] Several schemes of codeword coupling degree adopted by the transmitter for retransmission are shown below.

[0557] 1. Determine the maximum supported codeword coupling degree based on the maximum mother code length and the code length of the initial transmission sub-block. When the total code length of the sub-blocks sent by the transmitter to the receiver (including the initial transmission sub-blocks and the retransmitted sub-blocks) is less than the maximum mother code length, the transmitter can use a larger codeword coupling degree (but not greater than the maximum codeword coupling degree) for retransmission (similar to the retransmission method of IR-HARQ). When the sub-blocks sent by the transmitter to the receiver (including the total code length of the initial transmission sub-blocks and the retransmitted sub-blocks) reach or exceed the maximum mother code length, the codeword coupling degree will no longer be increased, and the transmitter can use a fixed codeword coupling degree for retransmission (for example, the maximum codeword coupling degree can be used for retransmission, similar to the retransmission method of IR-HARQ), which can fully utilize hardware resources and ensure performance gains. In this way, the calculation method of the maximum codeword coupling degree includes the following two methods:

[0558] 1. The code length of the initial sub-block is N, and the initial mother code length is in, To round x upwards. max is the maximum mother code length specified by the communication protocol, or the maximum code length supported by the decoder. Then the maximum codeword coupling degree is p = N max / N0. The codeword coupling degree refers to the number of sub-blocks having codeword coupling relationship among the T sub-blocks.

[0559] 2. The code length of the first transmitted sub-block is N, N max is the maximum mother code length specified by the communication protocol, or is the maximum code length supported by the decoder, then the maximum codeword coupling degree is in The floor of x.

[0560] 2. Determine the maximum supported codeword coupling degree according to the first target code length and the code length of the initial transmission sub-block. When the total code length of the sub-blocks (including the initial transmission sub-blocks and the retransmission sub-blocks) sent by the transmitter to the receiver is less than the first target code length, the transmitter can use a larger codeword coupling degree (but not greater than the maximum codeword coupling degree) for retransmission (similar to the retransmission method of IR-HARQ). When the total code length of the sub-blocks (including the initial transmission sub-blocks and the retransmission sub-blocks) sent by the transmitter to the receiver is greater than or equal to the first target code length, the codeword coupling degree is no longer increased, and the transmitter can use a fixed codeword coupling degree for retransmission (for example, the maximum codeword coupling degree can be used for retransmission (similar to the retransmission method of IR-HARQ). When the total code length of the sub-blocks sent by the transmitter to the receiver is greater than or equal to the second target code length, no encoding is performed, and the transmitter repeats the retransmission sub-blocks that have been sent in a certain order (similar to the retransmission method of CC-HARQ).

[0561] The first target code length N1 and the second target code length N2 are specified in the communication protocol. The first target code length N1 can be understood as the maximum mother code length specified in the communication protocol, or the maximum mother code length supported by the decoder.

[0562] For example, the code length of the initial sub-block is N, and the initial mother code length is in, is rounded upwards for x. When the total code length of the sub-blocks sent by the transmitter to the receiver (including the initially transmitted sub-blocks and the retransmitted sub-blocks) is K, the maximum codeword coupling degree is p1 = N1 / N0 or The relationship among N0, N1, and N2 is N0≤N1≤N2. When K is less than N1, the largest possible codeword coupling (but not greater than the maximum codeword coupling p1) is used for retransmission; when the total code length K is greater than or equal to the first target code length N1 and less than or equal to the second target code length N2, the codeword coupling p1 is still used for retransmission; when the total code length K is greater than N2, the transmitter no longer encodes and repeatedly sends the encoded bits.

[0563] 3. Determine the code coupling degree used in retransmission based on the total code rate of the sub-blocks sent by the transmitter to the receiver. When the total code rate of the sub-blocks sent by the transmitter to the receiver (including the sub-blocks sent initially and the sub-blocks retransmitted) is less than the first preset target code rate, the transmitter adopts a larger code coupling degree (not greater than the first preset code coupling degree) for retransmission (similar to the retransmission method of IR-HARQ); when the total code rate of the sub-blocks sent by the transmitter to the receiver (including the sub-blocks sent initially and the sub-blocks retransmitted) is greater than or equal to the first preset target code rate and less than or equal to the second preset target code rate, the transmitter adopts a fixed code coupling degree (for example, the first preset code coupling degree, similar to the retransmission method of IR-HARQ) for retransmission; when the total code rate of the sub-blocks sent by the transmitter to the receiver (including the sub-blocks sent initially and the sub-blocks retransmitted) is greater than the second preset target code rate, the transmitter no longer encodes and repeatedly sends the encoded bits (similar to the retransmission method of CC-HARQ).

[0564] Example 2: Assume that the initial transmission code length is N, the information bits are K, and the initial transmission code rate is R0 = K / N. Assume that the total code length of the initial transmission sub-blocks and retransmission sub-blocks already sent from the current transmitter to the receiver is M. Assume that the total code rate is R = K / M. Assume that R1 is the first preset target code rate specified by the communication protocol, and p1 is the coupling degree 1 specified by the communication protocol. R2 is the second preset target code rate specified by the communication protocol. The relationship among R0, R1, and R2 is R0≥R1≥R2. Then when the total code rate R of the initial transmission sub-blocks and retransmission sub-blocks is < R1, the transmitter performs retransmission with the largest possible codeword coupling degree (but the adopted codeword coupling degree p < p1); when the total code rate R of the initial transmission sub-blocks and retransmission sub-blocks satisfies R1≤R≤R2, the transmitter still performs retransmission with the codeword coupling degree p1; when the total code rate R of the initial transmission sub-blocks and retransmission sub-blocks is > R2, the transmitter stops encoding and repeats the already encoded bits.

[0565] It can be seen from this that the retransmission method in the embodiments of the present application is integrated with IR-HARQ and CC-HARQ, and is more competitive in terms of performance gain and encoding / decoding complexity.

[0566] In the embodiments of the present application, K bits to be encoded are obtained, where K is a positive integer; then, an input vector is generated, and the input vector includes T sub-blocks. The first information bits on the first sub-block are copied from the second information bits on the second sub-block, where the first sub-block and the second sub-block are sub-blocks among the T sub-blocks, and the sequence number of the first sub-block is after the sequence number of the second sub-block, and T is an integer between 2 and T; then, polar encoding is performed on the input vector to obtain the encoded bits. It can be seen from this that during the encoding process, the first information bits on the first sub-block are copied from the second information bits on the second sub-block, which is equivalent to setting the information coupling relationship between the first sub-block and the second sub-block, so that there is a check relationship between the first information bits on the first sub-block and the second information bits on the second sub-block. Then, during the encoding / decoding process, encoding / decoding can be performed according to the information coupling relationship between the first sub-block and the second sub-block, thereby reducing the encoding / decoding complexity.

[0567] Next, in combination with Fig. 10A introduce another encoding method. Fig. 10A is a schematic diagram of another embodiment of the encoding method in the embodiments of the present application. Please refer to Fig. 10A , the method includes:

[0568] 1001. Generate an input vector.

[0569] Among them, the input vector includes information bits carried on sub-channels, and some of the sub-channels carrying information bits carry the same information bits.

[0570] Specifically, the information bits carried on the subchannel include the K bits to be encoded. The subchannels carrying the information bits carry the same information bits, including the following two possible situations. Fig. 10B and Fig. 10C Give examples.

[0571] See also Fig. 10B , the input vector includes the bits carried on subchannels 1 to 16. The K bits to be encoded are the information bit "1" carried on subchannels 1, 5, 6 and 7 respectively. The information bit "1" carried on subchannel 11 is copied from the information bit "1" carried on subchannel 5, and the information bit "1" carried on subchannel 12 is copied from the information bit "1" carried on subchannel 6. That is, it can be understood that subchannels 11 and subchannel 6 carry the same information bits, and subchannels 12 and subchannel 7 carry the same information bits. And subchannels 11 and 12 copy some of the K bits to be encoded.

[0572] See also Fig. 10B and Fig. 10C , the input vector includes the bits carried on subchannel 1 to subchannel 24. Fig. 10B For related introductions, please refer to the previous paragraph. The information bit "1" carried on subchannel 17 is copied from the information bit "1" carried on subchannel 12, and the information bit "1" carried on subchannel 12 is copied from the information bit "1" carried on subchannel 6. Subchannel 12 and subchannel 7 carry the same information bit, and subchannel 7 carries a bit among the K bits to be encoded.

[0573] Optionally, the input vector also includes other new information bits or frozen bits. In subsequent embodiments or implementations, the frozen bits are also used as an example for illustration.

[0574] 1002. Perform polarization coding on the input vector to obtain coded bits.

[0575] Optional, Fig. 10A The illustrated embodiment also includes step 1003 .

[0576] Step 1003: Obtain K bits to be encoded.

[0577] Step 1003 and the aforementioned Figure 4A Step 403 in the embodiment shown is similar, please refer to the aforementioned Figure 4A The detailed description of step 403 in the illustrated embodiment will not be repeated here.

[0578] The following describes the above Figure 4AAnother description method of step 402 in the illustrated embodiment.

[0579] In a possible implementation, step 402 specifically includes:

[0580] Polarization encoding is performed on the input vector using a first generator matrix to obtain encoded bits.

[0581] That is, the first generation matrix can reflect the codeword coupling relationship between the encoded bit sequences corresponding to the T sub-blocks included in the input vector.

[0582] The first generation matrix is ​​generated according to the second generation matrix, the second generation matrix includes at least two matrix blocks distributed according to a preset position relationship, and the matrix block includes multiple first generation matrix cores. The first generation matrix includes A matrix blocks, and the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, and A is a positive integer.

[0583] The second generator matrix is ​​equivalent to Figure 4A The matrix blocks in the embodiment shown are: Figure 4A The description of the matrix block in the illustrated embodiment can be referred to as the second generation matrix herein, which will not be described in detail here.

[0584] The second generating matrix includes a first submatrix block and a second submatrix block, the first submatrix block is located at the upper left corner of the second submatrix block, the second submatrix block is located at the lower right corner of the first generating matrix, the first submatrix block and the second submatrix block are the same, and along the diagonal direction of the second generating matrix, the distance between the first element in the first submatrix block and the second element in the second submatrix block (hereinafter also referred to as the distance between the first submatrix block and the second submatrix block) is u, and u is an integer greater than or equal to 1.

[0585] Optionally, the first element may be an element at the upper left corner of the first submatrix block, and the second element may be an element at the upper left corner of the second submatrix block. The distance between the first element and the second element refers to the difference in row numbers or column numbers between the first element and the second element. For example, the first element is 0 or 1.

[0586] In the second generation matrix, all elements except the first sub-matrix block and the second sub-matrix block may be 0 elements.

[0587] Optionally, the first sub-matrix block and the second sub-matrix block may include one or more matrix units, and the matrix unit may be G N or 0 N The first sub-matrix block and the second sub-matrix block are both square matrices. N and 0 N For a description of Figure 4A The embodiment shown.

[0588] The second generation matrix satisfies self-similarity (or shift self-similarity), which means that after the first submatrix block in the second generation matrix is ​​moved (for example, along the main diagonal of the first generation matrix) by a preset matrix, the first submatrix block can be moved to the position where the second submatrix block is located, and the contents of the first submatrix block and the second submatrix block are the same. When the second generation matrix has similarity, the elements in the second generation matrix: a i,j =a i+u,j+u , where i is an integer, j is an integer, v is the size of the second generator matrix, v is a positive integer, u is an integer, 1≤i <v,1≤j<v,1<i+u≤v,1<j+u≤v。

[0589] Combine the following FIG. 11A to FIG. 11C , the second generation matrix includes a first sub-matrix block and a second sub-matrix block.

[0590] Fig.11A A schematic diagram of a second generation matrix provided in an embodiment of the present application. Fig.11A The first generation matrix includes a first sub-matrix block and a second sub-matrix block, the first sub-matrix block is located at the upper left corner (or, called the upper left corner region) of the second generation matrix, and the second sub-matrix block is located at the lower right corner (or called the upper right corner region) of the second generation matrix. The first sub-matrix block and the second sub-matrix block are the same. The first sub-matrix block and the second sub-matrix block partially overlap.

[0591] Fig. 11B A schematic diagram of another second generation matrix provided in an embodiment of the present application. Fig. 11B , the second generation matrix includes a first submatrix block and a second submatrix block, the first submatrix block is located at the upper left corner (or called the upper left corner region) of the second generation matrix, and the second submatrix block is located at the lower right corner (or called the lower right corner region) of the second generation matrix. The first submatrix block and the second submatrix block are the same. There is a certain distance between the first submatrix block and the second submatrix block, that is, there is a certain distance between an element at the lower right corner of the first submatrix block (referred to as element 1) and an element at the upper left corner of the second submatrix block (referred to as element 2), for example, the difference between the row numbers of element 2 and element 1 is greater than 1.

[0592] Fig. 11C This is a schematic diagram of another second generation matrix provided in an embodiment of the present application. Fig. 11C, the second generation matrix includes a first submatrix block and a second submatrix block, the first submatrix block is located at the upper left corner (or called the upper left corner region) of the second generation matrix, and the second submatrix block is located at the lower right corner (or called the lower right corner region) of the second generation matrix. The first submatrix block and the second submatrix block are the same. The first submatrix block and the second submatrix block are adjacent, that is, an element at the lower right corner of the first submatrix block (referred to as element 1) is adjacent to an element at the upper left corner of the second submatrix block (referred to as element 2), for example, the row number of element 2 is 1 greater than the row number of element 1, and the column number of element 2 is 1 greater than the column number of element 1.

[0593] Optionally, the elements in the second generator matrix are symmetric along a secondary diagonal line of the second generator matrix.

[0594] The second generation matrix is ​​illustrated below by using a specific example.

[0595] Fig. 12A A schematic diagram of another second generation matrix provided in an embodiment of the present application. Fig. 12A The second generation matrix includes a first sub-matrix block and a second sub-matrix block, and the first sub-matrix block and the second sub-matrix block each include a G N Assuming that N is 128, the distance between the first sub-matrix block and the second sub-matrix block is 128.

[0596] Fig. 12B A schematic diagram of another second generation matrix provided in an embodiment of the present application. Fig. 12B The second generation matrix includes a first sub-matrix block and a second sub-matrix block, and the first sub-matrix block and the second sub-matrix block each include four matrix units. Assuming that N is 128, the distance between the first sub-matrix block and the second sub-matrix block is 256.

[0597] It should be noted that for the convenience of description and viewing, Figure 12A-12B 0 is omitted in the figure N The annotation, that is, Figure 12A-12B The blank matrix cells are all 0 N . Figure 12A-12B The first generation matrix is ​​merely illustrated in an exemplary manner, and is not intended to be limiting of the first generation matrix.

[0598] The first generator matrix is ​​introduced below.

[0599] The first generating matrix includes A second generating matrices, the A second generating matrices are distributed along the diagonal of the second generating matrix (for example, the diagonal can be the main diagonal), the first submatrix block of the b+1th second generating matrix in the A second generating matrices overlaps with the second submatrix block of the bth second generating matrix, b is an integer greater than or equal to 1, and T is an integer greater than or equal to 2.

[0600] Next, combine Fig.13 , the first generation matrix is ​​explained.

[0601] Fig.13 This is a schematic diagram of another first generation matrix provided in an embodiment of the present application. Fig.13 , the first generator matrix includes 5 second generator matrices. The 5 second generator matrices are distributed along the main diagonal of the first generator matrix. Along the main diagonal of the first generator matrix extending downward and to the right, the numbers of the second generator matrices increase successively. The matrix located at the upper left corner of the first generator matrix is ​​the first second generator matrix. For example, see Fig.13 , the second generator matrix indicated by number 1 is the first second generator matrix, the second generator matrix indicated by number 2 is the second second generator matrix, and so on, the second generator matrix indicated by number 5 is the fifth second generator matrix.

[0602] See also Fig.13 , the second submatrix block of the first second generator matrix overlaps with the first submatrix block of the second second generator matrix. The second submatrix block of the second second generator matrix overlaps with the first submatrix block of the third second generator matrix. The second submatrix block of the third second generator matrix overlaps with the first submatrix block of the fourth second generator matrix. The second submatrix block of the fourth second generator matrix overlaps with the first submatrix block of the fifth second generator matrix.

[0603] Optionally, A is the minimum integer that satisfies the first condition, which is: the size of the first generation matrix is ​​greater than or equal to the code length M of the T sub-blocks included in the input vector.

[0604] For example, A satisfies the following relationship:

[0605] v+(A-2)*u <M≤v+(A-1)*u;

[0606] Wherein, v is the size of the second generation matrix, M is the code length M of the T sub-blocks included in the input vector, and M is an integer greater than 1.

[0607] For example, assuming that the size v of the matrix block is 256, the code length of the T sub-blocks included in the input vector is 512, and the distance u between two adjacent second generation matrices is 128, then A is 3.

[0608] For example, assuming that the size v of the matrix block is 384, the code length of the T sub-blocks included in the input vector is 512, and the distance u between two adjacent second generation matrices is 128, then A is 2.

[0609] Optionally, the number A of second generator matrices included in the first generator matrix may be determined according to the code lengths of the T sub-blocks included in the input vector and the second generator matrix, and the first generator matrix may be generated according to the second generator matrix and the number A. For example, the second generator matrix may be copied and moved A-1 times along the main diagonal direction of the second generator matrix to obtain the first generator matrix, each moving distance being u, where the moving distance refers to the number of rows or columns moved, for example, if 3 rows are moved, the moving distance is 3.

[0610] Combine the following Fig.14 , a process of generating a first generation matrix based on the second generation matrix is ​​described.

[0611] Fig.14 For a schematic diagram of a process for generating a first generation matrix provided in an embodiment of the present application, see Fig.14 The second generation matrix includes 16 matrix units, some of which are G N , some matrix cells are 0 N The second generator matrix satisfies self-similarity, and the distance (row distance or column distance) between the first submatrix block and the second submatrix block in the second generator matrix is ​​u. Assuming that it is determined that the first generator matrix includes three second generator matrices, the second generator matrix needs to be copied and moved twice.

[0612] See also Fig.14 In the first copy and move process, the second generator matrix 1 is copied and the copied second generator matrix 1 is moved along the main diagonal direction by u rows (the diagonal distance corresponding to the u rows is ), and obtain the second generation matrix 2. The first sub-matrix block of the second generation matrix 2 coincides with the second sub-matrix block of the second generation matrix 1.

[0613] See also Fig.14 In the second copy and move process, the second generator matrix 2 is copied and the copied second generator matrix 2 is moved along the main diagonal direction by u rows (the diagonal distance corresponding to the u rows is ), and obtain the second generation matrix 3. The first sub-matrix block of the second generation matrix 3 coincides with the second sub-matrix block of the second generation matrix 2.

[0614] Determine that the first generation matrix includes the second generation matrix 1, the second generation matrix 2, and the second generation matrix 3.

[0615] It should be noted that Fig.14 This is just an example to illustrate a method of generating a first generation matrix based on a second generation matrix, and is not intended to limit this method. Fig.14 In addition to G N All matrix cells outside are 0 N, for the convenience of description and viewing, 0 is omitted in the figure N The annotation, that is, Fig.14 The blank matrix cells are all 0 N .

[0616] Fig.15A A schematic diagram of a first generation matrix provided in an embodiment of the present application. Fig.15A The second generation matrix includes 16 matrix units, some of which are G N , some matrix cells are 0 N The second generator matrix satisfies self-similarity.

[0617] Assuming that the size of each matrix unit is 64 (including 64 rows and 64 columns), the size of the second generator matrix is ​​512, the distance between the two first generator matrices in the second generator matrix is ​​128, and assuming that the code length M of the T sub-blocks included in the input vector is 512, the first generator matrix includes 3 second generator matrices, and in every two adjacent generator matrices of the 3 second generator matrices, the first sub-matrix block of the latter generator matrix overlaps with the second sub-matrix block of the previous second generator matrix. The size of the first generator matrix (the number of rows or columns included in the first generator matrix) is 512.

[0618] Fig. 15B This is a schematic diagram of another first generation matrix provided in an embodiment of the present application. Fig. 15B The second generation matrix includes 16 matrix units, some of which are G N , some matrix cells are 0 N The second generator matrix satisfies self-similarity.

[0619] Assuming that the size of each matrix unit is 128 (including 128 rows and 128 columns), the size of the second generation matrix is ​​512, the distance between the two first generation matrices in the second generation matrix is ​​256, and assuming that the code length M of the T sub-blocks included in the input vector is 1500, the first generation matrix includes 5 second generation matrices, and in every two adjacent generation matrices of the 5 second generation matrices, the first sub-matrix block of the latter generation matrix overlaps with the second sub-matrix block of the previous second generation matrix. The size of the first generation matrix (the number of rows or columns included in the first generation matrix) is 1536.

[0620] Fig. 15C A schematic diagram of a first generation matrix provided in an embodiment of the present application. Fig. 15C The second generation matrix includes 16 matrix units, some of which are G N , some matrix cells are 0 N The second generator matrix satisfies self-similarity.

[0621] Assuming that the size of each matrix unit is 128 (including 128 rows and 128 columns), the size of the second generation matrix is ​​256, the distance between two sub-blocks in the first generation matrix is ​​128, and assuming that the code length M of the T sub-blocks included in the input vector is 1024, the first generation matrix includes 7 second generation matrices, and in every two adjacent generation matrices of the 7 second generation matrices, the first sub-matrix block of the latter generation matrix overlaps with the second sub-matrix block of the previous second generation matrix. The size of the first generation matrix (the number of rows or columns included in the first generation matrix) is 1024.

[0622] It should be noted that in Figure 15A-Figure 15C In addition to G N All matrix cells outside are 0 N , for the convenience of description and viewing, 0 is omitted in the figure N The annotation, that is, Figure 15A-Figure 15C The blank matrix cells are all 0 N .

[0623] The following is based on Figure 4A Based on the encoding method shown, the decoding method based on the above encoding method is introduced below.

[0624] Fig.16 A decoding schematic diagram provided in the embodiment of the present application. Fig.16 , the method comprising:

[0625] 1601. Receive bit information to be decoded.

[0626] The bit information to be decoded includes Q first log-likelihood ratios (LLRs), where Q is a positive integer. The bit information to be decoded includes information about bits of a first sub-block and information about bits of a second sub-block, where bits on the first sub-block are obtained by copying bits on the second sub-block, and the second sub-block is after the first sub-block.

[0627] Optionally, for the introduction of the first sub-block and the second sub-block, please refer to the aforementioned Figure 4A The embodiments shown will not be described in detail here.

[0628] Optionally, the Q first LLRs include P second LLR sequences, that is, the Q first LLRs can be divided into P first LLR sequences, one first LLR sequence includes at least two LLRs, one LLR sequence corresponds to one sub-block, and P is an integer greater than or equal to 2. For example, the P first LLR sequences are first LLR sequences corresponding to the 1st sub-block to the Pth sub-block, respectively.

[0629] It should be noted that when the transmitting end sends data to the receiving end, it can send data of code length N corresponding to one sub-block each time, or send data of code length N less than one sub-block, or send multiple sub-blocks at a time, which is not limited in this application. In addition, the order in which the transmitting end sends data to the receiving end can be the same as the sequence number order of the sub-blocks, or it can be different, which is not limited here.

[0630] 1602. Perform polarization decoding according to the bit information to be decoded to obtain polarization-decoded bits.

[0631] Optionally, step 1602 specifically includes: performing polarization decoding on the bit information to be decoded according to the first generation matrix and the mapping relationship to obtain polarization-decoded bits.

[0632] The mapping relationship can be found in the above Figure 4A In the embodiment shown in the figure, the first generation matrix is Figure 4A The matrix for performing polarization coding in the illustrated embodiment will not be described in detail here.

[0633] Then, polarization decoding is performed on the bit information to be decoded according to the first generation matrix and the mapping relationship, and the polarization-decoded bits are obtained, which specifically include:

[0634] Determine P second LLR sequences corresponding to the P first LLR sequences, where one first LLR sequence corresponds to one sub-block, and one second LLR sequence corresponds to one sub-block;

[0635] Determine, according to the Pth second LLR sequence, a codeword decoding result of the Pth sub-block and an information decoding result of the Pth sub-block;

[0636] The codeword decoding result of the i-th sub-block and the information decoding result of the i-th sub-block are determined according to the codeword decoding result of at least one sub-block from the codeword decoding result of the i+1-th sub-block to the codeword decoding result of the P-th sub-block, the information decoding result of at least one sub-block from the information decoding result of the i+1-th sub-block to the information decoding result of the P-th sub-block, and the i-th second LLR sequence, where i is an integer between 1 and P-1.

[0637] The decoding process of obtaining the information decoding result of the i-th sub-block through the above decoding is to decode the P sub-blocks one by one until the information decoding result of the first sub-block is obtained, so as to obtain the information decoding result of the first sub-block initially transmitted.

[0638] In the following, the decoding process is described by taking the decoding process of T sub-blocks received by the receiving end as an example, where Q is equal to the code length M of T sub-blocks. That is, the M first LLRs include T first LLR sequences, that is, the M first LLRs can be divided into T first LLR sequences, and one first LLR sequence includes N first LLRs.

[0639] One first LLR number corresponds to one sub-block. For example, assuming that the input vector includes T sub-blocks, and the second generator matrix is ​​as follows: Figure 3 As shown, the M first LLRs include 8 first LLR sequences, and the relationship between the 8 first LLR sequences and the T sub-blocks is shown in Table 2:

[0640] Table 2

[0641] Identification of the first LLR sequence sub-block First LLR sequence 1 The first sub-block, the second sub-block First LLR sequence 2 The second and third sub-blocks First LLR sequence 3 The third and fourth sub-blocks First LLR sequence 4 The 4th and 5th sub-blocks First LLR sequence 5 The 5th and 6th sub-blocks First LLR sequence 6 The 6th and 7th sub-blocks First LLR sequence 7 The 7th and 8th sub-blocks First LLR sequence 8 The 8th sub-block

[0642] and, Figure 3 In the coding scenario shown, there is an information coupling relationship between two adjacent sub-blocks. Therefore, during decoding, the i-th sub-block should be decoded in combination with the information decoding result of the i-1-th sub-block.

[0643] Referring to Table 2, the first LLR sequence 1 is associated with the first sub-block and the second sub-block, the first LLR sequence 2 is associated with the bits of the second sub-block and the second sub-block and the third sub-block, and so on.

[0644] In order to perform accurate decoding, the first LLR sequence can be decoupled to obtain a second LLR sequence corresponding to each first LLR sequence, so that one second LLR sequence corresponds to one sub-block. For example, the first LLR sequence shown in Table 3 is decoupled to obtain 8 second LLR sequences, and the relationship between the 8 second LLR sequences and the sub-blocks is shown in Table 3:

[0645] Table 3

[0646] The identifier of the second LLR sequence sub-block Second LLR sequence 1 The first sub-block Second LLR sequence 2 The second sub-block Second LLR sequence 3 The third sub-block Second LLR sequence 4 The 4th sub-block Second LLR sequence 5 The fifth sub-block Second LLR sequence 6 The 6th sub-block Second LLR sequence 7 The 7th sub-block Second LLR sequence 8 The 8th sub-block

[0647] Referring to Table 3, the second LLR sequence 1 is associated with the first sub-block, the second LLR sequence 2 is associated with the second sub-block, and so on.

[0648] Optionally, the i-th second LLR sequence may be determined in the following manner: according to the i-th first LLR sequence and the (i-1)-th second LLR sequence, the i-th second LLR sequence is determined, wherein the first second LLR sequence is the same as the first first LLR sequence.

[0649] Optionally, polarization decoding may be performed on the first bit information according to the first generation matrix and the mapping relationship in the following manner:

[0650] Determine T second LLR sequences corresponding to the T first LLR sequences, where one first LLR sequence corresponds to one sub-block, and one second LLR sequence corresponds to one sub-block;

[0651] Determine, according to the T-th second LLR sequence, a codeword decoding result of the T-th sub-block and an information decoding result of the T-th sub-block;

[0652] The information decoding result of the i-th sub-block is determined according to the information decoding result of the i+1-th sub-block, the codeword decoding result of the i+1-th sub-block, the i+1-th first LLR sequence, and the i-th second LLR sequence.

[0653] The information decoding process of the i-th sub-block is obtained through the above decoding, and the T sub-blocks are decoded one by one until the information decoding result of the first sub-block is obtained, so as to obtain the information decoding result of the first sub-block initially transmitted.

[0654] The following is a decoding process of the receiving end in conjunction with a specific example. i is the i-th first LLR sequence, l i is the i-th second LLR sequence, u i is the bit sequence of the ith sub-block before encoding, c i is the bit sequence of the i-th sub-block after encoding, i is determined by the number of sub-blocks decoded by the receiving end. For example, when the receiving end decodes four sub-blocks, i is an integer greater than or equal to 1 and less than or equal to 4. The first sub-block u1 is the sub-block for initial transmission, and the sub-blocks after the first sub-block u1 are all sub-blocks for retransmission. The operation of f is: f(L1, L2) = sgn(L1)sgn(L2)min(|L1|,|L2|). The operation of g is: Encode c to get u.

[0655] Example 1: Based on Figure 3 In the encoding scenario shown, the decoding method at the receiving end can be:

[0656] Determine the i-th second LLR sequence: determine the i-th second LLR sequence according to the i-th first LLR sequence and the i-1-th second LLR sequence, wherein the first second LLR sequence is the same as the first first LLR sequence.

[0657] The information decoding result of the i-th sub-block can be determined in the following manner: the information decoding result of the i-th sub-block is determined according to the information decoding result of the i+1-th sub-block, the codeword decoding result of the i+1-th sub-block, the i+1-th first LLR sequence and the i-th second LLR sequence.

[0658] Please refer to 17A, which describes the decoding process by taking the receiving end decoding the first four sub-blocks as an example. Fig.17A The basis is that the receiving end fails to decode the data of the first three sub-blocks received, and the sending end continues to retransmit to the receiving end. On this basis, after the receiving end receives a total of 4N LLRs, the received 4N LLRs are divided into 4 first LLR sequences, and the 4 first LLR sequences are respectively recorded as: l'1, l'2, l'3, l'4. The second LLR sequences corresponding to the above 4 first LLR sequences are respectively recorded as: l1, l2, l3, l4.

[0659] First determine the first second LLR sequence l1. Then perform f operation on the first second LLR sequence l1 and the second first LLR sequence l′2 to obtain the second second LLR sequence l2. Then perform f operation on the second second LLR sequence l2 and the third first LLR sequence l′3 to obtain the third second LLR sequence l3, and so on, until the above four second LLR sequences are obtained. It can be expressed as: l1 = l′1, l2 = f(l′2, l1), l3 = f(l′3, l2), l4 = f(l′4, l3).

[0660] First, the fourth second LLR sequence l4 is input to the decoder for decoding to obtain the information decoding result u4 of the fourth sub-block, wherein u4 includes N decoding bits. Encode u4 to obtain the codeword decoding result c4 of the fourth sub-block. Perform g operation on c4, l′4 and l3 to obtain the g operation result l3, and input it to the decoder; and, determine the information bit copied from u3 in u4 when encoding at the encoding end through the mapping relationship, and input the information bit to the decoder through the first input first output (FIFO) buffer. Then, the decoder decodes to obtain the information decoding result u3 of the third sub-block. Then, the decoder encodes according to u3 to obtain the codeword decoding result c3 of the third sub-block. When decoding, the decoder can decode the information bit as a special frozen bit with a specific value, that is, the information bit is used as the information decoding result of the information bit at the position of the copied bit in u3; or the information bit is used as a check bit, and its check value is used as the information decoding result of the information bit at the position of the copied bit in u3. And so on, until the first information decoding result u1 is determined, thereby obtaining the information decoding result u1 of the initially transmitted sub-block.

[0661] If in the above Fig.17A In the example shown, if the receiving end fails to decode, the sending end continues to retransmit to the receiving end. The following shows the process of the receiving end decoding the 8 sub-blocks sent by the sending end. Fig. 17B , l′ i is the i-th first LLR sequence, li is the i-th second LLR sequence, u i is the information decoding result of the i-th sub-block, c i is the codeword decoding result of the i-th sub-block, and i is an integer between 1 and 8. After receiving 8N LLRs at the receiving end, the received 8N LLRs are divided into 8 first LLR sequences, and the 8 first LLR sequences are respectively recorded as: l'1, l'2, l'3, l'4, l'5, l'6, l'7, l'8. The second LLR sequences corresponding to the above 8 first LLR sequences are respectively recorded as: l1, l2, l3, l4, l5, l6, l7, l8.

[0662] See also Fig. 17B , first determine the first second LLR sequence l1. Then perform f operation on the first second LLR sequence l1 and the second first LLR sequence l′2 to obtain the second second LLR sequence l2. Then perform f operation on the second second LLR sequence l2 and the third first LLR sequence l′3 to obtain the third second LLR sequence l3, and so on, until the above 8 second LLR sequences are obtained. It can be expressed as: l1 = l′1, l2 = f(l′2, l1), l3 = f(l′3, l2), l4 = f(l′4, l3), l5 = f(l′5, l4), l6 = f(l′6, l5), l7 = f(l′7, l6), l8 = f(l′8, l7).

[0663] See also Fig. 17B First, input the 8th second LLR sequence l8 into the decoder for decoding, and obtain the information decoding result u8 of the 8th sub-block, where u8 includes N decoding bits. Encode u8 to obtain the codeword decoding result c8 of the 8th sub-block. Perform g operation on c8, l′8 and l7 to obtain the g operation result And the result of g operation is Input to the decoder for decoding; and, determine the information bit copied from u7 in u8 when encoding at the encoder through the mapping relationship, and input the information bit to the decoder through the FIFO buffer. Then, the decoder decodes and obtains the information decoding result u7 of the 7th sub-block. Encode u7 to obtain the codeword decoding result c7 of the 7th sub-block. Perform g operation on c7, l′7 and l6 to obtain the g operation result And the result of g operation is Input to the decoder; and, the information bit copied from u6 in u7 during encoding at the encoding end is determined through the mapping relationship, and the information bit is input to the decoder through the FIFO. Then, the decoder decodes and obtains the information decoding result u6 of the 6th sub-block. And so on, until the first decoding result u1 is determined, thereby obtaining the information decoding result u1 of the initially transmitted sub-block.

[0664] Example 2: Based on Figure 4B In the encoding scenario shown, the decoding method at the receiving end can be:

[0665] Determine the i-th second LLR sequence: determine the i-th second LLR sequence according to the i-th first LLR sequence and the i-2-th second LLR sequence, where i is an integer between 3 and T. The first second LLR sequence is the same as the first first LLR sequence; and the second second LLR sequence is the same as the second first LLR sequence.

[0666] Combine the following 18A to 18D Make an introduction.

[0667] See also Fig.18A , Fig.18A The figure shows the process in which the receiving end decodes the two sub-blocks sent by the sending end. Fig.18A The basis is that the receiving end fails to decode the data of the first sub-block received, and the sending end continues to retransmit to the receiving end. On this basis, after the receiving end receives a total of 2N LLRs, the received 2N LLRs are divided into two first LLR sequences, and the two first LLR sequences are respectively recorded as: l′1, l′2.

[0668] First, according to l′ i Calculate l′ i ', where l'1'=l'1, l'2'=l'2. l' i ′ is the i-th second LLR sequence.

[0669] Then decode according to the parameters calculated above: input l2 into the decoder for decoding to obtain the information decoding result u2 of the second sub-block, where u2 includes N decoding bits. Encode u2 to obtain the codeword decoding result c2 of the second sub-block. Perform g operation on c2, l′2′, and l′1′, and add the result of g operation to the decoder. Input to the decoder; and, through the mapping relationship, determine the information bit copied from u1 in u2 when encoded at the encoding end, and input the information bit to the decoder through the data multiplexer (MUX). Then, the decoder performs decoding to obtain the information decoding result u1 of the first sub-block.

[0670] If in the above Fig.18A In the example shown, if the receiving end still fails to decode, the sending end continues to retransmit to the receiving end. The following shows the process of the receiving end decoding the three sub-blocks sent by the sending end. Fig.18B , based on the sending end Fig.18AAfter the receiving end retransmits the data again based on the received data, a total of 3N LLRs are received, and the received 3N LLRs are divided into three first LLR sequences, which are respectively recorded as: l′1, l′2, and l′3.

[0671] First, according to l′ i Calculate l′ i ′, where l′1′=l′1, l′2′=l′2, l′3′=f(l′3,l′1′). l′ i ′ is the i-th second LLR sequence.

[0672] Then decode according to the parameters calculated above: input l3 into the decoder for decoding to obtain the information decoding result u3 of the third sub-block, where u3 includes N decoding bits. Encode u3 to obtain the codeword decoding result c3 of the third sub-block. Perform g operation on c3, l′3′, and l′1′, and add the result of g operation to the decoder. For l′1, Perform operation f and return the result of operation f Input to the decoder; and, through the mapping relationship, determine the information bit copied from u2 in u3 when encoding at the encoding end, and input the information bit to the decoder through the data selector MUX. Then, the decoder decodes and obtains the information decoding result u2 of the second sub-block. Encode u2 to obtain the codeword decoding result c2 of the second sub-block. For c2, Perform g operation and convert the result of g operation into Input to the decoder; and through the mapping relationship, determine the information bit 1 copied from u1 in u3 and the information bit 2 copied from u1 in u2 when encoded at the encoding end, and input the information bit 1 and the information bit 2 to the decoder through the selector MUX respectively, and then decode to obtain the information decoding result u1 of the first sub-block.

[0673] If in the above Fig.18B In the example shown, if the receiving end still fails to decode, the sending end continues to retransmit to the receiving end. The following shows the process of the receiving end decoding the 4 sub-blocks sent by the sending end. Fig.18C , based on the sending end Fig.18B After the receiving end retransmits the data again based on the received data, a total of 4N LLRs are received, and the received 4N LLRs are divided into four first LLR sequences, which are respectively recorded as: l′1, l′2, l′3, and l′4.

[0674] First, according to l′ i Calculate l′ i′, where l′1′=l′1, l′2′=l′2, l′3′=f(l′3,l′1′), l′4′=f(l′4,l′2′).

[0675] According to l′ i Calculate l i , where l3=l′3′, l1=l′1′.

[0676] Then decode according to the parameters calculated above: input l4 into the decoder for decoding to obtain the information decoding result u4 of the 4th sub-block, where u4 includes N decoding bits. Encode u4 to obtain the codeword decoding result c4 of the 4th sub-block. Perform g operation on c4, l′4′, and l′3′, and convert the result of g operation into Input to the decoder; and, determine the information bit copied from u3 in u4 when encoding at the encoding end through the mapping relationship, and input the information bit to the decoder through the data selector MUX, and then decode it to obtain the information decoding result u3 of the third sub-block. Encode u3 to obtain the codeword decoding result c3 of the third sub-block. Perform g operation on c4+c3, l′4, l′2′ to obtain the g operation result right and Perform g operation and get g operation result in, is the result of performing g operation on c3, l′3, l′1′5. Input to the decoder; and determine the information bit 1 copied from u2 in u3 and the information bit 2 copied from u2 in u4 during encoding at the encoding end through the mapping relationship, and input the information bit 1 and the information bit 2 to the decoder through the data selector MUX, and then decode to obtain the information decoding result u2 of the third sub-block. Encode u2 to obtain the codeword decoding result c2 of the second sub-block. And so on, until it is determined that the first decoding result u1 is obtained, thereby obtaining the information decoding result u1 of the initially transmitted sub-block.

[0677] If in the above Fig.18C In the example shown, if the receiving end still fails to decode, the sending end continues to retransmit to the receiving end. The following shows the process of the receiving end decoding the 8 sub-blocks sent by the sending end. Fig.18D , based on the sending end Fig.18C After the receiving end retransmits the data again based on the received data, a total of 8N LLRs are received, and the received 8N LLRs are divided into 8 first LLR sequences, which are respectively recorded as: l′1, l′2, l′3, l′4, l′5, l′6, l′7, and l′8.

[0678] First, according to l′ iCalculate l″ i , where, l″1=l′1, l″2=l′2, l″3=f(l′3,l″1), l″4=f(l′4,l″2), l″5=f(l′5,l″3), l″6=f(l′6,l″4), l″7=f(l′7,l″5), l″8=f(l′8,l″6). l″ i is the i-th second LLR sequence.

[0679] According to l″ i Calculate l i , where l8=f(l″8,l″7), l7=l″7, l5=l″5, l3=l″3′, l1=l″1.

[0680] Then decode according to the parameters calculated above: input l8 into the decoder for decoding to obtain the 8th decoding result u8, where u8 includes N decoding bits. Encode u8 to obtain the 8th encoded bit sequence c8. Perform g operation on c8, l″8, l″7, and convert the g operation result into Input to the decoder; and determine the information bit copied from u7 in u8 when encoding at the encoding end through the mapping relationship, and input the information bit into the decoder through MUX, and then decode it to obtain the information decoding result u7 of the 7th sub-block; encode u7 to obtain the codeword decoding result c7 of the 7th sub-block. Perform g operation on c8+c7, l′8, l″6 to obtain the g operation result right and Perform g operation and get g operation result in, is the result of g operation on c7, l′7, l″5. Input to the decoder, and determine through the mapping relationship that the information bit a copied from u6 in u8 and the information bit b copied from u6 in u7 are input to the decoder when encoded at the encoding end, and then decoded to obtain the information decoding result u6 of the 6th sub-block. And so on, until it is determined that the first decoding result u1 is obtained, thereby obtaining the information decoding result u1 of the initially transmitted sub-block.

[0681] Next, combine Figures 19 to 21 , the decoding performance of the decoding method of the present application is explained.

[0682] Fig.19 A schematic diagram of decoding performance provided in an embodiment of the present application. Fig.19 , the horizontal axis represents the signal to noise ratio (SNR), and the vertical axis represents the block error rate (BLER).

[0683] See also Fig.19 , when the initial transmission code length N=128, the maximum mother code length supported is 1024, the number of information bits K is 112, and there is no coupling, the performance curve is shown as a dotted line. When the initial transmission code length N=128, the maximum mother code length supported is 1024, the number of information bits is 112, the information coupling degree is 8, and the codeword is not coupled (existing IF-HARQ method), the performance curve is shown as another dotted line. When the initial transmission code length N=128, the maximum mother code length supported is 1024, the number of information bits K is 112, the information coupling degree is 8, and the codeword coupling degree is 8 (existing IR-HARQ method), the performance curve is shown as another dotted line. When the initial transmission code length N=128, the maximum mother code length supported is 1024, the number of information bits K is 112, the information coupling degree is 2, and the codeword coupling degree is 8, the performance curve is shown as a solid line.

[0684] Fig. 20 Another decoding performance diagram provided by the embodiment of the present application. Fig. 20 , when the initial transmission code length N = 256, the maximum supported mother code length is 2048, the number of information bits K is 224, and there is no coupling, the performance curve is shown as a dotted line. When the initial transmission code length N = 256, the maximum supported mother code length is 2048, the number of information bits K is 224, the information coupling degree is 8, and the codeword is not coupled (existing IF-HARQ method), the performance curve is shown as another dotted line. When the initial transmission code length N = 256, the maximum supported mother code length is 2048, the number of information bits K is 224, the information coupling degree is 8, and the codeword coupling degree is 8 (existing IR-HARQ method), the performance curve is shown as another dotted line. When the initial transmission code length N = 256, the maximum supported mother code length is 2048, the number of information bits K is 224, the information coupling degree is 2, and the codeword coupling degree is 8, the performance curve is shown as a solid line.

[0685] Fig.21 Another decoding performance diagram provided by the embodiment of the present application. Fig.21, when the initial transmission code length N = 512, the maximum supported mother code length is 4096, the number of information bits K is 448, and there is no coupling, the performance curve is shown as a dotted line. When the initial transmission code length N = 512, the maximum supported mother code length is 4096, the number of information bits K is 448, the information coupling degree is 8, and the codeword is not coupled (existing IF-HARQ method), the performance curve is shown as another dotted line. When the initial transmission code length N = 512, the maximum supported mother code length is 4096, the number of information bits K is 448, the information coupling degree is 8, and the codeword coupling degree is 8 (existing IR-HARQ method), the performance curve is shown as another dotted line. When the initial transmission code length N = 512, the maximum supported mother code length is 4096, the number of information bits K is 448, the information coupling degree is 2, and the codeword coupling degree is 8, the performance curve is shown as a solid line.

[0686] Therefore, it can be seen that when a smaller information coupling degree and an appropriate codeword coupling degree are adopted, the best performance gain can be obtained, and the complexity of encoding and decoding is also lower in comparison.

[0687] Fig. 22 This is a schematic diagram of the structure of an encoding device provided in an embodiment of the present application. Fig. 22 , the encoding device may include a generating unit 2201 and an encoding unit 2202. Optionally, the encoding device further includes an acquiring unit 2203 and a determining unit 2204.

[0688] The generating unit 2201 is used to generate an input vector, where the input vector includes T sub-blocks, where a first information bit on a first sub-block is obtained by copying a second information bit on a second sub-block, where the first sub-block and the second sub-block are sub-blocks in the T sub-blocks, a sequence number of the first sub-block is after a sequence number of the second sub-block, and T is an integer greater than or equal to 2;

[0689] The encoding unit 2202 is configured to perform polarization encoding on the input vector to obtain encoded bits.

[0690] In a possible implementation, the acquisition unit 2203 is used to acquire K bits to be encoded, where K is a positive integer.

[0691] In another possible implementation, the information bits on the first sub-block are copied from the second information bits on the second sub-block according to a mapping relationship, and the mapping relationship includes a mapping relationship between the sub-channel carrying the first information bits in the first sub-block and the sub-channel carrying the second information bits in the second sub-block.

[0692] In another possible implementation, the determination unit 2204 is used to determine the number of first information bits carried on the first sub-block according to the first code rate allocation table; determine the sub-channel sequence number carrying the first information bit on the first sub-block according to a preset first reliability sequence, the first reliability sequence includes the reliability ranking of the sub-channels of the first sub-block, and the first information bit is obtained by copying the second information bit on the second sub-block.

[0693] In another possible implementation, the determination unit 2204 is configured to determine the number of information bits related to the second coupling sub-block carried by the first coupling sub-block according to the second code rate allocation table, the first coupling sub-block and the second coupling sub-block respectively including at least two sub-blocks, the first coupling sub-block being obtained by performing an XOR operation on the encoded bit sequences corresponding to the at least two sub-blocks, and the second coupling sub-block being obtained by performing an XOR operation on the encoded bit sequences corresponding to the at least two sub-blocks; and determine the sub-channel sequence number of the information bits related to the second coupling sub-block carried by the first coupling sub-block according to a preset second reliability sequence, the second reliability sequence including the reliability ranking of the sub-channels of the first coupling sub-block, and the information bits related to the second coupling sub-block carried by the first coupling sub-block being obtained by copying the information bits on the second coupling sub-block.

[0694] In another possible implementation, the determination unit 2204 is used to determine the subchannel sequence number carrying the first information bit on the first sub-block according to a preset third reliability sequence, the third reliability sequence includes the reliability ordering of the sub-channels of T sub-blocks, and the first information bit is obtained by copying the second information bit on the second sub-block.

[0695] In another possible implementation manner, the second sub-block includes a third sub-block, the first information bit on the first sub-block is obtained by copying the information bit on the third sub-block, the first coupling sub-block and the second coupling sub-block include the same third sub-block, and the third sub-block includes the first sub-channel; the determining unit 2204 is further used to:

[0696] When the first subchannel corresponds to multiple reliabilities, determining the reliability of the first subchannel according to a first preset rule;

[0697] The first sub-channel corresponding to multiple reliabilities includes: the first sub-channel corresponds to a first reliability in the first coupling sub-block, and the first sub-channel corresponds to a second reliability in the second coupling sub-block;

[0698] The first preset rule includes: when the first reliability is greater than or equal to the second reliability, the first reliability is used as the reliability of the first sub-channel; or, when the sequence number sequence of the first coupling sub-block is after the sequence number sequence of the second coupling sub-block, the first reliability is used as the reliability of the first sub-channel; or, when the first reliability is less than or equal to the second reliability, the second reliability is used as the reliability of the first sub-channel; or, when the sequence number sequence of the first coupling sub-block is before the sequence number sequence of the second coupling sub-block, the second reliability is used as the reliability of the first sub-channel.

[0699] In another possible implementation, the second sub-block includes a fourth sub-block and a fifth sub-block, the first information bit on the first sub-block is copied from the information bit on the fourth sub-block and the information bit on the fifth sub-block, the first reliability sequence is used to indicate the reliability ranking of the sub-channels of each sub-block, the fourth sub-block includes the second sub-channel, and the fifth sub-block includes the third sub-channel; the determining unit 2204 is further used to:

[0700] When the second sub-channel and the third sub-channel have the same reliability, determining the reliability of the second sub-channel and the reliability of the third sub-channel according to a second preset rule;

[0701] The second subchannel and the third subchannel having the same reliability include: the second subchannel corresponds to the third reliability in the first reliability sequence, and the third subchannel corresponds to the third reliability in the first reliability sequence;

[0702] The second preset rule includes: when the sequence number sequence of the fourth sub-block is after the sequence number sequence of the fifth sub-block, determining that the reliability of the second sub-channel is greater than the reliability of the third sub-channel; or, when the sequence number sequence of the fourth sub-block is before the sequence number sequence of the fifth sub-block, determining that the reliability of the third sub-channel is greater than the reliability of the second sub-channel.

[0703] In another possible implementation, the second sub-block includes M sub-blocks adjacent to the first sub-block, or the second sub-block includes M sub-blocks non-adjacent to the first sub-block, where M is an integer greater than or equal to 1 and less than T-1.

[0704] In another possible implementation, the determining unit 2204 is further configured to:

[0705] The M sub-blocks are determined according to a preset mapping sequence, the first information bit on the first sub-block is directly copied from the information bits on the M sub-blocks, and the mapping sequence is used to indicate a mapping relationship between the T sub-blocks.

[0706] In another possible implementation, when T=8, the mapping relationship includes:

[0707] There is a mapping relationship between the first sub-block and the second sub-block;

[0708] There is a mapping relationship between the second sub-block and the third sub-block;

[0709] There is a mapping relationship between the first sub-block and the fourth sub-block;

[0710] There is a mapping relationship between the 1st sub-block and the 5th sub-block;

[0711] There is a mapping relationship between the 1st sub-block and the 6th sub-block;

[0712] There is a mapping relationship between the 1st sub-block and the 7th sub-block;

[0713] There is a mapping relationship between the 1st sub-block and the 8th sub-block;

[0714] or,

[0715] The mapping sequence of the T sub-blocks includes:

[0716] There is a mapping relationship between the first sub-block and the second sub-block;

[0717] There is a mapping relationship between the second sub-block and the third sub-block;

[0718] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0719] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0720] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0721] There is a mapping relationship between the 7th sub-block and the 8th sub-block;

[0722] or,

[0723] The mapping sequence of the T sub-blocks includes:

[0724] There is a mapping relationship between the first sub-block and the second sub-block;

[0725] There is a mapping relationship between the second sub-block and the third sub-block;

[0726] There is a mapping relationship between the 3rd sub-block and the 4th sub-block;

[0727] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0728] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0729] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0730] There is a mapping relationship between the 7th sub-block and the 8th sub-block;

[0731] or,

[0732] The mapping sequence of the T sub-blocks includes:

[0733] There is a mapping relationship between the first sub-block and the second sub-block;

[0734] There is a mapping relationship between the second sub-block and the third sub-block;

[0735] There is a mapping relationship between the first sub-block and the fourth sub-block;

[0736] There is a mapping relationship between the 3rd sub-block and the 5th sub-block;

[0737] There is a mapping relationship between the 5th sub-block and the 6th sub-block;

[0738] There is a mapping relationship between the 6th sub-block and the 7th sub-block;

[0739] There is a mapping relationship between the 7th sub-block and the 8th sub-block.

[0740] In another possible implementation, the encoding unit 2202 is specifically used for:

[0741] Performing polarization encoding on the input vector using a first generator matrix;

[0742] Among them, the first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes at least two matrix blocks distributed according to a preset position relationship, the matrix block includes multiple first generating matrix cores, the first generating matrix includes A matrix blocks, the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, and A is a positive integer.

[0743] In another possible implementation manner, the code length of each sub-block in the T sub-blocks is the same as the dimension of the first generator matrix kernel.

[0744] In another possible implementation manner, the positional relationship between two adjacent matrix blocks in the A matrix blocks is the same as the preset positional relationship.

[0745] In another possible implementation manner, there is an overlapping portion between the at least two matrix blocks.

[0746] In another possible implementation manner, the first diagonal line of the matrix block includes the first generation matrix kernel.

[0747] In another possible implementation, the plurality of first generation matrix cores in the matrix block are distributed in a lower triangle.

[0748] In another possible implementation, the distribution of the first generation matrix core in the matrix block is the same as the distribution of the first element in the second generation matrix core, the number of elements included in the second generation matrix core is the same as the number of matrix units included in the matrix block, and the matrix units included in the matrix block are the first generation matrix core or 0 matrix.

[0749] In another possible implementation, the encoding unit 2202 is specifically used for:

[0750] Performing polarization encoding on the input vector using a first generator matrix;

[0751] The first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes a first submatrix block located at the upper left corner of the second submatrix block, the second submatrix block is located at the lower right corner of the first generating matrix, the first submatrix block and the second submatrix block are the same, along the diagonal direction of the second generating matrix, the distance between the first element in the first submatrix block and the second element in the second submatrix block is u, and u is an integer greater than or equal to 1; the first generating matrix includes A second generating matrices, the A second generating matrices are distributed along the diagonal of the second generating matrix (for example, the diagonal can be the main diagonal), the first submatrix block of the b+1th second generating matrix among the A second generating matrices coincides with the second submatrix block of the bth second generating matrix, b is an integer greater than or equal to 1, and T is an integer greater than or equal to 2.

[0752] In this implementation, a codeword coupling degree is set by a first generation matrix. Combined with the third aspect above, the embodiment of the present application provides a flexible code construction framework. In the code construction process, appropriate information coupling and codeword coupling can be set to obtain performance gains similar to IR-HARQ, providing a flexible compromise between the complexity of encoding and decoding and performance gain. A smaller information coupling degree can be set to save hardware overhead and avoid complex switching networks due to information replication processes.

[0753] In another possible implementation manner, there are no overlapping elements in the first sub-matrix block and the second sub-matrix block.

[0754] In another possible implementation, the size of the second generator matrix is ​​v*v, and the elements in the second generator matrix satisfy: a i,j =a i+u,j+u , where i is an integer, j is an integer, v is a positive integer, u is an integer, 1≤i <v,1≤j<v,1<i+u≤v,1<j+u≤v。

[0755] In this possible implementation, the second generator matrix satisfies a i,j =a i+u,j+u When the second generation matrix satisfies self-similarity, the codeword coupling degree can be set by the first generation matrix. In the code construction process, appropriate information coupling degree and codeword coupling degree can be set to obtain performance gain similar to IR-HARQ, providing a flexible trade-off between the complexity of encoding and decoding and performance gain.

[0756] In another possible implementation, the elements of the second generation matrix are symmetric along the secondary diagonal of the second generation matrix. From this implementation, it can be seen that the elements of the second generation matrix are symmetric along the secondary diagonal of the second generation matrix, so that the encoding complexity is low.

[0757] In another possible implementation, A is a minimum integer that satisfies a first condition, which is that a size of the first generator matrix is ​​greater than or equal to a code length M of T sub-blocks included in the input vector.

[0758] In another possible implementation, A satisfies the following relationship:

[0759] v+(A-2)*u <M≤v+(A-1)*u;

[0760] Wherein, v is the size of the second generation matrix, M is the code length M of the T sub-blocks included in the input vector, and M is an integer greater than 1.

[0761] Fig.23 This is a schematic diagram of the structure of a decoding device provided in an embodiment of the present application. Fig.23 , the decoding device may include a receiving unit 2301 and a decoding unit 2302.

[0762] The receiving unit 2301 is configured to receive bit information to be decoded, where the bit information to be decoded includes bit information of a first sub-block and bit information of a second sub-block, where the bits on the first sub-block are copied from the bits on the second sub-block, and a sequence number of the second sub-block is subsequent to a sequence number of the first sub-block;

[0763] The decoding unit 2302 is configured to perform polarization decoding according to the bit information to be decoded to obtain polarization-decoded bits.

[0764] In one possible implementation, the bits on the first sub-block are obtained by copying the bits on the second sub-block, including: the first information bits on the first sub-block are copied from the second information bits on the second sub-block according to a mapping relationship, and the mapping relationship includes a mapping relationship between the sub-channel carrying the first information bit in the first sub-block and the sub-channel carrying the second information bit in the second sub-block.

[0765] In another possible implementation, the decoding unit 2302 is specifically used for:

[0766] Performing polarization decoding on the bit information to be decoded according to the first generation matrix and the mapping relationship to obtain polarization-decoded bits;

[0767] Among them, the first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes at least two matrix blocks distributed according to a preset position relationship, the matrix block includes multiple first generating matrix cores, the first generating matrix includes A matrix blocks, the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, A is a positive integer, the mapping relationship includes a mapping relationship between the sub-channel carrying the first information bit on the first sub-block and the sub-channel carrying the second information bit on the second sub-block, and T is an integer greater than or equal to 2.

[0768] In another possible implementation manner, the bit information to be decoded includes Q first log-likelihood ratios (LLRs), where Q is a positive integer.

[0769] In another possible implementation, the Q first LLRs include P first LLR sequences, the first LLR sequence includes at least two first LLRs, and P is an integer greater than or equal to 2; the decoding unit 2302 is specifically configured to:

[0770] Determine P second LLR sequences corresponding to the P first LLR sequences, where one first LLR sequence corresponds to one sub-block, and one second LLR sequence corresponds to one sub-block;

[0771] Determine, according to the Pth second LLR sequence, a codeword decoding result of the Pth sub-block and an information decoding result of the Pth sub-block;

[0772] The codeword decoding result of the i-th sub-block and the information decoding result of the i-th sub-block are determined according to the codeword decoding result of at least one sub-block from the codeword decoding result of the i+1-th sub-block to the codeword decoding result of the P-th sub-block, the information decoding result of at least one sub-block from the information decoding result of the i+1-th sub-block to the information decoding result of the P-th sub-block, and the i-th second LLR sequence, where i is an integer between 1 and P-1.

[0773] In another possible implementation manner, the positional relationship between two adjacent matrix blocks in the A matrix blocks is the same as the preset positional relationship.

[0774] In another possible implementation, the decoding unit 2302 is specifically used for:

[0775] Performing polarization decoding on the bit information to be decoded according to the first generation matrix and the mapping relationship to obtain polarization-decoded bits;

[0776] The first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes a first submatrix block located at the upper left corner of the second submatrix block, the second submatrix block is located at the lower right corner of the first generating matrix, the first submatrix block and the second submatrix block are the same, along the diagonal direction of the second generating matrix, the distance between the first element in the first submatrix block and the second element in the second submatrix block is u, and u is an integer greater than or equal to 1; the first generating matrix includes A second generating matrices, the A second generating matrices are distributed along the diagonal of the second generating matrix (for example, the diagonal can be the main diagonal), the first submatrix block of the b+1th second generating matrix in the A second generating matrices overlaps with the second submatrix block of the bth second generating matrix, b is an integer greater than or equal to 1, and T is an integer greater than or equal to 2; the mapping relationship includes a mapping relationship between a subchannel carrying a first information bit on the first subblock and a subchannel carrying a second information bit on the second subblock, and T is an integer greater than or equal to 2.

[0777] Fig.24 This is a hardware structure diagram of a coding device provided in an embodiment of the present application. Fig.24 , the encoding device 2400 may include: a processor 2401 and a memory 2402, wherein,

[0778] Memory 2402, used to store computer programs and can also be used to store intermediate data;

[0779] The processor 2401 is used to execute the computer program stored in the memory to implement each step in the above encoding method. For details, please refer to the relevant description in the previous method embodiment.

[0780] Optionally, the memory 2402 may be independent or integrated with the processor 2401. In some implementations, the memory 2402 may even be located outside the encoding device 2400.

[0781] When the memory 2402 is a device independent of the processor 2401 , the encoding device 2400 may further include a bus 2403 for connecting the memory 2402 and the processor 2401 .

[0782] Optionally, the encoding device 2400 may further include a transmitter. For example, the transmitter is used to send the encoded bits.

[0783] The encoding device 2400 provided in this embodiment can be a terminal device, or can also be a network device, which can be used to execute the above-mentioned encoding method. Its implementation method and technical effect are similar, and this embodiment will not be repeated here.

[0784] Fig.25 This is a schematic diagram of the hardware structure of the decoding device provided in the embodiment of the present application. Fig.25 , the decoding device 2500 may include: a processor 2501 and a memory 2502, wherein,

[0785] Memory 2502, used to store computer programs and can also be used to store intermediate data;

[0786] The processor 2501 is used to execute the computer program stored in the memory to implement each step in the above decoding method. For details, please refer to the relevant description in the above method embodiment.

[0787] Optionally, the memory 2502 may be independent or integrated with the processor 2501. In some implementations, the memory 2502 may even be located outside the decoding device 2500.

[0788] When the memory 2502 is a device independent of the processor 2501 , the decoding device 2500 may further include a bus 2503 for connecting the memory 2502 and the processor 2501 .

[0789] Optionally, the decoding device 2500 may further include a receiver. For example, the receiver is used to receive polarization-encoded bit information.

[0790] The decoding device 2500 provided in this embodiment may be a terminal device, or may also be a network device, which may be used to execute the above-mentioned decoding method. Its implementation method and technical effect are similar, and will not be described in detail in this embodiment.

[0791] Fig.26 This is a schematic diagram of the structure of another encoding device provided in an embodiment of the present application. Fig.26 , the encoding device 2600 may include a communication interface 2601 and a logic circuit 2602, wherein,

[0792] Optionally, the communication interface 2601 may have Fig. 22 The logic circuit 2602 may have the function of obtaining the function of the acquisition unit 2203 in the embodiment shown. Fig. 22 The functions of the generating unit 2201, the encoding unit 2202 and the determining unit 2204 in the illustrated embodiment.

[0793] Optionally, the logic circuit 2602 may have Fig.24 The functions of the processor 2401 in the illustrated embodiment. The logic circuit 2602 may be used to execute the steps in the above encoding method.

[0794] Optionally, the communication interface is also used to output encoded bits.

[0795] The encoding device 2600 provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0796] Fig. 27 This is a schematic diagram of the structure of another decoding device provided in an embodiment of the present application. Fig. 27 , the decoding device 2700 may include an input interface 2701 and a logic circuit 2702, wherein,

[0797] Optionally, the input interface 2701 may have Fig.23 The logic circuit 2702 may have the following functions: Fig.23 The function of the decoding unit 2302 in the embodiment shown.

[0798] Optionally, the logic circuit 2702 may have Fig.25 Functions of the processor 2501 in the embodiment. The logic circuit 2702 can be used to execute the steps in the above decoding method.

[0799] Optionally, the decoding device 2700 may further include an output interface. For example, the output interface may output the decoded bits.

[0800] The decoding device 2700 provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar and will not be repeated here.

[0801] An embodiment of the present application further provides a storage medium, wherein the storage medium includes a computer program, and the computer program is used to implement the encoding method as described above.

[0802] An embodiment of the present application further provides a storage medium, wherein the storage medium includes a computer program, and the computer program is used to implement the decoding method as described above.

[0803] The embodiment of the present application also provides a chip or integrated circuit, including: a memory and a processor;

[0804] The memory is used to store program instructions and can also be used to store intermediate data;

[0805] The processor is used to call the program instructions stored in the memory to implement the encoding method as described above.

[0806] Optionally, the memory may be independent or integrated with the processor. In some implementations, the memory may be located outside the chip or integrated circuit.

[0807] The embodiment of the present application also provides a chip or integrated circuit, including: a memory and a processor;

[0808] The memory is used to store program instructions and can also be used to store intermediate data;

[0809] The processor is used to call the program instructions stored in the memory to implement the decoding method as described above.

[0810] Optionally, the memory may be independent or integrated with the processor. In some implementations, the memory may be located outside the chip or integrated circuit.

[0811] An embodiment of the present application also provides a program product, which includes a computer program stored in a storage medium, and the computer program is used to implement the above-mentioned encoding method.

[0812] An embodiment of the present application further provides a program product, which includes a computer program stored in a storage medium, and the computer program is used to implement the above-mentioned decoding method.

[0813] The steps of the method or algorithm described in conjunction with the disclosure of the embodiments of the present application can be implemented in a hardware manner, or can be implemented by a processor executing a software instruction. The software instruction can be composed of corresponding software modules, and the software module can be stored in a random access memory (Random Access Memory, RAM), a flash memory, a read-only memory (Read Only Memory, ROM), an erasable programmable read-only memory (Erasable Programmable ROM, EPROM), an electrically erasable programmable read-only memory (Electrically EPROM, EEPROM), a register, a hard disk, a mobile hard disk, a read-only compact disk (CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and can write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a base station or a terminal. Of course, the processor and the storage medium can also be present in a receiving device as discrete components.

[0814] It should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the invention may be directly implemented by a hardware processor or implemented by a combination of hardware and software modules in the processor.

[0815] The memory may include a high-speed RAM memory, and may also include a non-volatile storage NVM, such as at least one disk memory, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a magnetic disk or an optical disk, etc.

[0816] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0817] The above storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The storage medium can be any available medium that can be accessed by a general or special purpose computer.

[0818] In the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0819] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0820] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0821] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0822] In addition, each functional module in each embodiment of the present application can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The above-mentioned module-composed unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

Claims

1. A polar code encoding method, characterized in that: The method comprises: Generate an input vector, the input vector including T sub-blocks, a first information bit on a first sub-block is obtained by copying a second information bit on a second sub-block, wherein the first sub-block and the second sub-block are sub-blocks in the T sub-blocks, a sequence number of the first sub-block is after a sequence number of the second sub-block, and T is an integer greater than or equal to 2; Performing polarization encoding on the input vector using a first generator matrix; Among them, the first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes at least two matrix blocks distributed according to a preset position relationship, the matrix block includes multiple first generating matrix cores, the first generating matrix includes A matrix blocks, the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, A is a positive integer, the first generating matrix is ​​used to indicate the codeword coupling relationship of the T sub-blocks, there is an overlapping part between the at least two matrix blocks, and the code length of each sub-block in the T sub-blocks is the same as the dimension of the first generating matrix core.

2. The encoding method according to claim 1, characterized in that The information bits on the first sub-block are copied from the second information bits on the second sub-block according to a mapping relationship, wherein the mapping relationship includes a mapping relationship between a sub-channel on the first sub-block that carries the first information bits and a sub-channel on the second sub-block that carries the second information bits.

3. The encoding method according to claim 1 or 2, characterized in that: The method further comprises: Determine, according to a first code rate allocation table, the number of the first information bits carried by the first sub-block; The sequence number of the subchannel carrying the first information bit on the first subblock is determined according to a preset first reliability sequence, where the first reliability sequence includes the reliability ranking of the subchannels of the first subblock.

4. The encoding method according to claim 1 or 2, characterized in that: The method further comprises: Determine the number of information bits related to the second coupling sub-block carried by the first coupling sub-block according to the second code rate allocation table, wherein the first coupling sub-block and the second coupling sub-block respectively include at least two sub-blocks, the first coupling sub-block is obtained by performing an XOR operation on the encoded bit sequences corresponding to the at least two sub-blocks, and the second coupling sub-block is obtained by performing an XOR operation on the encoded bit sequences corresponding to the at least two sub-blocks; The subchannel sequence number of the information bit related to the second coupling subblock and carried by the first coupling subblock is determined according to a preset second reliability sequence, wherein the second reliability sequence includes the reliability ranking of the subchannels of the first coupling subblock.

5. The encoding method according to claim 1 or 2, characterized in that: The method further comprises: The sequence number of the subchannel carrying the first information bit on the first subblock is determined according to a preset third reliability sequence, wherein the third reliability sequence includes the reliability ranking of the subchannels of the T subblocks.

6. The encoding method according to claim 4, characterized in that: The second sub-block includes a third sub-block, the first information bit on the first sub-block is copied from the information bit on the third sub-block, the first coupling sub-block and the second coupling sub-block include the same third sub-block, and the third sub-block includes a first sub-channel; the method further includes: When the first sub-channel corresponds to multiple reliabilities, determining the reliability of the first sub-channel according to a first preset rule; The first sub-channel corresponds to multiple reliabilities including: The first subchannel corresponds to a first reliability in the first coupling subblock, and the first subchannel corresponds to a second reliability in the second coupling subblock; The first preset rule includes: When the first reliability is greater than or equal to the second reliability, taking the first reliability as the reliability of the first sub-channel; or, When the sequence number of the first coupling sub-block is after the sequence number of the second coupling sub-block, the first reliability is used as the reliability of the first sub-channel; or, When the first reliability is less than or equal to the second reliability, taking the second reliability as the reliability of the first sub-channel; or, When the sequence number of the first coupling sub-block is before the sequence number of the second coupling sub-block, the second reliability is used as the reliability of the first sub-channel.

7. The encoding method according to claim 3, characterized in that: The second sub-block includes a fourth sub-block and a fifth sub-block, the first information bit on the first sub-block is copied from the information bit on the fourth sub-block and the information bit on the fifth sub-block, the first reliability sequence is used to indicate the reliability ranking of the sub-channels of each sub-block, the fourth sub-block includes the second sub-channel, and the fifth sub-block includes the third sub-channel; the method further includes: When the second sub-channel and the third sub-channel have the same reliability, determining the reliability of the second sub-channel and the reliability of the third sub-channel according to a second preset rule; The second sub-channel and the third sub-channel having the same reliability include: The second sub-channel corresponds to a third reliability in the first reliability sequence, and the third sub-channel corresponds to the third reliability in the first reliability sequence; The second preset rule includes: When the sequence number of the fourth sub-block is after the sequence number of the fifth sub-block, determining that the reliability of the second sub-channel is greater than the reliability of the third sub-channel; or, When the sequence number order of the fourth sub-block is before the sequence number order of the fifth sub-block, it is determined that the reliability of the third sub-channel is greater than the reliability of the second sub-channel.

8. The encoding method according to claim 1 or 2, characterized in that: The second sub-block includes M sub-blocks adjacent to the first sub-block, or the second sub-block includes M sub-blocks non-adjacent to the first sub-block, where M is an integer greater than or equal to 1 and less than T-1.

9. The encoding method according to claim 8, characterized in that: The method further comprises: The M sub-blocks are determined according to a preset mapping sequence, the first information bit on the first sub-block is directly copied from the information bits on the M sub-blocks, and the mapping sequence is used to indicate a mapping relationship between the T sub-blocks.

10. The encoding method according to claim 9, characterized in that: When T=8, the mapping sequence includes: There is a mapping relationship between the first sub-block and the second sub-block; There is a mapping relationship between the second sub-block and the third sub-block; There is a mapping relationship between the first sub-block and the fourth sub-block; There is a mapping relationship between the first sub-block and the fifth sub-block; There is a mapping relationship between the first sub-block and the sixth sub-block; There is a mapping relationship between the first sub-block and the seventh sub-block; There is a mapping relationship between the first sub-block and the eighth sub-block; or, The mapping sequence includes: There is a mapping relationship between the first sub-block and the second sub-block; There is a mapping relationship between the second sub-block and the third sub-block; There is a mapping relationship between the third sub-block and the fifth sub-block; There is a mapping relationship between the fifth sub-block and the sixth sub-block; There is a mapping relationship between the sixth sub-block and the seventh sub-block; There is a mapping relationship between the 7th sub-block and the 8th sub-block; or, The mapping sequence includes: There is a mapping relationship between the first sub-block and the second sub-block; There is a mapping relationship between the second sub-block and the third sub-block; There is a mapping relationship between the third sub-block and the fourth sub-block; There is a mapping relationship between the third sub-block and the fifth sub-block; There is a mapping relationship between the fifth sub-block and the sixth sub-block; There is a mapping relationship between the sixth sub-block and the seventh sub-block; There is a mapping relationship between the 7th sub-block and the 8th sub-block; or, The mapping sequence includes: There is a mapping relationship between the first sub-block and the second sub-block; There is a mapping relationship between the second sub-block and the third sub-block; There is a mapping relationship between the first sub-block and the fourth sub-block; There is a mapping relationship between the third sub-block and the fifth sub-block; There is a mapping relationship between the fifth sub-block and the sixth sub-block; There is a mapping relationship between the sixth sub-block and the seventh sub-block; There is a mapping relationship between the 7th sub-block and the 8th sub-block.

11. The encoding method according to claim 1 or 2, characterized in that: The positional relationship between two adjacent matrix blocks in the A matrix blocks is the same as the preset positional relationship.

12. The encoding method according to claim 1 or 2, characterized in that: The first generation matrix kernel is included on the first diagonal line of the matrix block.

13. The encoding method according to claim 1 or 2, characterized in that: The plurality of first generation matrix cores in the matrix block are distributed in a lower triangle.

14. The encoding method according to claim 1 or 2, characterized in that: The distribution of the first generation matrix core in the matrix block is the same as the distribution of the first element in the second generation matrix core, the number of elements included in the second generation matrix core is the same as the number of matrix units included in the matrix block, and the matrix units included in the matrix block are the first generation matrix core or 0 matrix.

15. A polar code decoding method, characterized in that: The method comprises: receiving bit information to be decoded, the bit information to be decoded including bit information of T sub-blocks, the T sub-blocks including a first sub-block and a second sub-block, the bits on the first sub-block are copied from the bits on the second sub-block, and the sequence number of the second sub-block is after the sequence number of the first sub-block; Performing polarization decoding on the bit information to be decoded according to the first generation matrix and the mapping relationship to obtain polarization-decoded bits; Among them, the first generating matrix is ​​generated according to the second generating matrix, the second generating matrix includes at least two matrix blocks distributed according to a preset position relationship, the matrix block includes multiple first generating matrix cores, the first generating matrix includes A matrix blocks, the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, A is a positive integer, the first generating matrix is ​​used to indicate the codeword coupling relationship of the T sub-blocks, there is an overlapping part between the at least two matrix blocks, the code length of each sub-block in the T sub-blocks is the same as the dimension of the first generating matrix core, and the mapping relationship includes a mapping relationship between a sub-channel of a first information bit carried by the first sub-block and a sub-channel of a second information bit carried by the second sub-block.

16. The decoding method according to claim 15, characterized in that: The bits on the first sub-block are obtained by copying the bits on the second sub-block: The first information bit on the first sub-block is copied from the second information bit on the second sub-block according to a mapping relationship, and the mapping relationship includes a mapping relationship between a sub-channel carrying the first information bit on the first sub-block and a sub-channel carrying the second information bit on the second sub-block.

17. The decoding method according to claim 15 or 16, characterized in that: The bit information to be decoded includes Q first log-likelihood ratios (LLRs), where Q is a positive integer.

18. The decoding method according to claim 17, characterized in that: The Q first LLRs include P first LLR sequences, the first LLR sequences include at least two first LLRs, and P is an integer greater than or equal to 2; performing polarization decoding on the bit information to be decoded according to the first generation matrix and the mapping relationship to obtain polarization-decoded bits includes: Determine P second LLR sequences corresponding to the P first LLR sequences, where one first LLR sequence corresponds to one sub-block, and one second LLR sequence corresponds to one sub-block; Determine, according to a P-th second LLR sequence, a codeword decoding result of a P-th sub-block and an information decoding result of a P-th sub-block, wherein the P-th second LLR sequence is a P-th second LLR sequence among the P second LLR sequences; The codeword decoding result of the i-th sub-block and the information decoding result of the i-th sub-block are determined according to the codeword decoding result of at least one sub-block from the codeword decoding result of the i+1-th sub-block to the codeword decoding result of the P-th sub-block, the information decoding result of at least one sub-block from the information decoding result of the i+1-th sub-block to the information decoding result of the P-th sub-block, and the i-th second LLR sequence, where i is an integer between 1 and P-1.

19. The decoding method according to claim 15 or 16, characterized in that: The positional relationship between two adjacent matrix blocks in the A matrix blocks is the same as the preset positional relationship.

20. A coding device, characterized in that: The encoding device includes a memory, a processor, and a computer program, wherein the computer program is stored in the memory, and the processor runs the computer program to perform the encoding method according to any one of claims 1 to 14.

21. A decoding device, characterized in that: The decoding device includes a memory, a processor, and a computer program. The computer program is stored in the memory, and the processor runs the computer program to execute the decoding method according to any one of claims 15 to 19.

22. A coding device, characterized in that: The encoding device includes a communication interface and a logic circuit; The logic circuit is used to generate an input vector, the input vector includes T sub-blocks, the first information bit on the first sub-block is obtained by copying the second information bit on the second sub-block, wherein the first sub-block and the second sub-block are sub-blocks in the T sub-blocks, the sequence number of the first sub-block is after the sequence number of the second sub-block, and T is an integer greater than or equal to 2; the input vector is polarized encoded by a first generation matrix to obtain encoded bits; wherein the first generation matrix is ​​generated according to the second generation matrix, the second generation matrix includes at least two matrix blocks distributed according to a preset position relationship, the matrix block includes a plurality of first generation matrix cores, the first generation matrix includes A matrix blocks, the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, A is a positive integer, the first generation matrix is ​​used to indicate the codeword coupling relationship of the T sub-blocks, the at least two matrix blocks have overlapping parts, and the code length of each sub-block in the T sub-blocks is the same as the dimension of the first generation matrix core; The communication interface is used to output the encoded bits.

23. The encoding device according to claim 22, characterized in that The logic circuit is also used to execute the encoding method according to any one of claims 2 to 14.

24. A decoding device, characterized in that: The decoding device includes an input interface and a logic circuit; The input interface is used to receive bit information to be decoded, the bit information to be decoded includes information of bits of T sub-blocks, the T sub-blocks include a first sub-block and a second sub-block, the bits on the first sub-block are copied from the bits on the second sub-block, and the sequence number of the second sub-block is after the sequence number of the first sub-block; The logic circuit is used to perform polarization decoding on the bit information to be decoded according to the first generation matrix and the mapping relationship to obtain the polarization-decoded bits; wherein the first generation matrix is ​​generated according to the second generation matrix, the second generation matrix includes at least two matrix blocks distributed according to a preset position relationship, the matrix block includes multiple first generation matrix cores, the first generation matrix includes A matrix blocks, the position relationship between two adjacent matrix blocks in the A matrix blocks is determined according to the preset position relationship, A is a positive integer, the first generation matrix is ​​used to indicate the codeword coupling relationship of the T sub-blocks, there is an overlapping part between the at least two matrix blocks, the code length of each sub-block in the T sub-blocks is the same as the dimension of the first generation matrix core, and the mapping relationship includes a mapping relationship between a sub-channel of a first information bit carried by the first sub-block and a sub-channel of a second information bit carried by the second sub-block.

25. The decoding device according to claim 24, characterized in that: The logic circuit is also used to execute the decoding method described in any one of claims 15 to 19.

26. A storage medium, characterized in that The storage medium comprises a computer program, and the computer program is used to implement the encoding method according to any one of claims 1 to 14 or the decoding method according to any one of claims 15 to 19.

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