Semiconductor device and method for forming the same

Abstract

A semiconductor device and a method for forming the same, wherein the semiconductor device comprises: a substrate; a gate structure located on the substrate and comprising a first region and a second region, wherein the length of the gate structure in the first region is greater than the length of the gate structure in the second region; a stop layer located on the substrate and within the gate structure in the first region; in the formation of the gate structure, due to the existence of the stop layer, the stop layer serves as a stop mark in the process of forming the gate structure, which can reduce the loss of the gate structure and ensure that the quality of the formed gate structure is improved, thereby ensuring that the quality of the semiconductor device finally formed is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] The electronics industry is constantly moving toward the demand for smaller and faster electronic devices that can simultaneously support a greater number of increasingly complex and sophisticated functions. Therefore, a continuing trend in the semiconductor industry is to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been achieved to a large extent by scaling down the size of semiconductor ICs (e.g., minimum feature size (CD)) to improve production efficiency and reduce associated costs. However, this scaling down also increases the complexity of semiconductor manufacturing processes. Therefore, the continued advancement of semiconductor ICs and devices requires the simultaneous advancement of semiconductor manufacturing processes and technologies.

[0003] As a part of the device, the gate structure and its material greatly affect the performance of the device. The traditional polysilicon gate process has the "polysilicon depletion" effect, which affects the conduction of the device, so a metal gate is introduced. After the metal gate is introduced, an interconnect metal layer needs to be formed on the metal gate to form an electrical connection with the outside world.

[0004] However, the quality of the gate structure formed in the prior art needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor device and a method for forming the same, so that the formation quality of the gate structure is improved, thereby ensuring that the quality of the semiconductor device finally formed is improved.

[0006] To solve the above problems, the present invention provides a semiconductor device, a substrate; a gate structure located on the substrate, including a first region and a second region, the length of the gate structure in the first region is greater than the length of the gate structure in the second region; a stop layer located on the substrate and within the gate structure in the first region.

[0007] Optionally, the number of the stop layers is one or more.

[0008] Optionally, the material of the stop layer is one or more of silicon nitride, silicon oxide, silicon nitride, silicon carbon oxide, silicon nitride, silicon nitride, and silicon boride.

[0009] Correspondingly, the present invention also provides a method for forming a semiconductor device: comprising: providing a substrate, forming a dummy gate structure on the substrate, the dummy gate structure comprising a first region and a second region, the length of the dummy gate structure in the first region being greater than the length of the gate structure in the second region; etching a portion of the dummy gate structure in the first region, forming an opening in the dummy gate structure in the first region, the bottom of the opening exposing the surface of the substrate; forming a stop layer in the opening, the stop layer filling the opening; removing the dummy gate structure, forming a gate opening on the substrate, and forming an initial gate structure in the gate opening; flattening the initial gate structure until the top surface of the stop layer is exposed, to form a gate structure.

[0010] Optionally, the number of the openings is equal to the number of the stop layers.

[0011] Optionally, the number of the openings is one, the number of the stop layers is one or the number of the openings is a plurality of the stop layers is a plurality of the stop layers.

[0012] Optionally, the material of the stop layer is one or more of silicon nitride, silicon oxide, silicon nitride, silicon carbon oxide, silicon nitride, silicon nitride, and silicon boride.

[0013] Optionally, the process for forming the stop layer is one or more combinations of a chemical vapor deposition process, an atomic layer deposition process, or a physical vapor deposition process.

[0014] Optionally, the method for forming the stop layer is: forming an initial stop layer on the top surface of the dummy gate structure; and planarizing the initial stop layer until the top surface of the dummy gate structure is exposed.

[0015] Optionally, the gate structure includes a gate dielectric layer formed on the substrate, a work function layer formed on the gate dielectric layer, and a metal layer formed on the work function layer.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0017] In the structure of the present invention, due to the existence of the stop layer, on the one hand, the stop layer divides the gate structure of the first area to achieve the cutting (gate cut) of the gate structure of the first area; on the other hand, during the formation of the gate structure, the stop layer serves as a stop mark of the gate structure during the formation process, which can avoid excessive loss of the gate structure during the formation process, thereby improving the formation quality of the gate structure.

[0018] A dummy gate structure is formed on a substrate, the dummy gate structure comprising a first region and a second region, wherein the length of the dummy gate structure in the first region is greater than the length of the gate structure in the second region, an opening is formed in the dummy gate structure in the first region by etching part of the dummy gate structure in the first region, the bottom of the opening exposes the surface of the substrate, a stop layer is formed in the opening, the stop layer fills the opening, the dummy gate structure is removed to form a gate opening, an initial gate structure is formed in the gate opening, the initial gate structure is flattened until the top surface of the stop layer is exposed, thereby forming a gate structure. The gate structure formed by this method has good quality and can ensure the high quality of the semiconductor device finally formed. This is because in the process of flattening the initial gate structure, due to the presence of the stop layer, when the top surface of the stop layer is exposed during the flattening process, the flattening process can no longer be continued, which reduces the loss of the gate structure and ensures that the quality of the formed gate structure is improved, thereby ensuring that the quality of the semiconductor device finally formed is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1 to 12 It is a schematic diagram of the structure of each step in the formation process of a semiconductor device;

[0020] Figures 13 to 27 It is a schematic structural diagram of each step of an embodiment of a semiconductor device and a method for forming the same according to the present invention. DETAILED DESCRIPTION

[0021] In the prior art, during the planarization process of the gate structure, there is a lot of loss, resulting in poor quality of the formed gate structure and unstable threshold voltage, which affects the performance of the semiconductor device.

[0022] Figures 1 to 12 It is a schematic diagram of the structures of various steps in the formation process of a semiconductor device.

[0023] Please refer to Figures 1 to 3 , Figure 1 yes Figure 2 and Figure 3 A top view of Figure 2 yes Figure 1 Section view at section line AA; Figure 3 yes Figure 1 A cross-sectional view at section line BB. A step of forming a semiconductor device includes: providing a base 100, the base 100 includes a substrate 101, a plurality of discretely arranged fins 110 located on the substrate 101, the fins 110 include a sparse area 111 and a dense area 112, and the distance between adjacent fins in the sparse area 111 is greater than the distance between adjacent fins in the dense area 112.

[0024] The method further includes forming an isolation layer 102 on the substrate 101 , wherein the isolation layer 102 covers a portion of a side wall of a root of the fin 110 .

[0025] Please refer to Figure 4 and Figure 5 , a dummy gate structure is formed on the substrate 101 , wherein the dummy gate structure spans across the fin 110 .

[0026] Figure 4 is Figure 2 Schematic diagram of the foundation; Figure 5 is Figure 3 Schematic diagram based on the foundation.

[0027] The dummy gate structure includes a dummy gate dielectric layer 103 and a dummy gate electrode layer 104 located on the dummy gate dielectric layer 103 .

[0028] The dummy gate dielectric layer 103 is located on the top and sidewalls of the fin 110 , and is also located on the top surface of the isolation layer 102 .

[0029] The dummy gate electrode layer 104 is located on the dummy gate dielectric layer 103 .

[0030] A sidewall spacer 107 is also formed on the sidewall of the dummy gate structure.

[0031] The dummy gate structure includes a first region 105 and a second region 106 . The dummy gate structure length of the first region 105 is greater than the dummy gate structure length of the second region 106 .

[0032] The pseudo gate structure length refers to: a pseudo gate structure distance perpendicular to the extension direction of the fin and spanning between adjacent fins.

[0033] Please refer to Figure 6 , a source-drain doped layer 120 is formed in the fin 110 on both sides of the dummy gate structure.

[0034] Figure 6 The viewing direction and Figure 4 The viewing direction is the same.

[0035] Please refer to Figure 7 An interlayer dielectric layer 130 is formed on the source / drain doped layer 120 and the sidewalls of the spacer 107 , and the top surface of the interlayer dielectric layer 130 is flush with the top surface of the dummy gate structure.

[0036] Figure 7 is Figure 6 Schematic diagram based on the foundation.

[0037] Please refer to Figures 8 to 10 , Fig.11 and Fig.12 , remove the pseudo gate structure to form a gate opening (not shown in the figure), form an initial gate structure in the gate opening, flatten the initial gate structure to form a gate structure 140 in the gate opening, and the gate structure includes a gate dielectric layer 141, a work function layer 142 and a metal layer 143.

[0038] Fig.10 yes Figure 8 and Fig. 9 A top view of Figure 8 yes Fig.10 Section view at AA; Fig. 9 yes Fig.10 Sectional view in BB; Fig.11 yes Fig.10 Sectional view at CC; Fig.12 yes Fig.10 Sectional view of DD.

[0039] The inventor found that, compared Figure 8 and Fig.11 ,contrast Fig. 9 and Fig.12 In the semiconductor device formed by this method, during the process of flattening the initial gate structure to form the gate structure, the middle part of the initial gate structure has more loss, and the edge part has very little loss. For the first region with a longer gate structure, during the process of flattening the initial gate structure, the middle part of the initial gate structure will have more loss, and when the gate structure is formed, the work function layer in the gate structure of the first region is easily exposed, and even the fin of the first region is exposed, which causes damage to the work function layer and the fin surface, resulting in unstable threshold voltage, which reduces the performance of the semiconductor device finally formed.

[0040] The inventors have discovered that before removing the dummy gate structure, a stop layer is formed in the dummy gate structure in the first region. In this way, when removing the dummy gate structure to form an initial gate structure and planarizing the initial gate structure, the stop layer serves as a stop mark in the planarization process. When the top surface of the stop layer is exposed, the initial gate structure is no longer further planarized, thereby reducing the loss of the gate structure in the first region, thereby avoiding damage to the performance of the gate structure finally formed in the first region, and enhancing the performance of the finally formed semiconductor device.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 13 to 27 It is a structural schematic diagram of a formation process of a semiconductor device according to an embodiment of the present invention.

[0043] Please refer to Figures 13 to 15 , providing a substrate 200.

[0044] in Fig.13 yes Fig.14 , Fig.15 A top view of Fig.14 yes Fig.13 In the AA section, Fig.15 yes Fig.13 A cross-sectional view of the BB.

[0045] In this embodiment, the base 200 includes a substrate 210 and a plurality of fins 220 separated from each other and located on the substrate 210 .

[0046] In this embodiment, the material of the substrate 210 is single crystal silicon. In other embodiments, the substrate 210 may also be polycrystalline silicon or amorphous silicon. The material of the substrate 210 may also be semiconductor materials such as germanium, silicon germanium, and gallium arsenide.

[0047] In this embodiment, the method for forming the substrate 210 and the fin 220 includes: providing an initial substrate (not shown); forming a patterned layer on the initial substrate; and etching the initial substrate using the patterned layer as a mask to form the substrate 210 and the fin 220 .

[0048] In this embodiment, the material of the fin 220 is single crystal silicon. In other embodiments, the material of the fin may also be single crystal silicon germanium or other semiconductor materials.

[0049] In other embodiments, the substrate 200 may also be a structure without the fin portion.

[0050] In this embodiment, there are multiple fins 220 , and the distances between adjacent fins are different. The fin area with a large distance between adjacent fins is defined as a sparse area 221 , and the fin area with a small distance between adjacent fins is defined as a dense area 222 .

[0051] In this embodiment, the method further includes: forming an isolation layer 201 on the substrate 210 , wherein the isolation layer 201 covers a portion of the sidewalls of the fin 220 .

[0052] The method for forming the isolation layer 201 includes: forming an initial isolation layer (not shown) on the substrate 210, wherein the initial isolation layer covers the fin 220; performing a planarization process on the initial isolation layer until the top surface of the fin 220 is exposed; after the planarization process, removing a portion of the initial isolation layer to form the isolation layer 201, wherein the top surface of the isolation layer 201 is lower than the top surface of the fin 220.

[0053] In this embodiment, the material of the isolation layer 201 includes silicon oxide; in other embodiments, the material of the isolation layer 201 may also include silicon nitride or silicon oxynitride.

[0054] Please refer to Figures 16 to 18 , a dummy gate structure is formed on the substrate 200 , the dummy gate structure includes a first region 202 and a second region 203 , and the length of the dummy gate structure in the first region 202 is greater than the length of the dummy gate structure in the second region 203 .

[0055] The pseudo gate structure length refers to: a pseudo gate structure distance perpendicular to the extension direction of the fin and spanning between adjacent fins.

[0056] from Fig.16 It can be seen from the figure that the fins extend along the Y direction, and the length of the dummy gate structure is the length of the dummy gate structure spanning between adjacent fins along the X direction.

[0057] Fig.16 yes Fig.17 and Fig.18 A top view of Fig.17 yes Fig.16 In the AA section, Fig.18 yes Fig.16 A cross-sectional view of the BB.

[0058] In this embodiment, the dummy gate structure includes a dummy gate dielectric layer 204 and a dummy gate electrode layer 205 .

[0059] The material of the dummy gate dielectric layer 204 is silicon oxide.

[0060] In this embodiment, the formation process of the dummy gate dielectric layer 204 is an in-situ steam generation process (ISSG). The dummy gate dielectric layer 204 formed by the in-situ steam generation process has good step coverage, and can make the formed dummy gate dielectric layer 204 tightly cover the sidewall surface of the fin structure 220, and the thickness of the formed dummy gate dielectric layer 204 is uniform.

[0061] The material of the dummy gate electrode layer 205 is polysilicon.

[0062] In another embodiment, the formation process of the dummy gate dielectric layer 204 is a chemical oxidation process; the method of the chemical oxidation process includes: using an aqueous solution into which ozone is introduced to oxidize the exposed sidewalls and top surface of the fin structure 220 to form the dummy gate dielectric layer 204.

[0063] In this embodiment, a dummy gate structure is formed on the substrate 210 , and the dummy gate structure spans the fins 220 . The dummy gate structure of the first region 202 is located between the fins 220 in the sparse region 221 , and the dummy gate structure of the second region 203 is located between the fins 220 in the dense region 222 .

[0064] In this embodiment, the method further includes: forming a protection layer 206 on the top of the dummy gate structure.

[0065] In this embodiment, the material of the protective layer 206 is silicon nitride; in other embodiments, the material of the protective layer 206 may also be one or more combinations of materials such as silicon oxide, silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon carbon boron nitride (SiCBN).

[0066] In this embodiment, the protection layer 206 is used to protect the top surface of the dummy gate structure from being damaged in subsequent processes.

[0067] In this embodiment, the method further includes: forming a sidewall spacer 207 on the sidewalls of the dummy gate structure and the protection layer 206 .

[0068] The function of the sidewall 207 is to define the position of the subsequently formed source and drain doping layer, and the sidewall 207 is used to protect the sidewall of the dummy gate electrode layer 205 to prevent the subsequently formed gate electrode layer from having morphological defects and affecting the electrical performance of the semiconductor structure.

[0069] In this embodiment, the material of the sidewall 207 is silicon oxide; in other embodiments, the material of the sidewall 206 may also be silicon nitride, silicon carbide, silicon oxynitride, etc.

[0070] Please refer to Fig.19 A source-drain doping layer 208 is formed in the fins 220 on both sides of the dummy gate structure, and an interlayer dielectric layer 209 is formed on the source-drain doping layer 208 , and the interlayer dielectric layer 209 covers the sidewalls of the gate structure.

[0071] Fig.19 The viewing direction and Fig.17 The viewing direction is the same.

[0072] In this embodiment, source-drain doped layers 208 are formed in the fins 220 on both sides of the sidewall spacer 207 , and an interlayer dielectric layer 209 is formed on the source-drain doped layers 208 . The interlayer dielectric layer 209 covers the sidewalls of the sidewall spacer 207 .

[0073] In this embodiment, the interlayer dielectric layer 209 is formed by a chemical vapor deposition process; in other embodiments, the interlayer dielectric layer 209 may be formed by an atomic layer deposition process or a physical vapor deposition process.

[0074] In this embodiment, the material of the interlayer dielectric layer 209 is silicon oxide; in other embodiments, the material of the interlayer dielectric layer 209 may also be one or more combinations of materials such as silicon nitride, silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon carbon boron nitride (SiCBN).

[0075] Please refer to Fig. 20 , a patterned layer 300 is formed on the top surface of the protective layer 206, and a portion of the pseudo gate structure of the first region 202 is etched using the patterned layer 300 as a mask, so as to form an opening 230 in the pseudo gate structure of the first region 202, and the bottom of the opening 230 exposes the surface of the substrate 200.

[0076] Fig. 20 The viewing direction and Fig.18 The viewing direction is the same.

[0077] In this embodiment, a portion of the dummy gate electrode layer 205 in the first region 202 is etched to form an opening 230 in the dummy gate electrode layer 205 in the first region 202 , and the bottom of the opening 230 exposes the surface of the dummy gate dielectric layer 204 .

[0078] In this embodiment, the number of the opening 230 is one; in other embodiments, the number of the opening 230 may be more than one.

[0079] In this embodiment, the purpose of forming the opening 230 is to provide space for the subsequent formation of a stop layer.

[0080] In this embodiment, the process of forming the opening 230 is a dry etching process; in other embodiments, the process of forming the opening 230 is a wet etching process.

[0081] Please refer to Figure 21 to Figure 22 , a stop layer 231 is formed in the opening 230 , and the stop layer 231 completely fills the opening 230 .

[0082] Fig.21 The viewing direction and Fig. 20 The viewing direction is the same; Fig. 22 The viewing direction and Fig.19 The viewing direction is the same.

[0083] In this embodiment, the number of the stop layer 231 is one, and the number of the stop layer 231 is the same as the number of the openings 230 .

[0084] In other embodiments, there may be more than one stop layer 231 .

[0085] In this embodiment, before forming the stop layer 231 in the opening 230 , the patterning layer 300 and the protection layer 206 are removed, and the stop layer 231 completely fills the opening 230 .

[0086] In this embodiment, the process of removing the patterned layer 300 and the protective layer 206 is an etching process; in other embodiments, the process of removing the patterned layer 300 and the protective layer 206 may also be an ashing process.

[0087] In this embodiment, the step of forming the stop layer 231 includes: forming an initial stop layer on the top surface of the dummy gate structure and in the opening 230 , flattening the initial stop layer until the top surface of the dummy gate structure is exposed, and forming the stop layer 231 in the opening 230 .

[0088] In this embodiment, the stop layer 231 is formed by an atomic layer deposition process because the atomic layer deposition process can form the stop layer 231 with a better coverage gradient and can fill the opening 230 to a higher degree, thereby improving the quality of the formed stop layer 231 .

[0089] In this embodiment, the material of the stop layer 231 is silicon nitride;

[0090] In other embodiments, the material of the stop layer 231 is one or more combinations of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, and silicon carbon boronitride.

[0091] Please refer to Figure 23 to Figure 24 , remove the dummy gate structure, form a gate opening (not shown in the figure) on the substrate 200, and form an initial gate structure in the gate opening.

[0092] Fig.23 The viewing direction and Fig.21 The viewing direction is the same; Fig.24 The viewing direction and Fig. 22 The viewing direction is the same.

[0093] In this embodiment, the dummy gate dielectric layer 204 , the dummy gate electrode layer 205 , and the protection layer 206 located on the top of the dummy gate electrode layer 205 are removed.

[0094] In this embodiment, the initial gate structure includes: a gate dielectric layer 241, a work function layer 242 and an initial gate electrode layer 240, the gate dielectric layer 241 forms the sidewalls and top of the gate opening, the work function layer 242 is formed on the gate dielectric layer 241, and the gate electrode layer 240 is formed on the work function layer 242 and fills the gate opening.

[0095] The material of the gate dielectric layer 241 is a high-k dielectric material (dielectric constant greater than 3.9); the high-k dielectric material includes one or more combinations of hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.

[0096] The material of the work function layer 242 includes one or more combinations of TaN, TiSiN, TaSiN, TaAl, TiAlC, AlN, TiAlN or TaAlN.

[0097] The material of the initial gate electrode layer 240 is metal, and the metal material includes one or more combinations of copper, tungsten, nickel, chromium, titanium, tantalum and aluminum.

[0098] Please refer to Figure 25 to Figure 27 , the initial gate structure is planarized until the top surface of the stop layer 231 is exposed to form a gate structure 244.

[0099] In this embodiment, the initial gate electrode layer 240 is planarized until the top surface of the stop layer 231 is exposed to form a gate electrode layer 243 .

[0100] Fig.25 yes Fig.26 , Fig. 27 A top view of Fig.26 yes Fig.25 In the section view along section line AA, Fig. 27 yes Fig.25 Section view at section line BB.

[0101] In this example, please compare Fig.26 and Fig.12 , Fig. 27 and Fig.11Due to the existence of the stop layer 231, during the process of planarizing the initial gate electrode layer 240, when the top surface of the stop layer 231 is exposed, the planarization process can no longer continue, so that the planarization process is stopped, thereby reducing the loss of the initial gate electrode layer 240 and preventing the formed gate electrode layer 243 from being excessively lost, thereby ensuring that the work function layer at the bottom has good quality and avoiding the impact on the threshold voltage. At the same time, the fin surface at the bottom is protected, thereby ensuring the quality of the formed gate structure and the quality of the fin, ensuring that the semiconductor device has a stable threshold voltage during use, and improving the performance of the semiconductor device.

[0102] In this embodiment, the process for planarizing the initial gate electrode layer 240 is a chemical mechanical polishing process.

[0103] Correspondingly, the present invention also provides a semiconductor device, comprising: a substrate 200; a gate structure 244, located on the substrate 200, including a first region 202 and a second region 203, wherein the length of the gate structure of the first region 202 is greater than the length of the gate structure of the second region 203; and a stop layer 231, located on the substrate 200 and within the gate structure of the first region 202.

[0104] In this embodiment, the stop layer 231 is located on the substrate 200 and in the gate structure 244 of the first area 202. Due to the existence of the stop layer 231, on the one hand, the stop layer 231 divides the gate structure 244 of the first area 202 to achieve the gate cut of the gate structure 244 of the first area 202; on the other hand, during the formation of the gate structure, the stop layer serves as a stop mark of the gate structure during the formation process, which can avoid excessive loss of the gate structure during the formation process, thereby improving the formation quality of the gate structure.

[0105] The number of the stop layer 231 is one or more. In this embodiment, the number of the stop layer 231 is one; in other embodiments, the number of the stop layer 231 may be more than one.

[0106] In this embodiment, the material of the stop layer 231 is silicon nitride;

[0107] In other embodiments, the material of the stop layer 231 is one or more combinations of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, and silicon carbon boronitride.

[0108] In this embodiment, the base 200 includes: a substrate 210 and a plurality of discretely arranged fins 220 located on the substrate 210 , and the fins 220 include a sparse area 221 and a dense area 222 .

[0109] The distance between the fins in the dense area 222 is smaller than the distance between the fins in the sparse area 221 .

[0110] In this embodiment, the gate structure 244 is located on the substrate 210 and spans across the fins 220 . The gate structure 244 in the first region 202 is located between the fins 220 in the sparse region 221 , and the gate structure 244 in the second region 203 is located between the fins 220 in the dense region 222 .

[0111] In this embodiment, the gate structure 244 includes a gate dielectric layer 241, a work function layer 242 and a gate electrode layer 243. The gate dielectric layer 241 is located on the top and side walls of the fin 220, the work function layer 242 is located on the gate dielectric layer 241, and the gate electrode layer 243 is located on the work function layer 242. The material of the gate electrode layer 243 is metal.

[0112] In this embodiment, it further includes: an isolation layer 201 , which is located on the substrate 210 and covers a portion of the sidewalls of the fins 220 . The isolation layer 201 is used for electrically isolating adjacent fins 220 .

[0113] In this embodiment, the material of the isolation layer 201 is silicon oxide; in other embodiments, the material of the isolation layer 201 may also be silicon nitride, silicon oxynitride, etc.

[0114] In this embodiment, the structure further includes: a source-drain doped layer 208 located in the fin 220 on both sides of the gate structure 244 .

[0115] The formation process of the source-drain doping layer 208 includes epitaxial growth and in-situ doping processes.

[0116] In this embodiment, the structure further includes: an interlayer dielectric layer 209 , which is located on the source / drain doping layer 208 and covers the sidewall surface of the gate structure 244 .

[0117] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a plurality of fins arranged discretely from each other; a gate structure located on the substrate and comprising a first region and a second region, wherein the gate structure in the first region is longer than the gate structure in the second region, the gate structure spans a plurality of the fins that are arranged separately from each other, and the length of the gate structure is perpendicular to an extension direction of the fins; A stop layer is located on the substrate and within the gate structure of the first region.

2. The semiconductor device according to claim 1, wherein The number of the stop layer is one or more.

3. The semiconductor device according to claim 1, wherein The material of the stop layer is one or more combinations of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, and silicon carbon boron nitride.

4. A method for forming a semiconductor device, characterized in that: include: Providing a substrate having a plurality of fins arranged discretely thereon, and forming a dummy gate structure on the substrate, wherein the dummy gate structure includes a first region and a second region, wherein the dummy gate structure length in the first region is greater than the dummy gate structure length in the second region, and the dummy gate structure spans the plurality of fins arranged discretely thereon, and the length direction of the dummy gate structure is perpendicular to an extension direction of the fins; Etching a portion of the dummy gate structure in the first region to form an opening in the dummy gate structure in the first region, wherein a bottom of the opening exposes the surface of the substrate; forming a stop layer in the opening, wherein the stop layer completely fills the opening; removing the dummy gate structure, forming a gate opening on the substrate, and forming an initial gate structure in the gate opening; The initial gate structure is planarized until the top surface of the stop layer is exposed to form a gate structure.

5. The method for forming a semiconductor device according to claim 4, wherein: The number of the openings is equal to the number of the stop layers.

6. The method for forming a semiconductor device according to claim 5, wherein: The number of the opening is one and the number of the stop layer is one, or the number of the opening is multiple and the number of the stop layer is multiple.

7. The method for forming a semiconductor device according to claim 4, wherein: The material of the stop layer is one or more combinations of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, and silicon carbon boron nitride.

8. The method for forming a semiconductor device according to claim 4, wherein: The process of forming the stop layer is one or a combination of chemical vapor deposition process, atomic layer deposition process or physical vapor deposition process.

9. The method for forming a semiconductor device according to claim 4, wherein: The method for forming the stop layer is: forming an initial stop layer on the top surface of the dummy gate structure; and planarizing the initial stop layer until the top surface of the dummy gate structure is exposed.

10. The method for forming a semiconductor device according to claim 4, wherein: The gate structure includes a gate dielectric layer formed on the substrate, a work function layer formed on the gate dielectric layer, and a metal layer formed on the work function layer.

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