Integrated circuit and system including integrated circuit

Abstract

The present invention relates to an integrated circuit and a system including the integrated circuit. An integrated circuit is described that utilizes logic elements (e.g., flip-flops) driven by internal state machines within input and / or output wrapper chains, which are used to test the internal core logic of the integrated circuit. One or more individual logic elements in the wrapper chain within the integrated circuit are implemented as multi-flip-flop state machines rather than single digital flip-flops. As a multi-flip-flop state machine, each enhanced logic element in the wrapper chain can be individually configured to output a pre-selected value to decouple the flip-flops driven by the state machine from signal transmission delays that may occur in the input or output wrapper chain of the integrated circuit.

Description

Technical Field

[0001] The present disclosure relates to application specific integrated circuits (ASICs), integrated circuits (ICs), and other circuits. Background Art

[0002] Semiconductor integrated circuits (also referred to as "chips") such as application specific integrated circuits (ASICs) include a variety of different types of logic elements such as logic gates, flip-flops, and multiplexers. Data processing integrated circuits such as packet processing ASICs include internal logic elements that operate on data and ultimately control the flow of data through the chip. In some examples, the tester performs tests to determine whether the data flows through the chip in an expected manner. For example, the tester transmits data for input to the chip, receives data output from the chip, and compares the data output from the chip with the expected output data. Based on the comparison, the tester can identify one or more defects in the chip. Summary of the invention

[0003] The present disclosure describes an example of an integrated circuit that utilizes internal state machine driven logic elements (e.g., flip-flops) within an input and / or output wrapper chain for testing the internal core logic of the integrated circuit. As described herein, one or more individual logic elements in the wrapper chain within the integrated circuit are implemented as corresponding multi-flip flop state machines rather than single digital flip-flops. Moreover, each state machine-driven logic element in the wrapper chain is capable of operating in one of a set of programmable operating modes to provide desired behavior during testing of the integrated circuit.

[0004] More specifically, as a multi-flip flop state machine, each enhanced logic element in a wrapper chain can be individually configured to output a pre-selected value to decouple the state machine driven flip-flops from signal transmission delays that may occur in an input or output wrapper chain of an integrated circuit. During testing of the core logic of an integrated circuit, the flip-flops in an input or output wrapper chain are typically connected in series, and each flip-flop in a given input wrapper chain provides outputs to the core logic and consecutive flip-flops in the input wrapper chain. Due to slow interconnections between consecutive flip-flops in an input wrapper chain (e.g., bandwidth-constrained internal electrical connections, distances between flip-flops, etc.), the outputs from conventional flip-flops in the wrapper chain may be unknown for a short period of time (e.g., because the flip-flops output data before receiving data at their inputs). As described herein, by replacing one or more conventional flip-flops in an input or output wrapper chain with corresponding state machine driven flip-flops, the exemplary techniques described herein can provide immunity to slow connections (e.g., internal transmission delays) that would otherwise result in undefined states in the input or output wrapper chain. For example, because state machine driven flip-flops can be configured to operate in a scan mode that defines pre-selected output values, the outputs of these elements in a wrapper chain can be decoupled from the input values ​​of logic elements when the input signals may be uncertain due to transmission delays along the scan path of a given wrapper chain.

[0005] In this manner, the techniques herein describe an enhanced wrapper chain in which conventional flip-flops at the receiving end of a slow interconnect along a scan path are replaced with additional circuitry to create a state machine driven multi-flip flop logic element referred to herein as a 'state machine driven flip-flop.' As further described, when configured to operate in a scan mode, the state machine driven flip-flop no longer relies on input signals from the slow connection so that the state machine driven flip-flop operates to capture expected data bit values ​​during the capture phase of testing. In other words, even though one or more slow connections may be present in the scan path of an input or output wrapper chain, the conversion of at least one flip-flop in the wrapper chain to a state machine driven flip-flop allows the core logic to capture all expected input data bit values ​​during the capture phase.

[0006] In this manner, in some examples, state machine driven flip-flops may be individually configured, which provides the flexibility to output pre-selected values ​​according to a programmable mode of operation. For example, as described in more detail, a state machine driven flip-flop in a wrapper chain may be configured to provide a constant output (e.g., maintain the mode of operation) based on a current value previously shifted into the flip-flop during the capture phase, rather than providing an output based on an input signal present at the input of the flip-flop, which current value was shifted during the load phase. As another example, a state machine driven flip-flop in an input or output wrapper chain may be configured to output an inverse value (e.g., switch the mode of operation) of a current value previously shifted into the flip-flop during the capture phase, rather than based on an input received at the flip-flop, which current value was shifted during the load phase. In this manner, as described herein, a state machine driven flip-flop may be used within a slow wrapper chain path to provide fine-grained control of the values ​​and / or transformations present at the function and scan outputs during the capture phase, thereby eliminating any timing issues that may otherwise arise due to a slow internal wrapper chain path within an integrated circuit.

[0007] In some examples, the present disclosure describes an integrated circuit (IC) including a core logic having functional logic elements and a wrapper chain having a plurality of flip-flops for testing the core logic. The plurality of flip-flops in the wrapper chain are interconnected in sequence along a scan path for shifting scan data through consecutive flip-flops during testing of the core logic. The IC also includes at least one state machine driven flip-flop connected along the scan path of the wrapper chain. The state machine driven flip-flops can be individually configured during testing to output values ​​independent of scan data shifted along the scan path and received by the state machine driven flip-flops.

[0008] In some examples, the present disclosure describes a system including a tester and an integrated circuit (IC). The IC includes a core logic having functional logic elements and an input wrapper chain having a plurality of flip-flops for testing the core logic. The plurality of flip-flops in the wrapper chain are interconnected in sequence along a scan path for shifting scan data through consecutive flip-flops during testing of the core logic. The IC also includes an output wrapper chain and at least one state machine driven flip-flop connected along the scan path of the input wrapper chain. The state machine driven flip-flops can be individually configured to output values ​​independent of the scan data shifted along the scan path and received by the state machine driven flip-flops during testing. In one or more examples, the input wrapper chain is configured to load an input data string from the tester in response to receiving a set of load phase clock signals at a slow clock frequency during a loading phase to load values ​​into a plurality of flip-flops and configure the state machine driven flip-flops to output values ​​independent of the scan data shifted along the scan path. In one or more examples, the output wrapper chain is configured to capture captured data strings from multiple functional paths through core logic in response to receiving a set of capture phase clock signals at a fast clock rate during a capture phase and to unload the captured data strings to a tester in response to receiving a set of unload phase clock signals at a slow clock rate during an unload phase.

[0009] The summary is intended to provide an overview of the subject matter described in the present disclosure. It is not intended to provide an exclusive or exhaustive description of the systems, devices, and methods described in detail in the accompanying drawings and the following description. Further details of one or more examples of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating an example system including a set of logic blocks having one or more state machine driven flip-flops in an input or output wrapper chain, in accordance with one or more techniques of this disclosure.

[0011] Figure 2 is a block diagram illustrating a system including an input wrapper chain including a trigger and a set of input wrapper chain connections, in accordance with one or more techniques of this disclosure.

[0012] Figure 3A is a block diagram illustrating a flip-flop including a set of inputs and a set of outputs, in accordance with one or more techniques of this disclosure.

[0013] Figure 3B is a block diagram illustrating one example of a state machine driven flip-flop in accordance with one or more techniques of this disclosure.

[0014] Figure 4 is a block diagram illustrating a state machine driven flip-flop at the end of a slow connection in accordance with one or more techniques of this disclosure.

[0015] Figure 5 is a diagram illustrating a clock signal diagram, a first control signal diagram, and a second control signal diagram for loading, capturing, and unloading data through flip-flops in an input or output wrapper chain in accordance with one or more techniques of this disclosure.

[0016] Figure 6 is a flow diagram illustrating example operations for performing testing operations in accordance with one or more techniques of this disclosure.

[0017] Like reference numerals refer to like elements throughout the text and drawings. DETAILED DESCRIPTION

[0018] Figure 1 1 is a block diagram illustrating an exemplary system 2 in which an integrated circuit 8 of a semiconductor device includes a set of logic blocks 10A-10N (collectively referred to as “logic blocks 10”) for testing the integrated circuit 8, the set of logic blocks having one or more state machine driven flip-flops in an input wrapper chain or an output wrapper chain according to one or more techniques of the present disclosure. Figure 1 As seen in the figure, in this example, system 2 includes an integrated circuit (IC) 8, which includes a logic block 10 and a top logic 18. System 2 also includes a tester 20. Logic block 10A includes a first group of input / output (I / O) triggers 12A–12N (collectively referred to as "triggers 12"), a second group of I / O triggers 14A–14N (collectively referred to as "triggers 14"), and core logic 16. As described in more detail, trigger 12 forms an input wrapper chain and trigger 14 forms an output wrapper chain. As described in more detail, in one or more examples, one of the triggers in trigger 12 or trigger 14 can be replaced by a state machine driven multi-trigger logic element, referred to herein as a "state machine driven trigger" or SMDF. For example, Figure 1 An SMDF 13 is shown in the input wrapper chain and an SMDF 15 is shown in the output wrapper chain.

[0019] Although one SMDF 13 is shown in the input wrapper chain, there may be multiple SMDFs in the input wrapper chain. Although one SMDF 15 is shown in the output wrapper chain, there may be multiple SMDFs in the output wrapper chain. In some examples, there may be one or more SMDFs such as SMDF 13 in the input wrapper chain without any SMDF in the output wrapper chain. In some examples, there may be one or more SMDFs such as SMDF 15 in the output wrapper chain without any SMDF in the input wrapper chain.

[0020] In some cases, IC 8 is an application specific integrated circuit (ASIC), and logic block 10 and top logic 18 represent components in the ASIC, but this is not required. In some cases, logic block 10 and top logic 18 can be components in some other circuit.

[0021] Each of logic blocks 10 includes one or more semiconductor-based logic elements configured to control the flow of data. For example, Figure 1 A functional path 17 is shown, which represents a chain of one or more logic elements within the core logic 16, which are configured to process electrical signals (e.g., data bits) according to the functional logic elements within the core logic 16. That is, during normal operation of the IC 8, the functional path 17 represents a path from input to output through the functional logic elements of the core logic 16. For example, the functional path 17 can accept input data bit values ​​and generate output data bit values, which are generated in response to the logic elements of the path applying one or more logic operations to the data bit values. In some examples, the core logic 16 may include one or more core flip-flops. One or more functional paths 17 may start with a corresponding core flip-flop and end with a flip-flop 14. One or more functional paths 17 may start with a flip-flop 12 and end with a core flip-flop.

[0022] Figure 1 Also shown is a scan path 19 used to test the integrated circuit 8. The scan path 19 is an example of a path through a wrapper chain formed by a series of flip-flops 12 used to test corresponding logic elements in the core logic 16 that receive data from corresponding flip-flops 12 of the wrapper chain. For example, as described in more detail, during testing of the IC 8, such as during testing of the core logic 16, the scan path 19 represents a path used to propagate test data through the wrapper chain, where the various flip-flops 12 are connected in series and each flip-flop 12 receives data from a previous one of the flip-flops 12 and outputs to a subsequent flip-flop 12 and a corresponding logic element in the core logic 16.

[0023] For example, a wrapper chain (e.g., an input wrapper chain) includes a plurality of flip-flops 12 for testing core logic 16. The plurality of flip-flops 12 are interconnected in sequence along a scan path (e.g., scan path 19) for shifting scan data through successive flip-flops in the flip-flops 12 during testing of the core logic 16. Although only the input wrapper chain is described, similar interconnections can also be used for an output wrapper chain having a plurality of flip-flops 14.

[0024] In some examples, logic block 10A uses functional path 17 when logic block 10A functions according to its intended purpose. For example, when logic block 10A is applied to process data as designed, the logic block 10A processes data using functional path 17 instead of scan path 19. On the other hand, scan path 19 is operable during testing.

[0025] In the functional mode of the system 2, the logic block 10A is configured to receive data via the flip-flop 12, the logic operation of the functional path 17 uses the core logic 16 to process the data, and output the data to the top logic 18 via the flip-flop 14. Therefore, the flip-flop 12 can be referred to as an "input wrapper chain" in this article, which receives data from the outside of the logic block 10A, and the flip-flop 14 can be referred to as an "output wrapper chain" in this article, which forwards the data from the logic block 10A after the core logic 16 processes the data.

[0026] As described in more detail, the SMDF 13 is configured to operate similarly to the trigger 12 in the functional mode. For example, the SMDF 13 is configured to output the received data to the core logic 16. However, during the test, the SMDF 13 is configured to output the pre-stored data to the core logic 16, and the subsequent triggers in the input wrapper chain. As shown, the SMDF 13 is connected along the scan path (e.g., scan path 19) of the wrapper chain (e.g., the input wrapper chain). As described in more detail, the SMDF 13 can be configured separately during the test to output a value that is independent of the scan data shifted along the scan path and received by the SMDF 13. For example, as described in more detail, during the loading phase of the test, the SMDF 13 can be configured to output the data received from the previous trigger at its input. However, during the capture phase, the SMDF 13 does not output the data received at the input of the SMDF 13, but outputs a value that is independent of the scan data shifted along the scan path and received by the SMDF 13.

[0027] For testing, one or more flip-flops 12 are configured to output to a consecutive set of flip-flops and core logic 16 during testing. One or more flip-flops 14 are configured to output to a consecutive set of flip-flops and receive from core logic 16 during testing. That is, the input wrapper chain includes a first plurality of flip-flops 12, wherein one or more flip-flops in the first plurality of flip-flops 12 are configured to output to a consecutive set of flip-flops in the first plurality of flip-flops 12 and core logic 16 during testing. In addition, the output wrapper chain includes a second plurality of flip-flops 14, wherein one or more flip-flops in the second plurality of flip-flops 14 are configured to output to a consecutive set of flip-flops in the second plurality of flip-flops 14 and receive from core logic 16 during testing. For example, as shown, during testing, flip-flop 12A outputs to flip-flop 12B, flip-flop 12B outputs to flip-flop 12C, and so on, and then to flip-flop 12N, and similarly, during testing, flip-flop 14A outputs to flip-flop 14B, flip-flop 14B outputs to flip-flop 14C, and so on, and then to flip-flop 14N. Thus, for testing, each of the flip-flops 12 or 14 shifts data to consecutive flip-flops in the flip-flops 12 or 14 .

[0028] As described in the present disclosure, one or more of the triggers in the trigger 12 or the trigger 14 are replaced by a state machine driven multi-trigger logic element referred to herein as a 'state machine driven trigger'. For example, there is no trigger 12C, which is replaced by a state machine driven trigger (SMDF) 13, and there is no trigger 14B, which is replaced by SMDF 15. SMDF 13 and SMDF 15 are examples of wrapper units. For example, as described in more detail, SMDF 13 and SMDF 15 include circuits associated with the trigger 12 or the trigger 14 (e.g., a trigger in a scan wrapper chain such as an input wrapper chain or an output wrapper chain), and provide all the functions of the trigger 12 and the trigger 14, and it is expected that SMDF 13 and SMDF 15 are configured to not output continuous trigger data received at the input of SMDF 13 or SMDF 15 during testing (such as during the capture phase of testing).

[0029] For example, SMDF 13 and SMDF 15 may be individually configured to output pre-selected values ​​so that SMDF 13 and SMDF 15 are independent of the delays of the connections in the input wrapper chain or the output wrapper chain. That is, SMDF 13 or SMDF 15 may be individually configured to output values ​​independent of the scan data shifted along the scan path and received by SMDF 13 or SMDF 15 during testing. Such output of values ​​independent of the scan data occurs during the capture phase of the test, where the shift delay affects SMDF 13 or SMDF 15 and the data cannot be received in time. Therefore, SMDF 13 and SMDF 15 can provide immunity to the shift delay of data shifted through the input wrapper chain or the output wrapper chain.

[0030] For example, depending on the specific implementation and layout of the integrated circuit being tested, there may be slow signal transmission along the connections between consecutive flip-flops in the input wrapper chain and / or the output wrapper chain relative to the signal transmission speed within the core logic 16. For example, there may be a possibility that a connection between two flip-flops in an input or output wrapper chain propagates data at a rate that is less than the operating rate of the core logic 16 (e.g., less than the rate at which the core logic 16 operates or can operate). Slow connections along the scan path 19 may, for example, affect testing because errors may be caused by the slow connection as scan data is shifted through the flip-flops 12 / 14 along the scan path rather than by functional circuit failures such as circuits within the core logic 16.

[0031] As described in more detail, a slow connection between consecutive flip-flops can be identified during design, and a flip-flop in flip-flop 12 or flip-flop 14 at the end of the slow connection can be replaced by a state machine driven flip-flop that allows the output of the state machine driven flip-flop to be selectively set to a known value regardless of the input of the state machine driven flip-flop (e.g., regardless of the scan data shifted along the scan path and received by the state machine driven flip-flop). Thus, the dependency of the output of the state machine driven flip-flop on the input based on the state machine driven flip-flop is eliminated, and the impact of the slow connection can be mitigated.

[0032] For example, during design, flip-flop 12B may be designed to be connected to a similar flip-flop (e.g., flip-flop 12C), and flip-flop 12B and flip-flop 12C may be interconnected via connection 19 (e.g., via or microstrip). During design, connection 19 may be identified as a slow connection (e.g., due to the distance between flip-flop 12B and flip-flop 12C, or due to bandwidth constraints on connection 19). For example, data cannot be propagated through connection 19 at the same speed as data propagates through core logic 16. In other words, connection 19 propagates data at a rate less than the operating rate of core logic 16. Therefore, flip-flop 12C is replaced by SMDF 13 (i.e., a state machine driving a multi-flip-flop logic element). During testing, such as during the capture phase of testing, SMDF 13 is configured to output a pre-stored value (e.g., a value shifted into a flip-flop of SMDF 13 during a loading phase or an inverse value of a value shifted into a flip-flop of SMDF 13), rather than a value received at its input during testing. However, during normal operation, SMDF 13 is configured to output data received at its functional inputs to core logic 16 .

[0033] Similarly, during design, flip-flop 14A may be designed to be connected to another flip-flop (e.g., SMDF 15), and flip-flop 14A and SMDF 15 may be interconnected via connection 21. During design, connection 21 may be identified as a slow connection (e.g., due to the distance between flip-flop 14A and flip-flop 14B, or due to bandwidth constraints of connection 21). For example, data cannot propagate through connection 21 at the same speed as data propagates through core logic 16. Therefore, flip-flop 14B is replaced by SMDF 15 (i.e., a state machine driven multi-flip-flop logic element). During testing, such as during the capture phase of testing, SMDF 15 is configured to output a value that is independent of the scan data received by the flip-flops that are shifted along the scan path and driven by the state machine.

[0034] As shown, testing of IC 8 and logic block 10 is performed by tester 20. For illustration purposes only, use of tester 20 is shown. In some examples, tester 20 or functionality of tester 20 may be integrated on IC 8 to provide IC 8 with logic testing capabilities.

[0035] The tester 20 may include, for example, a microprocessor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA), or equivalent discrete or integrated logic circuits, or a combination of any of the foregoing devices or circuits. Therefore, as used herein, the terms "processor," "controller," and "tester" may refer to any one or more of the foregoing structures or any other structure operable to perform the techniques described herein. In some examples, the tester 20 may execute a program executed by a memory ( Figure 1 1 ) to control one or more components in the system 2. For example, the tester 20 may configure the scan path 19 so that each trigger 12 outputs to consecutive triggers 12.

[0036] However, if a flip-flop 12 is replaced by an SMDF 13, the SMDF 13 may output a current value or an inverse value of the current value to a subsequent one of the flip-flops 12, rather than a value received at the input of the SMDF 13. For example, the SMDF 13 may be configured to hold as an output the current value of the SMDF 13 during testing, the current value of the SMDF 13 being shifted into the SMDF 13 during a previous shift cycle. As another example, the SMDF 13 may be configured to output, during testing, an inverse value of the current value of the SMDF 13, the current value being shifted into the SMDF 13 during a previous shift cycle. For example, during a loading phase of a test that occurs prior to a capture phase of the test, the SMDF 13 may be configured to hold as an output the current value of the SMDF 13 that was shifted into the SMDF 13 during the loading phase, or may be configured to output the inverse value of the current value of the SMDF 13 that was shifted into the SMDF 13 during the loading phase.

[0037] In order to determine whether the IC 8 including the logic block 10 is performing the expected function, the tester 20 performs a test operation on the functional path 17 (e.g., the functional logic element of the core logic 16) to identify whether a set of data output from the flip-flop 14 matches a set of expected data. When the set of data output from the flip-flop 14 during the test operation does not match the set of expected data, the tester 20 determines that the core logic 16 is associated with at least one error. However, if there is a slow connection between the flip-flop 12 or the flip-flop 14 that causes the error, the tester 20 cannot determine whether the error is caused by the slow connection or a fault exists in the core logic 16.

[0038] For example, as described in more detail, during the capture phase of the test, a clock signal causes the output of the flip-flop 12 or flip-flop 14 to a consecutive flip-flop. The clock signal used in the capture phase is a relatively fast clock signal (e.g., a relatively high frequency). If there is a slow connection between consecutive flip-flops 12 or flip-flops 14, the flip-flop at the end of the slow connection may close the input sampling window before the bit from the previous flip-flop is at the input of the flip-flop. In this case, the output from the flip-flop may be unknown, and the cause of the error (e.g., due to a failure of the core logic 16 or due to a slow connection) is unknown.

[0039] The test operation performed by the tester 20 includes three phases: a loading phase, a capture phase, and an unloading phase. During the loading phase, the tester 20 directs a data pattern including a data bit string to the trigger 12, causing the trigger 12 to "load" the data bit string while preserving the order of the data bit string. That is, the trigger 12N loads the first data bit of the data bit string, the previous trigger of the trigger 12N loads the second data bit of the data bit string, and so on. The trigger 12 vertically loads the data bit string along the input wrapper chain in response to receiving a set of loading phase clock signals at a slow clock frequency. During the loading phase, the SMDF 13 shifts the data received from the trigger 12B along the scan path.

[0040] During the capture phase of the test operation, the flip-flops 12 of the input wrapper chain output a data bit string for processing by the functional path 17 in response to receiving a set of capture phase clock signals at a fast clock frequency, so that the flip-flops 14 of the output wrapper chain receive the "captured" data bit string. During the unload phase, the flip-flops 14 receive a set of unload phase clock signals at a slow clock frequency, so that the flip-flops 14 unload the captured data bit string to the tester 20. The tester 20 compares the captured data bit string with the expected captured data bit string, and the comparison shows whether the functional path 17 causes one or more errors when processing the data bit string output from the flip-flops 12 during the capture phase. The core logic 16 may include one or more core flip-flops and core flip-flop chains. For example, one or more core flip-flop chains can output data to the tester 20 and receive data from the flip-flops 12. One or more slow connections between the flip-flops 12 may not affect the data received by the core logic chain from the flip-flops 12. In this way, the core flip-flop chain can perform one or more techniques described herein that are performed by the output wrapper chain including the flip-flops 14.

[0041] During testing, a set of connections connects the flip-flops 12 together. However, during normal operation, the flip-flops 12 may not be connected together, or may be connected together but the output of the previous flip-flop is not used as the input of the current flip-flop. For example, flip-flop 12 and similar flip-flops 14 may include a multiplexer (MUX) at the input, and the MUX selects between one connection from the previous flip-flop and another connection for regular data (e.g., for flip-flop 12, data from another circuit connected to the ASIC, and for flip-flop 14, data from core logic 16). For testing, the MUX selects the connection from the previous flip-flop.

[0042] However, during the capture phase, SMDF 13 and SMDF 15 can be configured to receive data from a previous trigger, but not output the data received from the previous trigger. Instead, SMDF 13 and SMDF 15 output the value or the inverse of the value that has been shifted into the trigger of SMDF 13 and SMDF 15 (i.e., unrelated to the scan data shifted along the scan path and received by SMDF 13 or SMDF 15). In this way, even if connections 19 and 21 are slow connections (e.g., connections of the scan path that cannot propagate data as fast as the inline components of core logic 16), the impact of connections 19 and 21 is mitigated because SMDF 13 and SMDF 15 are configured to output the current value of SMDF 13 or SMDF 15 or the inverse of the current value.

[0043] That is, for testing, each pair of consecutive flip-flops is connected by a corresponding connection in the set of connections. For example, flip-flops 12A and 12B are linked by a first connection in a set of connections. The connections that link flip-flops 12 represent electrical connections configured to carry data (e.g., electrical signals indicating one or more data bit values) between corresponding flip-flops in the input wrapper chain. The connections interconnect flip-flops 12 sequentially along the scan path for shifting scan data through consecutive flip-flops in flip-flops 12 during testing of core logic 16.

[0044] The bandwidth of a connection link affects the time it takes for an electrical signal to propagate through each connection in a set of connections that form an input wrapper chain. In some cases, at least one connection in the set of connections that form the input wrapper chain represents a "slow" connection such as connection 19, where the amount of time it takes for an electrical signal to propagate through the slow connection link 19 is greater than a threshold amount of time. For example, a connection 19 between an SMDF 13 and a previous flip-flop in a wrapper chain propagates data to the SMDF 13 at a rate that is less than the operating rate of the core logic 16 (e.g., a connection 19 in a scan path cannot propagate data as fast as an inline component of the core logic 16). Although described only with respect to flip-flop 12, this also applies to flip-flops 14 in the output wrapper chain.

[0045] If the amount of time it takes for an electrical signal to propagate through a slow connection is greater than a threshold amount of time, then when flip-flop 12 receives a capture phase clock signal at a fast clock frequency (e.g., the frequency at which components of core logic 16 operate), the slow connection is unable to operate effectively during the capture phase. In the example where connection link 19 represents a slow connection, the first capture phase clock signal causes flip-flop 12B to output a data bit value, while the second capture phase clock signal reaches SMDF 13 before the data bit value travels from flip-flop 12B across slow connection link 19 to SMDF 13. Similar to flip-flop 12B, if flip-flop 12C is used instead of SMDF 13, flip-flop 12C will output an erroneous data bit value to core logic 16, thereby adversely affecting the test performed by tester 20.

[0046] In other words, the tester 20 operates under the assumption that data propagates across each of the set of connections in a sufficient amount of time so that each of the flip-flops 12 outputs the correct data bit value to the core logic 16 in response to the clock signal of the capture phase. In this way, the tester 20 determines whether the functional path 17 of the core logic 16 is processing the data incorrectly while ruling out the possibility that the input wrapper chain is the source of the discovered error. Again, for convenience, the above is described only with respect to the input wrapper chain, but similar errors can propagate through the flip-flops 14 in the output wrapper chain.

[0047] Errors associated with slow connections 19 may occur during testing, however, it may be determined during design that slow connections will occur, and thus steps may be taken during design to address issues caused by slow connections 19. In some examples, during design of logic block 10, a set of slow connections (such as connections 19) are identified as part of an input wrapper chain, such as by simulation. For example, a connection link linking flip-flop 12B with flip-flop 12C (i.e., before flip-flop 12C is replaced by SMDF 13) may be identified as a slow connection. Rather than redesigning or recreating logic block 10A to address the slow connection, the present disclosure describes an example of a state machine driven flip-flop circuit that is used to modify flip-flop 12C to mitigate the effects of a slow connection from connection link 19 between flip-flop 12B and flip-flop 12C, such that the slow connection does not negatively impact testing of the core logic performed by tester 20.

[0048] As described, flip-flop 12C may have been part of the design until connection 19 was identified as a slow connection, and then flip-flop 12C was replaced by SMDF 13. In some examples, SMDF 13 includes flip-flops that are the same as flip-flops used for other flip-flops 12. However, SMDF 13 includes one or more additional flip-flops that together form state machine logic (e.g., together form state machine driven flip-flops) that allow SMDF 13 to output known data bit values ​​to core logic 16 during the capture phase of testing performed by tester 20 even in the presence of slow connection 19.

[0049] SMDF 13 is an example of a state machine driven trigger that can be individually configured to output a value that is independent of the scan data shifted along the scan path and received by the state machine driven trigger during testing. During the loading phase, when the data is shifted through the scan path with a slow frequency clock signal, SMDF 13 shifts the data (e.g., outputs the data received at the input of SMDF 13) along the scan path. However, during the capture phase, when the data is shifted through the scan path with a fast frequency clock signal, SMDF 13 can be configured to prohibit the scan data from being shifted into SMDF 13. Instead, SMDF 13 can be configured to output a value that is independent of the scan data shifted along the scan path and received by SMDF 13 during the capture phase.

[0050] As an example, SMDF 13 can be configured to keep the current value of SMDF 13 as output during the test, and the current value was shifted into SMDF 13 during the previous shift cycle (e.g., during the loading phase). As another example, SMDF 13 can be configured to output the inverse value of the current value of SMDF 13 during the test, and the current value was shifted into SMDF 13 during the previous shift cycle (e.g., during the loading phase). Moreover, there can be multiple SMDFs such as SMDF 13 in the input wrapper chain. Each SMDF can be configured separately. For example, SMDF 13 (e.g., the first SMDF) can be configured to output the current value of SMDF 13, and another SMDF (e.g., the second SMDF) in the input wrapper chain can be configured to output the inverse value of the current value of the second SMDF. In addition, although described with respect to the input wrapper chain, similar operations can also occur in the output wrapper chain.

[0051] According to one or more examples described in the present disclosure, SMDF 13 is a multi-trigger state machine, rather than a single digital flip-flop. SMDF 13 may also be referred to as a wrapper unit to indicate that there is additional circuitry added to a single flip-flop to form a multi-trigger state machine. Similarly, SMDF 15 is a multi-trigger state machine, rather than a single digital flip-flop. SMDF 15 may also be referred to as a wrapper unit to indicate that there is additional circuitry added to a single flip-flop to form a multi-trigger state machine.

[0052] As described in more detail, the SMDF 13 or SMDF 15 in the input wrapper chain or the output wrapper chain may include a first flip-flop, a second flip-flop, and an exclusive OR (XOR) logic gate that together form a state machine, respectively. In addition, in some examples, the SMDF 13 may include a first multiplexer and a second multiplexer, the first multiplexer controlling whether the first flip-flop receives an electrical signal from a previous trigger in the input wrapper chain, and the second multiplexer controlling whether the second flip-flop receives an electrical signal from the first flip-flop or from the output of the second flip-flop. As used herein, the terms "first" flip-flop and "second" flip-flop are not meant to indicate a specific order within the corresponding SMDF. The terms "first" and "second" are used to distinguish the flip-flops of the corresponding SMDF.

[0053] Only for the purpose of convenience of illustration and exemplary, SMDF 13 and SMDF 15 are described using flip-flops and XOR logic gates. However, exemplary techniques are not limited thereto. Other design choices can be made. For example, SMDF 13 or SMDF 15 can be a trigger driven by a state machine forming (e.g., representing) a state machine, which can be configured separately to output the current value of the state machine for maintaining the operating mode during the capture phase, rather than providing the output of the input signal present at the input of SMDF 13 or SMDF15. As another example, SMDF 13 or SMDF 15 can be configured to output the inverse value of the current value (e.g., switching operating mode) during the capture phase, rather than based on the input received at the trigger. Therefore, SMDF 13 or SMDF 15 no longer depends on the output value of the clock based on the input value from the previous trigger. Instead, SMDF 13 or SMDF 15 can be configured separately to output the current value or the opposite value of the current value that is independent of the value output from the previous trigger (e.g., regardless of the value output from the previous trigger). Forming a state machine with an XOR and an additional toggle flip-flop is one exemplary way in which the state machine may be formed, but other ways are possible.

[0054] As described in more detail, the electrical signal output by the first flip-flop SMDF 13 or SMDF 15 can represent the data bit referred to as "local data bit" in this article, and the electrical signal output by the second flip-flop SMDF 13 or SMDF 15 can represent the data bit referred to as "switching state data bit" in this article. As used in this article, the term "data bit" can refer to an electrical signal that occupies one of the two possible data bit values ​​(low data bit value or high data bit value). The low amplitude of the corresponding electrical signal represents the low data bit value and the high amplitude of the corresponding electrical signal represents the high data bit value. The low or high data bit value of the switching state data bit indicates whether SMDF 13 and SMDF15 are in switching mode or in holding mode. For example, the low data bit value can correspond to the holding mode and the high data bit value can correspond to the switching mode. In addition, in some cases, the local data bit includes a data bit value in the high data bit value or the low data bit value. The local data bit represents that SMDF 13 outputs to the core logic 16 and outputs to the data bit of the next trigger in the input wrapper chain.

[0055] In one or more examples, the SMDF 13 can be configured to control whether the local data bit is a high data bit value or a low data bit value during the capture phase, so that the identity of the local data bit does not depend on the slow connection between the modified flip-flop and the previous flip-flop in the input wrapper chain. This control can be achieved by the tester 20 loading the switch state data bit to the second flip-flop during the loading phase of the test operation performed by the tester 20, thereby setting the modified flip-flop to a switching mode or a holding mode, which in turn controls the identity of the local data bit (e.g., high or low). The holding mode represents a mode in which the SMDF 13 outputs the current value of the local data bit (e.g., the value shifted in the first flip-flop of the SMDF 13 during the loading phase) in response to receiving a clock signal. The switching mode represents a mode in which the SMDF 13 outputs the opposite value of the current value of the local data bit (e.g., the opposite value of the value shifted in the first flip-flop of the SMDF 13 during the loading phase) in response to receiving a clock signal. The SMDF 15 can operate in a substantially similar manner.

[0056] In some examples, the tester 20 performs a test operation including a loading phase, in which the tester 20 loads a data string to the trigger 12. By directing the data string to the input wrapper chain during the loading phase, the tester 20 sets the local data bit of the SMDF 13 to a high data bit value or a low data bit value, and the tester 20 sets the switching state data bit of the SMDF 13 to a high data bit value or a low data bit value. Therefore, by directing the data string to the input wrapper chain, the tester 20 "programs" the SMDF 13 with the initial local data bit value and programs the SMDF 13 to be in a switching mode or a holding mode. In this way, the tester 20 sets the SMDF 13 to perform as expected during the capture phase (e.g., configure the trigger driven by the state machine) without relying on a slow connection between the SMDF 13 and the previous trigger in the wrapper chain. To perform as expected, SMDF 13 outputs expected output data bits during the capture phase that allow tester 20 to identify one or more errors in the test operation as errors generated by core logic 16 rather than errors caused by the input wrapper chain.

[0057] During the loading phase of the test operation performed by the tester 20, the first flip-flop of the SMDF 13 can receive an electrical signal from the previous flip-flop in the input wrapper chain to allow the tester 20 to load the data string into the flip-flop 12 via a set of connections of the link flip-flop 12, so as to form the input wrapper chain. During the capture phase, the first flip-flop of the SMDF 13 can receive an electrical signal from the XOR logic gate, rather than receiving an electrical signal from the previous flip-flop in the wrapper chain via a slow connection. In this way, when the capture phase occurs, the SMDF 13 does not rely on the slow connection to operate. Instead, in some examples, the SMDF 13 operates based on the signal output by the XOR logic gate, and the XOR logic gate turns to output a signal based on the signal from the second flip-flop. In this way, when the clock signal is transmitted at a fast clock frequency, the XOR logic gate can perform one or more operations during the capture phase. However, during the loading phase and the unloading phase, when the first flip-flop of the SMDF 13 receives data via a slow connection, because the clock signal is transmitted at a slow clock frequency, the slow connection does not interfere with the operation of the SMDF 13.

[0058] As discussed above, the tester 20 may load a data string into the input wrapper chain and / or the output wrapper chain such that one or more data bits are loaded into each flip-flop 12. During the capture phase, the flip-flops 12 receive a set of capture phase clock signals, causing each flip-flop 12 to output a corresponding data bit to the core logic 16. The core logic 16 includes functional paths 17, wherein each of the functional paths 17 represents a path from the flip-flop 12 to the flip-flop 14 through a set of elements that are part of the core logic 16. The tester 20, in some cases, performs a test operation including a load phase, a capture phase, and an unload phase to determine whether each of the functional paths 17 correctly processes the data according to the expected logic operation that the corresponding functional path 17 is programmed to perform. When the flip-flops 12 output data bit values ​​during the capture phase, one or more corresponding functional paths in the functional paths 17 are configured to process each data bit output by the flip-flops in the flip-flops 12 to transfer the corresponding captured data bits to the flip-flops 14. During the offload phase, the tester 20 causes the flip-flops 14 to offload captured data to the tester 20 for comparison with a set of expected data. When one or more functional paths 17 start from the flip-flops 12, the flip-flops 14 may represent a core scan chain configured to capture a set of data.

[0059] According to one or more examples described in the present disclosure, based on whether the SMDF 13 is configured in a hold mode or a toggle mode, the SMDF 13 outputs a data bit value to the core logic 16. For example, the SMDF 13 may be configured to output a current value in a first flip-flop of the SMDF 13 or an inverse value of a current value in a first flip-flop of the SMDF 13, rather than outputting a data bit received from the flip-flop 12B.

[0060] Figure 1 Logic block 10A is shown including flip-flop 12, flip-flop 14, SMDF 13, SMDF 15, and core logic 16. In some examples, each of logic blocks 10B-10N may also include an input wrapper chain, an output wrapper chain, and core logic. Tester 20 may be configured to test the functional paths of any one or more logic blocks 10 using the techniques described herein.

[0061] Figure 2 2 is a block diagram illustrating a system 27 including an input wrapper chain including flip-flops 22A-22D and a set of input wrapper chain connections 24A-24E, in accordance with one or more techniques of the present disclosure. Figure 2 As shown in , the input wrapper chain includes SMDF 23, while the non-input wrapper chain includes only flip-flops like flip-flops 22A-22D. For testing, scan data can be shifted through scan path 30. However, as described below, because connection 24C is a slow connection in scan path 30, during the capture phase of the test, SMDF 23 is configured to output the value in SMDF 23 or the inverse of the value to flip-flop 22D instead of outputting the value received from connection 24C. During the load phase, SMDF 23 can output the value that SMDF 23 received from flip-flop 22C to flip-flop 22D. Figure 2 Also shown is core logic 26 , which includes a functional path 28 similar to functional path 17 .

[0062] Triggers 22A-22D (collectively referred to as "triggers 22") are Figure 1 22A-22D form an input wrapper chain. SMDF 23 is an example of a flip-flop 12 in FIG. Figure 1 The core logic 26 is Figure 1 Example of core logic 16 in FIG. Functional path 28 is Figure 1 Example of functional path 17 in FIG. Scan path 30 is Figure 1 An example of a scan path in 19.

[0063] Input wrapper chain connections 24A-24E (collectively referred to as "input wrapper chain connections 24") represent connections between consecutive pairs of flip-flops in flip-flops 22 other than SMDF 23. For example, Figure 2 As can be seen in FIG. 2 , input wrapper chain connection 24A represents a connection between flip-flop 22A and flip-flop 22B, input wrapper chain connection 24B represents a connection between flip-flop 22B and flip-flop 22C, and so on, but connection 24C represents a connection between flip-flop 22C and SMDF 23. Thus, flip-flop 22, SMDF 23, and input wrapper chain connection 24 form an input wrapper chain.

[0064] Each of the flip-flops 22 and the SMDF 23 includes a functional data input ("D"), a scan data input ("SI"), and a data output ("Q"). In addition, each flip-flop 22 and the SMDF 23 includes a control input ("SE") and a clock input ("CLK").

[0065] Flip-flops 22 and SMDF 23 represent flip-flops in an input wrapper chain that are configured to receive data from one or more other systems and output data to core logic 26. For example, during a functional mode of system 27, flip-flops 22 and SMDF 23 may receive electrical signals at corresponding functional inputs D and output electrical signals at outputs Q, where outputs Q are electrically connected to core logic 26. In this manner, flip-flops 22 and SMDF 23 may serve as interfaces between core logic 26 and other devices, systems, and circuits during a functional mode of system 27.

[0066] The trigger 22 and SMDF 23 may also allow for, for example, Figure 1 The tester 20 in the embodiment of the present invention performs test operations on the core logic 26 while isolating the core logic 26 from other circuits (e.g., the core logic of other logic blocks, external circuits, and top logic). In this way, when the tester 20 performs the test operation, the flip-flop 22 and the SMDF 23 can be used as an isolated input wrapper chain, which means that the flip-flop 22 and the SMDF 23 receive data from the tester 20 via the SI input instead of receiving data from an external source via the D input.

[0067] The test operation performed by the tester 20 may include a loading phase, a capture phase, and an unloading phase. During the loading phase, the tester 20 directs the data string to the trigger 22 and the SMDF 23 via the SI input of the trigger 22 and the SMDF 23 and the input wrapper chain connection 24. Therefore, the trigger 22 and the SMDF 23 receive data at the D input or receive data at the SI input according to the operating mode of the system 27, and by transmitting a control signal to the SE input, which input of the D input or the SI input can be controlled to transmit data to the trigger 22 or the SMDF 23. For testing, the MUX in the trigger 22 and the SMDF 23 can be configured to output data from the SI input. However, the SMDF 23 can be configured to output data from the SI input during the loading phase of the test. For the capture phase of the test, the SMDF 23 does not output data from the SI input, but outputs the current value or the inverse value of the current value, and does not output data from the SI input. That is, the SMDF 23 may be configured to inhibit the shifting of scan data into the SMDF 23 (eg, during testing, such as during a capture phase).

[0068] In some examples, each of the flip-flops 22 is configured to transfer data from one of the functional data input D and the scan data input SI to the data output Q in response to receiving a clock signal at the corresponding clock input CLK. For example, when the flip-flop 22B receives a low data bit value at the scan data input SI and outputs a high data bit at the data output Q, the flip-flop 22B may transfer the low data bit value from the scan data input SI to the data output Q in response to receiving the clock signal at the clock input CLK, thereby causing the flip-flop 22B to output the low data bit value to the core logic 26 and the scan data input SI of the flip-flop 22C. Furthermore, in some cases, when the flip-flop 22B receives a low data bit value at the functional data input D and outputs a high data bit at the data output Q, the flip-flop 22B transfers the low data bit value from the functional data input D to the data output Q in response to receiving the clock signal at the clock input CLK, thereby causing the flip-flop 22B to output the low data bit value to the core logic 26. In any case, each of flip-flops 22 may be configured to “advance” or “shift” a data bit value in response to receiving a clock signal that initiates advancement.

[0069] The flip-flops 22 and SMDF 23 may receive a sequence of one or more clock signals to cause a data bit to pass through one or more flip-flops 22. In some examples, the sequence of clock signals includes a first clock signal that transfers a data bit value from the SI input of flip-flop 22A to the Q output of flip-flop 22A, a second clock signal that transfers a data bit value from the SI input of flip-flop 22B to the Q output of flip-flop 22B, a third clock signal that transfers a data bit value from the SI input of flip-flop 22C to the Q output of flip-flop 22C, a fourth clock signal that transfers a data bit value from the SI input of SMDF 23 to the Q output of flip-flop 22D, and the like. In some examples, the clock signal transfers a data bit value from the D input of flip-flop 22A to the Q output of flip-flop 22A, causing the data bit value to be output to the core logic 26. In this example, when the SI input of flip-flops 22 and SMDF 23 is disabled, the D input of flip-flops 22 and SMDF 23 is enabled, which means that the data bit is transferred to the core logic 26 through flip-flop 22A but not to flip-flop 22B. In any case, the clock signal received at the clock input of flip-flop 22 may cause one or more flip-flops in the input wrapper chain to propagate data (e.g., from a previous flip-flop if the SI input is selected, or from another source if the D input is selected).

[0070] The control input of the corresponding flip-flop (e.g., flip-flop 22B) can receive a control signal that causes the flip-flop to receive data from a function input (e.g., D input) or to receive data from a scan input (e.g., SI input). The control signal can include a high control signal amplitude or a low control signal amplitude. For example, when the flip-flop 22B receives a control signal with a high control signal amplitude at the SE input of the flip-flop 22B, the flip-flop 22B can receive data via the SI input of the flip-flop 22B without receiving data from the D input of the flip-flop 22B. On the other hand, when the flip-flop 22B receives a control signal with a low control signal amplitude at the SE input of the flip-flop 22B, the flip-flop 22B can receive data via the D input of the flip-flop 22B without receiving data from the SI input of the flip-flop 22B.

[0071] In some examples, during the functional mode of system 27, flip-flop 22 forwards data from outside of system 27 to core logic 26. For example, during the functional mode of system 27, a control signal received through the SE input of flip-flop 22 may represent a low control signal amplitude, causing flip-flop 22 to receive data at the D input and output data at the Q output. That is, flip-flop 22A receives data at the D input of flip-flop 22A and outputs data via the Q output of flip-flop 22A, flip-flop 22B receives data at the D input of flip-flop 22B and outputs data via the Q output of flip-flop 22B, flip-flop 22C receives data at the D input of flip-flop 22C and outputs data via the Q output of flip-flop 22C, SMDF 23 receives data at the D input of SMDF 23 and outputs data via the Q output of SMDF 23, and flip-flop 22D receives data at the D input of flip-flop 22D and outputs data via the Q output of flip-flop 22D. In this example, the clock signal causes flip-flop 22 and SMDF 23 to transfer data from the D input to the Q output while the SI input is disabled.

[0072] In some cases, system 27 is configured to operate in a scan mode (e.g., for testing). For example, during the scan mode of system 27, the control signal received through the SE input of flip-flop 22 can represent a high control signal amplitude, causing flip-flop 22 to receive data at the SI input and output data at the Q output. That is, flip-flop 22A receives data at the SI input of flip-flop 22A and outputs data via the Q output of flip-flop 22A, flip-flop 22B receives data at the SI input of flip-flop 22B and outputs data via the Q output of flip-flop 22B, flip-flop 22C receives data at the SI input of flip-flop 22C and outputs data via the Q output of flip-flop 22C, and so on, except for SMDF 23. In this example, when the D input is disabled, the clock signal causes flip-flop 22 to transfer data from the SI input to the Q output, which means that flip-flop 22 does not transfer data from the D input to the core logic 26 during the scan mode.

[0073] During the loading phase of the test, the SMDF 23 outputs the data received at the SI input of the SMDF 23 via the Q output of the SMDF 23. However, during the capture phase of the test, the SMDF 23 does not output the data received at the SI input of the SMDF 23 via the Q output of the SMDF 23. Instead, the SMDF 23 outputs the current value in the SMDF 23 or the inverse value of the current value in the SMDF 23. For example, during the loading phase, the SMDF 23 can be configured to be in a holding mode or a switching mode based on the bits shifted into the SMDF 23 during the loading phase. In the holding mode, during the capture phase, the SMDF 23 outputs the current value of the SMDF 23 for holding, which was shifted into the SMDF 23 during the previous shift cycle (e.g., during the loading phase). In the switching mode, during the capture phase, the SMDF 23 outputs the inverse of the current value of the SMDF 23, which was shifted into the SMDF 23 during the previous shift cycle (e.g., during the load phase). In this way, because the SMDF 23 can be configured in either the holding mode or the switching mode, the SMDF 23 is an example of a flip-flop driven by a separately configurable state machine that can be configured to output a value that is independent of the scan data shifted along the scan path and received by the SMDF 23 during testing (such as during the capture phase, etc.).

[0074] While the scan mode is enabled, a tester such as tester 20 can perform test operations on core logic 26. The test operations can include a loading phase, a capture phase, and an unloading phase. During the loading phase, the tester 20 guides the data bit string to an input wrapper chain including a trigger 22 and an SMDF 23. In one example, the data bit string includes "01001", which represents a first low data bit value (e.g., the first "0"), a first high data bit value (e.g., the first "1"), a second low data bit value, a third low data bit value, and a second high data bit value. The trigger 22 and SMDF 23 load the data bit string during the loading phase. For example, the trigger 22A can receive the first low data bit value at the SI input of the trigger 22A. In response to receiving a loading phase clock signal sequence at the clock inputs of the trigger 22 and the SMDF 23, the trigger 22A can load the data bit value string in a sequential order, so that the trigger 22D loads the first low data bit value to the data output Q of the trigger 22D, the SMDF 23 loads the first high data bit value to the data output Q of the SMDF 23, the trigger 22C loads the second low data bit value to the data output Q of the trigger 22C, the trigger 22B loads the third low data bit value to the data output Q of the trigger 22B, and the trigger 22A loads the second high data bit value to the data output Q of the trigger 22A.

[0075] Typically, during the loading phase, the frequency of the clock signal received at CLK is relatively low (e.g., slower than the clock signal used during normal operation). Because the frequency of the clock signal during the loading phase is relatively low, even if there is a slow connection such as connection 24C, the effect of the slowness of connection 24C does not affect the bits being loaded into SMDF 23. For example, the clock signal used during the loading phase is slow enough so that even if connection 24 is a slow connection, there is enough time for the output of flip-flop 22C to propagate to SMDF 23.

[0076] After the load phase of the test operation in which the flip-flop 22 and the SMDF 23 load the string of data bit values, the tester 20 can perform a capture phase. To perform the capture phase, the tester 20 can output a set of two or more capture phase clock signals to the clock inputs of the flip-flops 22 and the SMDF 23, while the control signal received by each of the flip-flops 22 maintains a high control signal amplitude, thereby enabling the SI input of the flip-flop 22 and disabling the D input of the flip-flop 22. When the flip-flop 22C receives the capture phase clock signal, for example, the flip-flop 22C transfers the data bit value at the SI input of the flip-flop 22C (e.g., the data bit output by the flip-flop 22B through the connection 24B) to the Q output of the flip-flop 22C, thereby causing the flip-flop 22C to output the data bit to the core logic 26 and the SI input of the flip-flop SMDF 23. In this way, the flip-flops 22 can form an "isolated" input wrapper chain that outputs the data bit value from the SI input of the flip-flop 22 to the core logic 26, rather than outputting the data bit value from the D input of the flip-flop 22 to the core logic 26. During the capture phase, data bit values ​​output by flip-flops 22 may propagate to an output wrapper chain or a core chain via functional paths 28. Subsequently, tester 20 may perform an unload phase and compare the captured data bit values ​​of the output wrapper chain to a set of expected data bit values.

[0077] During the capture phase, the frequency of the clock signal received at CLK is relatively fast (e.g., the frequency is the same as the frequency at which the core logic 26 operates). Because the frequency of the clock signal during the capture phase is relatively fast and connection 24C is a slow connection, there may not be enough time for the data to propagate from trigger 22C to SMDF 23 before the next clock signal arrives to cause SMDF 23 to output. According to one or more examples described in the present disclosure, during the capture phase, SMDF 23 can be configured to output the current value of SMDF 23 or the inverse value of the value of SMDF 23, so that the impact of connection 24 (slow connection) is mitigated. For example, regardless of the value of the data bit received at the SI input of SMDF 23, SMDF 23 is configured to output the current value in the flip flip-flop of SMDF 23 or the inverse value of the current value in the flip flip-flop of SMDF 23.

[0078] Figure 3A is a block diagram illustrating a flip-flop 32 including a set of inputs and a set of outputs according to one or more techniques of the present disclosure. Flip-flop 32 includes a function data input 34, a scan data input 36, a control input 40, a clock input 42, and a data output 38. Data output 38 transmits data via connection 44 and connection 46. In some examples, flip-flop 32 is Figure 1 In some examples, trigger 32 is Figure 1 In some examples, trigger 32 is Figure 2 An example of one of the triggers 22 in FIG.

[0079] When flip-flop 32 is part of an input wrapper chain of a logic block, such as logic block 10A, functional data input 34 is configured to input data from an "external" environment. The external environment refers to devices and circuits that are not part of the logic block on which flip-flop 32 is located. For example, flip-flop 32 may receive data from another logic block or from top logic of another system. In some examples, scan data input 36 is configured to receive data from a previous flip-flop in the input wrapper chain. When flip-flop 32 is the first flip-flop in the input wrapper chain, scan data input 36 is configured to receive data from a tester (e.g., Figure 1The control input 40 receives data from the tester 20 or other circuit in the control input. The control input 40 receives a control signal (sometimes referred to herein as a "shift enable" signal). The trigger 32 controls whether the functional data input or the scan data input is enabled based on the control signal received at the control input. When the control signal includes a high control signal amplitude, the trigger 32 can enable the scan data input 36 and disable the functional data input 34. When the control signal includes a low control signal amplitude, the trigger 32 can enable the functional data input 34 and disable the scan data input 36.

[0080] Data output 38 outputs data via connection 44 and connection 46. When flip-flop 32 is part of an input wrapper chain, connection 44 links flip-flop 32 to the next flip-flop in the input wrapper chain and connection 46 links flip-flop 32 to the core logic of the logic block on which flip-flop 32 is located. In some examples, data output 38 outputs a data bit representing a low data bit value (e.g., "0") or a high data bit value (e.g., "1"). Thus, flip-flop 32 is configured to process binary data. Data output 38 transmits the data bit via connection 44 and connection 46. For example, when data output 38 outputs a low data bit, data output 38 transmits an electrical signal at a low voltage such that the electrical signal including the low voltage is passed across both connection 44 and connection 46. In this way, both the circuit at the end of connection 44 and the circuit at the end of connection 46 can receive the electrical signal including the low voltage, and thereby receive the low data bit value. On the other hand, when data output 38 outputs a high data bit, data output 38 transmits an electrical signal at a high voltage, so that the electrical signal including the high voltage is transmitted across both connection 44 and connection 46. In this way, both the circuit at the end of connection 44 and the circuit at the end of connection 46 can receive the electrical signal including the high voltage, and thereby receive the high data bit value. The amplitude of the high voltage is greater than the amplitude of the low voltage.

[0081] The flip-flop 32 may receive one or more clock signals at a clock input 42. A clock signal is a signal that drives the flow of data across the flip-flop 32. For example, the flip-flop 32 may transfer a data bit from an input of the flip-flop 32 to an output of the flip-flop 32 based on the received clock signal. From which input the flip-flop 32 transfers data is determined by a control signal received at a control input 40. For example, when the control signal includes a low control signal amplitude and the flip-flop 32 receives a clock signal, the flip-flop 32 transfers a data bit value from the functional data input 34 to the data output 38. When the control signal includes a high control signal amplitude and the flip-flop 32 receives a clock signal, the flip-flop 32 transfers a data bit value from the scan data input 36 to the data output 38.

[0082] Figure 3Bis a block diagram showing one example of a state machine driven flip-flop (SMDF) 31. For example, the SMDF 31 is an example of a wrapper unit such as a scan wrapper unit included in an input wrapper chain or an output wrapper chain.

[0083] In some examples, SMDF 31 includes Figure 3A Components similar to these flip-flops 32 in FIG. 3 and additional circuits are used to form a state machine. However, the example used for SMDF 31 is not limited thereto.

[0084] exist Figure 3B In the example shown, the SMDF 31 according to one or more techniques of the present disclosure includes a main trigger 32, an additional trigger 48, and a state machine logic 50. Therefore, the SMDF 31 is a trigger driven by a multi-trigger state machine. The main trigger 32 includes a functional data input 34, a scan data input 36, a control input 40, a clock input 42, and a data output 38. The additional trigger 48 includes a functional data input, a scan data input, a control input, a clock input, and a data output in some cases. In this way, the additional trigger 48 can be roughly the same as the main trigger 32. The SMDF 31 can represent a deformation of the main trigger 32, so that the additional trigger 48 and the state machine logic 50 are integrated with the trigger 32. Therefore, the SMDF 31 is an enhanced trigger driven as a state machine, wherein the enhancement comes from the additional circuits and additional triggers used to form the state machine. In some examples, during the design period, the connection 41 is identified as a slow connection. The flip-flop 32 may be supplemented with additional flip-flops 48 and state machine logic 50 so that the slow connection 41 does not negatively affect the test operation of the core logic when the modified flip-flop 31 operates in scan mode. Figure 3B A replacement for the scan wrapper unit in SMDF 31.

[0085] Figure 4 1 is a block diagram illustrating a scan wrapper cell 130 that forms a multi-flip flop state machine driven flip flop located at the end of connection 141 in accordance with one or more techniques of the present disclosure. Connection 141 is a slow connection on a scan path between flip flops in a wrapper chain. Scan wrapper cell 130 is an example of a state machine driven flip flop (SMDF) that provides immunity to the effect of connection 141 being a slow connection. Thus, scan wrapper cell 130 can be a scan wrapper cell that provides shift path delay immunity. Shift path delay refers to the delay from data shifting between flip flops during the capture phase of testing.

[0086] from Figure 4As can be seen in FIG. 1 , unit 130 includes flip-flops 122A-122B (collectively referred to as “flip-flops 122”), multiplexers 124A-24C (collectively referred to as “multiplexers 124”), and an exclusive OR (XOR) logic gate 126. The first flip-flop 122A includes a first flip-flop function data input 131, a first flip-flop scan data input 132, a first flip-flop data output 134, a first flip-flop control input 135, and a first flip-flop clock input 136. The second flip-flop 122B includes a second flip-flop data input 142, a second flip-flop data output 144, and a second flip-flop clock input 146. The first multiplexer 124A includes a first multiplexer data input 152, a second multiplexer data input 154, a first multiplexer data output 156, and a first multiplexer control input 158. The second multiplexer 124B includes a third multiplexer data input 162, a fourth multiplexer data input 164, a second multiplexer data output 166, and a second multiplexer control input 168. The third multiplexer 124C includes a fifth multiplexer data input 172, a sixth multiplexer data input 174, a third multiplexer data output 176, and a third multiplexer control input 178. The XOR logic gate 126 includes a first XOR data input 182, a second XOR data input 184, and an XOR data output 186.

[0087] Unit 130 is configured to operate in both the functional mode of logic block 10A and the scan mode of logic block 10A. During the functional mode of logic block 10A, unit 130 can communicate with a controller such as Figure 3A 10A operates similarly to the non-modified flip-flops of the flip-flops 32 in the logic block 10A. For example, during the functional mode, the flip-flop 122A may receive the control signal 206 at the first flip-flop control input 135, thereby causing the flip-flop 122A to activate the first flip-flop function data input 131 and to disable the first flip-flop scan data input 132. Therefore, during the functional mode of the logic block 10A, the flip-flop 122A may transfer data from the first flip-flop function data input 131 to the first flip-flop data output 134. In other words, the flip-flop 122A may transfer data from the external circuit of the logic block 10A to the core logic 16 of the logic block 10A. In this way, while the functional mode is enabled, the unit 130 may rely on the flip-flop 122A to transfer data from the external circuit to the core logic, without relying on the second flip-flop 122B, the first multiplexer 124A, the second multiplexer 124B, and the XOR logic gate 126.

[0088] While the scan mode of logic block 10A is enabled, flip-flop 122, multiplexer 124, and XOR logic gate 126 may operate to prevent connection 141 from adversely affecting the testing of core logic 16. In other words, unit 130 may provide immunity to delays generated by connection 141 during testing, so that tester 20 may unambiguously determine that one or more errors are caused by core logic 16, rather than the input / output wrapper chain of logic block 10A.

[0089] In some examples, the tester 20 performs a test operation including a loading phase, a capture phase, and an unloading phase. During the loading phase, the unit 130 is configured to process data received from a previous trigger through the connection 141. For example, the first multiplexer 124A receives the control signal 216 at the first multiplexer control input 158, thereby causing the first multiplexer 124A to activate the second multiplexer data input 154 and disable the first multiplexer data input 152, and the second multiplexer 124B receives the control signal 216 at the second multiplexer control input 168, thereby causing the second multiplexer 124B to activate the fourth multiplexer data input 164 and disable the third multiplexer data input 162. During the loading phase, the tester 20 can load the data bit value to the first flip-flop data output 134 of the first flip-flop 122A, and the tester 20 can load the data bit value to the second flip-flop data output 144 of the second flip-flop 122B.

[0090] To “load” a data bit value into the first flip-flop data output 134 of the first flip-flop 122A and into the second flip-flop data output 144 of the second flip-flop 122B, the respective clock inputs of the first flip-flop 122A and the second flip-flop 122B may receive a set of load phase clock signals that cause the flip-flops 122 to advance the data bits through the cell 130. Because the second multiplexer data input 154 and the fourth multiplexer data input 164 are activated during the load phase, advancement of the data bits through the cell 130 during the load phase may occur as follows.

[0091] The first flip-flop clock input 136 can receive a first loading phase clock signal that causes the first flip-flop 122A to advance the first data bit from the first flip-flop scan data input 132 to the first flip-flop data output 134, thereby outputting the first data bit to the second flip-flop data input 142 via the multiplexer 124B. In addition, the first loading phase clock signal causes the first flip-flop scan data input 132 to receive the second data bit via the connection 141 and the multiplexer 124A. The second flip-flop clock input 146 and the first flip-flop clock input 136 can receive a second loading phase clock signal that causes the second flip-flop 122B to advance the first data bit from the second flip-flop data input 142 to the second flip-flop data output 144. In addition, the second loading phase clock signal causes the first flip-flop 122A to advance the second data bit from the first flip-flop scan data input 132 to the first flip-flop data output 134. In this manner, after the first flip-flop 122A and the second flip-flop 122B receive the first loading phase clock signal and the second loading phase clock signal, the first data bit can be loaded to the second flip-flop data output 144 and the second data bit can be loaded to the first flip-flop data output 134. Thus, the first data bit can represent a “toggleState” data bit and the second data bit can represent a “localQ” data bit output to the core logic.

[0092] In some examples, the local Q data bit represents a low data bit value "0" or a high data bit value "1". In addition, the switch state data bit can represent a low data bit value or a high data bit value. The identification of the local Q data bit value (e.g., a low data bit value or a high data bit value) and the identification of the switch state data bit value can determine how the unit 130 operates during the capture phase of the test operation performed by the tester 20. Therefore, it can be beneficial to program the local Q data bit and the switch state data bit so that the unit 130 performs during the test operation without relying on the connection 141 that connects the unit 130 to the previous trigger in the input wrapper chain. In order to program the local Q data bit and the switch state data bit, a data string leading to the input wrapper chain can be customized, and two consecutive data bits in the data string (representing the local Q data bit and the switch state data bit) respectively include the desired data bit values. For example, a data string can be generated so that the switch state data bit is "1" and the local Q data bit (consecutive to the switch state data bit in the data string) is "0". When the input wrapper chain loads the data string, unit 130 may load the data string, thereby "programming" the local Q data bits and the switch state data bits.

[0093] During the capture phase of the test operation, the unit 130 can be configured to operate in one of a toggle state and a hold state. That is, when the unit 130 operates in the toggle mode, the unit 130 switches the value of the local Q data bit in response to receiving the capture phase clock signal, and when the unit 130 operates in the hold mode, the unit 130 holds the value of the local Q data bit in response to receiving the capture phase clock signal. When the toggle state data bit is "1", the unit 130 operates in the toggle mode, and when the toggle state data bit is "0", the unit 130 operates in the hold mode. Therefore, by generating a data string including a custom value of the toggle state data bit, the toggle state data bit guides the operation of the unit 130 when it is loaded into the second flip-flop data output 144.

[0094] The unit 130 can operate according to one of the four bit combinations. The first bit combination occurs when the local Q data bit is "0" and the switch state data bit is "0". The second bit combination occurs when the local Q data bit is "0" and the switch state data bit is "1". The third bit combination occurs when the local Q data bit is "1" and the switch state data bit is "0". The fourth bit combination occurs when the local Q data bit is "1" and the switch state data bit is "1". When the unit 130 receives the capture phase clock signal while the first bit combination is loaded to the flip-flop 122, the first flip-flop 122A maintains the local Q data bit value as "0" and the second flip-flop 122B maintains the switch state data bit value as "0". When the unit 130 receives the capture phase clock signal while the second bit combination is loaded to the flip-flop 122, the first flip-flop 122A switches the local Q data bit value from "0" to "1", and the second flip-flop 122B maintains the switch state data bit value as "1". When the unit 130 receives the capture phase clock signal while the third bit combination is loaded into the flip-flop 122, the first flip-flop 122 maintains the local Q data bit value as "1" and the second flip-flop 122B maintains the toggle state data bit value as "0". When the unit 130 receives the capture phase clock signal while the fourth bit combination is loaded into the flip-flop 122, the first flip-flop 122A switches the local Q data bit value from "1" to "0" and the second flip-flop 122B maintains the toggle state data bit value as "1".

[0095] The XOR logic gate 126 causes the unit 130 to switch the local Q data bit during the switching phase and to maintain the local Q data bit during the holding phase. For example, when the second bit combination is loaded to the flip-flop 122, the switching state data bit is "1", which means that the unit 130 is in the switching mode. The second flip-flop data output 144 outputs the "1" data bit to the first XOR data input 182. In addition, when the second bit combination is loaded to the flip-flop 122, the local Q data bit is "0", which means that the first flip-flop data output 134 outputs the "0" data bit to the second XOR data input 184. The XOR logic gate 126 outputs a "0" data bit value or a "1" data bit value based on the data bit values ​​sent to the first XOR data input 182 and the second XOR data input 184. For example, when the sum of the data bits sent to the first XOR data input 182 and the second XOR data input 184 is an odd number, the XOR logic gate 126 outputs a "1" data bit value. When the sum of the data bits sent to the first XOR data input 182 and the second XOR data input 184 is an even number, the XOR logic gate 126 outputs a “0” data bit value. Therefore, in the case of the second bit combination, the XOR logic gate 126 outputs a “1” data bit value because the first XOR data input 182 receives a “1” data bit and the second XOR data input 184 receives a “0” data bit, which means that the two data bits received through the XOR data inputs have an odd sum of 1. Because the first multiplexer data input 152 is enabled during the capture phase in order to connect the XOR data output 186 to the first toggle flip-flop scan data input 132, the first multiplexer data input 152 causes the toggle flip-flop 122A to receive the “1” data bit value at the first toggle flip-flop scan data input 132.

[0096] Although the flip-flop 130 includes the XOR logic gate 126, one or more other logic gates may be configured to perform one or more techniques described herein as performed by the XOR logic gate 126. The XOR logic gate may represent a type of next state logic element. In some examples, another next state logic element or a combination of next state logic elements may perform one or more techniques described herein as performed by the XOR logic gate 126. In some examples, a multiplexer (MUX), an exclusive NOR (XNOR) logic gate, an AND-OR inversion (AOI) logic gate, another type of next state logic gate, or any combination thereof may perform one or more techniques described herein as performed by the XOR logic gate 126.

[0097] When the second bit combination is loaded into the flip-flop 122, in response to the first flip-flop clock input 136 receiving the capture phase clock signal, the flip-flop 122A transfers the "1" data bit value from the first flip-flop scan data input 132 to the first flip-flop data output 134, thereby switching the local Q data bit value from "0" to "1". The flip-flop 122B receives the capture phase clock signal at the second flip-flop clock input 146, thereby causing the flip-flop 122B to maintain the switched state data bit as the "1" data bit value. This is because during the capture phase, the third multiplexer data input 162 is activated and the fourth multiplexer data input 164 is deactivated, thereby connecting the second flip-flop data output 144 to the second flip-flop data input 142.

[0098] Although the unit 130 including two flip-flops (eg, flip-flop 122A and flip-flop 122B) is shown, Figure 4 One or more exemplary flip-flops not shown in the figure may include more than two flip-flops. One or more exemplary flip-flops may include additional logic gates and additional circuits that allow one or more exemplary flip-flops to output desired data bits.

[0099] Figure 5 1 is a diagram 188 showing a clock signal diagram 190, a first control signal diagram 200, and a second control signal diagram 210 according to one or more techniques of the present disclosure. Figure 5 As can be seen in FIG. 1 , clock signal diagram 190 includes a set of loading phase clock signals 192A–192E (collectively referred to as “loading phase clock signals 192”), a set of capturing phase clock signals 194A–194B (collectively referred to as “capturing phase clock signals 194”), and a set of unloading phase clock signals 196A–196E (collectively referred to as “unloading phase clock signals 196”). First control signal diagram 200 includes a first control signal 206 that is at a high control signal value 202 throughout the loading phase, the capturing phase, and the unloading phase. Second control signal diagram 210 includes a second control signal 216 that is at a high control signal value 202 during the loading phase, at a low control signal value 204 during the capturing phase, and at a high control signal value 202 during the unloading phase. Figure 1 System 2 and Figure 4 130 pairs of triggers in Figure 5 However, Figure 5 The techniques in may be performed by different components or triggers 130 in system 2, or by additional or alternative systems and devices.

[0100] During the loading phase, such as Figure 1The input wrapper chain of the flip-flops 12 in the tester 20 can receive a set of loading phase clock signals 192. In addition, the tester 20 can guide the data bit string toward the input wrapper chain. The loading phase clock signal 192 causes the flip-flops 12 to load the data bit string via the scan input without using the functional input to load the data bit. In other words, the flip-flops 12 can represent an input wrapper chain that isolates the logic block 10A from the external circuit outside the test circuit during the test operation. In some examples, the loading phase clock signal 192 causes each flip-flop 12 to load at least one data bit. In the case of an SMDF (e.g., SMDF 13, 15, 23, or unit 130), the SMDF can load more than one data bit during the loading phase. For example, unit 130 includes a first flip-flop 122A and a second flip-flop 122B. During the loading phase, the first flip-flop 122A can load the local Q data bit and the second flip-flop 122B can load the switch state data bit.

[0101] The first control signal 206 and the second control signal 216 may represent control signals transmitted to different components in the cell 130 during a test operation performed by the tester 20. For example, the first flip-flop 122A may receive the first control signal 206 at the first flip-flop control input 135. The first multiplexer 124A, the second multiplexer 124B, and the third multiplexer 124C receive the second control signal 216 at the first multiplexer control input 158, the second multiplexer control input 168, and the third multiplexer control input 178, respectively. During the loading phase, both the first control signal 206 and the second control signal 216 are at the high control signal value 202. This means that data is configured to pass through the cell 130 via both the first flip-flop 122A and the second flip-flop 122B. At the high control signal value 202, the first control signal 206 activates the first toggle flip-flop scan data input 132 and deactivates the first toggle flip-flop functional data input 131, thereby allowing the first toggle flip-flop 122A to transfer data from the first toggle flip-flop scan data input 132 to the first toggle flip-flop data output 134 and preventing the first toggle flip-flop 122A from transferring data from the first toggle flip-flop functional data input 131. For example, during the load phase, a data bit may arrive at the cell 130 via the connection 141, transfer across the first toggle flip-flop 122A to the second toggle flip-flop 122B, and transfer across the second toggle flip-flop 122B to the next flip-flop in the input wrapper chain.

[0102] After the loading phase, the tester 20 may perform a capture phase. During the capture phase, the first control signal 206 remains at the high control signal value 202 while the second control signal 216 switches to the low control signal value 204. Thus, the first flip-flop 122A continues to transmit data from the first flip-flop scan data input 132 in response to receiving the capture phase clock signal 194, and the multiplexer 124 enables the "I0" inputs 152, 162, and 172 during the capture phase. This means that the first flip-flop scan data input 132 receives data from the XOR data output 186 during the capture phase rather than relying on receiving data via the connection 141, thereby preventing the connection 141 from causing errors during the test operation when the connection 141 is slow.

[0103] Thus, the first flip-flop 122A includes the current value, and based on the value in the second flip-flop 122B (e.g., whether the unit 130 is configured for switching mode or holding mode), the unit 130 can output the current value or the inverse value of the current value. In one or more examples (such as when there are multiple units 130 in the input or output wrapper chain), one of the units 130 (e.g., the first SMDF) can be configured to be in switching mode based on the value in the second flip-flop of the first SMDF, while another unit of the units 130 (e.g., the second SMDF) can be configured to be in holding mode based on the value in the second flip-flop of the second SMDF.

[0104] The unload phase follows the capture phase. During the unload phase, the first control signal 206 remains at the high control signal value 202 while the second control signal 216 switches back to the high control signal value 202. The unload phase clock signal 196 can enable the output wrapper chain (e.g., Figure 1 The trigger 14 in the tester sends the captured data bit string to the tester 20 for analysis.

[0105] Figure 6 is a flowchart illustrating example operations for performing test operations according to one or more techniques of the present disclosure. Figure 1 System 2 and Figure 4 Unit 130 of Figure 6 However, Figure 6 The techniques in may be performed by different components or units 130 in system 2, or by additional or alternative systems and devices.

[0106] To perform the loading phase of the test operation, the tester 20 uses a Figure 1The input wrapper chain of the trigger 12 and SMDF 13 in the tester loads the data string (602). For example, the trigger 12 and SMDF 13 can receive a set of loading phase clock signals, so that the trigger 12 and SMDF 13 load the data string. After the input wrapper chain loads the data string, the logic block 10A captures the data string by executing multiple functional paths 17 through the core logic 16 (604). For example, the trigger 12 and SMDF 13 can receive a set of capture phase clock signals, which cause the trigger 12 and SMDF 13 to send the data bit string to the trigger 14 through the functional path 17. In this way, the functional path 17 can perform one or more logic operations to generate a captured data bit string. The tester 20 uses a plurality of functional paths 17 through the core logic 16 to capture the data string (604). Figure 1 The output wrapper chain of the trigger 14 and SMDF 15 in the outputs the captured data string (606). For example, the output trigger 14 and SMDF 15 can receive a set of unloading phase clock signals, so that the output trigger 14 and SMDF 15 output the captured data bit string to the tester 20.

[0107] The tester 20 may compare the captured data string to an expected data string (608). The expected data string may represent a string of data bits that the functional path 17 is expected to generate given the data string loaded by the input wrapper chain. Differences between the captured data string and the expected data string may be caused by errors in the core logic 16. Therefore, the tester 20 may be configured to determine whether the functional path 17 causes one or more errors based on the comparison (610).

[0108] The techniques described herein may be implemented in hardware, software, firmware, or any combination thereof. The various features described as modules, units, or components may be implemented together in an integrated logic device or individually as discrete but interoperable logic devices or other hardware devices. In some cases, the various features of the electronic circuit may be implemented as one or more integrated circuit devices such as an integrated circuit chip or chipset.

[0109] If implemented in hardware, the present disclosure may specify a device such as a processor or an integrated circuit device, such as an integrated circuit chip or a chipset. Alternatively or in addition, if implemented in software or firmware, the present technology may be implemented at least in part by a computer-readable data storage medium including instructions that, when executed, cause a processor to perform one or more of the methods described above. For example, a computer-readable data storage medium may store the instructions for execution by a processor.

[0110] The computer readable medium may form part of a computer program product that may include the grouped materials. The computer readable medium may include computer data storage media such as random access memory (RAM), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic or optical data storage media, etc. In some examples, an article of manufacture may include one or more computer readable storage media.

[0111] In some examples, computer-readable storage media may include non-volatile media. The term "non-volatile" may indicate that the storage media is not contained in a carrier wave or propagating signal. In a specific example, a non-volatile storage medium may store data that may change over time (e.g., in RAM or cache).

[0112] The code or instructions may be software and / or firmware executed by a processing circuit including one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein may refer to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. In addition, in some aspects, the functions described in the present disclosure may be provided within a software module or a hardware module.

Claims

1. An integrated circuit (IC), comprising: Core logic, with functional logic elements; a wrapper chain having a plurality of flip-flops for testing the core logic, wherein a plurality of the flip-flops in the wrapper chain are sequentially interconnected along a scan path for shifting scan data through consecutive flip-flops during testing of the core logic; and at least one state machine driven flip-flop connected along said scan path of said wrapper chain, wherein the state machine driven flip-flops are individually configurable during the test to output to the core logic a first value that is independent of the scan data shifted along the scan path and received by the state machine driven flip-flops, and At least one of the plurality of flip-flops is configured to output a second value to the core logic, wherein the second value is equivalent to the scan data shifted along the scan path and received by the at least one flip-flop.

2. The IC according to claim 1, wherein: The state machine driven flip-flop can be configured during testing to hold as an output a current value of the state machine driven flip-flop, the current value being shifted into the state machine driven flip-flop during a previous shift cycle of the wrapper chain.

3. The IC according to claim 1, wherein: The state machine driven flip-flop can be configured during testing to output an inverse value of a current value of the state machine driven flip-flop that was shifted into the state machine driven flip-flop during a previous shift cycle of the wrapper chain.

4. The IC according to claim 1, wherein: The state machine driven flip-flop can be configured to inhibit shifting of the scan data into the state machine driven flip-flop during testing.

5. The IC of claim 1, wherein: The wrapper chain includes one of: (1) an input wrapper chain including a first plurality of flip-flops to provide input data to test the core logic; and (2) an output wrapper chain including a second plurality of flip-flops to receive output data from the core logic.

6. The IC of claim 1, wherein: The connection between the state machine driven flip-flop and a previous flip-flop in the wrapper chain propagates data to the state machine driven flip-flop at a rate that is less than an operation rate of the core logic.

7. The IC of claim 1, wherein: At least one of the state machine driven triggers is a first state machine driven trigger, and the first state machine driven trigger is configured to output the current value of the first state machine driven trigger, wherein the IC also includes a second state machine driven trigger, and the second state machine driven trigger is configured to output the inverse value of the current value of the second state machine driven trigger.

8. The IC of claim 1, wherein: The state machine driven trigger includes a first flip-flop and a second flip-flop, wherein the value shifted in the first flip-flop is the current value of the state machine driven trigger, and the value shifted in the second flip-flop configures the state machine driven trigger to output the current value of the state machine driven trigger or the inverse value of the current value of the state machine driven trigger.

9. The IC of claim 8, wherein: The state machine driven flip-flops are configured as: loading a first data bit of an input data string into the first flip-flop during a loading phase, wherein the first data bit represents a local data bit; loading a second data bit of the input data string into the second flip-flop during the loading phase, wherein the second data bit represents a switching state data bit indicating whether the flip-flop driven by the state machine is in a switching mode or a holding mode; wherein, when the state machine driven flip-flop is in the hold mode, the state machine driven flip-flop outputs the current value of the local data bit; and Wherein, when the state machine driven trigger is in the switching mode, the state machine driven trigger outputs the inverse value of the current value of the local data bit.

10. The IC of claim 1, wherein: During a loading phase of the test, a plurality of the flip-flops and the flip-flops driven by the state machine are configured to load data bits received from connections with corresponding flip-flops in response to a clock signal having a first frequency, and wherein, during a capture phase of the test, the flip-flops driven by the state machine are configured to output the value independent of the shifted scan data in response to a clock signal having a second frequency greater than the first frequency.

11. The IC of claim 1, wherein: The state machine driven flip-flop includes a next state logic gate including a first next state logic gate input, a second next state logic gate input, and a next state logic gate output.

12. The IC of claim 11, wherein: When the state machine driven flip-flop operates in a switching mode to output an inverse value of a current value, the second flip-flop is configured to forward the switching mode data bit value to the first next state logic gate input, and the next state logic gate is configured to switch the current value to the inverse value of the current value in response to receiving the switching mode data bit value.

13. The IC of claim 11, wherein: When the state machine driven flip-flop operates in a hold mode to output a current value, the second flip-flop is configured to forward the hold mode data bit value to the first next state logic gate input, and the next state logic gate is configured to hold the current value in response to receiving the hold mode data bit value at the first next state logic gate input.

14. The IC according to claim 1, in, The wrapper chain comprises an input wrapper chain, and wherein the IC further comprises an output wrapper chain, Wherein, the input wrapper chain is configured as: During the loading phase, in response to receiving a set of loading phase clock signals at a slow clock frequency, loading an input data string from the tester; Wherein, the output wrapper chain is configured as: During a capture phase, in response to receiving a set of capture phase clock signals at a fast clock rate, capturing captured data strings from a plurality of functional paths by the core logic; and During an offload phase, the captured data burst is offloaded to the tester in response to receiving a set of offload phase clock signals at the slow clock frequency.

15. A system comprising: Tester; as well as Integrated Circuits (ICs), including: Core logic, with functional logic elements; an input wrapper chain having a plurality of flip-flops for testing the core logic, wherein a plurality of the flip-flops in the wrapper chain are interconnected sequentially along a scan path for shifting scan data through consecutive flip-flops during testing of the core logic; Output wrapper chain; and at least one state machine driven flip-flop connected along the scan path of the input wrapper chain, wherein the state machine driven flip-flop is individually configurable during the testing to output a value independent of the scan data shifted along the scan path and received by the state machine driven flip-flop; Wherein, the input wrapper chain is configured as: During a load phase, in response to receiving a set of load phase clock signals at a slow clock frequency, loading an input data string from the tester to load values ​​into a plurality of the flip-flops and configuring the flip-flops driven by the state machine to output the values ​​independent of the scan data shifted along the scan path; Wherein, the output wrapper chain is configured as: During a capture phase, in response to receiving a set of capture phase clock signals at a fast clock rate, capturing captured data strings from a plurality of functional paths by the core logic; and During an offload phase, the captured data burst is offloaded to the tester in response to receiving a set of offload phase clock signals at the slow clock frequency.

16. The system of claim 15, wherein: The tester is configured to: comparing the captured data string to an expected data string, wherein the expected data string represents data that the core logic is expected to generate based on the input data string; and A determination is made based on the comparison whether the plurality of functional paths executed one or more errors when generating the captured data string.

17. The system of claim 15, wherein: The state machine driven flip-flop can be configured during testing to hold as an output a current value of the state machine driven flip-flop, the current value being shifted into the state machine driven flip-flop during a previous shift cycle of the wrapper chain.

18. The system of claim 15, wherein: The state machine driven flip-flop can be configured during testing to output an inverse value of a current value of the state machine driven flip-flop that was shifted into the state machine driven flip-flop during a previous shift cycle of the wrapper chain.

19. The system of claim 15, wherein: The state machine driven flip-flops can be configured to inhibit shifting of scan data into the state machine driven flip-flops during testing.

20. The system of claim 15, wherein: The state machine driven trigger includes a first flip-flop and a second flip-flop, wherein the value shifted in the first flip-flop is the current value of the state machine driven trigger, and the value shifted in the second flip-flop configures the state machine driven trigger to output the current value of the state machine driven trigger or the inverse value of the current value of the state machine driven trigger.

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