A simplified storage and computing circuit that can be used for data reading
By using a simplified storage computing unit array and operation unit array in the memory and computing integrated circuit, the calculation results are directly output as read data, which solves the problems of redundant circuits and high power consumption in the traditional memory and computing integrated core, and improves the The frequency and reliability of data reading and writing.
Patent Information
- Application Number
- CN202111115907.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-09-23
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2041-09-23
AI Technical Summary
The traditional memory and computing integrated core has a redundant static random memory read and write architecture during data reading, resulting in large circuit area, high power consumption and susceptible to external interference, affecting the reliability and frequency of data read and write operations.
A simplified integrated storage and computing circuit is designed, using a storage computing unit array, a data input unit array and an operation unit array, and selecting the target storage computing unit through the read address decoder to perform data input and calculation, and directly output the calculation results as The read data avoids the traditional static random memory reading circuit architecture, and uses adder arrays and multipliers to perform operations.
The circuit is simplified, the area and power consumption of the memory and computing core are reduced, the frequency and reliability of data read and write operations are improved, and the impact on external interference is reduced.
Smart Images
Figure CN113838497B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of chip design technology, and in particular to a simplified storage-computing integrated circuit, chip, and computing device that can be used for data reading. Background Art
[0002] At present, in the integrated storage and computing chip, the integrated storage and computing core mainly includes storage structure, multiplication and addition structure and logic control structure. For the storage structure, the integrated storage and computing core needs to write data into the storage and computing unit array and perform operations with the input product number. The design of the storage structure read and write function in the current conventional integrated storage and computing design mainly continues the read and write design architecture of the traditional static random access memory.
[0003] At present, the design architecture of the storage structure of the traditional storage-computing integrated core is similar to that of the traditional static random access memory, which is divided into two basic functions of reading and writing, and the implementation method is basically similar to that of the traditional static random access memory. When the storage-computing integrated core is in standby state, the bit line and the non-bit line are in a pre-charged high potential state, the word line is in a low potential, and the storage unit is in a data retention state. When the clock rises, the memory read and write functions are started, and the bit line and the non-bit line are pre-charged. If it is a data read cycle, the word line corresponding to the read address is opened in order under the control of the internal clock, and the data in the storage cell is transmitted to the bit line and the bit line's negation in a floating high potential state. The end storing '0' gradually lowers the voltage of the corresponding bit line or the bit line's negation, thereby forming a voltage difference with the bit line's negation or the high potential of the bit line on the other side. The voltage difference is transmitted to the sensitive amplifier along with the bit line and the bit line's negation signal. When the voltage difference reaches the threshold, the sensitive amplifier starts working and pulls down the lower voltage side of the bit line and the bit line's negation to '0', while maintaining the high potential '1' on the other side. The read data is then transmitted to the output port via the output unit of the storage and computing core to complete the read operation. Summary of the invention
[0004] An embodiment of the present disclosure provides a simplified storage-computation integrated circuit that can be used for data reading, and the circuit includes: a storage computing unit array, a data input unit array, an operation unit array, and a read address decoder; wherein the storage computing units included in the storage computing unit array correspond one-to-one to the data input units included in the data input unit array; the read address decoder is used to select a corresponding target storage computing unit from the storage computing unit array according to an input address of data to be read; the data input unit array is used to input first data to the target storage computing unit and second data to other storage computing units; the storage computing unit array is used to calculate the first data and the second data respectively with the storage data in the corresponding storage computing unit in a first preset manner, and input the obtained calculation results into the operation unit array; the operation unit array is used to calculate the input calculation results in a second preset manner to obtain the storage data in the target storage computing unit.
[0005] In some embodiments, the storage computing unit in the storage computing unit array includes a multiplier, and the multiplier is used to multiply the storage data in the storage computing unit with the data input by the corresponding data input unit.
[0006] In some embodiments, the first data is a digital 1 and the second data is a digital 0.
[0007] In some embodiments, the storage computing units in the storage computing unit array respectively include a first preset number of single-bit storage computing sub-units, each single-bit storage computing sub-unit includes a single-bit memory and a single-bit multiplier, and the single-bit multiplier is used to multiply the data in the corresponding single-bit memory with the data input by the corresponding data input unit.
[0008] In some embodiments, the operation unit array includes an adder array, and the adder array is used to add the calculation results input from the storage calculation unit to obtain the storage data in the target storage calculation unit.
[0009] In some embodiments, the adder array includes a second preset number of adder groups, the second preset number of adder groups are connected in sequence in a cascade manner, and the input ends of the adders included in the first-level adder group in the second preset number of adder groups are respectively connected to adjacent storage computing unit groups.
[0010] In some embodiments, the circuit also includes a main controller, which is used to: obtain the address of the data to be read, and send the address of the data to be read to a read address decoder; determine the target data input unit from the data input unit array based on the address of the data to be read; generate first data corresponding to the target data input unit and second data corresponding to other data input units in the data input unit array; send the first data to the target data input unit, and send the second data to other data input units.
[0011] In some embodiments, the main controller is further used to: receive data output by the computing unit array, and determine the received data as data read from the target storage computing unit.
[0012] According to another aspect of an embodiment of the present disclosure, a chip is provided, which includes the above-mentioned simplified storage-computation-in-one circuit that can be used for data reading.
[0013] According to another aspect of an embodiment of the present disclosure, a computing device is provided, which includes the above chip.
[0014] The simplified storage-computing integrated circuit, chip and computing device for data reading provided by the above-mentioned embodiments of the present disclosure provide a new storage-computing integrated circuit for data reading compared to the traditional data reading architecture. By utilizing the existing storage computing unit array, data input unit array, computing unit array and read address decoder, when reading data, the data input unit array is used to input the first data to the target storage computing unit to be read, and the second data to other storage computing units. The storage computing unit array performs calculation based on the input data, and the obtained calculation result is input into the computing unit array. The computing unit array outputs the calculated data, which is the data read from the target storage computing unit. Compared with the existing storage-computing integrated circuit, it further realizes simplification, and it does not need to set the reading circuit architecture of the traditional static random access memory including the sensitive amplifier, etc., which reduces the area of the storage-computing integrated core, reduces the circuit scale, and reduces the power consumption of the storage-computing integrated core. In addition, since the embodiment of the present disclosure does not adopt the reading data architecture of the traditional static random access memory, the frequency of storing data no longer considers the reading operation frequency, which improves the working frequency of the storage-computing integrated core in data reading and writing operations. The disclosed embodiment does not adopt the architecture of the traditional static random access memory's sense amplifier to read data, so that the design is less affected by external interference factors such as process deviation, read interference, voltage and temperature, and the reliability of the data reading operation is higher.
[0015] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The above and other purposes, features and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps.
[0017] Figure 1 It is a structural diagram of a simplified storage-computation-in-one circuit that can be used for data reading provided by an exemplary embodiment of the present disclosure.
[0018] Figure 2 It is a schematic diagram of the structure of a single-bit storage computing subunit provided by an exemplary embodiment of the present disclosure.
[0019] Figure 3 Schematic diagram of the structure of an adder array provided by an exemplary embodiment of the present disclosure.
[0020] Figure 4 It is another structural schematic diagram of a simplified storage-computation-in-one circuit that can be used for data reading provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION
[0021] Below, the exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described here.
[0022] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
[0023] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.
[0024] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.
[0025] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.
[0026] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.
[0027] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.
[0028] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.
[0029] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.
[0030] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.
[0031] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.
[0032] Application Overview
[0033] There are currently two main technical solutions for the design of multiplication and addition units. One is to use multiple simple integer multipliers to build a large-scale array. This solution has poor support for data bit width flexibility and data volume flexibility, and does not support floating-point operations. Data needs to be quantized in advance on the computer before use. The other is to use a general floating-point calculation unit to perform multiplication and addition operations in a loop. This solution has more redundant processing and is inefficient when the data volume is large.
[0034] Exemplary Structure
[0035] Figure 1 This is a schematic diagram of a simplified storage-computation-in-one circuit for data reading provided by an exemplary embodiment of the present disclosure. The various components included in the circuit can be integrated into one chip, or can be set in different chips or circuit boards, and data communication links are established between these chips or circuit boards.
[0036] like Figure 1 As shown, the circuit includes: a storage calculation unit array 101, a data input unit array 102, an operation unit array 103, and a read address decoder 104. The storage calculation units included in the storage calculation unit array 101 correspond to the data input units included in the data input unit array 102. The storage calculation unit array 101 includes a plurality of storage calculation units, and each storage calculation unit includes a preset number of single-bit storage calculation sub-units. Figure 1 As shown, four cells (i.e., single-bit storage sub-units) in each row represent a storage computing unit, i.e., a storage computing unit can store a 4-bit data. Each data input unit in the data input unit array 102 corresponds to a storage computing unit.
[0037] In this embodiment, the read address decoder 104 is used to select a corresponding target storage computing unit from the storage computing unit array 101 according to the input data address to be read. The read address decoder 104 can activate the corresponding word line according to the data address to be read, thereby selecting the target storage computing unit. Figure 1 As shown, the read address decoder 104 determines that the storage computing unit in the first row is the target storage computing unit according to the input address add1 of the data to be read, that is, the target storage computing unit stores the data to be read.
[0038] In this embodiment, the data input unit array 102 is used to input the first data to the target storage computing unit and the second data to other storage computing units. Among them, the data input unit that transmits the first data can be determined according to the address of the data to be read. Specifically, since the data input unit and the storage computing unit are one-to-one corresponding, the data input unit corresponding to the target storage computing unit can be determined according to the address of the data to be read. Usually, the data input unit inputs a single bit of data to the corresponding storage computing unit each time, that is, the first data and the second data are single bit data. For example, the first data can be 1 (or 0), and the second data can be 0 (or 1).
[0039] In this embodiment, the storage calculation unit array 101 is used to perform a first preset calculation on the first data and the second data respectively with the storage data in the corresponding storage calculation unit, and input the obtained calculation result into the calculation unit array 103. The first preset method can be various calculation methods set as needed, such as multiplication operation or bitwise AND operation.
[0040] Optionally, the first preset mode may be a multiplication calculation, and the storage calculation unit in the storage calculation unit array 101 includes a multiplier, and the multiplier is used to multiply the storage data in the storage calculation unit with the data input by the corresponding data input unit. Optionally, the first data may be a number 1, and the second data may be a number 0. At this time, the storage data stored in the target storage calculation unit is multiplied by the number 1, and the calculation result is equal to the storage data; the storage data stored in other storage calculation units are multiplied by the number 0, and the calculation results are all 0. Subsequently, the various calculation results can be added, and the sum obtained is equal to the storage data in the target storage calculation unit.
[0041] It should be noted that the first data and the second data can also be set to other data. For example, the first data can be 0 and the second data can be 1. In this case, after inputting the storage calculation unit, the first data and the second data need to be inverted before performing the multiplication operation.
[0042] The above optional implementation method, by setting a multiplier in the storage computing unit, can multiply the input data with the storage data, which can not only support the multiplication and addition operations in scenarios such as neural networks, but also use the principle of multiplication and addition to read the storage data from the target storage computing unit, thereby expanding the application scenarios of the storage and computing integrated circuit.
[0043] Optionally, the storage computing units in the storage computing unit array 101 each include a first preset number (eg Figure 1 As shown, the first preset number is 4) single-bit storage computing subunits. Figure 2As shown, each single-bit storage calculation subunit 201 includes a single-bit memory 2011 and a single-bit multiplier 2012, and the single-bit multiplier 2012 is used to multiply the data in the corresponding single-bit memory 2011 and the data input by the corresponding data input unit. Each data input unit usually inputs a single-bit data at a time, and the single-bit data is multiplied with the single-bit stored in each single-bit memory included in the corresponding storage calculation unit to obtain the single-bit product corresponding to each stored single-bit. The bits output by each single-bit multiplier included in a storage calculation unit constitute the data output by the storage calculation unit, and the data is input into the operation unit array 103.
[0044] As an example, Figure 1 As shown, the first row sets the storage calculation unit as the target storage calculation unit, which stores data W=1010, that is, W[0]=0, W[1]=1, W[2]=0, W[3]=1, and the input first data IN=1, then the four single-bit multipliers in the target storage calculation unit calculate W[0]×IN, W[1]×IN, W[2]×IN, W[4]×IN respectively, and the calculated product data is S=1010=W. The second data received as input by other storage calculation units is 0, and according to the same calculation process, the product data output by other storage calculation units are all 0. As an example, the single-bit multiplier may include a NOR gate, and the NOR gate is used to perform a NOR operation on the single bit included in the inverted storage data and the single bit included in the inverted input data to obtain the single-bit product data.
[0045] This implementation method arranges a single-bit memory and a single-bit multiplier in a single-bit storage calculation subunit, and can use a simple architecture and calculation process to implement in-memory multiplication operations, thereby improving the efficiency of reading stored data.
[0046] In this embodiment, the operation unit array 103 is used to perform a second preset method of calculation on the input calculation result to obtain the storage data in the target storage calculation unit. The second preset method can be set arbitrarily as needed, for example, it can be an addition calculation (implemented by an adder array) or a bitwise OR operation (implemented by an OR gate array).
[0047] The circuit provided by the above-mentioned embodiment of the present disclosure provides a new type of simplified storage-computation integrated circuit that can be used for data reading, compared with the traditional data reading architecture. By utilizing the existing storage computing unit array, data input unit array, operation unit array, and read address decoder, when reading data, the data input unit array is used to input the first data to the target storage computing unit to be read, and the second data to other storage computing units. The storage computing unit array performs calculations based on the input data, and the obtained calculation results are input into the operation unit array. The operation unit array outputs the calculated data, which is the data read from the target storage computing unit. Compared with the existing storage-computation integrated circuit, it further realizes simplification, and it does not need to set the traditional static random access memory read circuit architecture including sensitive amplifiers, etc., which reduces the area of the storage-computation integrated core, reduces the circuit scale, and reduces the power consumption of the storage-computation integrated core. In addition, since the embodiment of the present disclosure does not adopt the traditional static random access memory read data architecture, the frequency of storing data no longer considers the read operation frequency, which improves the working frequency of the storage-computation integrated core in data reading and writing operations. The disclosed embodiment does not adopt the architecture of the traditional static random access memory's sense amplifier to read data, so that the design is less affected by external interference factors such as process deviation, read interference, voltage and temperature, and the reliability of the data reading operation is higher.
[0048] In some optional implementations, the operation unit array 103 includes an adder array, which is used to add the calculation results input from the storage calculation unit to obtain the storage data in the target storage calculation unit. In combination with the above examples, if the calculation result input from the target storage calculation unit is 1, and the calculation result input from other storage calculation units is 0, then the calculation results are added through the adder array, and the data obtained is the storage data in the target storage calculation unit.
[0049] This implementation method can add the calculation results output by the storage computing unit array to obtain the storage data in the target storage computing unit by setting an adder array. It can not only support multiplication and addition operations in scenarios such as neural networks, but also use the principle of multiplication and addition to read storage data from the target storage computing unit, thereby expanding the application scenarios of the storage and computing integrated circuit.
[0050] In some optional implementations, the adder array includes a second preset number of adder groups, the second preset number of adder groups are connected in sequence in a cascade manner, and the input ends of the adders included in the first-level adder group in the second preset number of adder groups are respectively connected to adjacent storage computing unit groups.
[0051] like Figure 3As shown, the operation unit array 103 is composed of an adder array, which includes M (i.e., the second preset number) columns, and the adders included in each column are an adder group, that is, the first column marked as "adder_1" is the first-level adder group, the second column marked as "adder_2" is the second-level adder group, ..., the Mth column marked as "adder_M" is the Mth-level adder group. Starting from the second-level adder group, each adder corresponds to the two adders of the previous level, that is, the outputs of the two adders of the previous level serve as the inputs of the adder of the next level. Each adder included in the first-level adder group receives the calculation result input by the corresponding storage calculation unit, and the Mth-level adder group includes only one adder, and its output data is the sum of the data output by the N storage calculation units respectively.
[0052] This implementation method can effectively save the area occupied by the adder array, improve the area utilization of the circuit, and shorten the length of the data transmission line in the circuit, which is conducive to reducing power consumption when reading data, by setting a cascaded adder group.
[0053] In some optional implementations, such as Figure 4 As shown, the circuit further includes a main controller 105, and the main controller 105 is used to perform the following steps:
[0054] Step 1: Obtain the address of the data to be read, and send the address of the data to be read to the read address decoder.
[0055] The address to be read may be obtained according to the running data reading program. After sending the address add1 of the data to be read to the read address decoder 104, the read address decoder 104 further selects the target storage computing unit. Figure 4 As shown, the storage computing unit located in the first row is the target storage computing unit.
[0056] Step 2: determining a target data input unit from a data input unit array based on the address of the data to be read.
[0057] Specifically, the main controller 105 can determine the target data input unit corresponding to the target storage computing unit from the data input unit array 102 according to the correspondence between the data input unit and the storage computing unit and the address of the data to be read. Figure 4 As shown, the data input unit located in the first row is the target data input unit.
[0058] Step three, generating first data corresponding to the target data input unit and second data corresponding to other data input units in the data input unit array.
[0059] Step 4: sending the first data to the target data input unit, and sending the second data to other data input units.
[0060] As an example, Figure 4 As shown, the first data is number 1, and the second data is number 0. Number 1 is input into the target storage computing unit through the target data input unit, and number 0 is input into other storage computing units.
[0061] This implementation method can effectively control the data transmission of each component in the circuit by setting up a main controller, so as to improve the data reading function of the storage-computing integrated circuit and improve the efficiency of reading data from the storage-computing integrated circuit.
[0062] In some optional implementations, the main controller 105 is further configured to: receive data output by the computing unit array 103, and determine the received data as data read from the target storage computing unit.
[0063] like Figure 4 As shown, after receiving the first data and the second data input by the data input unit array 102, the storage computing unit array 101 performs operations in each storage computing unit, and inputs each calculation result obtained into the computing unit array 103. The computing unit array 103 further performs calculations on each input calculation result, and inputs the obtained data "1010" into the main controller 105. After obtaining the storage data in the target storage computing unit, the main controller 105 can continue to perform a series of operations on the storage data.
[0064] This implementation method can control the storage-computing integrated circuit to read data in the storage-computing mode by receiving the data output by the computing unit array as the data read from the target storage computing unit, without setting the storage-computing integrated circuit to the traditional data reading mode, thereby expanding the application scenarios of the storage-computing integrated circuit and simplifying the circuit architecture for reading data.
[0065] The embodiment of the present disclosure further provides a chip on which a simplified storage-computation-in-one circuit for data reading is integrated. The technical details of the simplified storage-computation-in-one circuit for data reading are as follows: Figure 1-Figure 4 As shown in the relevant description, no further description is given here.
[0066] The embodiments of the present disclosure also provide a computing device, which includes the chip described in the above embodiments. In addition, the computing device may also include an input device, an output device, and necessary memory, etc. Among them, the input device may include such as a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting the address of the data to be read, etc. The output device may include such as a display, a printer, and a communication network and its connected remote output device, etc., for outputting the data read from the target storage computing unit as described in the above embodiments, etc. The memory is used to store the data input by the above input device, as well as the data generated during the operation of the simplified storage and calculation integrated circuit that can be used for data reading. The memory may include a volatile memory and / or a non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc.
[0067] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.
[0068] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other.
[0069] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.
[0070] The circuits of the present disclosure may be implemented in many ways. For example, the circuits of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps of the method used in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, which include machine-readable instructions for implementing the functions of the circuits of the present disclosure. Thus, the present disclosure also covers recording media storing programs for executing the functions of the circuits of the present disclosure.
[0071] It should also be noted that in the circuit of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as an equivalent solution of the present disclosure.
[0072] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.
[0073] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.
Claims
1. A simplified storage-computation integrated circuit for data reading, comprising: A storage calculation unit array, a data input unit array, an operation unit array, and a read address decoder; wherein the storage calculation units included in the storage calculation unit array correspond one to one with the data input units included in the data input unit array; The read address decoder is used to select a corresponding target storage computing unit from the storage computing unit array according to the input data address to be read; The data input unit array is used to input first data to the target storage computing unit and input second data to other storage computing units; The storage and calculation unit array is used to perform a first preset calculation on the first data and the second data respectively with the storage data in the corresponding storage and calculation unit, and input the obtained calculation results into the calculation unit array, wherein the first preset method includes a multiplication operation or a bitwise AND operation; The operation unit array is used to perform a second preset method of calculation on the input calculation result to obtain the storage data in the target storage calculation unit, wherein the second preset method includes addition calculation or bitwise OR operation.
2. The circuit according to claim 1, wherein The storage computing unit in the storage computing unit array includes a multiplier, and the multiplier is used to multiply the storage data in the storage computing unit with the data input by the corresponding data input unit.
3. The circuit according to claim 2, wherein: The first data is a number 1, and the second data is a number 0.
4. The circuit according to claim 2, wherein: The storage computing units in the storage computing unit array respectively include a first preset number of single-bit storage computing sub-units, each single-bit storage computing sub-unit includes a single-bit memory and a single-bit multiplier, and the single-bit multiplier is used to multiply the data in the corresponding single-bit memory with the data input by the corresponding data input unit.
5. The circuit according to claim 1, wherein: The operation unit array includes an adder array, and the adder array is used to add the calculation results input from the storage calculation unit to obtain the storage data in the target storage calculation unit.
6. The circuit according to claim 5, wherein: The adder array includes a second preset number of adder groups, the second preset number of adder groups are connected in sequence in a cascade manner, and the input ends of the adders included in the first-level adder group in the second preset number of adder groups are respectively connected to adjacent storage computing unit groups.
7. The circuit according to claim 1, wherein: The circuit further comprises a main controller, wherein the main controller is configured to: Acquire the address of the data to be read, and send the address of the data to be read to the read address decoder; Based on the address of the data to be read, determining a target data input unit from the data input unit array; Generate first data corresponding to the target data input unit and second data corresponding to other data input units in the data input unit array; The first data is sent to the target data input unit, and the second data is sent to the other data input unit.
8. The circuit according to claim 7, wherein: The main controller is also used for: The data output by the computing unit array is received, and the received data is determined as data read from the target storage computing unit.
9. A chip, characterized in that: It comprises a simplified storage-computation-in-one circuit that can be used for data reading according to any one of claims 1-8.
10. A computing device, characterized in that: Comprising the chip according to claim 9.