A Top Com array structure

Abstract

The present invention discloses a Top Com array structure, including a glass substrate, a gate GE layer is provided on the glass substrate, an inorganic insulating GI layer is deposited on the gate GE layer, an active SE layer is provided on the inorganic insulating GI layer, an etching stopper ES layer is provided on the active SE layer, a source-drain SD layer is provided on the etching stopper ES layer, an inorganic insulating PV layer is deposited on the source-drain SD layer, an organic insulating OC layer is coated on the inorganic insulating PV layer, an OC hole is opened on the organic insulating OC layer, a PV hole is etched on the inorganic insulating PV layer, a pixel electrode PE layer is deposited on the organic insulating OC layer, an inorganic CH layer is deposited on the pixel electrode PE layer, and a common electrode BC layer is deposited on the inorganic CH layer. Based on the existing Top-Com design principle and without changing the process technology, the present invention effectively uses a photomask to dry-etch the ES layer to form an ES hole and the PV layer to form a PV hole, so that the original 9 masks are reduced to 8 masks, thereby achieving the purpose of reducing production costs and improving product benefits.

Description

Technical Field

[0001] The invention belongs to the technical field of touch panels, and in particular relates to a Top Com array structure. Background Art

[0002] At present, amorphous metal oxide semiconductors are developing rapidly. Among them, amorphous InGaZnO (IGZO) has become an ideal material for TFT preparation due to its simple preparation process and excellent optoelectronic properties. The TFT prepared by it has the characteristics of high mobility and high switching ratio, and has the potential to replace a-Si. Compared with a-Si TFT, the carrier mobility of IGZO-TFT can reach 10-30cm 2 / V·S, greatly improving the charging and discharging efficiency and response speed of TFT to pixel electrodes. More importantly, the IGZO process is highly compatible with the existing a-Si production line, and has a lower investment cost than low-temperature polysilicon (LTPS), which has a more complex production process and higher equipment investment.

[0003] With the rapid development of current display technology, In-cell panel technology that embeds touch panel functions into liquid crystal pixels has been widely used in various smart phones and tablet computers. This touch panel technology mainly combines the touch panel and the liquid crystal panel into one, so that the liquid crystal panel that originally has display function also has touch input function. Its biggest advantage is that it can effectively reduce the thickness of the entire display screen. The thinning of the thickness can not only reduce the weight of the entire mobile phone, but also free up more space for expanding the battery or other parts, etc.

[0004] The mainstream design in the current market is based on Mid-com In cell technology. This design requires a total of 10 masks to complete the array process. The main purpose is to design the touch metal layer connected to the transparent common electrode on the organic flat layer. In terms of the array process, only two layers, VA (inorganic layer) and CM (touch metal layer), are added. In order to simplify the process flow, the existing mass production also adopts a Top-Com design array structure with 9 masks. This solution forms TPLine and Data Line at the same time through the SD process, reducing the two processes of CM layer and VA layer to simplify the process flow. In order to reduce production costs and improve product benefits, how to further optimize the process mode on the existing Top-Com structure has become the key to improving the solution. To this end, we propose a Top Com array structure to solve the problems mentioned in the above background technology. Summary of the invention

[0005] The object of the present invention is to provide a Top Com array structure to solve the problems raised in the above background technology.

[0006] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a Top Com array structure, comprising a glass substrate, a gate GE layer is provided on the glass substrate, an inorganic insulating GI layer is deposited on the gate GE layer, an active SE layer is provided on the inorganic insulating GI layer, an etch stopper ES layer is provided on the active SE layer, a source and drain electrode SD layer is provided on the etch stopper ES layer, an inorganic insulating PV layer is deposited on the source and drain electrode SD layer, an organic insulating OC layer is coated on the inorganic insulating PV layer, an OC hole is opened on the organic insulating OC layer, a PV hole is etched on the inorganic insulating PV layer, a pixel electrode PE layer is deposited on the organic insulating OC layer, an inorganic CH layer is deposited on the pixel electrode PE layer, and a common electrode BC layer is deposited on the inorganic CH layer.

[0007] The glass substrate is a plain glass on the TFT side, on which active devices such as TFT are sequentially formed.

[0008] The gate GE layer is a non-transparent gate GE layer with low resistivity, and can be made of aluminum / molybdenum / titanium / nickel / copper / and other metals with good conductivity and alloys, and Mo / Al / Mo or Ti / Ai / Ti is taken as an example here;

[0009] The inorganic insulating GI layer is an insulating layer with a relatively large dielectric constant, and SiOx or SiNx may be selected for this design;

[0010] The active SE layer is a semiconductor layer of a TFT device, such as a-Si, MOx, and LTPS, etc., and IGZO can be selected for this design scheme;

[0011] The etching stop ES layer is an insulating layer with a large dielectric constant, which protects the active SE layer in the channel area from being etched by the etching gas or liquid of the source and drain SD layer;

[0012] The source and drain SD layers are Mo / Al / Mo or Ti / Ai / Ti as examples;

[0013] The inorganic insulating PV layer has an insulating layer with a relatively large dielectric constant, and SiOx or SiNx may be selected for this design;

[0014] The organic insulating OC layer is mainly an organic material, covering the insulating layer, used to flatten the surface of the TFT device, and the OC hole is developed after exposure;

[0015] The pixel electrode PE layer is transparent conductive ITO;

[0016] The inorganic CH layer has an insulating layer with a large dielectric constant, and SiOx and SiNx can be selected for this design;

[0017] The material of the common electrode BC layer is transparent conductive ITO.

[0018] A manufacturing process of a Top Com array structure specifically comprises the following steps:

[0019] S1, manufacturing a gate GE layer on a glass substrate of a substrate;

[0020] S2, depositing an inorganic insulating GI layer on the gate GE layer;

[0021] S3, manufacturing an active SE layer on the inorganic insulating GI layer;

[0022] S4, manufacturing an etch stop ES layer on the active SE layer;

[0023] S5, manufacturing a source and drain electrode SD layer on the etching stopper ES layer;

[0024] S6, depositing an inorganic insulating PV layer on the source and drain SD layer;

[0025] S7, coating an organic insulating OC layer on the inorganic insulating PV layer, and opening an OC hole;

[0026] S8, using the same ES layer mask exposure development etching PV hole;

[0027] S9, depositing a pixel electrode PE layer on the organic insulating OC layer;

[0028] S10, depositing an inorganic CH layer on the pixel electrode PE layer;

[0029] S11 . Depositing a common electrode BC layer on the inorganic CH layer.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows: a Top Com array structure provided by the present invention, based on the existing Top-Com design principle and without changing the process technology, effectively uses a Mask (i.e., an etch-blocking ES layer and an inorganic insulating PV layer share a mask) to dry-etch ES holes in the ES layer and dry-etch PV holes in the PV layer, thereby reducing the original 9 Masks to 8, thereby achieving the purpose of reducing production costs and improving product benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a structural schematic diagram of step S1 of the present invention;

[0032] Figure 2 It is a structural schematic diagram of step S2 of the present invention;

[0033] Figure 3 It is a structural schematic diagram of step S3 of the present invention;

[0034] Figure 4 It is a structural schematic diagram of step S4 of the present invention;

[0035] Figure 5 It is a structural schematic diagram of step S5 of the present invention;

[0036] Figure 6 It is a structural schematic diagram of step S6 of the present invention;

[0037] Figure 7 It is a structural schematic diagram of step S7 of the present invention;

[0038] Figure 8 It is a structural schematic diagram of step S8 of the present invention;

[0039] Fig. 9 It is a structural schematic diagram of step S9 of the present invention;

[0040] Fig.10 It is a structural schematic diagram of step S10 of the present invention;

[0041] Fig.11 It is a structural schematic diagram of step S11 of the present invention;

[0042] Fig.12 Schematic diagram of array structure designed for existing mass-produced Top-com.

[0043] In the figure: 1. glass substrate; 2. gate GE layer; 3. inorganic insulating GI layer; 4. active SE layer; 5. etching stopper ES layer; 6. source and drain SD layer; 7. inorganic insulating PV layer; 8. organic insulating OC layer; 9. pixel electrode PE layer; 10. inorganic CH layer; 11. common electrode BC layer; 12. OC hole; 13. PV hole. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] Embodiment 1: The present invention provides Figure 1-11A Top Com array structure comprises a glass substrate 1, wherein a gate GE layer 2 is provided on the glass substrate 1, an inorganic insulating GI layer 3 is deposited on the gate GE layer 2, an active SE layer 4 is provided on the inorganic insulating GI layer 3, an etching stopper ES layer 5 is provided on the active SE layer 4, a source and drain electrode SD layer 6 is provided on the etching stopper ES layer 5, an inorganic insulating PV layer 7 is deposited on the source and drain electrode SD layer 6, an organic insulating OC layer 8 is coated on the inorganic insulating PV layer 7, an OC hole 12 is opened on the organic insulating OC layer 8, a PV hole 13 is etched on the inorganic insulating PV layer 7, a pixel electrode PE layer 9 is deposited on the organic insulating OC layer 8, an inorganic CH layer 10 is deposited on the pixel electrode PE layer 9, and a common electrode BC layer 11 is deposited on the inorganic CH layer 10.

[0046] The glass substrate 1 is a plain glass on the TFT side, on which active devices such as TFT are sequentially formed.

[0047] The gate GE layer 2 is a non-transparent gate GE layer with low resistivity, and can be made of aluminum / molybdenum / titanium / nickel / copper / and other metals with good conductivity and alloys, and Mo / Al / Mo or Ti / Ai / Ti is used as an example here;

[0048] The inorganic insulating GI layer 3 is an insulating layer with a relatively large dielectric constant, and SiOx or SiNx may be selected for this design;

[0049] The active SE layer 4 is a semiconductor layer of a TFT device, such as a-Si, MOx and LTPS, etc., and IGZO can be selected for this design;

[0050] The etching stop ES layer 5 is an insulating layer with a relatively large dielectric constant, protecting the active SE layer 4 in the channel region from being etched by the etching gas or liquid of the source and drain SD layer 6;

[0051] The source / drain SD layer 6 is Mo / Al / Mo or Ti / Ai / Ti as an example;

[0052] The inorganic insulating PV layer 7 has an insulating layer with a relatively large dielectric constant, and SiOx or SiNx may be selected for this design;

[0053] The organic insulating OC layer 8 is mainly an organic material, covering the insulating layer, and is used to flatten the surface of the TFT device, and the OC hole 12 is developed through exposure;

[0054] The pixel electrode PE layer 9 is transparent conductive ITO;

[0055] The inorganic CH layer 10 is an insulating layer with a relatively large dielectric constant, and SiOx and SiNx may be selected for this design;

[0056] The material of the common electrode BC layer 11 is transparent conductive ITO.

[0057] A manufacturing process of a Top Com array structure specifically comprises the following steps:

[0058] S1, manufacturing a gate GE layer 2 on a glass substrate 1 of a substrate;

[0059] S2, depositing an inorganic insulating GI layer 3 on the gate GE layer 2;

[0060] S3, manufacturing an active SE layer 4 on the inorganic insulating GI layer 3;

[0061] S4, manufacturing an etching stop ES layer 5 on the active SE layer 4;

[0062] S5, manufacturing a source and drain electrode SD layer 6 on the etching stopper ES layer 5;

[0063] S6, depositing an inorganic insulating PV layer 7 on the source and drain electrode SD layer 6;

[0064] S7, coating an organic insulating OC layer 8 on the inorganic insulating PV layer 7, and opening an OC hole 12;

[0065] S8, using the same ES layer photomask exposure development etching PV hole 13;

[0066] S9, depositing a pixel electrode PE layer 9 on the organic insulating OC layer 8;

[0067] S10, depositing an inorganic CH layer 10 on the pixel electrode PE layer 9;

[0068] S11 , depositing a common electrode BC layer 11 on the inorganic CH layer 10 .

[0069] The existing In-Cell technology refers to a method of embedding the touch panel function into the liquid crystal pixel, thereby realizing the integrated design of the touch panel component and the liquid crystal panel. The current mainstream design in the market is mainly based on Mid-com In cell technology. This design requires a total of 10 masks to complete the array process. In order to simplify the process flow, such as Fig.12 As shown, the existing mass production also uses a Top-Com design array structure with 9 masks. This solution forms TP Line and Data Line simultaneously through the SD process, reducing the two processes of CM layer and VA layer to simplify the process flow.

[0070] To sum up, compared with the prior art, the present invention is based on the existing Top-Com design principle and does not change the process technology. By effectively using one mask (the etching barrier ES layer 5 and the inorganic insulating PV layer 7 share the mask), the ES layer is dry-etched to form ES holes and the PV layer is dry-etched to form PV holes 13, so that the existing 9-mask Top-Com design is reduced by one mask compared with the mainstream 10-mask Mid-Com design. Based on the existing Top-Com design principle, the present invention further reduces the number of masks to 8 by etching the blocking ES layer 5 and the inorganic insulating PV layer 7 sharing one mask (i.e., mask), thereby reducing production costs and improving product benefits.

[0071] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A manufacturing process of a Top Com array structure, characterized in that: The Top Com array structure comprises a glass substrate (1), wherein a gate electrode GE layer (2) is provided on the glass substrate (1), an inorganic insulating GI layer (3) is deposited on the gate electrode GE layer (2), an active SE layer (4) is provided on the inorganic insulating GI layer (3), an etching stopper ES layer (5) is provided on the active SE layer (4), a source and drain electrode SD layer (6) is provided on the etching stopper ES layer (5), an inorganic insulating PV layer (7) is deposited on the source and drain electrode SD layer (6), an organic insulating OC layer (8) is coated on the inorganic insulating PV layer (7), an OC hole (12) is opened on the organic insulating OC layer (8), a PV hole (13) is etched on the inorganic insulating PV layer (7), a pixel electrode PE layer (9) is deposited on the organic insulating OC layer (8), an inorganic CH layer (10) is deposited on the pixel electrode PE layer (9), and a common electrode BC layer (11) is deposited on the inorganic CH layer (10); The manufacturing process specifically includes the following steps: S1, manufacturing a gate electrode GE layer (2) on a glass substrate (1) of a substrate; S2, depositing an inorganic insulating GI layer (3) on the gate GE layer (2); S3, manufacturing an active SE layer (4) on the inorganic insulating GI layer (3); S4, manufacturing an etch stop ES layer (5) on the active SE layer (4); S5, manufacturing a source and drain SD layer (6) on the etching stop ES layer (5); S6, depositing an inorganic insulating PV layer (7) on the source and drain SD layer (6); S7, coating an organic insulating OC layer (8) on the inorganic insulating PV layer (7), and opening an OC hole (12); S8, using a mask of the same ES layer for exposure, development and etching to form a PV hole (13); S9, depositing a pixel electrode PE layer (9) on the organic insulating OC layer (8); S10, depositing an inorganic CH layer (10) on the pixel electrode PE layer (9); S11, depositing a common electrode BC layer (11) on the inorganic CH layer (10).

2. The manufacturing process of a Top Com array structure according to claim 1, characterized in that: The glass substrate (1) is plain glass on the TFT side, on which TFT active devices are sequentially formed.

3. The manufacturing process of a Top Com array structure according to claim 1, characterized in that: The gate GE layer (2) is made of aluminum, molybdenum, titanium, nickel, copper or an alloy.

4. The manufacturing process of a Top Com array structure according to claim 1, characterized in that: The material of the inorganic insulating GI layer (3) is SiOx or SiNx.

5. The manufacturing process of a Top Com array structure according to claim 1, characterized in that: The active SE layer (4) is a TFT device semiconductor layer, and its material is a-Si, LTPS or IGZO.

6. The manufacturing process of a Top Com array structure according to claim 1, characterized in that: The material of the inorganic insulating PV layer (7) is SiOx or SiNx.

7. The manufacturing process of a Top Com array structure according to claim 1, characterized in that: The material of the inorganic CH layer (10) is SiOx or SiNx.

8. The manufacturing process of a Top Com array structure according to claim 1, characterized in that: The material of the common electrode BC layer (11) is transparent conductive ITO.

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