Clock transmitting apparatus and method, clock receiving apparatus and method

Abstract

Embodiments of the present application provide a clock sending device and method, a clock receiving device and method, wherein the clock sending device comprises: an input unit configured to input a first input clock and a second input clock; a sampling unit configured to obtain a first sampling clock and a second sampling clock, and determine a first frequency control word according to the first sampling clock and the second sampling clock; wherein the first frequency control word is used to indicate a relationship between the first sampling clock and the second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to the preset rule; and a sending unit configured to generate a clock signal according to the first input clock, and send the clock signal to a receiving side; wherein the clock signal at least carries the first frequency control word. Through the present application, the problem that clock line layout is too complex and difficult to implement in the clock distribution process of a communication device in the related art can be solved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of communication, in particular to a clock sending device and method, a clock receiving device and method. BACKGROUND

[0002] With the continuous improvement of network throughput, the types of service cards and rack slots in communication devices such as large-capacity switches and routers are increasing. Clock distribution corresponding to various services is an indispensable function in communication devices. Generally, a communication device needs to receive various frequency source clocks of external lines, the number of which ranges from 1 to infinity. For example, for a 20-slot system, 40 lines are needed for uplink and downlink clock wiring; if the system has two different frequency source clocks for distribution and backhaul, a total of 80 lines are needed, and if a differential wiring method is used, a total of 160 lines are needed. With the increase in the number of different frequency source clocks in each slot, the number of clock corresponding lines will increase exponentially.

[0003] Moreover, in a communication device, the above lines usually need to be laid continuously for tens of centimeters, and in some large communication devices, more than one meter of continuous wiring is needed to complete the connection. With the design concept of miniaturization, integration and low cost of communication devices, the space available for wiring in the backboard of the communication device is extremely limited, and the large number of clock lines that need to be wired over a long distance are difficult to implement in the backboard, which is extremely space-constrained.

[0004] For the problem of too complex and difficult to implement clock line layout in the clock distribution process of the communication device in the related technology, the related technology has not yet proposed an effective solution. SUMMARY

[0005] Embodiments of the present application provide a clock sending device and method, a clock receiving device and method to at least solve the problem of too complex and difficult to implement clock line layout in the clock distribution process of the communication device in the related technology.

[0006] According to an embodiment of the present application, a clock sending device is provided, the device comprising:

[0007] an input unit configured to input a first input clock and a second input clock;

[0008] The sampling unit is configured to acquire a first sampling clock and a second sampling clock, and determine a first frequency control word according to the first sampling clock and the second sampling clock; wherein the first frequency control word is used to indicate a relationship between the first sampling clock and the second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule.

[0009] The sending unit is configured to generate a clock signal according to the first input clock, and send the clock signal to a receiving side; wherein the clock signal at least carries the first frequency control word.

[0010] According to another embodiment of the present application, a clock receiving device is also provided, and the device comprises:

[0011] The receiving unit is configured to receive a clock signal sent by a sending side; wherein the clock signal is generated according to a first input clock of the sending side, the clock signal at least carries a first frequency control word, the first frequency control word is used to indicate a relationship between a first sampling clock and a second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by a second input clock of the sending side according to a preset rule; the receiving unit is further configured to determine the first input clock and the first frequency control word according to the clock signal;

[0012] The recovering unit is configured to determine the second input clock according to the first input clock and the first frequency control word.

[0013] According to another embodiment of the present application, a clock transmission system is also provided, and the system comprises:

[0014] The input unit is configured to input a first input clock and a second input clock;

[0015] The sampling unit is configured to acquire a first sampling clock and a second sampling clock, and determine a first frequency control word according to the first sampling clock and the second sampling clock; wherein the first frequency control word is used to indicate a relationship between the first sampling clock and the second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule;

[0016] The sending unit is configured to generate a clock signal according to the first input clock, and send the clock signal to a receiving side; wherein the clock signal at least carries the first frequency control word.

[0017] The receiving unit is configured to receive the clock signal and determine the first input clock and the first frequency control word according to the clock signal.

[0018] The restoring unit is configured to determine the second input clock according to the first input clock and the first frequency control word.

[0019] According to another embodiment of the present application, a clock sending method applied to a sending side is further provided, and the method comprises:

[0020] inputting a first input clock and a second input clock;

[0021] obtaining a first sampling clock according to the first input clock, obtaining a second sampling clock according to the second input clock, and determining a first frequency control word according to the first sampling clock and the second sampling clock, wherein the first frequency control word is used to indicate the relationship between the first sampling clock and the second sampling clock;

[0022] generating a clock signal according to the first input clock, and sending the clock signal to a receiving side, wherein the clock signal at least carries the first frequency control word.

[0023] According to another embodiment of the present application, a clock receiving method applied to a receiving side is further provided, and the method comprises:

[0024] receiving a clock signal sent by a sending side, wherein the clock signal is generated according to a first input clock of the sending side, the clock signal at least carries a first frequency control word, the first frequency control word is used to indicate the relationship between a first sampling clock and a second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by a second input clock of the sending side according to the preset rule;

[0025] determining the first input clock and the first frequency control word according to the clock signal;

[0026] determining the second input clock according to the first input clock and the first frequency control word.

[0027] According to another embodiment of the present application, a computer readable storage medium is further provided, and the computer readable storage medium stores a computer program, wherein the computer program is set to execute the steps in any of the above method embodiments when running.

[0028] According to another embodiment of the present application, an electronic device is also provided, comprising a memory and a processor, the memory has a computer program stored therein, and the processor is configured to execute the computer program to perform the steps in any of the above method embodiments.

[0029] According to the embodiment of the present application, since the clock can be sent at the sending end, for the first input clock and the second input clock to be sent input by the input unit, the first sampling clock determined by the first input clock according to the preset rule and the second sampling clock determined by the second input clock according to the preset rule are obtained by the sampling unit, and the first frequency control word for indicating the relationship between the first sampling clock and the second sampling clock is determined according to the first sampling clock and the second sampling clock; further, the clock signal carrying the first frequency control word is generated by the sending unit according to the first input clock, and the clock signal is sent to the receiving side; in this way, the clock sending device in the embodiment of the present application can send the first input clock and the second input clock at the same time, and there is no limitation on whether the first input clock and the second input clock are homologous. Therefore, the embodiment of the present application can solve the problem that the clock line layout is too complex and difficult to implement in the clock distribution process of the communication device in the related art, so as to achieve the effect of significantly simplifying the layout of the clock line in the clock distribution process, thereby reducing the cost in the backboard manufacturing. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a connection diagram of clock distribution provided according to the related art;

[0031] Figure 2 is a function diagram of the clock sending device provided according to the embodiment of the present application (one);

[0032] Figure 3 is a function diagram of the clock sending device provided according to the embodiment of the present application (two);

[0033] Figure 4 is a function diagram of the clock sending device provided according to the embodiment of the present application (three);

[0034] Figure 5 is a function diagram of the clock sending device provided according to the embodiment of the present application (four);

[0035] Figure 6 is a function diagram of the clock sending device provided according to the embodiment of the present application (five);

[0036] Figure 7 is a function diagram of the clock sending device provided according to the embodiment of the present application (six);

[0037] Figure 8This is a functional schematic diagram (a) of a clock receiving device provided according to an embodiment of the present invention;

[0038] Figure 9 This is a functional schematic diagram (II) of a clock receiving device provided according to an embodiment of the present invention;

[0039] Figure 10 This is a functional schematic diagram (III) of a clock receiving device provided according to an embodiment of the present invention;

[0040] Figure 11 This is a functional schematic diagram (IV) of a clock receiving device provided according to an embodiment of the present invention;

[0041] Figure 12 This is a clock network topology diagram provided according to an exemplary embodiment of the present invention;

[0042] Figure 13 This is an internal implementation topology diagram (I) of a clock network provided according to an embodiment of the present invention;

[0043] Figure 14 This is a framing diagram provided according to an exemplary embodiment of the present invention;

[0044] Figure 15 This is a schematic diagram of PWM encoding based on duty cycle modulation according to an exemplary embodiment of the present invention;

[0045] Figure 16 This is a schematic diagram of PWM encoding based on Manchester encoding according to an exemplary embodiment of the present invention;

[0046] Figure 17 This is a diagram (II) illustrating the internal implementation topology of a clock network according to an embodiment of the present invention.

[0047] Figure 18 This is a functional schematic diagram of a clock transmission system provided according to an embodiment of the present invention;

[0048] Figure 19 This is a flowchart of a clock transmission method provided according to an embodiment of the present invention;

[0049] Figure 20 This is a flowchart of a clock transmission system provided according to an embodiment of the present invention. Detailed Implementation

[0050] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.

[0051] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0052] To further illustrate the clock transmitting device and method, and the clock receiving device and method in the embodiments of the present invention, the application scenarios of the clock transmitting device and method, and the clock receiving device in the embodiments of the present invention are described below:

[0053] Figure 1 It is a connection diagram based on the clock distribution provided by relevant technologies, such as Figure 1 As shown, in related technologies, clock lines corresponding to non-same-source clocks need to be connected and transmitted in a point-to-point manner. That is, non-same-source clocks each occupy a fixed clock line. The transmitting module transmits the clock to the receiving module of the clock board or service board through uplink or downlink, so that the receiving module can lock and recover the corresponding non-same-source clocks respectively.

[0054] In the aforementioned circuit layout process, each clock signal from a different frequency source requires a fixed point-to-point physical transmission medium. Since clock signals from different frequency sources share a single physical link for transmission, when two or more clock lines are combined, the receiving module cannot lock onto any frequency source. Therefore, related technologies cannot achieve the transmission of non-same-source clocks on the same line. Consequently, non-same-source clocks require additional space on the printed circuit board (PCB) of the communication equipment's backplane, as well as space for connector pin assignments. This necessitates increasing traces, adding PCB layers, and increasing the number of connectors when laying clock lines from two or more frequency sources, making it difficult to implement such clock line layouts within the space of currently miniaturized backplanes.

[0055] To address this, embodiments of the present invention provide a clock transmitting device and method, and a clock receiving device and method, to enable the transmission of clocks from different frequency sources between the transmitting and receiving sides via the same clock line. The clock transmitting device and clock receiving device in these embodiments are respectively used on the transmitting and receiving sides during the clock distribution process in a communication device. The clock transmitting device and method, and clock receiving device and method in these embodiments of the present invention are described below:

[0056] This invention provides a clock transmitting device. Figure 2 This is a functional schematic diagram (I) of a clock transmitting device according to an embodiment of the present invention, as shown below. Figure 2 As shown, the apparatus in this embodiment of the invention includes:

[0057] Input unit 102 is configured to input a first input clock and a second input clock;

[0058] The sampling unit 104 is configured to acquire a first sampling clock and a second sampling clock, and determine a first frequency control word based on the first sampling clock and the second sampling clock; wherein, the first frequency control word is used to indicate the relationship between the first sampling clock and the second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule;

[0059] The transmitting unit 106 is configured to generate a clock signal according to a first input clock and transmit the clock signal to the receiving side; wherein the clock signal carries at least a first frequency control word.

[0060] In this embodiment of the invention, the input unit can be implemented by an input port. The first input clock and the second input clock input by the input unit can be from the same source or from different sources. In one example, the first input clock and the second input clock are from different sources. The following description uses the first input clock and the second input clock in this example.

[0061] After the first input clock and the second input clock are simultaneously input to the input unit of the clock transmitting unit, the first sampling clock and the second sampling clock can be determined from the first input clock and the second input clock according to a preset rule. It should be noted that the preset rule for the first input clock can be the same as or different from the preset rule for the second input clock. In one example, the first input clock can be frequency multiplied to obtain the first sampling clock, which is then transmitted to the sampling unit, while the second input clock can be directly transmitted to the sampling unit as the second sampling clock without any processing; alternatively, the first input clock and the second input clock can be frequency multiplied by different factors to obtain the first sampling clock and the second sampling clock. Figure 3 This is a functional schematic diagram (II) of a clock transmitting device according to an embodiment of the present invention, as shown below. Figure 3 As shown, the clock transmitting device in this embodiment of the invention may further include:

[0062] The frequency multiplier unit 108 is configured to multiply the first input clock by a preset first factor to obtain a first sampling clock; wherein the ratio of the clock frequencies of the first sampling clock and the second sampling clock is within a preset range.

[0063] It should be noted that the frequency multiplier unit multiplies the first input clock, ensuring that the ratio of the clock frequencies of the multiplied first input clock (i.e., the first sampling clock) to the second sampling clock is within a preset range. This allows for control over the sampling or confirmation time of the sampling unit during the confirmation process of the first frequency control word, thereby improving the processing efficiency of the clock transmitting device in this embodiment of the invention. Those skilled in the art can select the multiplication factor of the frequency multiplier unit based on the actual clock frequencies of the first and second input clocks, such as the first multiplication factor mentioned above; this invention does not limit this selection.

[0064] Optionally, the frequency multiplier unit 108 may further include:

[0065] The first frequency multiplication subunit 1082 is configured to multiply the first input clock by a preset second multiple to obtain a first transmission clock; wherein the first transmission clock is used by the transmission unit to generate a clock signal based on the first transmission clock.

[0066] The second frequency multiplication subunit 1084 is configured to multiply the first transmission clock by a preset third multiple to obtain the first sampling clock.

[0067] Through the first frequency multiplication subunit and the second frequency multiplication subunit, the first input clock can be multiplied by the first frequency multiplication subunit to obtain the first transmission clock, which is then sent to the transmission unit to generate a clock signal. At the same time, the first transmission clock is multiplied by the second frequency multiplication subunit to obtain the first sampling clock.

[0068] On the other hand, regarding the second input clock, if it is a low-frequency clock, such as 1001 Hz, 4002 Hz, or 8003 Hz, directly using this low-frequency second input clock as the second sampling clock would prevent effective judgment or counting of the low-frequency clock during sampling or confirmation by the sampling unit, thus causing certain errors. Therefore, the frequency multiplication unit in this embodiment may further include a third frequency multiplication unit 1086, configured to multiply the second input clock according to a preset fourth multiple to obtain the second sampling clock.

[0069] It should be noted that the frequency multiplication unit in the embodiments of the present invention, or its first frequency multiplication subunit, second frequency multiplication subunit, and third frequency multiplication subunit, can be implemented by frequency multiplication devices or methods such as pulse compensation gate, phase-locked loop, voltage-controlled oscillator (VCO) locked frequency divider, and the present invention does not limit this; those skilled in the art know the methods of frequency multiplication of a clock with a fixed frequency, and the embodiments of the present invention will not be described in detail here.

[0070] In this embodiment of the invention, the first frequency control word can indicate the relationship between the first sampling clock and the second sampling clock in various ways. In one example, the first frequency control word can indicate the ratio of the clock frequencies of the first sampling clock and the second sampling clock, or the difference between the clock frequencies of the first sampling clock and the second sampling clock. It should be noted that the above ratio or difference is only to more clearly illustrate the relationship between the first sampling clock and the second sampling clock indicated by the first frequency control word. Any parameter or mathematical relationship that can indicate the relationship between the first sampling clock and the second sampling clock can be used as the first frequency control word in this embodiment of the invention.

[0071] In the process of determining the first frequency control word, the sampling unit in this embodiment of the invention can determine the first frequency control word by sampling the clock frequency of the first sampling clock and the clock frequency of the second sampling clock respectively.

[0072] It should be noted that, in one example, the sampling unit in this embodiment of the invention can be implemented using a counter, that is, by counting the clock edges to sample the clock frequencies of the first sampling clock and the second sampling clock; in another example, the sampling unit in this embodiment of the invention can also be implemented using a frequency meter, that is, by directly measuring the sampling frequencies of the first sampling clock and the second sampling clock to sample the clock frequencies of the first sampling clock and the second sampling clock. The following description uses the above example of using a counter to count the clock edges to sample the clock frequencies of the first sampling clock and the second sampling clock.

[0073] Figure 4 This is a functional schematic diagram (III) of a clock transmitting device according to an embodiment of the present invention, as shown below. Figure 4 As shown, optionally, the sampling unit 104 includes:

[0074] The transmit accumulation subunit 1042 is configured to accumulate the clock edge of the first sampling clock;

[0075] Send decision subunit 1044, configured to make a decision on the clock edge of the second sampling clock;

[0076] The counting subunit 1046 is configured to count the clock edge of the second sampling clock according to the decision result of the sending decision subunit, and determine the count value of the clock edge of the second sampling clock when the count of the clock edge of the first sampling clock reaches a preset value, so as to obtain the first frequency control word.

[0077] like Figure 4 In the sampling unit shown, a first sampling clock is sent to a transmit-accumulate subunit to accumulate the clock edges of the first sampling clock, typically the rising edge. Simultaneously, a second sampling clock is sent to a transmit-decision subunit to determine the clock edges of the second sampling clock, typically the rising edge. Based on the determination result, a counting subunit can be instructed to count the clock edges of the second sampling clock. When the accumulation result of the clock edges of the first sampling clock by the transmit-accumulate subunit reaches a preset threshold, the counting subunit can be latched and cleared. The current count value of the clock edges of the second sampling clock in the latched state constitutes the first frequency control word in this embodiment of the invention. The cleared counter then restarts counting the clock edges of the second sampling clock.

[0078] In the above sampling unit, the transmission accumulation subunit can be composed of an accumulator, for example, 2 N An accumulator; the transmit decision subunit can be composed of a decision unit, and the counting subunit can be composed of a counter. In one example, the transmit accumulator subunit is set to 2. N Taking the accumulator as an example: Set the first sampling clock to 1000000080 Hz, and the second sampling clock to 10000004 Hz. N If the value of N in the accumulator is 32, then the working process of the above sampling unit is as follows:

[0079] 2 N The accumulator increments the number of rising edges of the 1000000080Hz clock corresponding to the first sampling clock. Simultaneously, the decision unit determines the number of rising edges of the 10000004Hz clock corresponding to the second sampling clock. The counter then counts the rising edges of the second sampling clock based on the determination result. When 2... N After the accumulator accumulates to the power of 2^32 rising edges, the counter latches the number of rising edges of the current second sampling clock. For example, 2 N After the accumulator accumulates the first sampling clock to 4294967296 (2^32) rising edges, the counter latches the second sampling clock with 42949687 rising edges. This 42949687 is the first frequency control word for the second sampling clock.

[0080] It should be noted that since the above counter can only record integers, that is, the first frequency control word obtained is an integer value, it has a certain error. Figure 5 This is a functional schematic diagram (four) of a clock transmitting device provided according to an embodiment of the present invention, as shown below. Figure 5 As shown, to address potential errors in the first frequency control word, the clock transmission unit in this embodiment of the invention may further include:

[0081] The filtering unit 110 is configured to filter the first frequency control word according to a preset filtering method and send the filtered first frequency control word to the transmitting unit so that the transmitting unit can carry the filtered first frequency control word in the clock signal.

[0082] It should be noted that the filtering unit described above can have multiple preset filtering methods. In one example, the filtering unit can use mean filtering as the filtering method, while in another example, it can use moving average filtering. For any filtering method, the sampling unit needs to provide multiple sets of data, i.e., multiple first frequency control words. The filtering process of the first frequency control word is explained below using mean filtering:

[0083] The sampling unit repeats the following operation to obtain multiple first frequency control words: determining the first frequency control word based on the first sampling clock and the second sampling clock. Specifically, in the example above, based on 2... N An example of a sampling unit for an accumulator and counter is given, where the counter is in 2... N The accumulator accumulates 2 rising edges of the first sampling clock. N At time 1, the counter latches and clears to zero, and outputs the first frequency control word (denoted as K1); after the counter is cleared, 2 N The accumulator continues to increment the count of rising edges of the first sampling clock, while the counter restarts counting the rising edges of the second sampling circuit. N The accumulator accumulates the number of rising edges of the first sampling clock again, reaching 2. N At each interval, the counter latches and clears to zero, and outputs the first frequency control word (denoted as K2); this process repeats, meaning the counter reaches 2... N The accumulator accumulates 2 rising edges of the first sampling clock. N Each time, a frequency control word (denoted as K1, K2...K) can be output. M (where M is a positive integer greater than 1).

[0084] The counter outputs K1, K2...K M Then, the filtering unit can use K1, K2...K... M If the mean value is used as the first frequency control word after filtering (denoted as K), then K should satisfy (K1, K2...K). M ) / M.

[0085] The filtered first frequency control word output by the above-mentioned filtering unit can be a non-integer, and it can also converge and stabilize the jitter that may exist in the first frequency control word output by a certain sampling unit. Therefore, the filtered first frequency control word can effectively reduce the error.

[0086] After outputting the first frequency control word, the transmitting unit in this embodiment can carry the first frequency control word in a clock signal generated based on the first input clock, and transmit it to the receiving side via the clock line. The transmitting unit may include a transmitting port for connecting to the clock line. Figure 6 This is a functional schematic diagram (V) of a clock transmitting device provided according to an embodiment of the present invention, as shown below. Figure 6 As shown, the transmitting unit 106 in this embodiment of the invention may further include:

[0087] The pulse width modulation (PWM) encoding subunit 1062 is configured to encode the first input clock to generate a clock signal and to enclose the first frequency control word in the clock signal; wherein the clock frequency of the clock signal is the clock frequency of the first input clock.

[0088] In this embodiment of the invention, the PWM encoding unit can modulate the first frequency control word into a clock signal based on a PWM wave based on a first input clock and send it to the receiving side. It should be noted that the modulation process of the PWM wave can be duty cycle modulation, Manchester encoding, 8B / 10B encoding, 64B / 66B encoding, etc., and this invention does not limit it.

[0089] The aforementioned PWM encoding subunit can employ a Direct Digital Synthesis (DDS) signal generator, a Digitally Controlled Oscillator (DCO), a Digital Phase Locked Loop (DPLL), a microcontroller, a Field Programmable Gate Array (FPGA), or other devices with encoding capabilities. Alternatively, it can employ an Integrated Circuit (IC) or a System-on-a-Chip (SOC). The aforementioned PWM encoding subunit is composed of one or more of these devices; that is, any device capable of encoding and synthesizing the first input clock into a PWM wave carrying a first frequency control word can constitute the PWM encoding subunit in this embodiment of the invention.

[0090] It should be noted that in the above example, when the clock transmitting device in the embodiment of the present invention includes a frequency multiplier unit and a filtering unit, the clock signal also needs to carry the frequency multiplication factor of the frequency multiplier unit, such as the first multiple, the second multiple, the third multiple and the fourth multiple, etc., and the first frequency control word carried in the clock signal is the filtered frequency control word.

[0091] The clock transmitting device in this embodiment of the invention can, when transmitting a clock at the transmitting end, obtain a first sampled clock determined by the first input clock according to a preset rule and a second sampled clock determined by the second input clock according to a preset rule through a sampling unit for the first input clock and the second input clock input by the input unit. A first frequency control word indicating the relationship between the first and second sampled clocks is then determined based on the first and second sampled clocks. Furthermore, the transmitting unit generates a clock signal carrying the first frequency control word based on the first input clock and transmits the clock signal to the receiving side. Therefore, the clock transmitting device in this embodiment of the invention can simultaneously transmit the first and second input clocks, without restriction on whether the first and second input clocks originate from the same source. Thus, this embodiment of the invention can solve the problem in related technologies where the clock line layout in the clock distribution process of communication devices is too complex and difficult to implement, thereby significantly simplifying the clock line layout in the clock distribution process and reducing the cost in backplane manufacturing.

[0092] It should be noted that the clock transmitting device in this embodiment of the invention enables the transmission of non-same-origin clocks on the same clock line. Therefore, when multiple non-same-origin clocks are involved in the clock distribution process of a communication device, clock transmission can be achieved through only one clock line, without the need to lay out a separate clock line for each non-same-origin clock. This significantly reduces the number of clock lines during clock distribution, thereby significantly improving the utilization of backplane routing space. Furthermore, with the clock transmitting device in this embodiment of the invention, the backplane does not require expansion of traces, PCB layers, or connectors during manufacturing to accommodate excessive lines, thus significantly improving the manufacturing cost of the backplane.

[0093] It should be noted that there can be multiple second input clocks in the embodiments of the present invention, that is, the clock transmitting device in the embodiments of the present invention can transmit any number of non-same-source clocks simultaneously. Figure 7 This is a functional schematic diagram (six) of a clock transmitting device provided according to an embodiment of the present invention, as shown below. Figure 7 In the example shown, the clock transmitting device in this embodiment of the invention can simultaneously transmit three non-same-source clocks to the receiving side. The following is a description of this example:

[0094] Optionally, the clock transmitting device in this embodiment of the invention further includes:

[0095] Input unit 102 is configured to input a first input clock, a second input clock, and a third input clock;

[0096] Sampling unit 104 includes a first sampling subunit 1104 and a second sampling subunit 2104; wherein,

[0097] The first sampling subunit 1104 is configured to determine a first frequency control word based on a first sampling clock and a second sampling clock.

[0098] The second sampling subunit 2014 is configured to determine a second frequency control word based on the first sampling clock and the third sampling clock; wherein, the second frequency control word is used to indicate the relationship between the first sampling clock and the third sampling clock, and the third sampling clock is determined by the third input clock according to a preset rule;

[0099] The transmitting unit 106 is configured to generate a clock signal based on a first input clock and transmit the clock signal to the receiving side; wherein the clock signal carries at least a first frequency control word and a second frequency control word.

[0100] It should be noted that the working process of the first sampling subunit and the second sampling subunit mentioned above is the same as the description of the working process of the sampling unit mentioned above, so it will not be repeated here.

[0101] Therefore, in the process of transmitting multiple non-same-source clocks, the clock transmitting device in this embodiment of the invention can set up a corresponding sampling module for any non-same-source clock, and use the first input clock as a reference to determine the corresponding frequency control word of the non-same-source clock.

[0102] It should be noted that the first input clock in the embodiments of the present invention can be any one of a plurality of non-same-source clocks that the transmitting side needs to send to the receiving side, or it can be the reference clock of the transmitting side. In one example, the first input clock can be the local clock of the transmitting side, and in another example, the first input clock can be an external reference clock introduced by the transmitting side.

[0103] This invention also provides a clock receiving device. Figure 8 This is a functional schematic diagram (I) of a clock receiving device according to an embodiment of the present invention, as shown below. Figure 8 As shown, the apparatus in this embodiment of the invention includes:

[0104] The receiving unit 202 is configured to receive a clock signal transmitted by the transmitting side; wherein the clock signal is generated based on a first input clock of the transmitting side, and the clock signal carries at least a first frequency control word, the first frequency control word being used to indicate the relationship between a first sampling clock and a second sampling clock, the first sampling clock being determined by the first input clock according to a preset rule, and the second sampling clock being determined by the second input clock of the transmitting side according to a preset rule; the receiving unit 202 is further configured to determine the first input clock and the first frequency control word based on the clock signal;

[0105] Recovery unit 204 is configured to determine the second input clock based on the first input clock and the first frequency control word.

[0106] It should be noted that the clock signal received by the clock receiving device in this embodiment of the invention is the clock signal transmitted by the clock transmitting device in the above-described embodiment of the invention. Therefore, the generation or preprocessing of the clock signal by the clock transmitting device corresponds to the description in the above-described clock transmitting device and will not be repeated here.

[0107] The receiving unit in this embodiment of the invention is used to receive a clock signal transmitted by the transmitting side through a clock line. The receiving unit may include a receiving port for connecting to the clock line. Figure 9 This is a functional schematic diagram (II) of the receiving unit provided according to an embodiment of the present invention, as shown below. Figure 9 As shown, the receiving unit may further include a PWM decoding subunit 2022, configured to decode the clock signal to recover the first input clock and extract the first frequency control word carried in the clock signal.

[0108] It should be noted that when the clock signal in the embodiment of the present invention is a PWM wave synthesized by the transmitting side through the PWM encoding subunit, the receiving unit can decode and recover the received PWM wave through the above-mentioned PWM decoding unit, thereby obtaining the corresponding first input clock and first frequency control word in the PWM wave.

[0109] Similar to the PWM encoding unit, the aforementioned PWM decoding subunit can employ a DDS signal generator, DCO, DPLL, microcontroller, field-programmable gate array processor, etc., which have decoding capabilities, or it can employ a dedicated IC, SOC, etc. The aforementioned PWM decoding subunit is composed of one or more of the above-mentioned devices; that is, any device capable of decoding a clock signal to obtain a first input clock and a first frequency control word can constitute the PWM decoding subunit in this embodiment of the invention.

[0110] In this embodiment of the invention, the first input signal and the first frequency control word obtained by the receiving unit can be sent to the recovery unit to recover the second input signal. The recovery unit 204 can also be configured to...

[0111] A first sampling clock is obtained based on a first input clock, and multiple first phase addresses are determined based on the first sampling clock and a first frequency control word; wherein, the first phase address is used to indicate the phase of the second sampling clock;

[0112] A second sampling clock is determined based on multiple first phase addresses, and a second input clock is determined based on the second sampling clock.

[0113] It should be noted that if the clock transmitting device for transmitting clock signals includes the aforementioned frequency multiplication unit, that is, the first sampling clock or the second sampling clock is obtained by multiplying the first input clock or the second input clock according to a preset frequency multiplication factor, then the receiving unit, in addition to obtaining the first input clock and the first frequency control word, can also obtain the frequency multiplication factor carried by the clock signal, such as the first multiplication factor, the second multiplication factor, the third multiplication factor, the fourth multiplication factor, etc. in the aforementioned frequency multiplication unit. In the clock receiving device of this embodiment, after the receiving unit obtains the first input clock, it also needs to use the same frequency multiplication factor as in the clock transmitting device to multiply the first input clock, and then the recovery unit further recovers the second input clock. In one example, the clock transmitting device multiplies the first input clock by 40 times using a frequency multiplier to obtain the first sampling clock. The second input clock is used directly as the second sampling clock without any processing. In this case, after the receiving unit obtains the first input clock, the first frequency control word, and the frequency multiplication factor, the clock receiving device in this embodiment of the invention needs to multiply the first input clock by 40 times and send the multiplied first input clock to the recovery unit for recovery. In another example, the clock transmitting device multiplies the first input clock by 40 times using the first frequency multiplication subunit in the frequency multiplication unit to obtain the first transmitting clock, and multiplies the first transmitting clock by 20 times using the second frequency multiplication subunit to obtain the first sampling clock. Simultaneously, the second input clock is multiplied by 20 times using the third frequency multiplication subunit to obtain the second sampling clock. In this case, the receiving unit directly obtains the first transmitting signal, the first frequency control word, and the frequency multiplication factors corresponding to the first, second, and third frequency multiplication subunits from the clock signal. In this embodiment, the clock receiving device needs to multiply the first transmitting signal by 20 times and send the multiplied first transmitting clock to the recovery unit for recovery. Simultaneously, the first transmitting clock needs to be divided by 1 / 40 times to recover the first input clock, and the clock directly output by the recovery unit needs to be divided by 1 / 20 times to recover the second input clock. The process of multiplying the first input clock according to the processing method of the clock transmitting device is the process of obtaining the first sampling clock according to the first input clock in the recovery unit.

[0114] It should be noted that the first phase address mentioned above is used to indicate the phase address of the corresponding waveform for the second sampling clock. In one example, the second sampling clock is a square wave or a sine wave.

[0115] It should be noted that after the second sampling clock is determined, the second input clock can be recovered from the second sampling clock according to the aforementioned rule of determining the second sampling clock based on the second input clock.

[0116] The following optional example illustrates the process of determining the first phase address. Figure 10 This is a functional schematic diagram (III) of a clock receiving device according to an embodiment of the present invention, as shown below. Figure 10 The recovery unit 204 includes:

[0117] The receiving accumulation subunit 2042 is configured to accumulate the first frequency control word according to the clock edge of the first sampling clock, and obtain multiple first phase addresses according to each accumulation result of the first frequency control word;

[0118] The query subunit 2044 is configured to obtain the waveform of the second sampling clock based on a plurality of first phase addresses and a preset mapping relationship; wherein, the mapping relationship is used to indicate the mapping relationship between the first phase address and the preset waveform parameters of the second sampling clock; the query subunit is further configured to determine the clock frequency of the second sampling clock based on the waveform of the second sampling clock.

[0119] like Figure 10 In the recovery unit shown, after the first sampling clock is sent to the receiving and accumulating subunit, the receiving and accumulating subunit can accumulate the first frequency control word according to the clock edge of the first sampling clock to obtain the first phase address. During the accumulation process, when the first sampling clock reaches its clock frequency once, the receiving and accumulating subunit can accumulate the first frequency control word once according to the clock edge of the first sampling clock in that case. Each accumulation result is a first phase address. In this way, the receiving and accumulating subunit can obtain multiple first phase addresses.

[0120] In the above recovery unit, the receiving accumulation subunit can be composed of an accumulator, for example, 2 N Accumulator. In one example, the receiving accumulator subunit is 2. N Taking the accumulator as an example: If the first sampling clock is set to 1 GHz and the first frequency control word is 42949672, then the operation of the recovery unit is as follows:

[0121] 2 N The accumulator accumulates data based on the rising edge of the first sampling clock, i.e., each time a rising edge of 1 GHz is reached. N The accumulator increments the automatic first frequency control word once. After each increment, a first phase address is obtained, which is the result of the current increment. When the incremented result exceeds a preset threshold, such as 2^32, then 2... N The accumulator clears the accumulated result to zero and restarts the accumulation process; the above accumulation process is as follows:

[0122] First time reaching 1GHz, 2 NThe accumulator accumulation result is 42949672*1=42949672, and the corresponding first phase address is 42949672;

[0123] The second time it reached 1GHz, 2 N The accumulator accumulation result is 42949672*2=85899344, and the corresponding first phase address is 85899344;

[0124] The third time it reached 1GHz, 2 N The accumulator accumulation result is 42949672*3=128849016, and the corresponding first phase address is 128849016;

[0125] ...

[0126] The 100th time it reached 1GHz, 2 N The accumulator accumulation result is 42949672*100=4294967200, and the corresponding first phase address is 4294967200;

[0127] The 101st time it reaches 1 GHz, since 42949672 * 101 = 4337916872, this value is greater than 2^32, therefore 2 N The accumulator is cleared and accumulation restarts, 2 N The accumulator accumulation result is 42949672*1=42949672, and the corresponding first phase address is 42949672;

[0128] The 102nd time it reached 1GHz, 2 N The accumulator accumulation result is 42949672*2=85899344, and the corresponding first phase address is 85899344.

[0129] For each accumulated first phase address, the query subunit can query the waveform parameters of the second sampling clock corresponding to the current first phase address. The waveform parameters indicate the parameters of a periodic waveform, and include at least one of the following: square wave output level, sine wave output level, triangle wave output level, sawtooth wave output level, and pulse output level (i.e., the output level corresponding to a waveform with a duty cycle not of 50%). In one example, the waveform parameter of the second sampling clock can be a sine wave output level; in another example, the waveform parameter of the second sampling clock can be a square wave output level. The following explanation focuses on the waveform parameters of the second sampling clock.

[0130] Taking the example above where the waveform parameter is a square wave output level, the query subunit 2044 is also configured to make a decision on multiple first phase addresses according to the mapping relationship, and obtain the waveform of the second sampling clock according to the decision result.

[0131] In the example above, since the waveform parameter is a square wave output level value, the query sub-unit can be directly constructed by a decision unit. That is, it determines whether to output a high or low level based on the first phase address corresponding to the accumulation result of the receiving accumulation sub-unit according to preset rules. The mapping relationship can be predetermined. For example, if the first phase address is less than or equal to 2^31, a low level is output; if the first phase address is greater than 2^31 (i.e., 2^32), a high level is output. Repeating this process, multiple square wave output level values ​​corresponding to the first phase addresses can be output through the decision of the query sub-unit, thus obtaining the waveform of the second sampling clock. Based on the square wave waveform of the second sampling clock, the clock frequency of the second sampling clock can be determined.

[0132] The above example illustrates the case where the waveform parameters are sinusoidal output levels. Figure 11 This is a functional schematic diagram (four) of a clock receiving device provided according to an embodiment of the present invention, as shown below. Figure 11 The query subunit 2044 is further configured to obtain multiple sine wave output level values ​​corresponding to the multiple first phase addresses based on the multiple first phase addresses and the preset mapping relationship;

[0133] The recovery unit 204 also includes a digital to analog converter (DAC) subunit 2046, which is configured to perform digital-to-analog conversion on multiple sine wave output level values ​​to obtain the waveform of the second sampling clock.

[0134] In the above example, since the waveform parameter is a sine wave output level value, the query sub-unit needs to include a preset local read-only memory (ROM) table. This local ROM table records the above mapping relationship, that is, the mapping relationship between the first phase address and the corresponding sine wave output level value. Taking the first phase address as 0, 1, 2, 3 as an example, the above local ROM table stores the mapping relationship between the first phase addresses 0, 1, 2, 3 and the sine wave output level value. This mapping relationship can be:

[0135] 0~0V;

[0136] 1~1.65V;

[0137] 2~3.3V;

[0138] 3~1.65V;

[0139] Therefore, when the first phase address corresponding to the accumulation result of the receiving accumulator subunit is 0, the query subunit can determine the sine wave output level value corresponding to the first phase address as 0V through the mapping relationship recorded in the local ROM table. Furthermore, the DAC subunit can output a 0V level through digital-to-analog conversion. By repeating this process, multiple sine wave output level values ​​corresponding to the first phase addresses can be continuously output by the query subunit and the DAC subunit, thereby obtaining the waveform of the second sampling clock. Based on the sine wave waveform of the second sampling clock, the clock frequency of the second sampling clock can be determined.

[0140] It should be noted that when there are more than two input clocks in the clock transmitting device, the clock receiving device in this embodiment of the invention can also recover them one by one. In an optional embodiment, the clock signal also carries a second frequency control word, which is used to indicate the relationship between the first sampling clock and the third sampling clock. The third sampling clock is determined by the third input clock on the transmitting side according to a preset rule. In the clock receiving device in this embodiment of the invention, the receiving unit can determine the second frequency control word based on the clock signal while determining the first input clock and the first frequency control word; and, referring to the above-described method of recovering the second input clock, determine the third input clock based on the first input clock and the second frequency control word.

[0141] To further illustrate the clock transmitting device, clock receiving device, and clock transmission system in the embodiments of the present invention, several exemplary embodiments are described below. It should be noted that in the following exemplary embodiments, the transmitting module is used to indicate the clock transmitting device in the embodiments of the present invention, and the receiving module is used to indicate the clock receiving module in the embodiments of the present invention. The transmitting module and the receiving module together constitute the clock transmission system in the embodiments of the present invention.

[0142] Exemplary Example 1

[0143] Figure 12 This is a topology diagram of a clock network provided according to an exemplary embodiment of the present invention. The network structure used in the clock distribution process in this exemplary embodiment is as follows: Figure 12 As shown. Figure 13 This is an internal implementation topology diagram (I) of a clock network according to an embodiment of the present invention. In this exemplary embodiment, the internal implementation of the transmitting module and the receiving module during the clock distribution process is as follows: Figure 13 As shown. Figure 13 As shown in this exemplary embodiment, the clock to be transmitted input to the transmitting module includes four different non-similar clocks of varying frequencies. These four non-similar clocks are, in order: the fundamental frequency clock F... clk=25000002hz, Non-same-source clock A=33000018hz, Non-same-source clock B=10000004hz, Non-same-source clock C=19440009hz.

[0144] Basic frequency clock F clk After the 25000002Hz clock enters the transmission module, it goes directly to the frequency multiplier unit for frequency multiplication. In this exemplary embodiment, the frequency multiplier unit multiplies the clock by 40, making the base frequency clock 40*F. clk =1000000080Hz, the base frequency clock after frequency multiplication is provided to sampling unit A, sampling unit B, and sampling unit C, and is used for edge decision and 2 N The accumulator provides the base clock. The other path of the base frequency clock is F. clk =25000002hz without frequency multiplication is sent to the PWM encoding unit to provide the basic clock for the PWM encoding unit.

[0145] A non-similar clock A = 33000018 Hz enters sampling unit A. The non-similar clock A is edge-sampled and judged by a 40x multiplier-based fundamental frequency clock, and the result is fed into a counter for incrementing. The 40x multiplier-based fundamental frequency clock 40*F... clk =1000000080hz input 2 N An accumulator performs accumulation in a single-accumulation manner, and the accumulated number equals 2. N Then, the subsequent counter is latched and cleared; correspondingly, 2 N The accumulator is also cleared to zero, and the accumulation starts again. 2 N The accumulator accumulates to 2 each time. N At that moment, the value latched by the counter is the frequency control word K of the non-same-source clock A at the current moment. A The calculation formula is as follows:

[0146]

[0147] In the above formula, C freqA C is used to indicate the clock frequency of non-homogeneous clocks A. x*fclk The clock frequency used to indicate the base frequency clock after frequency multiplication.

[0148] For example, when N=32, the accumulator will accumulate to 4,294,967,296 clock cycles of 40 times the base frequency, at which point the counter will latch the frequency control word |K. A |≈141733987, passed to the calculation and filtering unit.

[0149] Similarly, a non-similar clock B = 10000004 Hz enters sampling unit B. The 40x multiplied base frequency clock provided by the frequency multiplier performs edge sampling on non-similar clock B, and the result is fed into a counter for incrementing. The 40x multiplied base frequency clock provided by the frequency multiplier is 40*F. clk =1000000080hz input 2 N An accumulator performs accumulation in a single-accumulation manner, and the accumulated number equals 2. N Then, the subsequent counter is latched and cleared; correspondingly, 2 N The accumulator is also cleared to zero, and the accumulation starts again. 2 N The accumulator accumulates to 2 each time. N At that moment, the value latched by the counter is the frequency control word K of the non-same-source clock B at the current moment. B The calculation formula is as follows:

[0150]

[0151] In the above formula, C freqB Used to indicate the clock frequency of non-same-source clock B, C x*fclk The clock frequency used to indicate the base frequency clock after frequency multiplication.

[0152] For example, when N=32, the accumulator will accumulate to 4,294,967,296 clock cycles of 40 times the base frequency, at which point the counter will latch the frequency control word |K. B |≈42949687, passed to the calculation and filtering unit.

[0153] Similarly, a non-similar clock C = 19440009 Hz enters the sampling unit C. The non-similar clock C is edge-sampled and judged by a 40x multiplier-provided base frequency clock, and the result is fed into a counter for incrementing. The 40x multiplier-provided base frequency clock 40*F clk =1000000080hz input 2 N An accumulator performs accumulation in a single-accumulation manner, and the accumulated number equals 2. N Then, the subsequent counter is latched and cleared; correspondingly, 2 N The accumulator is also cleared to zero, and the accumulation starts again. 2 N The accumulator accumulates to 2 each time. N At that moment, the value latched by the counter is the frequency control word K of the non-same-source clock C at the current moment. C Its calculation formula is

[0154]

[0155] In the above formula, C freqC The clock frequency used to indicate non-homogeneous clocks C, C x*fclkThe clock frequency used to indicate the base frequency clock after frequency multiplication.

[0156] For example, when N=32, the accumulator will accumulate to 4,294,967,296 clock cycles of 40 times the base frequency, at which point the counter will latch the frequency control word |K. C |≈83494196, passed to the calculation and filtering unit.

[0157] It should be noted that this exemplary embodiment is Example 2. N The accumulator N=32 is for better illustration of the frequency synthesis method. N can also be any number such as 8, 16, 32, 48, 64. The larger the value of N within a certain threshold range, the longer the time for determining the frequency control word and the more accurate the precision. Those skilled in the art can adjust the value of N according to the error precision of the system. The embodiments of the present invention do not limit the value of N.

[0158] Due to the above K A K B K C The real-time frequency control words obtained by sampling units A, B, and C are integer frequency control words with the decimal part removed. If they are directly passed to recovery units A, B, and C of the receiving module, the recovered clocks are 33000018.0608 Hz, 10000004.0689 Hz, and 19440008.9512 Hz, respectively. The frequency errors between these clocks and the original non-same-source clocks A, B, and C are +1.8 ppb, +6.9 ppb, and -2.5 ppb, respectively.

[0159] To further reduce errors and jitter, the real-time frequency control word K obtained from sampling unit A, sampling unit B, and sampling unit C will be used. A K B K C The data is sent to the computational filtering unit. The computational filtering unit processes the real-time frequency control word K. A K B K C Perform filtering.

[0160] This exemplary embodiment uses mean filtering as the filtering method, and its algorithm is as follows:

[0161]

[0162] The algorithm described above instructs the sampling unit to perform M cumulative counts on the frequency control word, and then use the average of the M frequency control words to achieve filtering. The filtering accuracy depends on the value of M.

[0163] After calculation using the above mean-averaging algorithm, the three non-homogeneous frequency control words with one decimal place after filtering are, in order: K A =141733986.7, K B =42949686.7, K C =83494196.2.

[0164] It should be noted that the mean filtering algorithm in this exemplary embodiment is only an example, and those skilled in the art can sample other filtering methods for filtering. This embodiment of the invention is not limited in this respect.

[0165] Filtered post-frequency control word K A '、K B '、K C 'Sent to the PWM encoding unit, the PWM encoding unit is based on the base frequency clock F clk The three frequency control words K are framed together. A '、K B '、K C Each is encapsulated into the encoded and synthesized PWM carrier. Figure 14 This is a framing diagram provided according to an exemplary embodiment of the present invention, such as... Figure 14 As shown, the framing method is as follows: 0001 represents the frame header of frequency control word A, followed by frequency control word A; 0010 represents the frame header of frequency control word B, followed by frequency control word B; 0011 represents the frame header of frequency control word C, followed by frequency control word C; 1111 represents the frame header of configuration information D, followed by basic information of the accompanying frame, such as the frequency multiplication unit multiplier information, the sampling unit sampling number information, etc., and finally followed by a CRC check frame.

[0166] It should be noted that the frame header can be placed before or after the frequency control word. Similarly, the frame headers 0001-1111 exemplified in this exemplary embodiment are for better illustration of the framing method and do not specifically refer to the specific content, frame header capacity, or whether it is encrypted. Those skilled in the art can modify and encrypt the frame header according to the implementation method of business requirements. The embodiments of this invention do not limit the position, form, and content of the frame header.

[0167] The PWM encoding unit can perform encoding synthesis by modulating the duty cycle. Figure 15 This is a schematic diagram of PWM encoding based on duty cycle modulation according to an exemplary embodiment of the present invention, as shown below. Figure 15 As shown, 80% duty cycle represents 0 and 20% duty cycle represents 1. Alternatively, 30% duty cycle can represent 0 and 70% duty cycle can represent 1. This embodiment of the invention is not limited to this.

[0168] It should be noted that the duty cycle modulation used in this exemplary embodiment is for the purpose of better illustrating the frequency synthesis method. Those skilled in the art can use other encoding methods. Figure 16 This is a schematic diagram of PWM encoding based on Manchester encoding according to an exemplary embodiment of the present invention, that is, this exemplary embodiment can adopt as follows: Figure 16 The Manchester encoding shown is used for PWM encoding. In addition, 8B / 10B encoding, etc., can also be used to encode the PWM wave. This invention does not limit this.

[0169] After the PWM encoding unit completes the encoding and synthesis, it finally encodes frequency control word A, frequency control word B, and frequency control word C into the PWM carrier. The synthesized PWM carrier transmits the signal to the receiving module through a single transmission link. It should be noted that the single transmission link can be a PCB trace, connector, optical fiber, differential line, or a link using a mixture of physical media, etc., and this invention is not limited to this.

[0170] After receiving the PWM carrier transmitted from a single transmission link, the receiving module sends it to the PWM decoding unit for decoding. By recognizing the frame header, it decodes the frequency control word K. A '、K B '、K C 'and the multiplier of the frequency multiplier, K A '、K B '、K C The clock frequency is fed into recovery units A, B, and C; the frequency multiplier is fed into the frequency multiplier unit of the receiving module; the PWM decoding unit physically recovers the PWM carrier fundamental frequency clock F. clk =25000002hz, output receiving module, as the first receiving clock output; in addition, inside the receiving module, the fundamental frequency clock is led to the frequency multiplier unit.

[0171] After the frequency multiplier unit of the receiving module is set to the same multiplier unit as that of the transmitting module, the input fundamental frequency clock F is... clk Multiply by 40 to get 40*F clk =1000000080Hz. 40 times the base clock frequency is sent to recovery units A, B, and C as the reference clock for each recovery unit.

[0172] Filtered non-same-source clock frequency control word K A 'Entering recovery unit A, the reference clock is provided by a 40-fold multiplier base frequency clock, with K...' A The accumulator is used as an addend, and its maximum value is 2. N According to the following algorithm:

[0173]

[0174] In this exemplary embodiment, N=32, the local ROM table address is calculated by continuously accumulating the values. The local ROM table stores square waves with addresses corresponding to 1 and 0. When the required output clock duty cycle is 50%, the data corresponding to the first half of the addresses in the ROM is '1', and the data corresponding to the second half of the addresses is '0'.

[0175] The actual non-homogeneous clock frequency obtained by looking up the address output by the accumulator is F. reqA =33000017.990991225466132164001465 Hz, which differs from the original non-source clock A's corresponding 33000018 Hz by 0.272 ppb.

[0176] Similarly, the filtered non-same-source clock frequency control word K B 'Entering recovery unit B, the reference clock is provided by a 40-fold frequency base clock supplied by the frequency multiplier, with K...' B The accumulator is used as an addend, and its maximum value is 2. N According to the following algorithm:

[0177]

[0178] In this exemplary embodiment, N=32, the local ROM table address is calculated by continuously accumulating the values. The local ROM table stores square waves with addresses corresponding to 1 and 0. When the required output clock duty cycle is 50%, the data corresponding to the first half of the addresses in the ROM is '1', and the data corresponding to the second half of the addresses is '0'.

[0179] The actual non-homogeneous clock frequency obtained by looking up the address output by the accumulator is F. reqB =10000003.999093299731612205505371hz, which differs from the original non-source clock B's corresponding 10000004hz by 0.09ppb.

[0180] Similarly, the filtered non-same-source clock frequency control word K C 'Entering recovery unit B, the reference clock is provided by a 40-fold frequency base clock supplied by the frequency multiplier, with K...' C The accumulator is used as an addend, and its maximum value is 2. N According to the following algorithm:

[0181]

[0182] In this exemplary embodiment, N=32, the local ROM table address is calculated by continuously accumulating the values. The local ROM table stores square waves with addresses corresponding to 1 and 0. When the required output clock duty cycle is 50%, the data corresponding to the first half of the addresses in the ROM is '1', and the data corresponding to the second half of the addresses is '0'.

[0183] The actual non-homogeneous clock frequency obtained by looking up the address output by the accumulator is F. reqC =19440008.99780907109379768371582hz, which differs from the original non-co-source clock C corresponding to 19440009hz by 0.11ppb.

[0184] It should be noted that the 50% duty cycle described above is for better illustration of the local ROM table address determination process. Those skilled in the art can adjust the proportion and order of '1' and '0' corresponding to the address according to the actual duty cycle requirements, and this invention does not limit this. Similarly, the above-mentioned error is only the magnitude of the error between the recovered non-same-source clock and the original non-same-source clock of the transmitting module in this exemplary embodiment. In actual implementation, the above-mentioned error depends on factors such as the value of N in the accumulator, the filtering capability of the calculation filter, and the depth of the local ROM table. For example, the error can decrease as the value of N increases, or it can decrease as the filtering capability of the calculation filter improves. Those skilled in the art can control or adjust the error according to actual needs.

[0185] Exemplary Example 2

[0186] Figure 17 This is an internal implementation topology diagram (II) of the clock network provided according to an embodiment of the present invention, such as... Figure 17 As shown in this exemplary embodiment, the clock to be transmitted input to the transmitting module includes four different non-similar clocks of varying frequencies. These four non-similar clocks are, in order: the fundamental frequency clock F... clk =10000.0008hz, Non-same-source clock A =8001hz, Non-same-source clock B =10000004hz, Non-same-source clock C =6480003hz.

[0187] Basic frequency clock F clk After the frequency of 10000.0008 Hz enters the transmission module, it first enters the first-stage frequency multiplication unit D for frequency multiplication. After multiplying by 2500, d*F is obtained. clk = 25000002 Hz. One channel of d*F after the first multiplier. clk The signal is then fed to the second-stage frequency multiplier unit for frequency multiplication. This exemplary embodiment uses a 40x frequency multiplication, making the base frequency clock 40*d*F. clk=1000000080Hz, provided to sampling unit A, sampling unit B, and sampling unit C, for edge detection and 2 N The accumulator provides the base clock. The other path of the base frequency clock, d*F, after a first-stage frequency multiplication, is... clk =25000002hz without frequency multiplication is sent to the PWM encoding unit to provide the basic clock for the PWM encoding unit.

[0188] After a non-homogeneous clock A = 8001 Hz enters the transmitting module, it first enters frequency multiplication unit A, where it is multiplied by 2000 to increase the clock frequency to 1600-2000 Hz, before being sent to sampling unit A. In sampling unit A, the 40-fold multiplied base frequency clock provided by the frequency multiplier performs edge sampling and decision-making, and the result is fed into a counter for incrementing. The 40-fold multiplied base frequency clock provided by the frequency multiplier is 40 * d * F. clk =1000000080hz input 2 N An accumulator performs accumulation in a single-accumulation manner, and the accumulated number equals 2. N Then, the subsequent counter is latched and cleared; correspondingly, 2 N The accumulator is also cleared to zero, and the accumulation starts again. 2 N The accumulator accumulates to 2 each time. N At that moment, the value latched by the counter is the frequency control word K of the non-same-source clock A at the current moment. A The calculation formula is as follows:

[0189]

[0190] In the above formula, C freqA C is used to indicate the clock frequency of non-homogeneous clocks A. x*fclk The clock frequency used to indicate the base frequency clock after frequency multiplication.

[0191] For example, when N=32, the accumulator will accumulate to 4,294,967,296 clock cycles of 40 times the base frequency, at which point the counter will latch the frequency control word |K. A |≈68728061, passed to the calculation and filtering unit.

[0192] Similarly, a non-same-source clock B = 10000004 Hz enters frequency multiplication unit B for single frequency multiplication, maintaining the clock frequency at 10000004 Hz, before being sent to sampling unit B. In sampling unit B, the 40x multiplied base frequency clock provided by the frequency multiplier undergoes edge sampling and decision-making, and the result is fed into a counter for incrementing. The 40x multiplied base frequency clock provided by the frequency multiplier is 40*d*F. clk =1000000080hz input 2 N An accumulator performs accumulation in a single-accumulation manner, and the accumulated number equals 2. NThen, the subsequent counter is latched and cleared; correspondingly, 2 N The accumulator is also cleared to zero, and the accumulation starts again. 2 N The accumulator accumulates to 2 each time. N At that moment, the value latched by the counter is the frequency control word K of the non-same-source clock B at the current moment. B The calculation formula is as follows:

[0193]

[0194] In the above formula, C freqB Used to indicate the clock frequency of non-same-source clock B, C x*fclk The clock frequency used to indicate the base frequency clock after frequency multiplication.

[0195] For example, when N=32, the accumulator will accumulate to 4,294,967,296 clock cycles of 40 times the base frequency, at which point the counter will latch the frequency control word |K. B |≈42949687, passed to the calculation and filtering unit.

[0196] Similarly, a non-same-source clock C = 6480003 Hz enters the frequency multiplier unit C, undergoes a 3x multiplication, resulting in a clock frequency C = 19440009 Hz, and is then sent to the sampling unit C. In the sampling unit C, the 40x multiplied base frequency clock provided by the frequency multiplier performs edge sampling and decision-making, and the result is fed into a counter for incrementing. The 40x multiplied base frequency clock provided by the frequency multiplier is 40*d*F. clk =1000000080hz input 2 N An accumulator performs an accumulation; when the accumulated number equals 2... N Then, the subsequent counter is latched and cleared; correspondingly, 2 N The accumulator is also cleared to zero, and the accumulation starts again. 2 N The accumulator accumulates to 2 each time. N At that moment, the value latched by the counter is the frequency control word K of the non-same-source clock C at the current moment. C Its calculation formula is

[0197]

[0198] In the above formula, C freqC The clock frequency used to indicate non-homogeneous clocks C, C x*fclk The clock frequency used to indicate the base frequency clock after frequency multiplication.

[0199] For example, when N=32, the accumulator will accumulate to 4,294,967,296 clock cycles of 40 times the base frequency, at which point the counter will latch the frequency control word |K. C |≈83494196, passed to the calculation and filtering unit.

[0200] It should be noted that this exemplary embodiment is Example 2. N The accumulator N=32 is for better illustration of the frequency synthesis method. N can also be any number such as 8, 16, 32, 48, 64. The larger the value of N within a certain threshold range, the longer the time for determining the frequency control word and the more accurate the precision. Those skilled in the art can adjust the value of N according to the error precision of the system. The embodiments of the present invention do not limit the value of N.

[0201] Due to the above K A K B K C The real-time frequency control words obtained from sampling units A, B, and C are integer frequency control words with the decimal part removed. To further reduce errors and jitter, the real-time frequency control words obtained from sampling units A, B, and C are further reduced to frequency control word K. A K B K C The data is sent to the computational filtering unit. The computational filtering unit processes the real-time frequency control word K. A K B K C Perform filtering.

[0202] This exemplary embodiment uses mean filtering as the filtering method, and its algorithm is as follows:

[0203]

[0204] The algorithm described above instructs the sampling unit to perform M cumulative counts on the frequency control word, and then use the average of the M frequency control words to achieve filtering. The filtering accuracy depends on the value of M.

[0205] After calculation using the above mean-averaging algorithm, the three non-homogeneous frequency control words with one decimal place after filtering are, in order: K A =68728061.2, K B =42949686.7, K C =83494196.2.

[0206] Filtered post-frequency control word K A '、K B '、K C 'Sent to the PWM encoding unit, the PWM encoding unit is based on the base frequency clock F clk The three frequency control words K are framed together. A '、K B '、K C Each element is enveloped into the encoded and synthesized PWM carrier. For framing methods, please refer to [reference needed]. Figure 14The framing method is as follows: 0001 represents the frame header of frequency control word A, followed by frequency control word A; 0010 represents the frame header of frequency control word B, followed by frequency control word B; 0011 represents the frame header of frequency control word C, followed by frequency control word C; 1111 represents the frame header of configuration information D, followed by basic information of the accompanying frame, such as the frequency multiplication unit multiplier information, the sampling unit sampling number information, etc., and finally followed by a CRC check frame.

[0207] It should be noted that the frame header can be placed before or after the frequency control word. Similarly, the frame headers 0001-1111 exemplified in this exemplary embodiment are for better illustration of the framing method and do not specifically refer to the specific content, frame header capacity, or whether it is encrypted. Those skilled in the art can modify and encrypt the frame header according to the implementation method of business requirements. The embodiments of this invention do not limit the position, form, and content of the frame header.

[0208] The encoding synthesis method of the PWM encoding unit can be achieved through, for example... Figure 5 The duty cycle modulation shown can be represented by 80% duty cycle for 0 and 20% duty cycle for 1, or it can be represented by 30% duty cycle for 0 and 70% duty cycle for 1. This embodiment of the invention is not limited to this.

[0209] It should be noted that the duty cycle modulation used in this exemplary embodiment is for the purpose of better illustrating the frequency synthesis method. Those skilled in the art can encode the PWM wave using other encoding forms, such as Manchester encoding, 8B / 10B encoding, etc., and this invention does not limit this.

[0210] After the PWM encoding unit completes the encoding and synthesis, it finally encodes frequency control word A, frequency control word B, and frequency control word C into the PWM carrier. The synthesized PWM carrier transmits the signal to the receiving module through a single transmission link. It should be noted that the single transmission link can be a PCB trace, connector, optical fiber, differential line, or a link using a mixture of physical media, etc., and this invention is not limited to this.

[0211] After receiving the PWM carrier transmitted from a single transmission link, the receiving module sends it to the PWM decoding unit for decoding. By recognizing the frame header, it decodes the frequency control word K. A '、K B '、K C 'and the multiples of each harmonic unit, K A '、K B '、K C The frequency multipliers are distributed to recovery units A, B, and C, and each received multiplier is written into the frequency divider unit following the recovery unit; d*Fclk The frequency multiplier is fed into the frequency multiplier unit of the receiving module; the PWM decoding unit physically recovers the PWM carrier fundamental frequency clock d*F. clk =25000002 Hz, after being divided by a frequency divider D unit by 2500, F is obtained. clk =10000.0008Hz, output receiving module, as the first receiving clock output; also inside the receiving module, d*F clk The multiplier unit is derived from the base frequency clock.

[0212] After the frequency multiplier unit of the receiving module is set to the same multiplier unit as that of the transmitting module, the input fundamental frequency clock d*F is... clk Multiply by 40 to get 40*d*F clk =1000000080Hz. 40 times the base clock frequency is sent to recovery units A, B, and C as the reference clock for each recovery unit.

[0213] Filtered non-same-source clock frequency control word K A 'Entering recovery unit A, the reference clock is provided by a 40-fold multiplier base frequency clock, with K...' A The accumulator is used as an addend, and its maximum value is 2. N According to the following algorithm:

[0214]

[0215] In this embodiment, with N=32, the local ROM table address is obtained by continuously accumulating the values. The local ROM table stores square waves with addresses corresponding to 1 and 0. When the required output clock duty cycle is 50%, the data corresponding to the first half of the addresses in the ROM is '1', and the data corresponding to the second half of the addresses is '0'.

[0216] The actual non-homogeneous clock frequency obtained by looking up the address output by the accumulator is F. reqA =16002000.006438441574573516845703hz, then after passing through the next stage frequency divider, which matches the original transmitting module's frequency multiplication factor of 2000, the frequency obtained by multiplying by 2000 is 8001.0000032192207872867584228515hz, which differs from the original non-same-source clock A's corresponding 8001hz by 0.402ppb.

[0217] Similarly, the filtered non-same-source clock frequency control word K B 'Entering recovery unit B, the reference clock is provided by a 40-fold frequency base clock supplied by the frequency multiplier, with K...' B The accumulator is used as an addend, and its maximum value is 2.N According to the following algorithm:

[0218]

[0219] In this embodiment, with N=32, the local ROM table address is obtained by continuously accumulating the values. The local ROM table stores square waves with addresses corresponding to 1 and 0. When the required output clock duty cycle is 50%, the data corresponding to the first half of the addresses in the ROM is '1', and the data corresponding to the second half of the addresses is '0'.

[0220] The actual non-homogeneous clock frequency obtained by looking up the address output by the accumulator is F. reqB =10000003.999093299731612205505371hz. Since the frequency multiplication factor in the original transmitting module is a single multiplication factor, the subsequent frequency divider is not adjusted. The resulting non-same-source frequency differs from the original non-same-source clock B corresponding to 10000004hz by 0.09ppb.

[0221] Similarly, the filtered non-same-source clock frequency control word K C 'Entering recovery unit B, the reference clock is provided by a 40-fold frequency base clock supplied by the frequency multiplier, with K...' C The accumulator is used as an addend, and its maximum value is 2. N According to the following algorithm:

[0222]

[0223] In this embodiment, with N=32, the local ROM table address is obtained by continuously accumulating the values. The local ROM table stores square waves with addresses corresponding to 1 and 0. When the required output clock duty cycle is 50%, the data corresponding to the first half of the addresses in the ROM is '1', and the data corresponding to the second half of the addresses is '0'.

[0224] The actual non-homogeneous clock frequency obtained by looking up the address output by the accumulator is F. reqC =19440008.99780907109379768371582hz, then after passing through the next stage frequency divider, which matches the original transmitting module's frequency multiplication factor of 3, the frequency obtained by 3-fold frequency division is 6480002.9992696903645992279052734hz, which differs from the original non-same-source clock C's corresponding 6480003hz by 0.11ppb.

[0225] It should be noted that the 50% duty cycle described above is for better illustration of the local ROM table address determination process. Those skilled in the art can adjust the proportion and order of '1' and '0' corresponding to the address according to the actual duty cycle requirements, and this invention does not limit this. Similarly, the above-mentioned error is only the magnitude of the error between the recovered non-same-source clock and the original non-same-source clock of the transmitting module in this exemplary embodiment. In actual implementation, the above-mentioned error depends on factors such as the value of N in the accumulator, the filtering capability of the calculation filter, and the depth of the local ROM table. For example, the error can decrease as the value of N increases, or it can decrease as the filtering capability of the calculation filter improves. Those skilled in the art can control or adjust the error according to actual needs.

[0226] This invention also provides a clock transmission system. Figure 18 This is a functional schematic diagram of a clock transmission system provided according to an embodiment of the present invention, such as... Figure 18 As shown, the clock transmission system in this embodiment of the invention includes:

[0227] Input unit 302 is configured to input a first input clock and a second input clock;

[0228] The sampling unit 304 is configured to acquire a first sampling clock and a second sampling clock, and determine a first frequency control word based on the first sampling clock and the second sampling clock; wherein, the first frequency control word is used to indicate the relationship between the first sampling clock and the second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule;

[0229] The transmitting unit 306 is configured to generate a clock signal based on a first input clock and transmit the clock signal to the receiving side; wherein the clock signal carries at least a first frequency control word.

[0230] The receiving unit 308 is configured to receive a clock signal and determine a first input clock and a first frequency control word based on the clock signal.

[0231] Recovery unit 310 is configured to determine the second input clock based on the first input clock and the first frequency control word.

[0232] It should be noted that the input unit, sampling unit, and transmitting unit in the clock transmission system of this embodiment constitute the corresponding units in the clock transmitting device of this embodiment. Correspondingly, the receiving unit and recovery unit in the clock transmission system of this embodiment are the corresponding units in the clock receiving device of this embodiment. Therefore, the clock transmission system in this embodiment can be composed of the clock transmitting device and the clock receiving device of this embodiment. The other optional embodiments and technical implementations of the transmitting side of the clock transmission system in this embodiment correspond to the clock transmitting device in this embodiment, and the other optional embodiments and technical implementations of the receiving side of the clock transmission system in this embodiment correspond to the clock receiving device in this embodiment. They will not be described again here.

[0233] In an optional embodiment, the clock transmission system of the present invention further includes:

[0234] Line unit 312 is disposed between the transmitting unit and the receiving unit, and the line unit is configured to transmit clock signals to the receiving unit through the same line.

[0235] It should be noted that the line unit in the embodiments of the present invention constitutes the physical link between the transmitting unit and the receiving unit in the clock transmission system. The physical link indicated by the line unit is one, so that multiple input clocks on the transmitting side can be transmitted to the receiving side through the same line.

[0236] This invention also provides a clock transmission method, applied to the transmitting side. Figure 19 This is a flowchart of a clock transmission method provided according to an embodiment of the present invention, such as... Figure 19 As shown, the clock transmission method in this embodiment of the invention includes:

[0237] S102, input the first input clock and the second input clock;

[0238] S104, obtain a first sampling clock based on a first input clock, obtain a second sampling clock based on a second input clock, and determine a first frequency control word based on the first sampling clock and the second sampling clock; wherein, the first frequency control word is used to indicate the relationship between the first sampling clock and the second sampling clock;

[0239] S106, a clock signal is generated according to the first input clock, and the clock signal is sent to the receiving side; wherein the clock signal carries at least a first frequency control word.

[0240] It should be noted that the other optional embodiments and technical implementations of the clock transmission method in the embodiments of the present invention correspond to the clock transmission device in the embodiments of the present invention, and will not be described again here.

[0241] In an alternative embodiment, the first frequency control word is used to indicate at least one of the following: the ratio of the clock frequencies of the first sampling clock to the second sampling clock, and the difference between the clock frequencies of the first sampling clock and the second sampling clock.

[0242] In an optional embodiment, step S104 above, determining the first frequency control word based on the first sampling clock and the second sampling clock, includes:

[0243] The clock frequencies of the first sampling clock and the second sampling clock are sampled respectively to determine the first frequency control word.

[0244] In an optional embodiment, the above-mentioned sampling of the clock frequency of the first sampling clock and the clock frequency of the second sampling clock to determine the first frequency control word includes:

[0245] Accumulate the clock edges of the first sampling clock;

[0246] The clock edges of the second sampling clock are determined, and the clock edges of the second sampling clock are counted according to the determination results;

[0247] When the clock edge of the first sampling clock accumulates to a preset value, the count value of the clock edge of the second sampling clock is determined to obtain the first frequency control word.

[0248] In an optional embodiment, step S104 above, obtaining the first sampling clock based on the first input clock, includes:

[0249] The first input clock is multiplied by a preset first factor to obtain the first sampling clock; wherein the ratio of the clock frequencies of the first sampling clock and the second sampling clock is within a preset range.

[0250] In an optional embodiment, the above-mentioned multiplication of the first input clock according to a preset first multiple to obtain the first sampling clock further includes:

[0251] The first input clock is multiplied by a preset second multiple to obtain the first transmission clock; wherein the first transmission clock is used to generate a clock signal;

[0252] The first transmitting clock is multiplied by a preset third multiple to obtain the first sampling clock.

[0253] In an optional embodiment, step S104 above, obtaining the second sampling clock based on the second input clock, includes:

[0254] The second input clock is multiplied by a preset fourth factor to obtain the second sampling clock.

[0255] In an optional embodiment, the clock signal further carries a first multiple, a second multiple, a third multiple, and a fourth multiple.

[0256] In an optional embodiment, step S106 above, which involves generating a clock signal based on the first input clock and sending the clock signal to the receiving side, further includes:

[0257] The first frequency control word is filtered according to a preset filtering method;

[0258] A clock signal is generated based on the first input clock and sent to the receiving side; wherein the clock signal carries a filtered first frequency control word.

[0259] In an optional embodiment, step S104 above, determining the first frequency control word based on the first sampling clock and the second sampling clock, further includes:

[0260] Repeat the following operations to obtain multiple first frequency control words: determine the first frequency control word based on the first sampling clock and the second sampling clock;

[0261] The first frequency control word is filtered according to a preset filtering method, including: taking the average of multiple first frequency control words as the filtered first frequency control word.

[0262] In an optional embodiment, step S106 above, generating a clock signal based on the first input clock, includes:

[0263] The first input clock is encoded to generate a clock signal, and the first frequency control word is enveloped in the clock signal; wherein the clock frequency of the clock signal is the clock frequency of the first input clock.

[0264] In an optional embodiment, the clock transmission method of the present invention further includes:

[0265] Input the first input clock, the second input clock, and the third input clock;

[0266] The first frequency control word is determined based on the first sampling clock and the second sampling clock;

[0267] The third sampling clock is obtained based on the third input clock, and the second frequency control word is determined based on the first sampling clock and the third sampling clock; wherein, the second frequency control word is used to indicate the relationship between the first sampling clock and the third sampling clock;

[0268] A clock signal is generated based on the first input clock and sent to the receiving side; wherein the clock signal carries at least a first frequency control word and a second frequency control word.

[0269] In an alternative embodiment, the frequency source of the first input clock is different from the frequency source of the second input clock.

[0270] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0271] This invention also provides a clock receiving method, applied to the receiving side. Figure 20 This is a flowchart of a clock receiving method provided according to an embodiment of the present invention, such as... Figure 20 As shown, the clock receiving method in this embodiment of the invention includes:

[0272] S202, Receive clock signal transmitted by the transmitting side; wherein, the clock signal is generated based on the first input clock of the transmitting side, and the clock signal carries at least a first frequency control word, the first frequency control word is used to indicate the relationship between the first sampling clock and the second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock of the transmitting side according to a preset rule;

[0273] S204, determine the first input clock and the first frequency control word based on the clock signal;

[0274] S206, determine the second input clock based on the first input clock and the first frequency control word.

[0275] It should be noted that the other optional embodiments and technical implementations of the clock receiving method in the embodiments of the present invention correspond to the clock receiving device in the embodiments of the present invention, and will not be described again here.

[0276] In an optional embodiment, step S206 above, determining the second input clock based on the first input clock and the first frequency control word, includes:

[0277] A first sampling clock is obtained based on a first input clock, and multiple first phase addresses are determined based on the first sampling clock and a first frequency control word; wherein, the first phase address is used to indicate the phase of the second sampling clock;

[0278] The second sampling clock is determined based on multiple first phase addresses, and the second input clock is determined based on the second sampling clock.

[0279] In an optional embodiment, the above-described method of obtaining a first sampling clock based on a first input clock and determining a plurality of first phase addresses based on the first sampling clock and a first frequency control word includes:

[0280] The first frequency control word is accumulated according to the clock edge of the first sampling clock, and multiple first phase addresses are obtained based on each accumulation result of the first frequency control word.

[0281] The second sampling clock is determined based on multiple first phase addresses, including:

[0282] The waveform of the second sampling clock is obtained by mapping multiple first phase addresses to a preset mapping relationship; wherein the mapping relationship is used to indicate the mapping relationship between the first phase address and the preset waveform parameters of the second sampling clock.

[0283] The clock frequency of the second sampling clock is determined based on the waveform of the second sampling clock.

[0284] In an optional embodiment, the waveform parameters are used to indicate parameters of a periodic waveform, wherein the waveform parameters include at least one of the following: square wave output level value, sine wave output level value, triangle wave output level value, sawtooth wave output level value, and pulse output level value.

[0285] In an optional embodiment, when the waveform parameters are square wave output level values, the waveform of the second sampling clock is obtained according to a preset mapping relationship between multiple first phase addresses, including:

[0286] The first phase addresses are determined according to the mapping relationship, and the waveform of the second sampling clock is obtained based on the determination result.

[0287] In an optional embodiment, when the above waveform parameters are sinusoidal output level values, the waveform of the second sampling clock is obtained according to a preset mapping relationship between multiple first phase addresses, including:

[0288] Based on multiple first phase addresses and mapping relationships, multiple sine wave output level values ​​corresponding to the multiple first phase addresses are obtained respectively;

[0289] Multiple sine wave output level values ​​are digitally converted to analog values ​​to obtain the waveform of the second sampling clock.

[0290] In an optional embodiment, the clock signal further carries a second frequency control word, which is used to indicate the relationship between the first sampling clock and the third sampling clock. The third sampling clock is determined by the third input clock on the transmitting side according to a preset rule.

[0291] In the above-described case, the clock receiving method in this embodiment of the invention further includes:

[0292] The second frequency control word is determined based on the clock signal;

[0293] The third input clock is determined based on the first input clock and the second frequency control word.

[0294] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0295] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when executed.

[0296] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0297] Embodiments of the present invention also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0298] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0299] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0300] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0301] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A clock transmitting device, characterized in that, The device includes: The input unit is configured to input a first input clock and a second input clock; The sampling unit is configured to acquire a first sampling clock and a second sampling clock, and determine a first frequency control word based on the first sampling clock and the second sampling clock; wherein the first frequency control word is used to indicate the relationship between the first sampling clock and the second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule; The sampling unit includes: a transmission accumulation subunit configured to accumulate the clock edge of the first sampling clock; a transmission decision subunit configured to make a decision on the clock edge of the second sampling clock; and a counting subunit configured to count the clock edge of the second sampling clock according to the decision result of the transmission decision subunit, and determine the count value of the clock edge of the second sampling clock when the clock edge of the first sampling clock is accumulated to a preset value, so as to obtain the first frequency control word. The transmitting unit is configured to generate a clock signal based on the first input clock and transmit the clock signal to the receiving side; wherein the clock signal carries at least the first frequency control word.

2. The apparatus according to claim 1, characterized in that, The first frequency control word is used to indicate at least one of the following: the ratio of the clock frequencies of the first sampling clock to the second sampling clock, and the difference between the clock frequencies of the first sampling clock and the second sampling clock.

3. The apparatus according to claim 2, characterized in that, The sampling unit is also configured to, The clock frequency of the first sampling clock and the clock frequency of the second sampling clock are sampled respectively to determine the first frequency control word.

4. The apparatus according to any one of claims 1 to 3, characterized in that, The device further includes: The frequency multiplier unit is configured to multiply the first input clock by a preset first factor to obtain the first sampling clock; wherein the ratio of the clock frequencies of the first sampling clock and the second sampling clock is within a preset range.

5. The apparatus according to claim 4, characterized in that, The frequency multiplier unit includes: The first frequency multiplication subunit is configured to multiply the first input clock by a preset second factor to obtain a first transmission clock; wherein the first transmission clock is used by the transmission unit to generate the clock signal based on the first transmission clock; The second frequency multiplication subunit is configured to multiply the first transmission clock by a preset third multiple to obtain the first sampling clock.

6. The apparatus according to claim 5, characterized in that, The frequency multiplier unit also includes: The third frequency multiplication subunit is configured to multiply the second input clock by a preset fourth multiple to obtain the second sampling clock.

7. The apparatus according to claim 6, characterized in that, The clock signal also carries the first multiple, and / or the second multiple, and / or the third multiple, and / or the fourth multiple.

8. The apparatus according to any one of claims 1 to 3, characterized in that, The device further includes: The filtering unit is configured to filter the first frequency control word according to a preset filtering method, and send the filtered first frequency control word to the transmitting unit so that the transmitting unit can carry the filtered first frequency control word in the clock signal.

9. The apparatus according to claim 8, characterized in that, The sampling unit is also configured to, Repeat the following operations to obtain a plurality of the first frequency control words: determine the first frequency control word based on the first sampling clock and the second sampling clock; The filtering unit is further configured to use the average of the plurality of first frequency control words as the filtered first frequency control word.

10. The apparatus according to claim 1, characterized in that, The transmitting unit further includes: The PWM encoding subunit is configured to encode the first input clock to generate the clock signal and to enclose the first frequency control word in the clock signal; wherein the clock frequency of the clock signal is the clock frequency of the first input clock.

11. The apparatus according to claim 1, characterized in that, The input unit is further configured to input the first input clock, the second input clock, and the third input clock; The sampling unit includes a first sampling subunit and a second sampling subunit; wherein, The first sampling subunit is configured to determine the first frequency control word based on the first sampling clock and the second sampling clock; The second sampling subunit is configured to determine a second frequency control word based on the first sampling clock and the third sampling clock; wherein the second frequency control word is used to indicate the relationship between the first sampling clock and the third sampling clock, and the third sampling clock is determined by the third input clock according to a preset rule; The transmitting unit is further configured to generate the clock signal according to the first input clock and transmit the clock signal to the receiving side; wherein the clock signal carries at least the first frequency control word and the second frequency control word.

12. The apparatus according to claim 1, characterized in that, The frequency source of the first input clock is different from the frequency source of the second input clock.

13. A clock receiving device, characterized in that, The device includes: A receiving unit is configured to receive a clock signal transmitted by a transmitting side; wherein the clock signal is generated based on a first input clock of the transmitting side, and the clock signal carries at least a first frequency control word, the first frequency control word being used to indicate the relationship between a first sampling clock and a second sampling clock, the first sampling clock being determined by the first input clock according to a preset rule, and the second sampling clock being determined by the second input clock of the transmitting side according to a preset rule; the receiving unit is further configured to determine the first input clock and the first frequency control word based on the clock signal; The recovery unit is configured to determine the second input clock based on the first input clock and the first frequency control word; The recovery unit includes: a receiving and accumulating subunit configured to accumulate the first frequency control word according to the clock edge of the first sampling clock, and obtain a plurality of first phase addresses according to each accumulation result of the first frequency control word; and a query subunit configured to obtain the waveform of the second sampling clock according to the plurality of first phase addresses and a preset mapping relationship; wherein the mapping relationship is used to indicate the mapping relationship between the first phase addresses and preset waveform parameters of the second sampling clock; the query subunit is further configured to determine the clock frequency of the second sampling clock according to the waveform of the second sampling clock.

14. The apparatus according to claim 13, characterized in that, The recovery unit is further configured to, The first sampling clock is obtained based on the first input clock, and a plurality of first phase addresses are determined based on the first sampling clock and the first frequency control word; wherein, the first phase address is used to indicate the phase of the second sampling clock; The second sampling clock is determined based on the plurality of first phase addresses, and the second input clock is determined based on the second sampling clock.

15. The apparatus according to claim 14, characterized in that, The waveform parameters are used to indicate parameters of a periodic waveform, wherein the waveform parameters include at least one of the following: square wave output level value; sine wave output level value; triangle wave output level value; sawtooth wave output level value; pulse output level value.

16. The apparatus according to claim 15, characterized in that, When the waveform parameter is the square wave output level value, the query subunit is further configured to, The plurality of first phase addresses are determined according to the mapping relationship, and the waveform of the second sampling clock is obtained according to the determination result.

17. The apparatus according to claim 15, characterized in that, When the waveform parameter is the sine wave output level value, the query subunit is further configured to obtain the multiple sine wave output level values ​​corresponding to the multiple first phase addresses according to the multiple first phase addresses and the mapping relationship; The recovery unit further includes a digital-to-analog converter (DAC) subunit, which is configured to perform digital-to-analog conversion on multiple sinusoidal output level values ​​to obtain the waveform of the second sampling clock.

18. The apparatus according to claim 13, characterized in that, The receiving unit further includes: The PWM decoding subunit is configured to decode the clock signal to recover the first input clock and extract the first frequency control word carried in the clock signal.

19. A clock transmission system, characterized in that, include: The input unit is configured to input a first input clock and a second input clock; The sampling unit is configured to acquire a first sampling clock and a second sampling clock, and determine a first frequency control word based on the first sampling clock and the second sampling clock; wherein the first frequency control word is used to indicate the relationship between the first sampling clock and the second sampling clock, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule; The transmitting unit is configured to generate a clock signal based on the first input clock and transmit the clock signal to the receiving side; wherein the clock signal carries at least the first frequency control word; The receiving unit is configured to receive the clock signal and determine the first input clock and the first frequency control word based on the clock signal. The recovery unit is configured to determine the second input clock based on the first input clock and the first frequency control word; A line unit is disposed between the transmitting unit and the receiving unit, and the line unit is configured to transmit the clock signal to the receiving unit through the same line.

20. A clock transmission method, characterized in that, Applied to the transmitting side, the method includes: Input the first input clock and the second input clock; A first sampling clock is obtained based on the first input clock, a second sampling clock is obtained based on the second input clock, and a first frequency control word is determined based on the first sampling clock and the second sampling clock; wherein, the first frequency control word is used to indicate the relationship between the first sampling clock and the second sampling clock; A clock signal is generated based on the first input clock, and the clock signal is sent to the receiving side; wherein the clock signal carries at least the first frequency control word; The method of sampling the clock frequency of the first sampling clock and the clock frequency of the second sampling clock to determine the first frequency control word includes: accumulating the clock edges of the first sampling clock; making a decision on the clock edges of the second sampling clock and counting the clock edges of the second sampling clock according to the decision result; and determining the count value of the clock edges of the second sampling clock when the clock edges of the first sampling clock accumulate to a preset value, so as to obtain the first frequency control word.

21. The method according to claim 20, characterized in that, The first frequency control word is used to indicate at least one of the following: the ratio of the clock frequencies of the first sampling clock to the second sampling clock, and the difference between the clock frequencies of the first sampling clock and the second sampling clock.

22. The method according to claim 21, characterized in that, The step of determining the first frequency control word based on the first sampling clock and the second sampling clock includes: The clock frequency of the first sampling clock and the clock frequency of the second sampling clock are sampled respectively to determine the first frequency control word.

23. The method according to any one of claims 20 to 22, characterized in that, The step of obtaining the first sampling clock based on the first input clock includes: The first input clock is multiplied by a preset first factor to obtain the first sampling clock; wherein the ratio of the clock frequencies of the first sampling clock and the second sampling clock is within a preset range.

24. The method according to claim 23, characterized in that, The step of multiplying the first input clock by a preset first factor to obtain the first sampling clock further includes: The first input clock is multiplied by a preset second multiple to obtain a first transmission clock; wherein the first transmission clock is used to generate the clock signal; The first transmitting clock is multiplied by a preset third factor to obtain the first sampling clock.

25. The method according to claim 24, characterized in that, The step of obtaining the second sampling clock based on the second input clock includes: The second input clock is multiplied by a preset fourth factor to obtain the second sampling clock.

26. The method according to claim 25, characterized in that, The clock signal also carries the first multiple, and / or the second multiple, and / or the third multiple, and / or the fourth multiple.

27. The method according to any one of claims 20 to 22, characterized in that, The step of generating a clock signal based on the first input clock and sending the clock signal to the receiving side further includes: The first frequency control word is filtered according to a preset filtering method; The clock signal is generated based on the first input clock and sent to the receiving side; wherein the clock signal carries the filtered first frequency control word.

28. The method according to claim 27, characterized in that, The step of determining the first frequency control word based on the first sampling clock and the second sampling clock further includes: Repeat the following operations to obtain a plurality of the first frequency control words: determine the first frequency control word based on the first sampling clock and the second sampling clock; The step of filtering the first frequency control word according to a preset filtering method includes: taking the average of multiple first frequency control words as the filtered first frequency control word.

29. The method according to claim 20, characterized in that, The step of generating a clock signal based on the first input clock includes: The first input clock is encoded to generate the clock signal, and the first frequency control word is enveloped in the clock signal; wherein the clock frequency of the clock signal is the clock frequency of the first input clock.

30. The method according to claim 20, characterized in that, The method further includes: Input the first input clock, the second input clock, and the third input clock; The first frequency control word is determined based on the first sampling clock and the second sampling clock; A third sampling clock is obtained based on the third input clock, and a second frequency control word is determined based on the first sampling clock and the third sampling clock; wherein, the second frequency control word is used to indicate the relationship between the first sampling clock and the third sampling clock; The clock signal is generated according to the first input clock and sent to the receiving side; wherein the clock signal carries at least the first frequency control word and the second frequency control word.

31. The method according to claim 20, characterized in that, The frequency source of the first input clock is different from the frequency source of the second input clock.

32. A clock receiving method, characterized in that, Applied to the receiving side, the method includes: The receiver receives a clock signal transmitted from the transmitting side; wherein the clock signal is generated based on a first input clock of the transmitting side, and the clock signal carries at least a first frequency control word, the first frequency control word being used to indicate the relationship between a first sampling clock and a second sampling clock, the first sampling clock being determined by the first input clock according to a preset rule, and the second sampling clock being determined by the second input clock of the transmitting side according to a preset rule; The first input clock and the first frequency control word are determined based on the clock signal; Determining the second input clock based on the first input clock and the first frequency control word includes: obtaining the first sampling clock based on the first input clock, and determining a plurality of first phase addresses based on the first sampling clock and the first frequency control word; wherein the first phase address is used to indicate the phase of the second sampling clock; determining the second sampling clock based on the plurality of first phase addresses, and determining the second input clock based on the second sampling clock.

33. The method according to claim 32, characterized in that, The step of obtaining the first sampling clock based on the first input clock and determining multiple first phase addresses based on the first sampling clock and the first frequency control word includes: The first frequency control word is accumulated according to the clock edge of the first sampling clock, and the plurality of first phase addresses are obtained according to each accumulation result of the first frequency control word. Determining the second sampling clock based on the plurality of first phase addresses includes: The waveform of the second sampling clock is obtained by mapping the plurality of first phase addresses to a preset mapping relationship; wherein the mapping relationship is used to indicate the mapping relationship between the first phase address and the preset waveform parameters of the second sampling clock; The clock frequency of the second sampling clock is determined based on the waveform of the second sampling clock.

34. The method according to claim 33, characterized in that, The waveform parameters are used to indicate parameters of a periodic waveform, wherein the waveform parameters include at least one of the following: square wave output level value; sine wave output level value; triangle wave output level value; sawtooth wave output level value; pulse output level value.

35. The method according to claim 34, characterized in that, When the waveform parameters are the square wave output level values, obtaining the waveform of the second sampling clock based on the plurality of first phase addresses and a preset mapping relationship includes: The plurality of first phase addresses are determined according to the mapping relationship, and the waveform of the second sampling clock is obtained according to the determination result.

36. The method according to claim 34, characterized in that, When the waveform parameters are the sine wave output level values, obtaining the waveform of the second sampling clock based on the plurality of first phase addresses and a preset mapping relationship includes: Based on the multiple first phase addresses and the mapping relationship, the multiple sine wave output level values ​​corresponding to the multiple first phase addresses are obtained respectively; The multiple sinusoidal output level values ​​are digitally converted to analog values ​​to obtain the waveform of the second sampling clock.

37. The method according to claim 34, characterized in that, The clock signal also carries a second frequency control word, which is used to indicate the relationship between the first sampling clock and the third sampling clock. The third sampling clock is determined by the third input clock on the transmitting side according to a preset rule. The method further includes: The second frequency control word is determined based on the clock signal; The third input clock is determined based on the first input clock and the second frequency control word.

38. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program is configured to perform the method of any one of claims 20 to 31, or the method of any one of claims 32 to 37, when executed.

39. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method according to any one of claims 20 to 31, or to perform the method according to any one of claims 32 to 37.

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