OIS Circuit, OIS Data Sharing Device, and Operating Method Thereof

Abstract

An optical image stabilization (OIS) circuit, including a first OIS circuit configured to operate as a serial peripheral interface (SPI) master relative to a single sensor, read sensor data from the single sensor, and store the read sensor data, and configured to transmit control codes in a second SPI slave operation mode before a first SPI slave operation mode and provide sensor data in the first SPI slave operation mode while operating as an SPI slave; and a second OIS circuit configured to operate as an SPI master relative to the first OIS circuit, read control codes from the first OIS circuit in a first SPI master operation mode, and store the control codes, and further configured to read and store sensor data in a second SPI master operation mode after the first SPI master operation mode.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10 - 2020 - 0069003, filed on Jun. 8, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] The following description relates to an optical image stabilization (OIS) circuit and an OIS data sharing device and an operation method thereof. Background Art

[0004] Generally, a camera module may include an OIS circuit, and the OIS circuit may detect hand - shake information and may move a lens or an image sensor in a direction opposite to the hand - shake, so that a clear image unaffected by hand - shake can be obtained even when the camera shakes.

[0005] A general OIS circuit may use sensor data received from a gyro sensor to implement stable operation of the camera module.

[0006] The OIS circuit may read sensor data from the gyro sensor by implementing a Serial Peripheral Interface Bus (SPI) / Inter - Integrated Circuit (I2C).

[0007] In addition, in a conventional OIS circuit, one gyro sensor is configured to be set up with the OIS circuit in a one - to - one manner. Thus, when gyro sensors are required, multiple driver circuits (driver ICs) may be connected to multiple gyro sensors in a one - to - one manner.

[0008] In an example, when two OIS circuits applied to two camera modules are used, two gyro sensors may be required.

[0009] Recently, as electronic devices become more multifunctional and the performance of electronic devices becomes more enhanced, electronic cameras (such as those installed in vehicles or smartphones) may include an increasing number of camera modules.

[0010] When multiple camera modules are installed in an electronic device and multiple gyro sensors are used, the production cost may increase.

[0011] To solve the above problems, a single gyro sensor may be used instead of multiple gyro sensors. However, in this example, some problems related to sensor data sharing may occur between multiple OIS circuits connected to the single gyro sensor. Summary of the Invention

[0012] The present invention content section is intended to introduce, in a brief form, a selection of inventive concepts, which will be further described in the following detailed implementation section. The purpose of the present invention content section is not to identify the key features or essential features of the claimed subject matter, nor to assist in determining the scope of the claimed subject matter by this means.

[0013] In general, an optical image stabilization (OIS) circuit includes: a first OIS circuit configured to operate as a serial peripheral interface (SPI) master relative to a single sensor, read sensor data from the single sensor, and store the read sensor data, and further configured to transmit a control code in a second SPI slave operation mode before a first SPI slave operation mode, and transmit the read sensor data in the first SPI slave operation mode while operating as an SPI slave; and a second OIS circuit configured to operate as an SPI master relative to the first OIS circuit, read the control code from the first OIS circuit in a first SPI master operation mode, and store the read control code, and further configured to read and store sensor data in a second SPI master operation mode after the first SPI master operation mode.

[0014] The first OIS circuit may include: a first SPI master configured to read sensor data from a single sensor; a first memory configured to store the read sensor data; a second memory configured to store the control code; a first SPI slave configured to transmit the read sensor data based on a request from the second OIS circuit in the first SPI slave operation mode; and a second SPI slave configured to transmit the control code based on a request from the second OIS circuit in the second SPI slave operation mode.

[0015] The second OIS circuit may include: a second SPI master configured to operate as an SPI master relative to the first SPI slave and the second SPI slave of the first OIS circuit, and read the control code through the second SPI slave in the first SPI master operation mode, and read sensor data through the first SPI slave in the second SPI master operation mode; and a third memory configured to store the control code and sensor data read by the second SPI master.

[0016] The second OIS circuit may be configured to automatically identify the communication mode with the first OIS circuit by performing a process of identifying and determining the communication mode with the first OIS circuit before communicating with the first OIS circuit.

[0017] The second OIS circuit can be configured to identify the type of the corresponding memory to be read based on the header information stored in the second memory, which is an external memory or an internal memory of the first OIS circuit, and determine a frame structure suitable for the type of the identified memory.

[0018] In general aspects, an optical image stabilization (OIS) device includes: a single sensor configured to operate as a serial peripheral interface (SPI) slave device and transmit sensor data; a first OIS circuit configured to operate as an SPI master device relative to the single sensor, read sensor data from the single sensor, and store the read sensor data, and further configured to transmit a control code in a second SPI slave operation mode before a first SPI slave operation mode, and transmit the read sensor data in the first SPI slave operation mode while operating as an SPI slave device; and a second OIS circuit configured to operate as an SPI master device relative to the first OIS circuit, read the control code from the first OIS circuit in a first SPI master operation mode, and store the read control code, and further configured to read and store the sensor data in a second SPI master operation mode after the first SPI master operation mode.

[0019] The first OIS circuit can include: a first SPI master configured to read sensor data from the single sensor; a first memory configured to store the read sensor data; a second memory configured to store the control code; a first SPI slave configured to transmit the sensor data based on a request from the second OIS circuit in the first SPI slave operation mode; and a second SPI slave configured to transmit the control code based on a request from the second OIS circuit in the second SPI slave operation mode.

[0020] The first OIS circuit can include: a first SPI master configured to read sensor data from the single sensor; a first memory configured to store the read sensor data; and a first SPI slave configured to transmit the read sensor data based on a request from the second OIS circuit in the first SPI slave operation mode, wherein the OIS device further includes an external memory device configured to transmit the control code based on a request from the second OIS circuit, and wherein the external memory device includes: a fourth memory configured to store the control code; and a third SPI slave configured to transmit the control code based on a request from the second OIS circuit in the second SPI slave operation mode.

[0021] The second OIS circuit may include: a second SPI master configured to operate as an SPI master relative to a first SPI slave and a second SPI slave of the first OIS circuit, and read a control code through the second SPI slave in a first SPI master operation mode and read sensor data through the first SPI slave in a second SPI master operation mode; and a third memory configured to store the control code and the sensor data read by the second SPI master.

[0022] The second OIS circuit may be configured to identify a communication mode with the first OIS circuit by performing a process of identifying the communication mode with the first OIS circuit and determining the communication mode before communicating with the first OIS circuit.

[0023] The second OIS circuit may be configured to identify a type of a corresponding memory to be read based on header information stored in a second memory of the first OIS circuit or a third memory of an external memory device, and determine a frame structure suitable for the identified type of the memory.

[0024] The OIS device may include a PIN multiplexer configured to select one of the first SPI slave and the second SPI slave in response to a chip select signal of the second OIS circuit.

[0025] In general, an operation method includes: determining a communication mode by a second optical image stabilization (OIS) circuit through automatically identifying a communication mode with a first OIS circuit; determining a frame structure by the second OIS circuit based on a type of a memory storing a control code, wherein the second OIS circuit is configured to operate as a serial peripheral interface (SPI) master relative to the first OIS circuit while performing the determined communication mode; reading the control code stored in the memory using the frame structure in a first SPI master operation mode; changing a mode from the first SPI master operation mode to a second SPI master operation mode in the second OIS circuit, and reading sensor data from the first OIS circuit by the second OIS circuit.

[0026] Determining the communication mode may include automatically identifying the communication mode with the first OIS circuit by performing a process of identifying the communication mode with the first OIS circuit before performing communication with the first OIS circuit.

[0027] Reading the control code may include operating the second OIS circuit as an SPI master relative to the first OIS circuit in a first SPI master operation mode, selecting a second SPI slave of the first OIS circuit in the first SPI master operation mode, and reading and storing the control code from the memory by the second OIS circuit.

[0028] Determining a frame structure may include identifying, by a second OIS circuit, a type of a corresponding memory to be read based on header information stored in a memory of a first OIS circuit, and determining, by the second OIS circuit, a frame structure suitable for the type of the corresponding memory.

[0029] Reading sensor data may include selecting, in a second SPI master operation mode, a first SPI slave included in the first OIS circuit, reading sensor data through the first SPI slave, and storing the sensor data by the second OIS circuit.

[0030] In general, an electronic device includes an optical image stabilization (OIS) device, and the OIS device includes: a sensor; a first OIS circuit; and a second OIS circuit; wherein, the first OIS circuit includes a first serial peripheral interface (SPI) master configured to read sensor data from the sensor, a first SPI slave configured to transmit the sensor data to the second OIS circuit in a first SPI slave operation mode, and a second SPI slave configured to transmit a control code to the second OIS circuit in a second SPI slave operation mode; and wherein, the second OIS circuit is configured to operate as an SPI master with respect to the first SPI slave and the second SPI slave.

[0031] The device may further include a PIN multiplexer configured to select one of the first SPI slave and the second SPI slave based on a specific code value transmitted by the second OIS circuit.

[0032] The first OIS circuit and the second OIS circuit may be connected in one of a 4-wire communication mode and a 3-wire communication mode.

[0033] Other features and aspects will become apparent from the following detailed description, the drawings, and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a block diagram illustrating an exemplary OIS device according to one or more embodiments;

[0035] Figure 2 is a block diagram illustrating an exemplary OIS circuit according to one or more embodiments;

[0036] Figure 3 is a diagram illustrating an example of interfacing between a single sensor, a first OIS circuit, and a second OIS circuit shown in Figure 1 ;

[0037] Figure 4 is a diagram illustrating an example of interfacing between a single sensor, a first OIS circuit, and a second OIS circuit shown in Figure 1A diagram of an example of interfacing between a single sensor, a first OIS circuit, and a second OIS circuit as shown;

[0038] Figure 5 is a diagram showing that between Figure 1 A diagram of an example of interfacing between a single sensor, a first OIS circuit, and a second OIS circuit as shown;

[0039] Figure 6 is a diagram showing an exemplary communication mode between a first OIS circuit and a second OIS circuit according to one or more embodiments;

[0040] Figure 7 is a diagram showing an exemplary process of periodically checking the communication mode between a first OIS circuit and a second OIS circuit according to one or more embodiments;

[0041] Figure 8 shows an exemplary frame structure for reading a control code according to one or more embodiments;

[0042] Figure 9 shows an exemplary frame structure of an internal memory for reading according to one or more embodiments;

[0043] Figure 10 shows an exemplary frame structure of an external memory for reading according to one or more embodiments; and

[0044] Figure 11 is a flowchart showing an operation method of an OIS device according to one or more embodiments.

[0045] Throughout the drawings and the detailed description, unless otherwise described or provided, the same reference numerals will be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience purposes, the drawings may not be drawn to scale, and the relative dimensions, proportions, and depictions of elements in the drawings may be exaggerated. Detailed Description

[0046] The following detailed description is provided to assist the reader in obtaining a comprehensive understanding of the methods, apparatuses, and / or systems described in this application. However, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described in this application will be apparent after understanding the disclosure of this application. For example, the order of operations described in this application is merely exemplary and, except for operations that must occur in a specific order, is not limited to the order set forth in this application but may be changed as will be apparent after understanding the disclosure of this application. Additionally, descriptions of features known in the art may be omitted for greater clarity and conciseness.

[0047] The features described in this application can be implemented in different forms and should not be construed as limited to the examples described in this application. Rather, the examples described in this application are provided only to illustrate some of the many possible ways of implementing the methods, devices, and / or systems described in this application that will be apparent after understanding the disclosure of this application.

[0048] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on," "connected to," or "coupled to" another element, that element can be directly "on," directly "connected to," or directly "coupled to" the other element, or there can be one or more other elements between that element and the other element. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, there can be no other elements between that element and the other element.

[0049] As used in this application, the phrase "and / or" includes any one of the associated listed items and any combination of any two or more of them.

[0050] Although terms such as "first," "second," and "third" may be used in this application to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Thus, the first component, first part, first region, first layer, or first section referred to in these examples can also be referred to as the second component, second part, second region, second layer, or second section without departing from the teachings of the examples described in this application.

[0051] Spatial relative terms such as "above," "upper," "below," and "lower" may be used in this application for convenience in description to describe the relationship of one element to another as shown in the figures. In addition to covering the orientations depicted in the figures, these spatial relative terms are intended to also cover different orientations of the device during use or operation. For example, if the device in the figures is flipped, an element described as being "above" or "upper" relative to another element will be "below" or "lower" relative to that other element. Thus, depending on the spatial orientation of the device, the term "above" covers both the orientation of "above" and "below." The device can also be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative terms used in this application should be interpreted accordingly.

[0052] The terms used in this application are only for describing various examples and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include the plural forms as well. The phrases "comprising", "including", and "having" indicate the presence of the described features, numbers, operations, components, elements, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0053] In the drawings, the same reference numerals will be used to describe the same elements having the same functions throughout the specification.

[0054] Figure 1 is a block diagram showing an exemplary OIS device according to one or more embodiments.

[0055] Referring to Figure 1 , the OIS device 10 in the example may include a single sensor 50, a first OIS circuit 100, and a second OIS circuit 200.

[0056] The single sensor 50 including a serial peripheral interface (SPI) slave device 51 may operate as an SPI slave device relative to the first OIS circuit 100, may respond to a request from the first OIS circuit 100 operating as an SPI master device, and may transmit sensor data SD to the first OIS circuit 100.

[0057] The first OIS circuit 100 may operate as an SPI master device relative to the single sensor 50, may read and store the sensor data SD from the single sensor 50, may operate as an SPI slave device relative to the second OIS circuit 200, and may transmit the sensor data SD and the control code SC to the second OIS circuit 200. In the example, the control code may correspond to firmware code for driving.

[0058] The second OIS circuit 200 may operate as an SPI master device relative to the first OIS circuit 100, may read the control code SC from the first OIS circuit 100, and may store the control code, and may read and store the sensor data SD.

[0059] In the example, the control code SC may determine a frame structure according to the type of memory (e.g., the internal memory or external memory of the first OIS circuit 100), and may read the control code using a frame structure suitable for the corresponding memory. This configuration will be described in more detail later.

[0060] Figure 2 is a block diagram showing an exemplary OIS circuit according to one or more embodiments.

[0061] Referring to Figure 2, in the exemplary embodiment, the OIS circuit 20 may include a first OIS circuit 100 and a second OIS circuit 200.

[0062] The first OIS circuit 100 may operate as an SPI master with respect to a single sensor 50, may read sensor data SD received from the single sensor 50, and may store the sensor data. The first OIS circuit 100 may also operate as an SPI slave with respect to the second OIS circuit 200. The first OIS circuit 100 may provide a control code in a second SPI slave operation mode before a first SPI slave operation mode, and in the first SPI slave operation mode, the first OIS circuit 100 may provide sensor data.

[0063] The second OIS circuit 200 may operate as an SPI master with respect to the first OIS circuit 100, and may read a control code SC from the first OIS circuit 100 and store the control code in a first SPI master operation mode, and the second OIS circuit 200 may read and store sensor data SD in a second SPI master operation mode after the first SPI master operation mode.

[0064] Referring to Figure 1 and Figure 2 , the first OIS circuit 100 may include a first SPI master 110, a first memory 101, a first SPI slave 120, a second memory 102, and a second SPI slave 130.

[0065] The first SPI master 110 may operate as an SPI master with respect to a single sensor 50 and may read sensor data SD from the single sensor 50.

[0066] The first memory 101 may store the sensor data SD read by the first SPI master 110.

[0067] The second memory 102 may store the control code SC. In an example, the second memory 102 may include header information (header information or control value), and the header information may include a specific ID identifying the memory type.

[0068] The first SPI slave 120 may operate as an SPI slave with respect to the second OIS circuit 200 and may transmit the received sensor data SD to the second OIS circuit 200 based on a request from the second OIS circuit 200 in a first SPI slave operation mode.

[0069] In a second SPI slave operation mode, the second SPI slave 130 may transmit the control code SC according to a request from the second OIS circuit 200.

[0070] The second OIS circuit 200 may include a second SPI master 210 and a third memory 201.

[0071] The second SPI master 210 may operate as an SPI master relative to the first SPI slave 120 and the second SPI slave 130 of the first OIS circuit 100, and may select the second SPI slave 130 and read the control code SC in the first SPI master operation mode, and in the second SPI master operation mode, the second SPI master 210 may select the first SPI slave 120 and read the sensor data SD.

[0072] The third memory 201 may store the control code SC and the sensor data SD read by the second SPI master 210.

[0073] Figure 3 An example of interfacing between the single sensor, the first OIS circuit, and the second OIS circuit shown in Figure 1 is shown.

[0074] Referring to Figure 3 , the second memory 102 may be configured to store the control code SC and may be implemented as an internal memory of the first OIS circuit 100.

[0075] The second SPI slave 130 may transmit the control code SC stored in the second memory 102 to the second OIS circuit 200 according to the request of the second OIS circuit 200.

[0076] In Figure 3 , the SPI slave 51 of the single sensor 50 and the first SPI master 110 of the first OIS circuit 100 may be connected to each other through an SPI clock signal (SPI SCK), an SPI chip select signal (SPI CS), an SPI master output slave input (SPI MOSI), and an SPI master input slave output (SPI MISO). In addition, the first SPI slave 120 of the first OIS circuit 100 and the second SPI master 210 of the second OIS circuit 200 may be connected to each other through SPI SCK, SPI CS, SPI MOSI, and SPI MISO. In addition, the second SPI slave 130 of the first OIS circuit 100 and the second SPI master 210 of the second OIS circuit 200 may be connected to each other through SPI SCK, SPI MOSI, SPI MISO, and SPI CS2.

[0077] Figure 4 An example of interfacing between the single sensor, the first OIS circuit, and the second OIS circuit shown in Figure 1An example of interfacing between a single sensor, a first OIS circuit, and a second OIS circuit as shown.

[0078] Referring to Figure 4 , the first OIS circuit 100 may include a first SPI master 110, a first memory 101, and a first SPI slave 120.

[0079] The first SPI master 110 may read sensor data SD from the single sensor 50.

[0080] The first memory 101 may store the sensor data SD.

[0081] The first SPI slave 120 may transmit the sensor data SD based on a request from the second OIS circuit 200.

[0082] In addition, the OIS device may further include an external memory device 400. The external memory device 400 may transmit a control code SC based on a request from the second OIS circuit 200.

[0083] In the example, the external memory device 400 may include a fourth memory 401 and a third SPI slave 410.

[0084] The fourth memory 401 may store the control code SC.

[0085] The third SPI slave 410 may transmit the control code SC based on a request from the second OIS circuit 200.

[0086] In Figure 4 , the SPI slave 51 of the single sensor 50 and the first SPI master 110 of the first OIS circuit 100 may be connected to each other via SPI SCK, SPI CS, SPI MOSI, and SPI MISO. In addition, the first SPI slave 120 of the first OIS circuit 100 and the second SPI master 210 of the second OIS circuit 200 may be connected to each other via SPI SCK, SPI CS, SPI MOSI, and SPI MISO. Further, the third SPI slave 410 of the external memory device 400 and the second SPI master 210 of the second OIS circuit 200 may be connected to each other via SPI SCK, SPI MOSI, SPI MISO, and SPI CS2.

[0087] Figure 5 Illustrated is an example of interfacing between a single sensor, a first OIS circuit, and a second OIS circuit as shown in Figure 1 An example of interfacing between a single sensor, a first OIS circuit, and a second OIS circuit as shown.

[0088] Referring to Figure 5, The OIS device 10 may further include a PIN multiplexer 500.

[0089] The PIN multiplexer 500 may be synchronized with a change in the operation mode of the second OIS circuit 200 and may select one of the first SPI slave device 120 and the second SPI slave device 130. In an example, when the second OIS circuit 200 sends a specific code value to the first OIS circuit 100 while changing from an operation mode of reading a control code to an operation mode of reading sensor data, the first OIS circuit 100 may change from the second SPI slave device 130 that reads the control code SC to the first SPI slave device 120 that reads sensor data through the PIN multiplexer 500 according to the specific code value.

[0090] In Figure 5 , the SPI slave device 51 of the single sensor 50 and the first SPI master device 110 of the first OIS circuit 100 may be connected to each other through SPI SCK, SPI CS, SPI MOSI, and SPI MISO.

[0091] In addition, the PIN multiplexer (PIN MUX) 500 and the second SPI master device 210 of the second OIS circuit 200 may be connected to each other through SPI SCK, SPI CS, SPI MOSI, and SPI MISO. The PIN multiplexer 500 and the first SPI slave device 120 of the first OIS circuit 100 may be connected to each other through SPI SCK, SPI CS, SPI MOSI, and SPI MISO. Further, the PIN multiplexer 500 and the second SPI slave device 130 of the first OIS circuit 100 may be connected to each other through SPI SCK, SPI MOSI, SPI MISO, and SPI CS2.

[0092] The first OIS circuit 100 and the second OIS circuit 200 may be connected in a 4-wire communication mode or a 3-wire communication mode, and the 4-wire communication mode will be described with reference to Figure 6 An exemplary communication mode between the first OIS circuit and the second OIS circuit according to one or more embodiments is shown.

[0093] Figure 6 An exemplary communication mode between the first OIS circuit and the second OIS circuit according to one or more embodiments is shown.

[0094] Referring to Figure 6, the first SPI slave device 120 of the first OIS circuit 100 and the second SPI master device 210 of the second OIS circuit 200 can be connected in a 4-wire communication mode via an SPI clock signal (SPI SCK), an SPI chip select signal (SPI CS), an SPI master output slave input (SPI MOSI), and an SPI master input slave output (SPI MISO).

[0095] Alternatively, the first SPI slave device 120 of the first OIS circuit 100 and the second SPI master device 210 of the second OIS circuit 200 can be connected in a 3-wire communication mode via SPI SCK, SPI CS, and an SPI master input slave output (SPI MISO).

[0096] Figure 7 An exemplary process of periodically checking the communication mode between the first OIS circuit and the second OIS circuit is shown.

[0097] In the example, as Figure 7 shown, based on repeated signal transmissions and responses in the 4-wire (4-wire) communication mode and the 3-wire (3-wire) communication mode, signals can be transmitted in the 4-wire (4-wire) communication mode, and when there is a response to the signal transmission, the response can be confirmed in the 4-wire communication mode. When there is no response, signals can be transmitted in the 3-wire communication mode, and when there is a response to the signal transmission, the response can be configured in the 3-wire communication mode.

[0098] In this process, when there is no response, the process can be repeated until there is a response.

[0099] Through the above process, the second OIS circuit 200 can perform the process of identifying the communication mode with the first OIS circuit 100 as described above before communicating with the first OIS circuit 100, and the second OIS circuit 200 can automatically check the communication line (4-wire or 3-wire) with the first OIS circuit 100 and can determine the communication mode.

[0100] In the example, the second OIS circuit 200 can import header information from the internal memory (second memory 102) or external memory of the first OIS circuit 100. In this example, the header information can have a specific ID. For example, when assuming the hexadecimal value is 550F, the second OIS circuit 200 can continue to change the communication mode and can perform the communication mode until the corresponding value is entered.

[0101] When reading the corresponding values in a 3 - wire or 4 - wire communication mode, the communication mode can be fixed to the SPI communication mode, and all header information can be read. After reading all the information, the second OIS circuit 200 can read the control code SC for driving the second OIS circuit 200 from the second memory 102 of the first OIS circuit 100 or the fourth memory 401 in the external memory ( Figure 4 ), and can store the control code in the SRAM while operating as an SPI master relative to the first OIS circuit 100.

[0102] As described above, after reading, the second OIS circuit 200 can change from the first SPI master operation mode to the second SPI master operation mode to read sensor data, and the first OIS circuit 100 can select the second SPI slave 130 to share sensor data and can share the data.

[0103] Figure 8 An exemplary frame structure for reading the control code is shown.

[0104] Referring to Figure 8 , the frame structure for reading the control code can include a command area (CA), an address area (AA), and a data area (DA). In the example, the command region (CA) can refer to the control code, the address region (AA) can refer to the address location, and the data area (DA) can refer to the control value.

[0105] Figure 9 An exemplary frame structure of the internal memory to be read is shown. Figure 10 An exemplary frame structure of the external memory to be read is shown.

[0106] The second OIS circuit 200 can identify the type of the target memory to be read based on the header information stored in the control code SC, and can determine a frame structure suitable for the identified memory type.

[0107] In the example, the frame structure of the internal memory to be read is shown in Figure 9 , and the frame structure of the external memory to be read is shown in Figure 10 .

[0108] Referring to Figure 9 , the frame structure of the internal memory to be read can include a command area (CA), an address area (AA), and a data area (DA).

[0109] Referring to Figure 10 , the frame structure for reading the external memory can include a comment area (CA), an address area (AA), an idle area (IA), and a data area (DA).

[0110] The idle area (IA) is the time required to import data from the memory.

[0111] Figure 11 is a flowchart showing a method of operating an OIS device according to one or more embodiments. Figure 11 The operations in may be performed in the order and manner shown, although the order of some operations may be changed or some operations may be omitted without departing from the spirit and scope of the described illustrative examples. Figure 11 Many of the operations shown in may be performed in parallel or simultaneously. Figure 11 One or more blocks of and combinations of these blocks may be implemented by a dedicated hardware-based computer that performs the specified functions or a combination of dedicated hardware and computer instructions. Except for the following Figure 11 description of Figures 1-10 description of also applies to Figure 11 and is incorporated herein by reference. Accordingly, the above description will not be repeated here.

[0112] Reference will be made to Figures 1 to 11 " to describe the method of operating an OIS device in an exemplary embodiment. In the description of the method of operating an OIS device in an exemplary embodiment, the same description of the operations described with reference to Figures 1 to 10 may be applied, and therefore, the overlapping description will not be repeated in the description of the method of operating an OIS device.

[0113] Referring to the attached Figure 2 and Figure 11 , the method of operating an OIS device may be applied to an OIS device including a single sensor 50, a first OIS circuit 100, and a second OIS circuit 200.

[0114] Referring to Figure 11 , in operation S100, the second OIS circuit 200 may automatically identify the communication mode associated with the first OIS circuit 100 and may determine the communication mode.

[0115] In an example, in operation S100, before performing communication with the first OIS circuit 100, the communication line (4-wire or 3-wire) associated with the first OIS circuit 100 may be automatically checked, and the communication mode may be determined.

[0116] Thereafter, in operation S200, when performing the determined communication mode, the second OIS circuit 200 may operate as an SPI master with respect to the first OIS circuit 100 and may determine the frame structure based on the type of the memory ( Figure 1 the second memory 102 in or Figure 4 the fourth memory 401 in ) that has stored the control code SC.

[0117] In the example, in operation S200, the second OIS circuit 200 may identify the type of the target memory to be read based on the header information stored in the Figure 1 second memory 102 or Figure 4 the fourth memory 401, and may determine a frame structure suitable for the type of the identified memory ( Figure 1 the second memory 102 or Figure 4 the fourth memory 401).

[0118] Thereafter, in operation S300, the second OIS circuit 200 may use the frame structure to read the control code stored in the memory in the first SPI master operation mode.

[0119] In the example, in operation S300, the second OIS circuit 200 may operate as an SPI master with respect to the first OIS circuit 100 in the first SPI master operation mode, may select the second SPI slave of the first OIS circuit 100 in the first SPI master operation mode, may read the control code SC from the internal memory or the external memory through the first OIS circuit 100, and may store the control code.

[0120] In the example, the second OIS circuit 200 may read the control code SC stored in the second memory 102 from the first OIS circuit 100, may store the control code in the third memory 201, and may transfer a specific value to the first OIS circuit 100.

[0121] In this example, the first OIS circuit 100 may change the channel of the SPI slave based on the specific value. In other words, the second OIS circuit 200 may change from the first SPI master operation mode for reading the control code to the second SPI master operation mode for receiving sensor data. By changing the operation mode as described above, the second OIS circuit 200 may import the control code from the internal memory or the external memory of the first OIS circuit 100, and may also share and use the sensor data.

[0122] In operation S400, the second OIS circuit 200 may change from the first SPI master operation mode to the second SPI master operation mode, and may read the sensor data SD from the first OIS circuit 100.

[0123] In the example, in operation S400, the second OIS circuit 200 may select the first SPI slave included in the first OIS circuit 100 in the second SPI master operation mode, may read the sensor data SD through the first SPI slave, and may store the sensor data.

[0124] According to the above exemplary embodiment, by allowing data such as control codes and sensor data to be shared among OIS circuits, the circuits can have a reduced size.

[0125] In addition, by automatically identifying and determining the communication mode (3-wire and 4-wire) between the OIS circuits sharing the data, the operation efficiency can be improved.

[0126] In addition, the size of the chip can also be reduced by sharing the data, so that the space occupied by the camera module can be reduced.

[0127] Furthermore, it can correspond to the internal memory or external memory of the main OIS circuit (first OIS circuit) that can store control codes.

[0128] Although the present disclosure includes specific examples, it will be apparent after understanding the disclosure of the present application that various changes in form and detail can be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be understood only in a descriptive sense and not for the purpose of limitation. The description of the features or aspects in each example should be understood as applicable to similar features or aspects in other examples. Appropriate results can still be achieved if the described techniques are performed in a different order and / or if the components in the described system, architecture, device, or circuit are combined in a different manner and / or replaced or supplemented by other components or their equivalents. Therefore, the scope of the present disclosure is not limited by the specific embodiments, but is defined by the claims and their equivalents, and all variations within the scope of the claims and their equivalents should be construed as being included in the present disclosure.

Claims

1. Optical image stabilization circuit, comprising: A first optical image stabilization circuit configured to operate as a serial peripheral interface master relative to a single sensor, read sensor data from the single sensor, and store the read sensor data, and further configured to transmit control codes in a second serial peripheral interface slave operation mode before a first serial peripheral interface slave operation mode, and transmit the read sensor data in the first serial peripheral interface slave operation mode while operating as a serial peripheral interface slave; And A second optical image stabilization circuit configured to operate as a serial peripheral interface master relative to the first optical image stabilization circuit, read the control codes from the first optical image stabilization circuit in a first serial peripheral interface master operation mode, and store the read control codes, and further configured to read and store the sensor data in a second serial peripheral interface master operation mode after the first serial peripheral interface master operation mode.

2. The optical image stabilization circuit according to claim 1, wherein, The first optical image stabilization circuit includes: A first serial peripheral interface master configured to read the sensor data from the single sensor; A first memory configured to store the read sensor data; A second memory configured to store the control codes; A first serial peripheral interface slave configured to transmit the read sensor data based on a request from the second optical image stabilization circuit in the first serial peripheral interface slave operation mode; and A second serial peripheral interface slave configured to transmit the control codes based on a request from the second optical image stabilization circuit in the second serial peripheral interface slave operation mode.

3. The optical image stabilization circuit according to claim 2, wherein, The second optical image stabilization circuit includes: A second serial peripheral interface master configured to operate as a serial peripheral interface master relative to the first serial peripheral interface slave and the second serial peripheral interface slave of the first optical image stabilization circuit, and read the control codes through the second serial peripheral interface slave in the first serial peripheral interface master operation mode, and read the sensor data through the first serial peripheral interface slave in the second serial peripheral interface master operation mode; and A third memory configured to store the control codes and the sensor data read by the second serial peripheral interface master.

4. The optical image stabilization circuit according to claim 3, wherein, The second optical image stabilization circuit is configured to automatically identify a communication mode with the first optical image stabilization circuit by performing a process of identifying and determining the communication mode with the first optical image stabilization circuit before communicating with the first optical image stabilization circuit.

5. The optical image stabilization circuit according to claim 3, wherein, The second optical image stabilization circuit is configured to identify the type of the corresponding memory to be read based on header information stored in the second memory, and determine a frame structure suitable for the identified memory type, wherein the second memory is an external memory or an internal memory of the first optical image stabilization circuit.

6. Optical image stabilization device, comprising: A single sensor configured to operate as a Serial Peripheral Interface (SPI) slave device and transmit sensor data; A first optical image stabilization (OIS) circuit configured to operate as an SPI master device relative to the single sensor, read sensor data from the single sensor, and store the read sensor data, and further configured to transmit control codes in a second SPI slave operating mode before a first SPI slave operating mode and transmit the read sensor data in the first SPI slave operating mode while operating as an SPI slave device; And A second optical image stabilization (OIS) circuit configured to operate as an SPI master device relative to the first OIS circuit, read the control codes from the first OIS circuit in a first SPI master operating mode, and store the read control codes, and further configured to read and store the sensor data in a second SPI master operating mode after the first SPI master operating mode.

7. The optical image stabilization device according to claim 6, wherein, The first optical image stabilization (OIS) circuit includes: A first Serial Peripheral Interface (SPI) master configured to read the sensor data from the single sensor; A first memory configured to store the read sensor data; A second memory configured to store the control codes; A first Serial Peripheral Interface (SPI) slave configured to transmit the sensor data based on a request from the second optical image stabilization (OIS) circuit in the first SPI slave operating mode; and A second Serial Peripheral Interface (SPI) slave configured to transmit the control codes based on a request from the second optical image stabilization (OIS) circuit in the second SPI slave operating mode.

8. The optical image stabilization device according to claim 6, wherein, The first optical image stabilization (OIS) circuit includes: A first Serial Peripheral Interface (SPI) master configured to read the sensor data from the single sensor; A first memory configured to store the read sensor data; and A first Serial Peripheral Interface (SPI) slave configured to transmit the read sensor data based on a request from the second optical image stabilization (OIS) circuit in the first SPI slave operating mode, wherein the optical image stabilization device further includes an external memory device configured to transmit the control codes based on a request from the second optical image stabilization (OIS) circuit, and wherein the external memory device includes: A fourth memory configured to store the control codes; and A third Serial Peripheral Interface (SPI) slave configured to transmit the control codes based on a request from the second optical image stabilization (OIS) circuit in the second SPI slave operating mode.

9. The optical image stabilization device according to claim 7, wherein, The second optical image stabilization (OIS) circuit includes: A second serial peripheral interface master device, configured to operate as a serial peripheral interface master device relative to the first serial peripheral interface slave device and the second serial peripheral interface slave device of the first optical image stabilization circuit, and to read the control code through the second serial peripheral interface slave device in the first serial peripheral interface master device operation mode, and to read the sensor data through the first serial peripheral interface slave device in the second serial peripheral interface master device operation mode; and A third memory, configured to store the control code and the sensor data read by the second serial peripheral interface master device.

10. The optical image stabilization device according to claim 9, wherein, The second optical image stabilization circuit is configured to identify a communication mode with the first optical image stabilization circuit by performing a process of identifying the communication mode with the first optical image stabilization circuit and determining the communication mode before communicating with the first optical image stabilization circuit.

11. The optical image stabilization device according to claim 9, wherein, The second optical image stabilization circuit is configured to identify the type of the corresponding memory to be read based on the header information stored in the second memory of the first optical image stabilization circuit, and to determine a frame structure suitable for the type of the identified memory.

12. The optical image stabilization device according to claim 8, wherein the second optical image stabilization circuit is configured to identify the type of the corresponding memory to be read based on the header information stored in the fourth memory of the external memory device, and to determine a frame structure suitable for the type of the identified memory.

13. The optical image stabilization device according to claim 9, further comprising: A PIN multiplexer, configured to select one of the first serial peripheral interface slave device and the second serial peripheral interface slave device in response to a chip select signal of the second optical image stabilization circuit.

14. A method for operating an optical image stabilization circuit, comprising: Determining a communication mode by automatically identifying a communication mode with a first optical image stabilization circuit by a second optical image stabilization circuit; Determining a frame structure by the second optical image stabilization circuit based on the type of the memory storing the control code, wherein the second optical image stabilization circuit is configured to operate as a serial peripheral interface master device relative to the first optical image stabilization circuit when the second optical image stabilization circuit executes the determined communication mode; Reading the control code stored in the memory using the frame structure in a first serial peripheral interface master device operation mode; and Changing a mode from the first serial peripheral interface master device operation mode to a second serial peripheral interface master device operation mode in the second optical image stabilization circuit, and reading sensor data from the first optical image stabilization circuit by the second optical image stabilization circuit.

15. The method according to claim 14, wherein, Determining the communication mode includes automatically identifying a communication mode with the first optical image stabilization circuit by performing a process of identifying the communication mode with the first optical image stabilization circuit before performing communication with the first optical image stabilization circuit.

16. The method according to claim 15, wherein, Reading the control code includes operating the second optical image stabilization circuit as a serial peripheral interface master device relative to the first optical image stabilization circuit in the first serial peripheral interface master device operation mode, selecting the second serial peripheral interface slave device of the first optical image stabilization circuit in the first serial peripheral interface master device operation mode, and reading the control code from the memory by the second optical image stabilization circuit and storing the control code.

17. The method according to claim 15, wherein, Determining the frame structure includes: identifying, by the second optical image stabilization circuit, the type of the corresponding memory to be read based on the header information stored in the memory of the first optical image stabilization circuit, and determining, by the second optical image stabilization circuit, the frame structure suitable for the type of the corresponding memory.

18. The method according to claim 15, wherein Reading the sensor data includes selecting the first serial peripheral interface slave device included in the first optical image stabilization circuit in the second serial peripheral interface master device operation mode, reading the sensor data through the first serial peripheral interface slave device, and storing the sensor data by the second optical image stabilization circuit.

19. An electronic device, comprising: An optical image stabilization device, comprising: A sensor; A first optical image stabilization circuit; and A second optical image stabilization circuit; wherein the first optical image stabilization circuit includes: a first serial peripheral interface master device configured to read sensor data from the sensor; a first serial peripheral interface slave device configured to transmit the sensor data to the second optical image stabilization circuit in the first serial peripheral interface slave device operation mode; and a second serial peripheral interface slave device configured to transmit a control code to the second optical image stabilization circuit in the second serial peripheral interface slave device operation mode; and wherein the second optical image stabilization circuit is configured to operate as a serial peripheral interface master device relative to the first serial peripheral interface slave device and the second serial peripheral interface slave device.

20. The electronic device according to claim 19, further comprising a PIN multiplexer configured to select one of the first serial peripheral interface slave device and the second serial peripheral interface slave device based on a specific code value transmitted by the second optical image stabilization circuit.

21. The electronic device according to claim 19, wherein, The first optical image stabilization circuit and the second optical image stabilization circuit are connected in one of a 4-wire communication mode and a 3-wire communication mode.

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