Memory device and method of operating the same

Abstract

A memory device and a method for operating the same are provided herein. The memory device may include: a memory block coupled to a plurality of bit lines and a plurality of word lines; a voltage generator configured to apply at least one of a program voltage or a verification voltage to a word line selected from the plurality of word lines; a page buffer configured to precharge some or all of the bit lines during a verification operation performed on memory cells; operation logic configured to output verification information related to the verification operation performed during the programming operation in response to a command; and a page buffer controller configured to output a page buffer control signal based on the verification information, so as to selectively precharge some or all of the bit lines.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a memory device and a method of operating the memory device, and more particularly, to a memory device capable of performing a program operation and a verification operation on a memory cell and a method of operating the memory device. Background Art

[0002] The memory device may include a memory block in which data is stored, a peripheral circuit that may perform a program operation, a read operation, or an erase operation on the memory block, and a logic circuit that may control the peripheral circuit.

[0003] The programming operation may include a sub-programming operation to increase the threshold voltage of the memory cells included in the memory block and a verification operation to determine whether the threshold voltage of the memory cells has been increased to the target voltage. The programming operation may be performed in an incremental step pulse programming (ISPP) manner in which the programming voltage to be applied to the word line connected to the memory cell is increased in a step-by-step manner. For example, the sub-programming operation and the verification operation may form a single loop, and multiple loops may be performed during the programming operation. Whenever each programming loop is performed, the programming voltage may be increased by a step voltage.

[0004] The read operation may include an operation of sensing the memory cell using a read voltage and an operation of outputting data sensed from the memory cell to an external device. Here, the external device may be a controller that transmits a command and an address to the memory device.

[0005] The erase operation may be an operation to put the memory cells included in the memory block in an erased state. For example, the erase operation may include an operation of applying an erase voltage to all memory cells included in the memory block and an erase verification operation of determining whether the threshold voltage of the memory cell is in an erased state. Summary of the Invention

[0006] One embodiment of the present disclosure may provide a memory device. The memory device may include: a memory block coupled to a plurality of bit lines and a plurality of word lines, the memory block including a plurality of memory cells; a voltage generator configured to apply at least one of a program voltage and a verification voltage to a word line selected from the plurality of word lines; a page buffer configured to precharge some or all of the plurality of bit lines during a sub-verification operation performed on the memory cells; operation logic configured to output verification information related to a verification operation performed during a programming operation in response to a command; and a page buffer controller configured to output a page buffer control signal based on the verification information, so that some or all of the plurality of bit lines are precharged.

[0007] One embodiment of the present disclosure may provide a method for operating a memory device. The method may include: increasing a threshold voltage of a memory cell; and performing a main verification operation to verify the memory cell, wherein the main verification operation includes a plurality of sub-verification operations using different verification voltages, and wherein, during a sub-verification operation whose order among the sub-verification operations is within a range of a reference number of verification operations, a bit line is selectively precharged and then a sensing operation is performed, and during a sub-verification operation whose order is greater than or less than the range of the reference number of verification operations, all bit lines are precharged and then a sensing operation is performed.

[0008] One embodiment of the present disclosure may provide a method for operating a memory device. The method may include performing a first sub-verification operation, wherein the first sub-verification operation selectively precharges a bit line according to data stored in a page buffer and verifies a threshold voltage of a memory cell; and performing a second sub-verification operation, wherein the second sub-verification operation simultaneously precharges the bit line and verifies the threshold voltage of the memory cell regardless of the data stored in the page buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0010] Figure 2 is a diagram illustrating a memory cell array.

[0011] Figure 3 is a diagram illustrating a memory block.

[0012] Figure 4 is a diagram illustrating a page buffer group.

[0013] Figure 5 is a diagram illustrating page buffers included in a page buffer group.

[0014] Figure 6 and Figure 7 is a diagram illustrating a selective precharge operation according to an embodiment of the present disclosure.

[0015] Figure 8 and Figure 9 is a diagram illustrating a non-selective precharge operation according to an embodiment of the present disclosure.

[0016] Figure 10 is a diagram illustrating a sensing operation according to an embodiment of the present disclosure.

[0017] Figure 11 is a diagram illustrating the threshold voltage of a memory cell.

[0018] Figure 12is a diagram illustrating a plurality of loops included in a program operation.

[0019] Figure 13 is a diagram illustrating a cycle according to an embodiment of the present disclosure.

[0020] Figure 14 is a diagram illustrating a cycle according to an embodiment of the present disclosure.

[0021] Figure 15 is a diagram illustrating a verification operation according to the first embodiment of the present disclosure.

[0022] Figure 16 is a diagram illustrating a verification operation according to the second embodiment of the present disclosure.

[0023] Figure 17 is a diagram illustrating the effect of the program operation according to the first embodiment or the second embodiment of the present disclosure.

[0024] Figure 18 is a diagram illustrating a verification operation according to the third embodiment of the present disclosure.

[0025] Figure 19 is a diagram illustrating a verification operation according to the fourth embodiment of the present disclosure.

[0026] Figure 20 is a diagram illustrating the effect of the program operation according to the third embodiment or the fourth embodiment of the present disclosure.

[0027] Figure 21 is a diagram illustrating a page buffer controller according to an embodiment of the present disclosure.

[0028] Figure 22 is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0029] Figure 23 is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Various embodiments of the present disclosure may relate to a memory device capable of adjusting a program operation time and current consumption during a program operation of the memory device and a method of operating the memory device.

[0031] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0032] Reference Figure 1, the memory device 1100 may include a memory cell array 110 , a row decoder 120 , a voltage generator 130 , a page buffer group 140 , an input / output circuit 150 , a column decoder 160 , and a logic circuit 170 .

[0033] The memory cell array 110 may include a plurality of memory blocks in which data is stored. Each of the memory blocks may include a plurality of memory cells, and the memory blocks may be implemented in a two-dimensional (2D) structure in which memory cells are horizontally arranged on a substrate or a three-dimensional (3D) structure in which memory cells are vertically stacked on a substrate.

[0034] The row decoder 120 may select one memory block from among memory blocks included in the memory cell array 110 in response to the row address RADD and may transfer the operating voltage Vop to the selected memory block.

[0035] The voltage generator 130 may generate and output an operation voltage Vop required for various operations in response to the operation code OPCD. For example, the voltage generator 130 may generate and output a program voltage, a verification voltage, a read voltage, an erase voltage, a pass voltage, etc.

[0036] The page buffer group 140 can be connected to the memory cell array 110 through the bit line. For example, the page buffer group 140 may include a plurality of page buffers connected to the respective bit lines. The plurality of page buffers can operate simultaneously in response to the page buffer control signal PBSIGS and can temporarily store data during a programming operation or a read operation. The verification operation performed in the programming operation and the erase verification operation performed in the erase operation can be performed in the same manner as the read operation. During the verification operation, the page buffer can precharge the bit line to sense the threshold voltage of the memory cell, and can sense the data from the memory cell based on the voltage or current of the bit line. As used herein, the words "simultaneously" and "simultaneously" with respect to an event refer to the occurrence of the event at overlapping time intervals. For example, if a first event occurs within a first time interval and a second event occurs simultaneously within a second time interval, the first interval and the second interval at least partially overlap with each other, so that there is a time when both the first event and the second event occur.

[0037] The input / output circuit 150 can connect the memory device 1100 to an external device via an input / output line 10. Here, the external device may be a controller capable of controlling the memory device 1100. The input / output circuit 150 can receive a command CMD, an address ADD, and data from the external device, or output data to the external device via the input / output line 10, and can receive data from the page buffer group 140 via the data line DL#. The input / output circuit 150 can transmit the command CMD and address ADD received via the input / output line 10 to the logic circuit 170, and can transmit data to the page buffer group 140.

[0038] The column decoder 160 may couple the page buffer group 140 to the data line DL# in response to the column address CADD, thereby enabling data to be transferred between the page buffer group 140 and the input / output circuit 150 through the data line DL#.

[0039] The logic circuit 170 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIGS, and a column address CADD in response to a command CMD and an address ADD. For example, the logic circuit 170 may include software that executes an algorithm for various operations in response to the command CMD and hardware that outputs various signals based on the address ADD and the algorithm. For example, the logic circuit 170 may include operation logic 180 and a page buffer (PB) controller 190.

[0040] The operation logic 180 may be implemented as software that can execute an algorithm in response to a command CMD. When the command CMD for a program operation is input, the operation logic 180 according to an embodiment may execute an algorithm related to a sub-program operation and a verification operation, and may output verification information VFIF related to the verification operation. For example, the verification information VFIF may include information about the number of loops (i.e., loop count) and a verification voltage change.

[0041] The page buffer controller 190 can adjust the page buffer control signal PBSIGS based on the verification information VFIF. For example, when the number of changes in the verification voltage among the multiple verification voltages used in the same cycle falls within the range of the reference number of the verification operation, the page buffer controller 190 can precharge the bit lines based on a selective precharge scheme, in which only some bit lines are precharged. In addition, when the number of changes in the verification voltage has reached the reference number of the verification operation, the page buffer controller 190 can precharge the bit lines based on a non-selective precharge scheme, in which all bit lines are precharged. In the selective precharge scheme, current consumption can be reduced during the verification operation, but the programming operation time (i.e., the time required for the programming operation) will be extended. In the non-selective precharge scheme, current consumption can be increased during the verification operation, but the programming operation time can be shortened.

[0042] Therefore, in an embodiment, in order to optimize the time and current consumption for the programming operation time, the number of verification operations performed in each cycle is compared with a reference number of verification operations, and thus based on the comparison result, a selective precharging scheme can be used in some time periods and a non-selective precharging scheme can be used in the remaining time periods.

[0043] Figure 2 is a diagram illustrating a memory cell array.

[0044] Reference Figure 2 , the memory cell array 110 may be implemented as a single-plane structure or a multi-plane structure. The single-plane structure may be a structure in which the memory cell array 110 is implemented as a single plane, and the multi-plane structure may be a structure in which a plurality of planes are included in the memory cell array 110. Figure 2 , a memory cell array 110 having a multi-plane structure is illustrated.

[0045] The memory cell array 110 may include a first plane P1, a second plane P2, a third plane P3, and a fourth plane P4. Different row decoders and different page buffers may be coupled to the first to fourth planes P1 to P4. Each of the first to fourth planes P1 to P4 may include a plurality of memory blocks BLK1 to BLKi (where i is a positive integer). Different physical addresses may be assigned to the first to fourth planes P1 to P4, and different physical addresses may also be assigned to the plurality of memory blocks BLK1 to BLKi.

[0046] The first to fourth planes P1 to P4 can be simultaneously selected during a program operation, a read operation, or an erase operation, and the memory blocks selected from the first to fourth planes P1 to P4 can be the same as or different from each other depending on the row address. For example, depending on the row address, the first memory block BLK1 of the first plane P1 can be selected, the third memory block BLK3 of the second plane PL2 can be selected, the second memory block BLK2 of the third plane P3 can be selected, and the first memory block BLK1 of the fourth plane P4 can be selected.

[0047] For example, during a program operation, when data is input to page buffers connected to the first to fourth planes P1 to P4, respectively, a program operation can be simultaneously performed on selected memory blocks of the first to fourth planes P1 to P4. During a read operation, a read operation can be simultaneously performed on selected memory blocks of the first to fourth planes P1 to P4. During an erase operation, an erase operation can be simultaneously performed on selected memory blocks of the first to fourth planes P1 to P4.

[0048] Figure 3 is a diagram illustrating a memory block.

[0049] Reference Figure 3 , illustrated by example Figure 2 Any one memory block BLKi among the plurality of memory blocks BLK1 to BLKi shown.

[0050] The memory block BLKi may include a plurality of strings ST coupled between first to m-th bit lines BL1 to BLm (where m is a positive integer) and a source line SL. Each of the plurality of strings ST may include a source select transistor SST, first to n-th memory cells C1 to Cn, and a drain select transistor DST, coupled in series between the source line SL and a corresponding bit line among the first to m-th bit lines BL1 to BLm.

[0051] because Figure 3 The memory block BLKi shown in FIG is intended to illustrate the configuration of the memory block, so the number of source selection transistors SST, first to nth memory cells C1 to Cn, and drain selection transistors DST is not limited to Figure 3 Quantity shown.

[0052] The corresponding gates of the source selection transistors SST in different strings ST can be connected to the source selection line SSL, the corresponding gates of the first memory cell C1 to the nth memory cell Cn can be connected to the first word line WL1 to the nth word line WLn, and the corresponding gates of the drain selection transistors DST can be connected to the drain selection line DSL.

[0053] A group of memory cells connected to the same word line and included in different strings ST may form a page PG. A programming operation may be performed on a page (PG) basis. For example, a sub-programming operation and a verification operation may be performed on a page (PG) basis. For example, after a sub-programming operation has been performed on a selected page, a verification operation may be performed on the selected page.

[0054] Figure 4 is a diagram illustrating a page buffer group.

[0055] Reference Figure 4 The page buffer group 140 may include first to m-th page buffers PB1 to PBm (where m is a positive integer). The first to m-th page buffers PB1 to PBm may be coupled between the first to m-th bit lines BL1 to BLm and the first to m-th data lines DL1 to DLm, respectively. The first to m-th page buffers PB1 to PBm may sequentially store data loaded onto the first to m-th data lines DL1 to DLm, or sequentially output the stored data to the first to m-th data lines DL1 to DLm.

[0056] Figure 5 is a diagram illustrating page buffers included in a page buffer group, and shows by way of example Figure 4 A portion of the first page buffer PB1 among the first to m-th page buffers PB1 to PBm is shown.

[0057] Reference Figure 5 , the first page buffer PB1 may include a non-selective precharge circuit ALL_PC, a sensing circuit SC, and a latch group LG.

[0058] The non-selective precharge circuit ALL_PC can precharge the first bit line BL1 in response to the bit line precharge signal BL_PRE during a verify operation. For example, the non-selective precharge circuit ALL_PC can include a first switch S1 that transmits an external positive voltage Vext to the first bit line BL1 in response to the bit line precharge signal BL_PRE. The first switch S1 can be implemented as an NMOS transistor. The non-selective precharge circuit ALL_PC can perform the non-selective precharge operation ALL_PRE.

[0059] During a verify operation, the sensing circuit SC can selectively precharge the first bit line BL1 based on the data stored in the sense latch Ls and can sense the voltage or current of the first bit line BL1. For example, the sensing circuit SC may include second to seventh switches S2 to S7 and the sense latch Ls. Of these components, the fourth to seventh switches S4 to S7 may be included in the selective precharge circuit SEL_PC. The sensing circuit SC is described in detail below.

[0060] The second switch S2 may be implemented as an NMOS transistor that transmits the voltage of the first node N1 to the first bit line BL1 or the first node N1 in response to the bit line select signal BL_SEL. When the bit line precharge signal BL_PRE is activated, the bit line select signal BL_SEL may be disabled.

[0061] The third switch S3 may be implemented as an NMOS transistor whose conduction level is adjusted in response to the level of the page sensing signal PBSENSE, and may be coupled between the first node N1 and the current sensing node CSO.

[0062] The selective precharge circuit SEL_PC may include fourth to seventh switches S4 to S7 .

[0063] The fourth switch S4 may be implemented as an NMOS transistor that couples the second node N2 to the current sensing node CSO or decouples the second node N2 from the current sensing node CSO in response to the current sensing signal SA_CSOC. The fifth switch S5 may be implemented as a PMOS transistor that is turned on or off depending on data of the sense latch node QS and may be coupled between a terminal to which the power supply voltage VCC is applied and the second node N2. The sixth switch S6 may be implemented as a PMOS transistor that couples the second node N2 to the sense node SO or decouples the second node N2 from the sense node SO in response to the sense precharge signal SA_PRECH_N. The seventh switch S7 may be implemented as an NMOS transistor that couples the sense node SO to the current sensing node CSO or decouples the sense node SO from the current sensing node CSO in response to the sense node sense signal SA_SENSE.

[0064] During the selective precharge operation SEL_PRE, the fourth switch S4, the sixth switch S6, and the seventh switch S7 may be turned on, and the fifth switch S5 may be turned on or off according to the data of the sense latch node QS. Therefore, during the selective precharge operation SEL_PRE, the power supply voltage VCC or the ground voltage GND may be applied to the current sensing node CSO according to the data of the sense latch node QS.

[0065] When the non-selective pre-charge circuit ALL_PC is activated, the current sense signal SA_CSOC may be disabled, and when the non-selective pre-charge circuit ALL_PC is deactivated, the current sense signal SA_CSOC may be enabled. In an embodiment, when the selective pre-charge circuit SEL_PC or the discharge circuit DIS is activated, the non-selective pre-charge circuit ALL_PC is deactivated.

[0066] The discharge circuit DIS can selectively discharge the sense node SO based on the data of the sense latch node QS. For example, when the data of the sense latch node QS is "1," the discharge circuit DIS can be activated, thereby discharging the sense node SO. When the data of the sense latch node QS is "0," the discharge circuit DIS can be deactivated, thereby preventing the sense node SO from being discharged. Here, the data "1" can indicate that the potential of the sense latch node QS is high, while the data "0" can indicate that the potential of the sense latch node QS is low.

[0067] The sense latch Ls may include a first inverter I1 and a second inverter I2 coupled in parallel between a sense latch node QS and an inverted sense latch node QS_N. For example, an input terminal of the first inverter I1 and an output terminal of the second inverter I2 may be coupled to the sense latch node QS, and an output terminal of the first inverter I1 and an input terminal of the second inverter I2 may be coupled to the inverted sense latch node QS_N. A fifth switch S5 may be turned on or off depending on data at the sense latch node QS.

[0068] The latch group LG may include first to kth latches L1 to Lk capable of storing data. For example, the first to kth latches L1 to Lk may be coupled to the sense node SO through a transfer switch (not shown) and may transfer data to each other through the sense node SO and the transfer switch (not shown).

[0069] Among the first to kth latches L1 to Lk, the kth latch Lk may receive or output data through the first data line DL1 and may transfer the data stored in the first latch L1 to the sensing latch Ls. For example, the first latch L1 may store data sensed in a previous verification operation.

[0070] Figure 6 and Figure 7 is a diagram illustrating a selective precharge operation SEL_PRE according to an embodiment of the present disclosure.

[0071] Figure 6 A setting method is illustrated for transferring data stored in the first latch L1 to the sense latch Ls during the selective precharge operation SEL_PRE and selectively precharging the first bit line BL1 according to the data stored in the sense latch Ls, and Figure 7 An example of selectively precharging bit lines during the selective precharge operation SEL_PRE is illustrated.

[0072] To facilitate the description of this embodiment, Figure 6 A brief example is given in Figure 5Only components required for the selective precharge operation SEL_PRE are included among the components of the first page buffer PB1 shown in FIG.

[0073] Reference Figure 6 , when performing a programming operation, data sensed during a previous verification operation may be input to the first latch L1. When a selective precharge operation SEL_PRE is performed during the verification operation, data stored in the first latch L1 may be transferred to the sense latch Ls (61), and the selective precharge circuit SEL_PC may selectively apply the power supply voltage VCC (62) to the first bit line BL1 according to the data stored in the sense latch Ls. For example, when data loaded into the sense latch node QS included in the sense latch Ls is "1", the selective precharge circuit SEL_PC may transfer a precharge voltage Vpr having a level of the power supply voltage VCC to the first bit line BL1. When data loaded into the sense latch node QS is "0", the selective precharge circuit SEL_PC may not output the precharge voltage Vpr, and the first bit line BL1 may be discharged through the discharge circuit DIS (63). For example, the potential of the first bit line BL1 after discharge may have a level of the ground voltage GND.

[0074] Reference Figure 7 When the selective precharge operation SEL_PRE is performed in a state in which data '1' is stored in the sense latches Ls of the first to eighth page buffers PB1 to PB8 and data '0' is stored in the sense latches Ls of the second to eighth page buffers PB2 to PB5, the sixth to eighth page buffers PB6 and PB8, the precharge voltage Vpr may be selectively applied only to the first to third to fourth to seventh bit lines BL1 to BL7. That is, the precharge voltage Vpr may be applied to the first to third to fourth to seventh bit lines BL1 to BL7 coupled to program target memory cells, and the ground voltage GND may be applied to the remaining bit lines (i.e., the second to fifth to sixth to eighth bit lines BL6 and BL8).

[0075] Since the selective precharge operation SEL_PRE selectively precharges the bit line, the current consumption in the selective precharge operation can be smaller than the current consumption in the non-selective precharge operation, but due to the setup time when data is transferred to each latch, the programming operation time in the selective precharge operation can be longer than the programming time in the non-selective precharge operation.

[0076] Figure 8 and Figure 9 is a diagram illustrating a non-selective precharge operation according to an embodiment of the present disclosure.

[0077] Figure 8 A method of precharging the first bit line BL1 using the non-selective precharge circuit ALL_PC during the non-selective precharge operation ALL_PRE is illustrated, and Figure 9 An example is illustrated in which all bit lines are precharged during the non-selective precharge operation ALL_PRE.

[0078] In order to easily describe this embodiment, Figure 8 In the Figure 5 Only components required for the non-selective precharge operation ALL_PRE are shown among the components of the first page buffer PB1.

[0079] Reference Figure 8 When the non-selective precharge operation ALL_PRE is performed during the verification operation, the bit line precharge signal BL_PRE may be enabled, and thus the non-selective precharge circuit ALL_PC may transmit the precharge voltage Vpr (81) having the level of the external positive voltage Vext to the first bit line BL1. During the non-selective precharge operation ALL_PRE, the non-selective precharge circuit ALL_PC may output the precharge voltage Vpr to the first bit line BL1 regardless of the data stored in the sense latch Ls.

[0080] Reference Figure 9 In the non-selective precharge operation ALL_PRE, the bit lines are precharged using the non-selective precharge circuit ALL_PC regardless of the data stored in the page buffer. Therefore, the precharge voltage Vpr can be applied to the first to eighth bit lines BL1 to BL8 at the same time. That is, during the non-selective precharge operation ALL_PRE, all bit lines can be precharged at the same time.

[0081] Since all bit lines are simultaneously precharged regardless of data stored in the page buffer in the non-selective precharge operation ALL_PRE, an operation time may be shorter than that in the selective precharge operation SEL_PRE, but current consumption may be greater than that in the selective precharge operation SEL_PRE.

[0082] As in the case of the above embodiment, when a verification voltage is applied to a selected word line after the selective precharge operation SEL_PRE or the non-selective precharge operation ALL_PRE has been performed, a voltage or current of a bit line may be maintained or changed.

[0083] Figure 10is a diagram illustrating a sensing operation according to an embodiment of the present disclosure.

[0084] Reference Figure 10 When performing a sensing operation, the voltage or current of the first bit line BL1 may be maintained in a precharge state or may change depending on the threshold voltage of the memory cell coupled to the first bit line BL1. For example, when the threshold voltage of a memory cell is higher than a verification voltage, the memory cell is turned off, and thus the first bit line BL1 may be maintained in a precharge state. When the threshold voltage of a memory cell is lower than the verification voltage, the memory cell is turned on, and thus the voltage of the first bit line BL1 may decrease or its current may increase.

[0085] Data sensed according to the voltage or current of the first bit line BL1 may be stored in the first latch L1 .

[0086] Figure 11 is a diagram illustrating the threshold voltage of a memory cell.

[0087] Reference Figure 11 Programming operations can be categorized into various schemes based on the number of bits stored in each memory cell. For example, a scheme that stores three bits of data in a memory cell is called a triple-level cell (TLC) scheme, and a scheme that stores four bits of data in a memory cell is called a quad-level cell (QLC) scheme.

[0088] In the TLC scheme, the state of each memory cell can be identified as one erased state ER or any one of seven programmed states P1 to P7. In the QLC scheme, the state of each memory cell can be identified as one erased state ER or any one of 15 programmed states P1 to P15.

[0089] The number of bits that can be stored in one memory cell is 5 or more, and the present embodiment does not limit the number of bits to be stored in each memory cell.

[0090] The more data bits that can be stored in each memory cell, the more verification voltages are used in the verification operation. Therefore, during the verification operation, a sensing operation for each of the multiple verification voltages can be performed. The programming operation will be described in detail below.

[0091] Figure 12 is a diagram illustrating a plurality of loops included in a program operation.

[0092] Reference Figure 12, a programming operation on the selected page can be performed until the threshold voltages of the selected memory cells included in the selected page all reach the target voltage. For example, in the programming operation, the first loop LP1 to the j-th loop LPj can be performed in sequence. In each loop, a sub-programming operation and a main verification operation can be performed. The first loop LP1 is described below by way of example. During the first sub-programming operation PGM1, a programming voltage is applied to the selected word line so that the threshold voltage of the memory cell increases. During the first main verification operation MV1, the data of the memory cell can be sensed. Based on the sensed data, the verification operation can be passed or failed. For example, in the first loop LP1, the first main verification operation MV1 can be performed after the first sub-programming operation PGM1 has been performed. When the first main verification operation MV1 fails, the second loop LP2 can be performed. In this way, the first loop LP1 to the j-th loop LPj can be performed in sequence until the verification operation passes.

[0093] Figure 13 is a diagram illustrating a cycle according to an embodiment of the present disclosure.

[0094] Reference Figure 13 The programming operation may include a plurality of programming loops LP1, LP2, ... The loops may be performed until the threshold voltage of the selected memory cell reaches the target voltage. When the verification operation fails until the number of loops performed (i.e., the loop count) reaches a threshold value, the selected memory block may be processed as a bad block.

[0095] Each loop may include a sub-programming operation and a main verification operation. The first loop LP1 is described below by way of example. The first loop LP1 may include a first sub-programming operation PGM1 and a first main verification operation MV1. During the first sub-programming operation PGM1, a first program voltage Vpgm1 may be applied to a selected word line, thereby increasing the threshold voltage of a memory cell.

[0096] During the first main verification operation MV1, multiple sub-verification operations P1 to Pn may be sequentially performed according to the number of verification voltages. For example, when the first to nth verification voltages V1 to Vn are used in the first loop LP1, verification voltages may be sequentially used in the first main verification operation MV1, starting from the highest nth verification voltage Vn and decreasing in level. For example, when the first main verification operation MV1 begins, the nth verification voltage Vn may be used in the first sub-verification operation P1, and the n-1th verification voltage Vn-1, which is lower than the nth verification voltage Vn, may be used in the second sub-verification operation P2. In this manner, the lowest first verification voltage V1 may be used in the nth sub-verification operation Pn. When a failed verification operation is detected in the first to nth sub-verification operations P1 to Pn, the second loop LP2 may be performed.

[0097] In the second loop LP2, a second sub-programming operation PGM2 and a second main verification operation MV2 may be performed. During the second sub-programming operation PGM2, a second programming voltage Vpgm2 that is higher than the first programming voltage Vpgm1 by a step voltage may be used. The second main verification operation MV2 may be performed in the same manner as the first main verification operation MV1. Alternatively, if a passed sub-verification operation is detected in the first main verification operation MV1, the passed sub-verification operation may be omitted during the second main verification operation MV2.

[0098] Figure 14 is a diagram illustrating a cycle according to an embodiment of the present disclosure.

[0099] Reference Figure 14 The program operation may include a plurality of program loops LP1, LP2, ... The loops may be performed until the threshold voltage of the selected memory cell reaches the target voltage. When the verification operation fails until the number of loops performed reaches a threshold, the selected memory block may be processed as a bad block.

[0100] Each loop may include a sub-programming operation and a main verification operation. The first loop LP1 is described below by way of example. The first loop LP1 may include a first sub-programming operation PGM1 and a first main verification operation MV1. During the first sub-programming operation PGM1, a first program voltage Vpgm1 may be applied to a selected word line, thereby increasing the threshold voltage of a memory cell.

[0101] During the first main verification operation MPV1, multiple sub-verification operations P1 to Pn may be sequentially performed according to the number of verification voltages. For example, when using the first to nth verification voltages V1 to Vn in the first loop LP1, verification voltages may be sequentially used in the first main verification operation MV1, starting from the lowest first verification voltage V1 and increasing in level. For example, when the first main verification operation MV1 begins, the first verification voltage V1 may be used in the first sub-verification operation P1, and a second verification voltage V2, which is higher than the first verification voltage V1, may be used in the second sub-verification operation P2. In this way, the highest nth verification voltage Vn may be used in the nth sub-verification operation Pn. If a failed verification operation is detected in the first to nth sub-verification operations P1 to Pn, the second loop LP2 may be performed.

[0102] In the second loop LP2, a second sub-programming operation PGM2 and a second main verification operation MV2 may be performed. During the second sub-programming operation PGM2, a second programming voltage Vpgm2 that is higher than the first programming voltage Vpgm1 by a step voltage may be used. The second main verification operation MV2 may be performed in the same manner as the first main verification operation MV1. Alternatively, if a passed sub-verification operation is detected in the first main verification operation MV1, the passed sub-verification operation may be omitted during the second main verification operation MV2.

[0103] Figure 15 is a diagram illustrating a verification operation according to the first embodiment of the present disclosure.

[0104] Reference Figure 15 During some of the sub-verification operations performed in the same main verification operation, the bit lines may be precharged using a selective precharge scheme, while during the remaining sub-verification operations, the bit lines may be precharged using a non-selective precharge scheme. For example, when the first to sixth sub-verification operations P1 to P6 are sequentially performed during the first main verification operation MV1, during some of the sub-verification operations corresponding to the previous stages among the first to sixth sub-verification operations P1 to P6, the bit lines may be selectively precharged based on the selective precharge operation SEL_PRE, and the threshold voltages of the memory cells connected to the selectively precharged bit lines may be verified. Then, during the remaining sub-verification operations, all the bit lines may be precharged simultaneously based on the non-selective precharge operation ALL_PRE, and the threshold voltages of the memory cells connected to all the precharged bit lines may be verified. In order to distinguish the step of performing the selective precharge operation SEL_PRE from the step of performing the non-selective precharge operation ALL_PRE, a reference number Pref of verification operations may be set. The reference number Pref of the verification operation may be the number of sub-verification operations performed based on the selective precharge scheme in the same main verification operation. Alternatively, the reference number Pref of the verification operation may be the number of verification voltages changed in the same main verification operation. Therefore, the reference number Pref of the verification operation may be set to a positive integer of 1 or greater.

[0105] For example, when the reference number Pref of verification operations is set to 2 based on the number of sub-verification operations, the selective pre-charge operation SEL_PRE can be performed during the first sub-verification operation P1 and the second sub-verification operation P2 within the range of 2 (i.e., twice), and the non-selective pre-charge operation ALL_PRE can be performed during the remaining third sub-verification operations P3 to sixth sub-verification operations P6.

[0106] During the first and second sub-verification operations P1 and P2 in which the selective precharge operation SEL_PRE is performed, the bit lines may be selectively precharged based on data input to the latch of the page buffer, and while the bit lines are selectively precharged, a sensing operation on the selected memory cells may be performed. For example, during the first sub-verification operation P1, a set operation SET may be performed to selectively set data in the latch of the page buffer to select the bit lines to be precharged, a precharge operation BL_PRE may be performed to selectively precharge the bit lines based on the set data in the latch, and a sensing operation SS may be performed to sense the voltage or current of the memory cells. Even during the second sub-verification operation P2, the selective precharge operation SEL_PRE is performed, and thus the set operation SET, precharge operation BL_PRE, and sensing operation SS may be performed sequentially.

[0107] During the third to sixth sub-verification operations P3 to P6 of the non-selective precharge operation ALL_PRE, a non-selective precharge circuit (eg, Figure 5 All bit lines are precharged simultaneously using the non-selective precharge circuit ALL_PC. For example, during the third sub-verification operation P3, a precharge operation BL_PRE for precharging all bit lines simultaneously and a sensing operation SS for sensing the voltage or current of a memory cell may be sequentially performed. During the third to sixth sub-verification operations P3 to P6, all bit lines are precharged using the non-selective precharge circuit ALL_PC, and thus the set operation SET is omitted.

[0108] Although as an implementation Figure 15 The first main verification operation MV1 is illustrated in FIG. 2 , but when a program operation is performed on a selected page, even during the remaining main verification operations, a selective precharge operation SEL_PRE may be performed and then a non-selective precharge operation ALL_PRE may be performed.

[0109] Figure 16 is a diagram illustrating a verification operation according to the second embodiment of the present disclosure.

[0110] Reference Figure 16 , when the reference number Pref of the verification operation is set to "1", the selective precharge operation SEL_PRE can be performed only during the first sub-verification operation P1 among the first sub-verification operation P1 to the j-th sub-verification operation Pj performed in the first main verification operation MV1, and the non-selective precharge operation ALL_PRE can be performed during the remaining second sub-verification operations P2 to the j-th sub-verification operation Pj.

[0111] During the first sub-verification operation P1 in which the selective precharge operation SEL_PRE is performed, the bit lines may be selectively precharged based on data input to the latch of the page buffer. While the bit lines are selectively precharged, a sensing operation may be performed on the selected memory cells. For example, during the first sub-verification operation P1, a set operation SET may be performed to selectively set data in the latch of the page buffer to select the bit lines to be precharged, a precharge operation BL_PRE may be performed to selectively precharge the bit lines based on the latch set data, and a sensing operation SS may be performed to sense the voltage or current of the memory cells.

[0112] During the second to j-th sub-verification operations P2 to Pj of the non-selective precharge operation ALL_PRE, a non-selective precharge circuit (eg, Figure 5 All bit lines are precharged simultaneously using the non-selective precharge circuit ALL_PC. For example, during the second sub-verification operation P2, a precharge operation BL_PRE for precharging all bit lines simultaneously and a sensing operation SS for sensing the voltage or current of a memory cell may be sequentially performed. During the second sub-verification operation P2 to the j-th sub-verification operation Pj, all bit lines are precharged using the non-selective precharge circuit ALL_PC, and thus the set operation SET is omitted.

[0113] Although as an implementation Figure 16 The first main verification operation MV1 is illustrated in FIG. 2 , but when a program operation is performed on a selected page, even during the remaining main verification operations, a selective precharge operation SEL_PRE may be performed and then a non-selective precharge operation ALL_PRE may be performed.

[0114] Figure 17 is a diagram illustrating the effect of the program operation according to the first embodiment or the second embodiment of the present disclosure.

[0115] Reference Figure 17 , the selective precharge operation SEL_PRE and the non-selective precharge operation ALL_PRE may commonly include the precharge operation BL_PRE and the sensing operation SS, but the selective precharge operation SEL_PRE further includes a set operation SET.

[0116] It is assumed that an operation time required to perform the program operations of the first to third sub-verification operations P1 to P3 based on only the selective precharge operation SEL_PRE is a first program operation time tPROG1 , and a current consumption at this time is a first current consumption CR1 .

[0117] Assuming that the operation time required to perform the programming operations of the first sub-verification operation P1 to the third sub-verification operation P3 based only on the non-selective precharge operation ALL_PRE is the second programming operation time tPROG2, and the current consumption at this time is the second current consumption CR2, then the second programming operation time tPROG2 can be shorter than the first programming operation time tPROG1, and the second current consumption CR2 can be greater than the first current consumption CR1.

[0118] As in the present embodiment, assuming that the operation time required for the program operation in which the selective precharge operation SEL_PRE and the non-selective precharge operation ALL_PRE coexist is the third program operation time tPROG3, and the current consumption at this time is the third current consumption CR3, the third program operation time tPROG3 may be longer than the second program operation time tPROG2 and shorter than the first program operation time tPROG1. The third current consumption CR3 may be smaller than the second current consumption CR2 and larger than the first current consumption CR1.

[0119] That is, in this embodiment, the selective precharge operation SEL_PRE and the non-selective precharge operation ALL_PRE can be controlled by adjusting the reference number Pref of the verification operation, so the performance of the memory device can be improved by controlling the time required for the programming operation of the memory device and the current consumption occurring during the programming operation.

[0120] Figure 18 is a diagram illustrating a verification operation according to the third embodiment of the present disclosure.

[0121] Reference Figure 18During some of the sub-verification operations performed in the same main verification operation, the bit lines may be precharged using a selective precharge scheme, and during the remaining sub-verification operations, the bit lines may be precharged using a non-selective precharge scheme. For example, when the sixth sub-verification operation P6 to the first sub-verification operation P1 are sequentially performed during the first main verification operation MV1, during some of the sub-verification operations corresponding to the previous stage among the sixth sub-verification operation P6 to the first sub-verification operation P1, the bit lines may be selectively precharged based on the selective precharge operation SEL_PRE, and the threshold voltages of the memory cells connected to the selectively precharged bit lines may be verified. The sixth sub-verification operation P6 may be an operation of verifying the memory cells with the highest target voltage, and the first sub-verification operation P1 may be an operation of verifying the memory cells with the lowest target voltage. Then, during the remaining sub-verification operations, all bit lines may be precharged simultaneously based on the non-selective precharge operation ALL_PRE, and the threshold voltages of the memory cells connected to all precharged bit lines may be verified. In order to distinguish the step of performing the selective precharge operation SEL_PRE from the step of performing the non-selective precharge operation ALL_PRE, a reference number Pref of verification operations may be set. The reference number Pref of verification operations may be the number of sub-verification operations performed based on the selective precharge scheme in the same main verification operation. Alternatively, the reference number Pref of verification operations may be the number of verification voltages changed during the same main verification operation. Therefore, the reference number Pref of verification operations may be set to a positive integer of 1 or greater.

[0122] For example, when the reference number Pref of verification operations is set to 2 based on the number of sub-verification operations, the selective pre-charge operation SEL_PRE can be performed during the sixth sub-verification operation P6 and the fifth sub-verification operation P5 within the range of 2 (i.e., twice), and the non-selective pre-charge operation ALL_PRE can be performed during the remaining fourth sub-verification operation P4 to the first sub-verification operation P1.

[0123] During the sixth and fifth sub-verification operations P6 and P5, in which the selective precharge operation SEL_PRE is performed, the bit lines may be selectively precharged based on data input to the latches of the page buffer, and a sensing operation may be performed on the selected memory cells while the bit lines are selectively precharged. For example, during the sixth sub-verification operation P6, a set operation SET may be performed to selectively set data in the latches of the page buffer to select the bit lines to be precharged, a precharge operation BL_PRE may be performed to selectively precharge the bit lines based on the set data in the latches, and a sensing operation SS may be performed to sense the voltage or current of the memory cells. Even during the fifth sub-verification operation P5, the selective precharge operation SEL_PRE is performed, and thus the set operation SET, precharge operation BL_PRE, and sensing operation SS may be performed sequentially.

[0124] During the fourth sub-verification operation P4 to the first sub-verification operation P1 of the non-selective precharge operation ALL_PRE, a non-selective precharge circuit (eg, Figure 5 All bit lines are precharged simultaneously using the non-selective precharge circuit ALL_PC. For example, during the fourth sub-verification operation P4, a precharge operation BL_PRE for precharging all bit lines simultaneously and a sensing operation SS for sensing the voltage or current of a memory cell may be sequentially performed. During the fourth sub-verification operation P4 to the first sub-verification operation P1, all bit lines are precharged using the non-selective precharge circuit ALL_PC, and thus the set operation SET may be omitted.

[0125] Although as an implementation Figure 18 The first main verification operation MV1 is illustrated in FIG. 2 , but when a program operation is performed on a selected page, even during the remaining main verification operations, a selective precharge operation SEL_PRE may be performed and then a non-selective precharge operation ALL_PRE may be performed.

[0126] Figure 19 is a diagram illustrating a verification operation according to the fourth embodiment of the present disclosure.

[0127] Reference Figure 19 , when the reference number Pref of verification operations is set to "1", the selective precharge operation SEL_PRE may be performed only during the j-th sub-verification operation Pj among the j-th sub-verification operation Pj to the first sub-verification operation P1 performed in the first main verification operation MV1. During the remaining sub-verification operations (i.e., the j-1-th sub-verification operation Pj-1 to the first sub-verification operation P1), the non-selective precharge operation ALL_PRE may be performed.

[0128] During the j-th sub-verification operation Pj in which the selective precharge operation SEL_PRE is performed, the bit lines may be selectively precharged according to data input to the latch of the page buffer. While the bit lines are selectively precharged, a sensing operation on the selected memory cells may be performed. For example, during the j-th sub-verification operation Pj, a set operation SET may be performed to selectively set data in the latch of the page buffer to select the bit lines to be precharged, a precharge operation BL_PRE may be performed to selectively precharge the bit lines according to the latch set data, and a sensing operation SS may be performed to sense the voltage or current of the memory cells.

[0129] During the j-1th sub-verification operation Pj-1 to the first sub-verification operation P1 of the non-selective precharge operation ALL_PRE, a non-selective precharge circuit (eg, Figure 5 All bit lines are precharged simultaneously using the non-selective precharge circuit ALL_PC. For example, during the j-1th sub-verification operation Pj-1, a precharge operation BL_PRE for precharging all bit lines simultaneously and a sensing operation SS for sensing the voltage or current of a memory cell may be sequentially performed. During the j-1th sub-verification operation Pj-1 to the first sub-verification operation P1, all bit lines are precharged using the non-selective precharge circuit ALL_PC, and thus the set operation SET is omitted.

[0130] Although as an implementation Figure 19 The first main verification operation MV1 is illustrated in FIG. 2 , but when a program operation is performed on a selected page, even during the remaining main verification operations, a selective precharge operation SEL_PRE may be performed and then a non-selective precharge operation ALL_PRE may be performed.

[0131] Figure 20 is a diagram illustrating the effect of the program operation according to the third embodiment or the fourth embodiment of the present disclosure.

[0132] Reference Figure 20 , the selective precharge operation SEL_PRE and the non-selective precharge operation ALL_PRE may commonly include the precharge operation BL_PRE and the sensing operation SS, but the selective precharge operation SEL_PRE further includes a set operation SET.

[0133] It is assumed that an operation time required to perform the program operations of the third to first sub-verification operations P3 to P1 based on only the selective precharge operation SEL_PRE is a first program operation time tPROG1 , and a current consumption at this time is a first current consumption CR1 .

[0134] Assuming that the operation time required to perform the programming operation from the third sub-verification operation P3 to the first sub-verification operation P1 based only on the non-selective precharge operation ALL_PRE is the second programming operation time tPROG2, and the current consumption at this time is the second current consumption CR2, then the second programming operation time tPROG2 can be shorter than the first programming operation time tPROG1, and the second current consumption CR2 can be greater than the first current consumption CR1.

[0135] As in the present embodiment, assuming that the operation time required for the program operation in which the selective precharge operation SEL_PRE and the non-selective precharge operation ALL_PRE coexist is the third program operation time tPROG3, and the current consumption at this time is the third current consumption CR3, the third program operation time tPROG3 may be longer than the second program operation time tPROG2 and shorter than the first program operation time tPROG1. The third current consumption CR3 may be smaller than the second current consumption CR2 and larger than the first current consumption CR1.

[0136] That is, in this embodiment, the selective precharge operation SEL_PRE and the non-selective precharge operation ALL_PRE can be controlled by adjusting the reference number Pref of the verification operation, so the performance of the memory device can be improved by controlling the time required for the program operation of the memory device and the current consumption occurring during the program operation.

[0137] Figure 21 is a diagram illustrating a page buffer controller according to an embodiment of the present disclosure.

[0138] Reference Figure 21 , the page buffer controller 190 may include a verification counter VFC, a selective precharge controller SEL_PRE_CON, a non-selective precharge controller ALL_PRE_CON, and a signal output circuit SIG_OUT.

[0139] The verification counter VFC can count the number of sub-verification operations based on the verification information VFIF and can output a count value CV. The verification information VFIF may include information about the number of loops performed during the programming operation (i.e., loop count) and information about the verification voltage change. Whenever the verification voltage change information in the information is changed, the number of sub-verification operations can be counted. Whenever the loop count increases, the count value can be initialized. That is, since the sub-verification operation is performed whenever the verification voltage applied to the selected word line changes, the verification counter VFC can output a count value CV based on the verification voltage change information included in the verification information VFIF. Since the selective precharge operation and the non-selective precharge operation are repeatedly performed in each loop, the verification counter VFC can reset the count value CV to "0" when the loop count changes.

[0140] The selective pre-charge controller SEL_PRE_CON and the non-selective pre-charge controller ALL_PRE_CON can simultaneously receive the count value CV and can respectively compare the count value CV with a reference number for a verification operation. During the verification operation, when the selective pre-charge controller SEL_PRE_CON is activated, the non-selective pre-charge controller ALL_PRE_CON can be deactivated, and when the non-selective pre-charge controller ALL_PRE_CON is activated, the selective pre-charge controller SEL_PRE_CON can be deactivated. For example, when the count value CV is less than or equal to the reference number for the verification operation, the selective pre-charge controller SEL_PRE_CON can be activated. When the count value CV is greater than the reference number for the verification operation, the non-selective pre-charge controller ALL_PRE_CON can be activated.

[0141] The activated selective precharge controller SEL_PRE_CON may output a selective control signal SEL_CON, and the activated non-selective precharge controller ALL_PRE_CON may output a non-selective control signal ALL_CON.

[0142] The signal output circuit SIG_OUT may output the page buffer control signal PBSIGS in response to the selective control signal SEL_CON or the non-selective control signal ALL_CON. For example, the signal output circuit SIG_OUT may output the page buffer control signal PBSIGS so that a selective precharge operation is performed in response to the selective control signal SEL_CON, and may output the page buffer control signal PBSIGS so that a non-selective precharge operation is performed in response to the non-selective control signal ALL_CON.

[0143] Figure 22 is a diagram illustrating a memory system including a memory device according to the present disclosure.

[0144] Reference Figure 22 , the memory system 1000 may include a memory device 1100 storing data, and a controller 1200 performing communication between the memory device 1100 and a host 2000 .

[0145] Can be used Figure 1 The memory device 1100 is configured as shown.

[0146] The memory system 1000 may include a plurality of memory devices 1100, each of which may be coupled to the controller 1200 via at least one channel. For example, the plurality of memory devices 1100 may be coupled to one channel. Even if the plurality of channels are coupled to the controller 1200, the plurality of memory devices 1100 may be coupled to the corresponding channels.

[0147] The controller 1200 may perform communication between the host 2000 and the memory device 1100. The controller 1200 may control the memory device 1100 in response to a request from the host 2000, or may perform background operations for improving the performance of the memory system 1000 regardless of a request from the host 2000. The host 2000 may generate requests for various operations and may output the generated requests to the memory system 1000. For example, the requests may include a program request for controlling a program operation, a read request for controlling a read operation, an erase request for controlling an erase operation, and the like.

[0148] The host 2000 can communicate with the memory system 1000 through various interfaces such as: Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0149] Figure 23 is a diagram illustrating a memory system including a memory device according to the present disclosure.

[0150] Reference Figure 23 The memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a controller 1200 , and a card interface 7100 .

[0151] Can be used Figure 1 The memory device 1100 is configured as shown.

[0152] The controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. In an embodiment, the card interface 7100 may be, but is not limited to, a secure digital (SD) card interface or a multimedia card (MMC) interface.

[0153] The card interface 7100 can interface data exchange between the host 60000 and the controller 1200 according to the protocol of the host 60000. In an embodiment, the card interface 7100 can support the Universal Serial Bus (USB) protocol and the Inter-Chip (IC)-USB protocol. Here, the card interface 7100 can refer to hardware that can support the protocol used by the host 60000, software installed in the hardware, or a signal transmission method executed by the hardware.

[0154] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of the microprocessor (μP) 6100.

[0155] The present disclosure can shorten a program operation time and reduce current consumption during a program operation of a memory device, thereby improving performance of the memory device.

[0156] CROSS-REFERENCE TO RELATED APPLICATIONS

[0157] This application claims the benefit of Korean Patent Application No. 10-2020-0078371 filed on June 26, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a memory block coupled to a plurality of bit lines and a plurality of word lines, the memory block including a plurality of memory cells; a voltage generator configured to apply at least one of a program voltage and a verification voltage to a word line selected from among the plurality of word lines; a plurality of page buffers configured to precharge some or all of the plurality of bit lines during a sub-verification operation performed on the memory cells; operation logic configured to output verification information related to a verification operation performed during a program operation in response to a command; as well as A page buffer controller is configured to output a page buffer control signal in response to a selective control signal or a non-selective control signal output according to the verification information, so that the part of the plurality of bit lines is precharged in response to the selective control signal and all of the plurality of bit lines is precharged in response to the non-selective control signal.

2. The memory device according to claim 1, wherein Each of the plurality of page buffers comprises: a non-selective precharge circuit configured to precharge the corresponding bit line to a positive voltage; a sense latch configured to store sense data; a selective precharge circuit configured to selectively precharge a corresponding bit line according to the sensing data stored in the sensing latch; and A discharge circuit is configured to selectively discharge a corresponding bit line according to the sensing data stored in the sensing latch.

3. The memory device according to claim 2, wherein The non-selective pre-charging circuit comprises: A switch is configured to transmit an external positive voltage to the corresponding bit line in response to a bit line precharge signal included in the page buffer control signal.

4. The memory device according to claim 2, wherein When at least one of the selective pre-charge circuit and the discharge circuit is activated, the non-selective pre-charge circuit is deactivated.

5. The memory device according to claim 2, wherein When the selective precharge circuit is activated, the sense data is stored in the sense latch. The memory device according to claim 1 , wherein: The page buffer controller includes: a verification counter configured to output a count value obtained by counting the number of sub-verification operations in response to the verification information; a selective precharge controller configured to compare the count value with a reference number of verification operations and output the selective control signal when the count value is less than or equal to the reference number of verification operations; a non-selective precharge controller configured to compare the count value with a reference number of the verification operation and output the non-selective control signal when the count value is greater than the reference number of the verification operation; and A signal output circuit is configured to output the page buffer control signal so that a selective precharge operation is performed in response to the selective control signal or a non-selective precharge operation is performed in response to the non-selective control signal.

7. A method of operating a memory device, the method comprising the steps of: increasing the threshold voltage of the memory cell; as well as performing a master verify operation to verify the memory cell, wherein the main verification operation includes a plurality of sub-verification operations using different verification voltages, and During a sub-verification operation among the multiple sub-verification operations whose order is within the range of a reference number of verification operations, the bit lines are selectively precharged and then a sensing operation is performed, and during a sub-verification operation whose order is greater than or less than the range of the reference number of verification operations, all of the bit lines are precharged and then the sensing operation is performed.

8. The method according to claim 7, wherein: The step of increasing the threshold voltage of the memory cell increases a program voltage to be applied to a word line coupled to the memory cell.

9. The method according to claim 7, wherein: The plurality of sub-verification operations are sequentially performed using verification voltages that decrease in stages from a verification voltage having a highest level.

10. The method according to claim 7, wherein: The plurality of sub-verification operations are sequentially performed using verification voltages that increase in stages starting from a verification voltage having a lowest level.

11. The method according to claim 7, wherein: The step of selectively precharging the bit lines and then performing the sensing operation includes the following steps: setting the sense latch by transferring sense data stored in a first latch to a sense latch in a page buffer coupled to the bit line, wherein the sense data was stored in the first latch when a previous verification operation was performed; selectively precharging the bit lines according to data stored in the page buffer; and The voltage or current of the bit line is sensed by applying a verification voltage selected from among a plurality of verification voltages to a word line coupled to the memory cell.

12. The method according to claim 11, wherein Selectively precharging the bit lines is configured such that: precharging a bit line connected to a program target memory cell among the memory cells, and A ground voltage is applied to the remaining bit lines.

13. The method according to claim 7, wherein: The step of precharging all the bit lines and then performing the sensing operation includes the following steps: precharging all of the bit lines regardless of data stored in the page buffer; and The voltage or current of the bit line is sensed by applying a verification voltage selected from among a plurality of verification voltages to a word line coupled to the memory cell.

14. The method according to claim 7, wherein: The reference number of the verification operation is set to a positive integer of 1 or more.

15. A method of operating a memory device, the method comprising the steps of: performing a first sub-verification operation that selectively precharges a bit line according to data stored in the page buffer and verifies a threshold voltage of a memory cell; as well as A second sub-verification operation is performed that precharges all bit lines simultaneously regardless of data stored in the page buffer and verifies threshold voltages of the memory cells.

16. The method according to claim 15, wherein The first sub-verification operation and the second sub-verification operation are performed using different verification voltages.

17. The method according to claim 16, wherein The first sub-verification operation is performed using a first verification voltage, and The second sub-verification operation is performed using a second verification voltage lower than the first verification voltage.

18. The method according to claim 15, wherein The step of performing the first sub-verification operation includes the following steps: setting the sense latch by transferring sensing data stored in a first latch to a sense latch included in the page buffer, wherein the sensing data was stored in the first latch when a previous verification operation was performed; applying one of a precharge voltage and a ground voltage to the bit line according to data stored in the sense latch coupled to the bit line; and A threshold voltage of the memory cell is sensed by applying a verification voltage to a word line coupled to the memory cell.

19. The method according to claim 15, wherein The step of performing the second sub-verification operation includes the following steps: applying a precharge voltage to all the bit lines regardless of data stored in the page buffer; and A threshold voltage of the memory cell is sensed by applying a verification voltage to a word line coupled to the memory cell.

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