Semiconductor wafer support device, processing system and semiconductor wafer transfer method

Abstract

This disclosure provides a semiconductor wafer support device, a processing system, and a semiconductor wafer transfer method. The semiconductor wafer support device includes a lifting pin. The lifting pin has a first end configured to contact the back side of the semiconductor wafer and at least one stress-reducing feature. The stress-reducing feature is configured to reduce the contact stress between the lifting pin and the wafer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor wafer support device, a semiconductor wafer processing system, and a semiconductor wafer transfer method, and particularly to a semiconductor wafer support device, a semiconductor wafer processing system, and a semiconductor wafer transfer method including a lifting pin with stress reduction characteristics. Background Technology

[0002] To fabricate devices on semiconductor wafers, numerous unit operations (such as masking, etching, deposition, implantation, etc.) are performed. Semiconductor wafers can be transported between unit operations during device fabrication. Storage containers, such as front-opening unified pods (FOUPs), can be used to transport semiconductor wafers to and from each unit operation. Robotic arms can be used to load and unload semiconductor wafers from FOUPs. Transfer blades attached to an articulated robotic arm can be positioned beneath the wafer to lift it into and remove it from the FOUP. When a semiconductor wafer is transported to a unit operation, the articulated robotic arm can lift the wafer from the FOUP and transport it to a chuck for the unit operation. After the unit operation is completed, the robotic arm loads the semiconductor wafer back into the FOUP for transport to the next unit operation. Summary of the Invention

[0003] This disclosure provides a semiconductor wafer support device, including: a lifting pin configured to contact the back side of a semiconductor wafer. At least one of the lifting pins includes a support post configured to support the semiconductor wafer. The support post includes a first end and a second end. The lifting pin also includes a stress-reducing element connected to either the first or second end of the support post to reduce contact stress between the lifting pin and the semiconductor wafer. The stress-reducing element includes an elastic segment.

[0004] This disclosure provides a semiconductor wafer fabrication system, including: an articulated robotic arm having a first end and a second end, a transfer blade located at the first end of the articulated robotic arm, and semiconductor processing unit operation. The semiconductor processing unit operation includes a semiconductor wafer support device. The semiconductor wafer support device includes a lifting pin configured to contact the back side of a semiconductor wafer. At least one of the lifting pins includes a support post configured to support the semiconductor wafer. The support post includes a first end and a second end. The lifting pin also includes a stress-reducing element connected to either the first or second end of the support post to reduce contact stress between the lifting pin and the semiconductor wafer. The stress-reducing element includes at least one stress-reducing feature.

[0005] This disclosure provides a semiconductor wafer transfer method, including: lifting a semiconductor wafer with a first semiconductor wafer support device. The first semiconductor wafer support device includes a lifting pin configured to contact the back side of the semiconductor wafer. At least one of the lifting pins includes a support post configured to support the semiconductor wafer. The support post includes a first end and a second end. The lifting pin also includes a stress-reducing element connected to either the first or second end of the support post to reduce contact stress between the lifting pin and the semiconductor wafer. The stress-reducing element may include an elastic segment. A transfer blade is manipulated below the semiconductor wafer. The lifting pin of the first semiconductor wafer support device is lowered such that the semiconductor wafer is supported by the transfer blade. The semiconductor wafer is transferred from a first position to a second position using the transfer blade. Attached Figure Description

[0006] The concepts of embodiments of this disclosure will be better understood by referring to the following detailed description and the accompanying drawings. It should be noted that, according to standard practice in the art, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity. Similar features are designated with similar reference numerals throughout the specification and drawings.

[0007] Figure 1 A perspective view is shown of an electrostatic chuck with wafer support lift pins extending and supporting a semiconductor wafer, according to some embodiments.

[0008] Figure 2 A vertical cross-sectional view is shown of an electrostatic chuck having a wafer support lifting pin including a spring, according to some embodiments.

[0009] Figure 3 Illustrations based on some embodiments Figure 2 A close-up view of the wafer support lifting pin.

[0010] Figure 4A A side view of another wafer support lifting pin according to some embodiments is shown.

[0011] Figure 4B Illustrations based on some embodiments Figure 4A The vertical cross-sectional view of the wafer support lifting pin shown.

[0012] Figures 5A to 5C A side view of another wafer support lifting pin according to some embodiments is shown.

[0013] Figure 6A A plan view of a semiconductor wafer transfer system according to some embodiments is shown.

[0014] Figure 6B The following is shown along line AA' according to some embodiments. Figure 6AA vertical cross-sectional view of the wafer transfer system.

[0015] Figure 7 A horizontal sectional view showing a cross-section of a bundled device having a semiconductor wafer transfer system according to some embodiments.

[0016] Figure 8 A flowchart illustrating a method for transferring a semiconductor wafer according to some embodiments is shown.

[0017] The annotations in the attached figures are explained as follows:

[0018] 100: Semiconductor wafer support device

[0019] 102: Base

[0020] 104: Top surface

[0021] 106: Opening

[0022] 107: Support column

[0023] 107A: First end

[0024] 107B: Second end

[0025] 108: Lifting Pin

[0026] 109: Back

[0027] 110: Semiconductor wafers

[0028] 112: Spring

[0029] 114: Elastic cover

[0030] 116a, 116b, 116c: Tip

[0031] 200: Semiconductor Wafer Processing System

[0032] 201: Outer shell

[0033] 202: Wafer Transfer Equipment

[0034] 203: First End

[0035] 204: Articulated robotic arm

[0036] 205: Second end

[0037] 208: Transfer Blade

[0038] 209-1: First Front-Opening Teleport Box (Front-Opening Teleport Box)

[0039] 209-2: Second front-opening teleportation box (front-opening teleportation box)

[0040] 210: Semiconductor processing unit operation

[0041] 220: Beam-type equipment

[0042] 222: Entrance

[0043] 224: Exports

[0044] 300: Method

[0045] 302, 304, 306, 308: Step 6

[0046] AA': line

[0047] Φ: Spherical angle Detailed Implementation

[0048] It should be understood that the following disclosure provides many different embodiments or examples to implement different features of the embodiments of this disclosure. Specific examples of components and configurations are described below to simplify the description of the embodiments of this disclosure. Of course, these specific examples are merely illustrative and not intended to limit the embodiments of this disclosure. For example, in the following description, reference to a first feature being formed on or above a second feature indicates that it may include embodiments where the first and second features are in direct contact, or embodiments where additional features are formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations described.

[0049] In addition, spatially related terms may be used herein. For example, terms such as “below,” “under,” “lower,” “above,” “higher,” and similar terms are used to describe the relationship between one element or feature shown in the accompanying drawings and another element(s). Besides the orientations shown in the accompanying drawings, these spatially related terms are intended to include different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related terms used herein may be interpreted in the same way.

[0050] In general, the structures and methods disclosed herein can be used to transfer semiconductor wafers and perform cell operations on semiconductor wafers, while reducing damage to semiconductor wafers caused by rear lifting pins during loading and unloading of wafers from an electrostatic chuck (ESC).

[0051] As described above, numerous unit operations (e.g., masking, etching, deposition, implantation, etc.) can be performed on semiconductor wafers to fabricate devices on the semiconductor wafers. Semiconductor wafers can be transferred between unit operations during device fabrication. To transport semiconductor wafers to and from each unit operation, storage containers, such as front-opening unified (or universal) containers (front-opening transfer cassettes), can be used. Alternatively, a beamforming device can allow a robotic arm to transfer semiconductor wafers to different chambers within the beamforming device. Each chamber of the beamforming device can perform a different unit operation. A robotic arm can be used to load and remove semiconductor wafers from a front-opening transfer cassette, or to load and remove semiconductor wafers from different chambers within the beamforming device. Transfer blades attached to an articulated robotic arm can be positioned below the wafer and used to lift the semiconductor wafer. When transporting semiconductor wafers to a unit operation, the articulated robotic arm can transport the semiconductor wafers to an electrostatic chuck for the unit operation. When transporting a semiconductor wafer to an electrostatic chuck, the wafer is lowered onto a lifting pin of the chuck. The lifting pin can retract, further lowering the wafer onto the surface of the chuck. After the cell operation is completed, the lifting pin can be raised to lift the semiconductor wafer from the surface of the chuck, allowing an articulated robotic arm to load the wafer back into the front-opening transfer cassette for transport to the next cell operation.

[0052] Each time a semiconductor wafer is lowered onto the lift pin and each time the lift pin lifts the wafer away from the electrostatic chuck, the wafer may be damaged by the forces exerted on it by the lift pin. Damage to the semiconductor wafer can affect subsequent layers deposited on the front side of the wafer. Subsequent epitaxial layers may be more sensitive to wafer damage than non-epitaxy layers. For example, epitaxial layer defects may form due to substrate lattice dislocations that occur when the lift pin strikes the semiconductor wafer. Oxygen may be precipitated, potentially forming silicon oxide defects.

[0053] Furthermore, subjecting semiconductor wafers to high temperatures (such as those used in deposition and ion implantation unit operations) may reduce wafer rigidity. As a result, heated semiconductor wafers may be more susceptible to mechanical damage due to the repeated lifting and lowering performed by the electrostatic chuck's lifting pins.

[0054] In some embodiments, the electrostatic chuck is provided with a lifting pin, which includes a spring contacting the bottom end of the lifting pin. When a semiconductor wafer is loaded onto and / or lifted from the electrostatic chuck by the lifting pin of this embodiment, the spring included in the lifting pin can compress and absorb some of the stress that would otherwise be applied to the semiconductor wafer. In other embodiments, the tip of the lifting pin may be provided with a resilient cap. Similar to the lifting pin of the embodiment with a spring, the resilient cap can compress and absorb some of the stress that would otherwise be applied to the semiconductor wafer. In other embodiments, the lifting pin may be provided with a more rounded tip than a conventional lifting pin. That is, instead of terminating at a single point, the tip of the lifting pin includes a flattened or flattened ellipsoid. In this manner, the lifting pin of this embodiment can provide a larger contact surface area with the back side of the semiconductor wafer. This larger contact surface area can distribute the force applied to the semiconductor wafer by the lifting pin of this embodiment, thereby reducing the contact stress for a given contact force.

[0055] Figure 1 A perspective view of a semiconductor wafer support 100 is shown, which includes one or more stress-reducing electrostatic chucks, as described in more detail below. The stress-reducing features are configured to reduce the contact stress applied to the semiconductor wafer 110 by the lifting pin 108. The semiconductor wafer support 100 includes a base 102, which includes a plurality of openings 106 in its top surface 104. The lifting pin 108 can be extended or retracted through the openings 106 in the top surface 104 of the base 102. The lifting pin 108 may have an end configured to contact the back surface 109 of the semiconductor wafer 110. See below for reference. Figures 2 to 5C As detailed below, the lifting pin 108 may include a support post 107 having a first end 107A and a second end 107B. The lifting pin 108 may also include a stress-reducing element. In some embodiments, the stress-reducing element may be located at the first end 107A of the support post 107. However, in other embodiments, the stress-reducing element may also be located at the second end 107B of the support post 107. See below for further details. Figures 2 to 5C The detailed description states that the stress-reducing element can be an elastic segment or can be integrally formed with the support column 107.

[0056] During operation, the lifting pin 108 can extend when receiving the semiconductor wafer 110. The lifting pin 108 can then retract to lower the semiconductor wafer 110 to the top surface 104 of the substrate 102 of the semiconductor wafer support 100. Once the semiconductor wafer 110 engages the top surface 104 of the substrate 102 of the semiconductor wafer support 100, cell operations of the device process can be performed. After performing the cell operation, the semiconductor wafer 110 can be lifted by the lifting pin 108 away from the top surface 104 of the substrate 102 of the semiconductor wafer support 100, thereby allowing a transfer blade (not shown, but described in detail below) to be inserted to contact the back surface 109 of the semiconductor wafer 110. Once the transfer blade engages the back surface 109 of the semiconductor wafer 110, the semiconductor wafer 110 can be moved to the next chamber of the bundling apparatus or to a storage cassette, such as a front-opening transfer cassette. Cell operations can include, but are not limited to, masking, deposition, etching, chemical mechanical polishing, ion implantation, or cleaning.

[0057] Figure 2 and Figure 3 A lifting pin 108 with stress-reducing features is shown as an embodiment. (As shown) Figure 2 and Figure 3 As shown, before inserting the lifting pin 108 into the opening 106, an elastic element, such as a spring 112, can be disposed within the opening 106 of the base 102 of the semiconductor wafer support device 100. As described above, the lifting pin 108 may include a support post 107 and a stress-reducing element (e.g., spring 112). The support post 107 may be configured to support the semiconductor wafer 110. The stress-reducing element (spring 112 in this embodiment) is connected to a first end 107A of the support post 107 to reduce the contact stress between the lifting pin 108 and the semiconductor wafer 110. In an alternative embodiment, the spring 112 may be integrally formed with the lifting pin 108. In another alternative embodiment, the spring 112 may be sized to insert into a cavity (not shown) formed in the first end 107A of the support post 107. In yet another alternative embodiment, the spring 112 may be integrally formed with the bottom surface of the opening 106 and configured to contact the first end 107A of the support post 107 of the lifting pin 108.

[0058] The semiconductor wafer 110 can be placed on the lifting pin 108 (or the lifting pin 108 can be used to lift the semiconductor wafer 110 away from the top surface 104 of the base 102 of the semiconductor wafer support device 100). Figure 2 and Figure 3 In the illustrated embodiment of the lifting pin 108, the spring 112 can be compressed due to the weight of the semiconductor wafer 110, thereby absorbing some contact stress. In some embodiments, the spring 112 has a diameter between 7 × 10⁻⁶ and 10⁻⁶ mm. 3 kg / mm 2 Up to 8×10 3kg / mm 2 The lateral elastic constant is within the range of 19 × 10⁻⁶. 3 kg / mm 2 Up to 21×10 3 kg / mm 2 The spring constant is within the range specified in the manual, but larger or smaller spring constants may also be used in various embodiments of this disclosure. The spring constant can vary based on the material used to form the spring. Different materials may have different shear moduli. Additionally, the coiling of the spring 112 may affect the spring constant. The force F that the spring 112 can absorb can be determined by the following equation:

[0059] F = -kx

[0060] Where k is the elastic constant and x is the spring displacement.

[0061] In both cases where the semiconductor wafer 110 is placed on the lifting pin 108 or lifted from the electrostatic chuck by raising the lifting pin 108, the spring 112 can act as a buffer to absorb contact stress and mitigate damage to the semiconductor wafer 110. For example, mechanical contact forces exceeding 5.1 megapascal (GPa) may damage the semiconductor wafer 110. By providing the spring 112, contact stress can be absorbed and damage to the semiconductor wafer 110 can be mitigated.

[0062] Figure 4A This is a side view of the lifting pin 108 according to another embodiment, and Figure 4B yes Figure 4A A cross-sectional view of the lifting pin 108 in the illustrated embodiment. Figure 4A and Figure 4B The lifting pin 108 in the illustrated embodiment may include another stress-reducing element. The stress-reducing element in this embodiment includes a resilient segment, such as a resilient cover 114. In these embodiments, the resilient cover 114 may be disposed above the second end 107B of the support post 107 of the lifting pin 108. The semiconductor wafer 110 may be placed on the resilient cover 114 of the lifting pin 108 (or the lifting pin 108 may be used to lift the semiconductor wafer 110 from the top surface 104 of the semiconductor wafer support device 100). Figures 4A to 5CIn the illustrated embodiment, the resilient cover 114 is compressible due to the weight of the semiconductor wafer 110, thereby absorbing at least a portion of the contact stress applied to the semiconductor wafer 110. In some embodiments, the elastic modulus of the material used to form the resilient cover 114 may vary in a direction perpendicular to the main axis of the lifting pin 108. In some embodiments, the elastic modulus of the portion of the resilient cover 114 away from the surface of the support post 107 may be greater than that of the portion of the resilient cover 114 approaching the surface of the support post 107. In some embodiments, the resilient cover 114 may be made of a porous material. The elastic modulus can be changed by varying the amount of porosity in the resilient cover 114, where greater porosity generally results in a lower elastic modulus. In some embodiments, the elastic modulus of the resilient cover 114 may be in the range of 50 GPa to 140 GPa, but materials with larger or smaller elastic moduli may also be used.

[0063] Equation 1 can be used to determine the magnitude of the contact force that can be reduced by using an elastic cover, i.e., the magnitude of the force applied to the semiconductor wafer 110 by the lifting pin 108.

[0064]

[0065] In addition, Equation 2 can be used to determine the effective modulus E. eff :

[0066]

[0067] Where F N It is the normal force, D0 is the diameter of the lifting pin 108, E eff It is the effective modulus, ν is the Poisson ratio, and E n It is the Young's modulus of the elastic cover 114 of the semiconductor wafer 110 and the lifting pin 108. Normal force F N It is the force that lifts the semiconductor wafer 110.

[0068] The Poisson's ratio of a material is a measure of how much it expands or contracts in a direction perpendicular to the loading direction. Young's modulus is a measure of the amount of stress that causes a specific strain in a material. In other words, Young's modulus is a measure of hardness. The higher the Young's modulus, the harder the material. Poisson's ratio and Young's modulus are characteristics of the selected materials for the elastic cover 114 of the semiconductor wafer 110 and the lifting pin 108.

[0069] As shown in Equation 1 above, the contact force σ can be reduced by the stress reduction features of various embodiments. c Can be related to normal force F N and effective modulus E eff It is directly proportional to the diameter D0 of the lifting pin 108 and inversely proportional to the diameter D0. Therefore, it can be reduced by decreasing the normal force F.N and / or effective modulus E eff and / or by increasing the diameter D0 of the lifting pin 108 to reduce the contact force σ. c As shown in Equation 2 above, the effective modulus E eff (i.e., following (1-ν) 2 The change in the effective modulus E1 is weakly proportional to the Pausson's ratios ν1 and ν2 of the elastic cover 114 of the semiconductor wafer 110 and the lifting pin 108, but inversely proportional to the Young's modulus E1 and E2 of the elastic cover 114 of the semiconductor wafer 110 and the lifting pin 108. Therefore, the change in Pausson's ratio will affect the effective modulus E1. eff It has a very small effect, while an increase in Young's modulus will reduce the effective modulus E. eff .

[0070] Figures 5A to 5C This is a side view of the lifting pin 108 according to another embodiment. Figures 5A to 5C Additional stress-reducing features may be included. The stress-reducing element may be integrally formed with the support column 107. In various embodiments, the diameter of the support column 107 of the lifting pin 108 may be between 2 mm and 10 mm. However, the diameter of the support column 107 may be increased or decreased as needed.

[0071] exist Figure 5A As shown in the first aspect, the tip 116a disposed on the second end 107B of the support column 107 can have a rounded / flattened shape relative to a conventional lifting pin. The tip 116a can be spherical, or can be slightly flattened into an oblate spheroid. Figure 5A As shown, in the embodiment where the tip 116a is substantially spherical, the spherical angle is essentially 180 degrees. Therefore, the radius of curvature of the tip 116a in this embodiment can be the same as the radius of the support post 107. For example, if the diameter of the support post 107 is 4 mm, then the radius is 2 mm. Using... Figure 5A The tip shown, tip 116a, also has a radius of curvature of 2 mm and a spherical angle of approximately 180 degrees. Therefore, in this embodiment, the radius of curvature of tip 116a can be the same as the radius of the support column 107 (1:1).

[0072] exist Figure 5B In the second aspect shown, the tip 116b provided on the second end 107B of the support column 107 can have a greater than Figure 5A The tip 116a of the illustrated embodiment has greater flatness. In, as... Figure 5BIn the illustrated embodiment, the lifting pin 108 may have a tip 116b, the shape of which can be described as oblate or ellipsoidal. For example, the radius of curvature of the tip 116b may be twice the radius of the support post 107 of the lifting pin 108, resulting in a spherical angle φ of approximately 52.1 degrees. In the exemplary lifting pin 108, the support post 107 has a diameter of 4 mm and a radius of 2 mm, such as... Figure 5B The radius of curvature of the tip 116b shown can be 4 mm, and the spherical angle can be approximately 52.1 degrees. Therefore, in this embodiment, the radius of curvature of the tip 116b can be twice the radius of the support column 107 (2:1).

[0073] exist Figure 5C In the third aspect shown, the tip 116c provided at the second end 107B of the support column 107 may have a greater than Figure 5A Tip 116a of the illustrated embodiment and Figure 5B The tip 116b of the illustrated embodiment has greater flatness. That is, the tip 116c has a larger spherical angle. In some embodiments, the radius of curvature can be 5 times the radius of the support post 107 of the lifting pin 108, thereby forming a spherical angle of approximately 24 degrees. In the exemplary lifting pin 108, the diameter of the support post 107 is 4 mm and the radius of the support post is 2 mm, such as... Figure 5C The radius of curvature of the tip 116 shown can be 10 mm, and the spherical angle can be approximately 24 degrees. Therefore, in this embodiment, the radius of curvature of the tip 116c can be five times (5:1) the radius of the support column 107.

[0074] In various embodiments, the radius of curvature of the tips 116a to 116c can be between 1 and 5 times the radius of the support post 107 of the lifting pin 108. In other words, the radius of curvature of the tips 116a to 116c can be (1:1) to (5:1) compared to the radius of the support post 107 of the lifting pin 108. However, the radius of curvature of the tips 116a to 116c can be increased or decreased as needed. Alternatively, the tips 116a to 116c can be described in terms of spherical angle. In various embodiments, the spherical angle of the tips 116a to 116c can be between 24 degrees and 180 degrees. For example, the spherical angle of the tip can be between 50 degrees and 180 degrees. Furthermore, the spherical angle of the tip can be between 90 degrees and 180 degrees. By providing a flatter pin tip 116C (i.e., with a smaller spherical angle φ), the surface area of ​​the tips (116a to 116c) provided on the support post 107 of the lifting pin 108 can be increased. The increased surface area can distribute the force applied to the semiconductor wafer 110 over a larger surface area, thereby reducing contact stress.

[0075] The amount of contact force that can be reduced by using an elastic cover can be determined by using Equation 1, wherein the flat tips 116a to 116c can vary depending on the value of the diameter D0 of the lifting pin 108.

[0076] Figure 6A and Figure 6B A semiconductor wafer processing system 200 according to various embodiments is illustrated. The semiconductor wafer processing system 200 includes a semiconductor wafer transfer apparatus 202 having at least one articulated robotic arm 204. A first end 203 of the articulated robotic arm 204 includes a transfer blade 208, while a second end 205 is rotatably connected to a housing 201. The articulated robotic arm 204 can be configured to rotate and translate to facilitate the transfer of a semiconductor wafer 110. The transfer blade 208 can be configured to lift and support the semiconductor wafer 110 during transfer from a first front-opening transfer cassette 209-1 to a cell operation 210 in a semiconductor process. The cell operation can be, but is not limited to, masking, deposition, etching, chemical mechanical polishing (CMP), ion implantation, or cleaning. After performing the desired cell operation processing step, the semiconductor wafer 110 can be removed from the cell operation by the same or different articulated robotic arms 204. On one hand, the semiconductor wafer 110 can be transferred to a second front-opening transfer box 209-2. The second front-opening transfer box 209-2 can be manually or mechanically transported to the next unit operation 210 via a track system (not shown). On the other hand, the semiconductor wafer processing system 200 can be part of a bundled device (not shown) comprising multiple unit operations 210 within a cluster. In this respect, the semiconductor wafer transfer device 202 can transfer the semiconductor wafer 110 from one unit operation 210 within the same cluster to the next unit operation 210 without using a front-opening transfer box.

[0077] like Figure 6B As shown, a semiconductor wafer 110 supported on a transfer blade 208 of a wafer transfer apparatus 202 can be manipulated such that the semiconductor wafer 110 is positioned above a lifting pin 108 of a semiconductor wafer support device 100 (e.g., an electrostatic chuck) connected to unit operation 210. The lifting pin 108 can be raised to support the semiconductor wafer 110. Once the semiconductor wafer 110 is supported by the lifting pin 108, the transfer blade 208 can be removed. The lifting pin 108 may include reference... Figures 2 to 5C Any stress reduction features disclosed. For example, Figure 6B A lifting pin 108 equipped with a spring 112 is shown. The semiconductor wafer 110 can then be lowered to the top surface 104 of the semiconductor wafer support device 100 (e.g., an electrostatic chuck).

[0078] Figure 7 A beam-type device 220 is shown, which includes the wafer transfer device 202 as described above. Figure 7 As shown, the beamforming device 220 can be configured for four unit operation chambers 210. Each unit operation can be performed in a unit operation chamber 210. However, the beamforming device 220 can be configured for more or fewer unit operation chambers 210. The beamforming device 220 can be configured with a separate inlet 222 and a separate outlet 224, such that unprocessed semiconductor wafers 110 can be supplied to the beamforming device 220 through a separate inlet 222, and processed semiconductor wafers 110 can be removed from the beamforming device 220 through a separate outlet 224.

[0079] Figure 8 A flowchart illustrating a method 300 for transferring a semiconductor wafer 110 according to some embodiments is shown. Referring to step 302, the semiconductor wafer 110 can be lifted using a first semiconductor wafer support device 100. The first semiconductor wafer support device 100 may include a plurality of lifting pins 108 configured to contact the back surface 109 of the semiconductor wafer 110. At least one of the lifting pins 108 includes a support post 107 configured to support the semiconductor wafer 110. The support post 107 includes a first end 107A and a second end 107B. The lifting pins 108 also include Figures 2 to 5C The stress-reducing elements shown (e.g., spring 112, resilient cover 114, rounded tips 116A, 116B, and 116C) are connected to either the first end 107A or the second end 107B of the support post 107 to reduce the contact stress between the lifting pin 108 and the semiconductor wafer 110. The stress-reducing elements may include resilient segments or be integrally formed with the support post. Referring to step 304, the transfer blade 208 can be manipulated below the semiconductor wafer 110. Referring to step 306, the lifting pin 108 can be lowered so that the semiconductor wafer 110 is supported by the transfer blade 208. Referring to step 308, the semiconductor wafer 110 can be transferred from a first position to a second position using the transfer blade 208. In some embodiments, the first position may be a first semiconductor processing unit operation 210, and the second position may be a front-opening transfer box 209-2.

[0080] In some embodiments, the semiconductor wafer 110 can be transferred from a second position to a third position. In some embodiments, the second position may be a front-opening transfer cassette 209-1, and the third position may be a second unit operation 210. This method may include removing the semiconductor wafer 110 from the front-opening transfer cassette 209-1 using a transfer blade 208, maneuvering the semiconductor wafer 110 from the front-opening transfer cassette 209-1 to the second semiconductor processing unit operation 210, and lifting the second semiconductor wafer support device 100 to support the semiconductor wafer 110. The second unit operation 210 may include the second semiconductor wafer support device 100, which is configured to support the wafer 110. The second semiconductor wafer support device 100 may include a second lifting pin 108, which is configured to contact the back surface 109 of the semiconductor wafer 110 and Figures 2 to 5C At least one second stress-reducing feature is shown (e.g., spring 112, elastic cover 114, rounded tips 116a, 116b, and 116c). At least one second stress-reducing feature can be configured to reduce contact stress between the second lifting pin 108 and the semiconductor wafer 110. At least one second stress-reducing feature similar to the first stress-reducing feature may include a spring 112 configured to contact the first end 107a of the support post 107, an elastic cover 114 covering the first end 107a of the support post 107, the first end 107a of the support post 107 having a flattened spherical shape (116a to 116c), or a combination thereof.

[0081] Generally, the structures and methods disclosed herein can be used to transfer and perform unit operations 210 on a semiconductor wafer 110 while reducing damage to the semiconductor wafer 110 caused by the lifting pin 108 during loading and unloading of the semiconductor wafer 110 from a semiconductor wafer support device 100 (e.g., an electrostatic chuck). Reducing damage to the semiconductor wafer 110 further reduces the impact of a damaged semiconductor wafer on the layers deposited on the semiconductor wafer (particularly epitaxial layers). In some embodiments, the semiconductor wafer support device 100 may be provided with a spring 112 that contacts the bottom end of a support post 107. When the semiconductor wafer 110 is loaded / lifted onto the lifting pin 108, the spring 112 can compress and absorb a portion of the stress on the semiconductor wafer 110. In another embodiment, the tip of the lifting pin 108 may have an elastic cap 114. Similar to the spring 112 in the previous embodiment, the resilient cover 114 may have an elastic modulus that allows the resilient cover 114 to compress when the semiconductor wafer 110 is loaded / lifted onto the lift pin 108, thereby absorbing a portion of the stress on the semiconductor wafer 110. In another embodiment, the lift pin 108 may have a more rounded tip 116a to 116c than a conventional lift pin. That is, the tip of the support post of the lift pin 108 may be flat or spherical, rather than a point-terminated tip. In this way, the lift pin 108 may have a larger surface area in contact with the back side of the semiconductor wafer 110. A larger contact surface can distribute the force applied to the semiconductor wafer 110 over a larger surface area, thereby reducing contact stress for a given contact force.

[0082] The embodiment relates to a semiconductor wafer support device 100, including a lifting pin 108 configured to contact the back surface 109 of a semiconductor wafer 110. At least one of the lifting pins 108 includes a support post 107 configured to support the semiconductor wafer 110. The support post 107 includes a first end 107A and a second end 107B. The semiconductor wafer support device 100 also includes stress-reducing elements (e.g., a spring 112, an elastic cover 114, or rounded tips 116A, 116B, and 116C) connected to either the first end 107A or the second end 107B of the support post 107 to reduce stress. The stress-reducing elements may include an elastic segment (e.g., a spring 112, an elastic cover 114) or be integrally formed with the support post (e.g., rounded tips 116A, 116B, and 116C).

[0083] In some embodiments, the elastic segment includes a spring configured to contact a first end of a support post, a second end of the support post contacting the back surface of a semiconductor wafer, the spring being integrally formed with the support post and configured to absorb at least a portion of the contact stress between the lifting pin and the semiconductor wafer.

[0084] In some embodiments, the spring has a lateral elastic constant between 7 x 10⁻⁶. 3 kg / mm 2 Up to 8x10 3 kg / mm 2 Between, and with a longitudinal elastic constant between 19x10 3 kg / mm 2 Up to 21x10 3 kg / mm 2 between.

[0085] In some embodiments, the elastic segment includes an elastic cover that covers the second end of the support post, the elastic cover absorbing at least a portion of the contact stress between the lifting pin and the semiconductor wafer.

[0086] In some embodiments, the elastic modulus of the elastic cover varies in a direction perpendicular to the main axis of the lifting pin.

[0087] In some embodiments, the resilient cover comprises a porous material.

[0088] In some embodiments, the stress-reducing element is integrally formed with the support column and includes a second end of the support column having an oblate spheroidal shape, wherein the radius of curvature of the stress-reducing element is in the range of 1 to 5 times the radius of the support column.

[0089] In some embodiments, the semiconductor wafer support device further includes an electrostatic chuck, the electrostatic chuck comprising: a substrate configured to support the semiconductor wafer and a plurality of openings located in the substrate, wherein lifting pins are located in the openings and configured to lift the semiconductor wafer from the substrate and lower the semiconductor wafer onto the substrate.

[0090] Another embodiment relates to a semiconductor wafer fabrication system 200, including an articulated robotic arm 204 having a first end and a second end, a transfer blade 208 located at the first end of the articulated robotic arm 204, and a semiconductor fabrication unit operation 210. The semiconductor fabrication unit operation 210 includes a semiconductor wafer support 100. The semiconductor wafer support 100 may include lifting pins 108 configured to contact the back surface 109 of a semiconductor wafer 110. At least one of the lifting pins 108 includes a support post 107 configured to support the semiconductor wafer 110. The support post 107 includes a first end 107A and a second end 107B. The semiconductor wafer support 100 also includes stress-reducing elements (e.g., a spring 112, an elastic cover 114, rounded tips 116A, 116B, and 116C) connected to either the first end 107A or the second end 107B of the support post 107 to reduce contact stress between the lifting pins 108 and the semiconductor wafer 110. Stress-reducing elements may include elastic segments (e.g., spring 112, elastic cover 114) or be integrally formed with support columns (e.g., rounded tips 116A, 116B and 116C).

[0091] In some embodiments, the stress reduction features include: a spring that contacts a first end of a support post, wherein a second end of the support post contacts the back surface of a semiconductor wafer, the spring being configured to absorb at least a portion of the contact stress between the lifting pin and the semiconductor wafer; or an elastic cover that covers the second end of the support post, wherein the elastic cover absorbs at least a portion of the contact stress between the lifting pin and the semiconductor wafer; or the first end of the support post having an ellipsoidal shape; or a combination of the foregoing.

[0092] In some embodiments, the articulated robotic arm is configured to rotate and translate.

[0093] In some embodiments, the semiconductor wafer processing system further includes a beamforming device.

[0094] Another embodiment relates to a method 300 for transferring a semiconductor wafer 110, including lifting the semiconductor wafer 110 with a first semiconductor wafer support device 100. The semiconductor wafer 110 can be lifted using the first semiconductor wafer support device 100. The semiconductor wafer support device 100 may include lifting pins 108 configured to contact a back surface 109 of the semiconductor wafer 110. At least one of the lifting pins 108 includes a support post 107 configured to support the semiconductor wafer 110. The support post 107 includes a first end 107A and a second end 107B. The lifting pins 108 also include... Figures 2 to 5CThe stress-reducing elements shown (e.g., spring 112, resilient cover 114, rounded tips 116A, 116B, and 116C) are connected to either the first end 107A or the second end 107B of the support post 107 to reduce contact stress between the lifting pin 108 and the semiconductor wafer 110. The stress-reducing elements may include a resilient segment or be integrally formed with the support post. The transfer blade 208 can be manipulated below the semiconductor wafer 110. The lifting pin 108 can be lowered so that the semiconductor wafer 110 is supported by the transfer blade 208. Referring to step 308, the semiconductor wafer 110 can be transferred from a first position to a second position using the transfer blade 208.

[0095] In some embodiments, the method further includes absorbing contact stress by compressing a plurality of springs at the first end of the contact support column.

[0096] In some embodiments, the method further includes absorbing contact stress by compressing an elastic cap covering the second end of the support column.

[0097] In some embodiments, lifting a semiconductor wafer with a first semiconductor wafer support device includes contacting the semiconductor wafer with a lifting pin having a flattened ellipsoidal shape at a first end of the lifting pin.

[0098] In some embodiments, the first position includes operation of a first semiconductor processing unit, and the second position includes a front-opening transfer box.

[0099] In some embodiments, the method further includes transferring a semiconductor wafer from a second position to a third position by: removing the semiconductor wafer from a front-opening transfer cassette with a transfer blade; maneuvering the semiconductor wafer from the front-opening transfer cassette to a second semiconductor processing unit; and raising a second semiconductor wafer support to support the semiconductor wafer, the second semiconductor wafer support including: a plurality of second lifting pins including: a support post configured to support the semiconductor wafer, the support post including a first end and a second end; and at least one stress-reducing element connected to one of the first end and the second end of the support post to reduce contact stress between the second lifting pins and the semiconductor wafer, wherein the stress-reducing element includes at least one second stress-reducing feature.

[0100] In some embodiments, the second stress-reducing feature includes: a spring configured to contact the support post, wherein the spring is integrally formed with the support post and configured to absorb at least a portion of the contact stress between the first end of the second lifting pin and the semiconductor wafer; or an elastic cover covering the second end of the support post, wherein the elastic cover absorbs at least a portion of the contact stress between the second lifting pin and the semiconductor wafer; or the first end of the support post has an ellipsoidal shape; or a combination of the foregoing.

[0101] In some embodiments, the first semiconductor processing unit is configured to perform one of masking, deposition, etching, chemical mechanical polishing, ion implantation, or cleaning.

[0102] The foregoing has outlined the features of numerous embodiments to enable those skilled in the art to better understand the various embodiments of this disclosure. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of this disclosure to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of this disclosure. Various changes, substitutions, and modifications can be made to the embodiments of this disclosure without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor wafer support apparatus, comprising: a plurality of lift pins configured to contact a back surface of a semiconductor wafer, wherein at least one of the plurality of lift pins comprises: a support post configured to support the semiconductor wafer, the support post comprising a first end and a second end; and a stress reduction element coupled to one of the first end and the second end of the support post to reduce a contact stress between the plurality of lift pins and the semiconductor wafer, wherein the stress reduction element comprises an elastic section comprising an elastic cap covering the second end of the support post, an elastic modulus of the elastic cap varying in a direction perpendicular to a major axis of the plurality of lift pins, and an elastic modulus of a portion of the elastic cap distal from a surface of the support post being greater than an elastic modulus of a portion of the elastic cap proximal to the surface of the support post.

2. The semiconductor wafer support apparatus of claim 1, wherein the elastic section comprises a spring configured to contact the first end of the support post, the second end of the support post contacting the back surface of the semiconductor wafer, the spring being integral with the support post and configured to absorb at least a portion of the contact stress between the plurality of lift pins and the semiconductor wafer.

3. The semiconductor wafer support apparatus of claim 2 wherein the spring has a lateral spring constant between 7 x 10 3 kg / mm 2 and 8 x 10 3 kg / mm 2 and a longitudinal spring constant between 19 x 10 3 kg / mm 2 and 21 x 10 3 kg / mm 2 .

4. The semiconductor wafer support apparatus of claim 1, wherein the elastic cap absorbs at least a portion of the contact stress between the plurality of lift pins and the semiconductor wafer.

5. The semiconductor wafer support apparatus of claim 4, wherein the elastic cap comprises a porous material.

6. The semiconductor wafer support apparatus of claim 1, wherein the stress reduction element is integral with the support post and comprises the second end of the support post having a prolate spheroid shape, a radius of curvature of the stress reduction element being in a range of 1 to 5 times a radius of the support post.

7. The semiconductor wafer support apparatus of claim 1, further comprising an electrostatic chuck, the electrostatic chuck comprising: a base configured to support the semiconductor wafer; and a plurality of openings in the base, wherein the plurality of lift pins are in the plurality of openings and are configured to lift the semiconductor wafer from the base and lower the semiconductor wafer onto the base.

8. A semiconductor wafer processing system, comprising: an articulated robot having a first end and a second end; a transfer blade at the first end of the articulated robot; and a semiconductor processing cell operation comprising a semiconductor wafer support apparatus, the semiconductor wafer support apparatus comprising: a plurality of lift pins configured to contact a back surface of a semiconductor wafer, wherein at least one of the plurality of lift pins comprises: a support post configured to support the semiconductor wafer, the support post comprising a first end and a second end; and a stress reduction element coupled to one of the first end and the second end of the support post to reduce a contact stress between the plurality of lift pins and the semiconductor wafer, wherein the stress reduction element comprises an elastic section comprising an elastic cap covering the second end of the support post, an elastic modulus of the elastic cap varying in a direction perpendicular to a major axis of the plurality of lift pins, and an elastic modulus of a portion of the elastic cap distal from a surface of the support post being greater than an elastic modulus of a portion of the elastic cap proximal to the surface of the support post. ​ a stress reduction element coupled to one of the first end and the second end of the support post to reduce a contact stress between the plurality of lift pins and the semiconductor wafer, wherein the stress reduction element comprises at least one stress reduction feature, the stress reduction feature comprising a resilient cap covering the second end of the support post, the resilient cap having a modulus of elasticity that varies in a direction perpendicular to a major axis of the plurality of lift pins, and a portion of the resilient cap distal to a surface of the support post having a greater modulus of elasticity than a portion of the resilient cap proximal to the surface of the support post.

9. The semiconductor wafer processing system of claim 8, wherein the at least one stress reduction feature comprises: a spring contacting the first end of the support post, wherein the second end of the support post contacts the backside of the semiconductor wafer, the spring configured to absorb at least a portion of the contact stress between the plurality of lift pins and the semiconductor wafer; or the second end of the support post having a prolate spheroid shape; or a combination thereof.

10. The semiconductor wafer processing system of claim 9, wherein the articulated robotic arm is configured to rotate and translate.

11. The semiconductor wafer processing system of claim 10, further comprising a cluster tool.

12. A semiconductor wafer transfer method, comprising: lifting a semiconductor wafer with a first semiconductor wafer support apparatus, the first semiconductor wafer support apparatus comprising: a plurality of lift pins configured to contact a backside of a semiconductor wafer, wherein at least one of the plurality of lift pins comprises: a support post configured to support the semiconductor wafer, the support post comprising a first end and a second end; and a stress reduction element coupled to one of the first end and the second end of the support post to reduce a contact stress between the plurality of lift pins and the semiconductor wafer, wherein the stress reduction element comprises a resilient section comprising a resilient cap covering the second end of the support post, the resilient cap having a modulus of elasticity that varies in a direction perpendicular to a major axis of the plurality of lift pins, and a portion of the resilient cap distal to a surface of the support post having a greater modulus of elasticity than a portion of the resilient cap proximal to the surface of the support post; manipulating a transfer blade under the semiconductor wafer; lowering the plurality of lift pins of the first semiconductor wafer support apparatus such that the semiconductor wafer is supported by the transfer blade; and transferring the semiconductor wafer from a first location to a second location with the transfer blade.

13. The semiconductor wafer transfer method of claim 12, further comprising absorbing the contact stress by compressing a plurality of springs contacting the first end of the support post.

14. The semiconductor wafer transfer method of claim 12, further comprising absorbing the contact stress by compressing the resilient cap covering the second end of the support post.

15. The semiconductor wafer transfer method of claim 12, wherein lifting the semiconductor wafer with the first semiconductor wafer support apparatus comprises contacting the semiconductor wafer with the plurality of lift pins having a prolate spheroid shape at the second end of the plurality of lift pins.

16. The semiconductor wafer transfer method of claim 12, wherein the first location comprises a first semiconductor processing unit operation, and the second location comprises a front opening unified pod.

17. The semiconductor wafer transfer method of claim 16, further comprising transferring the semiconductor wafer from the second location to a third location by: removing the semiconductor wafer from the front opening unified pod with the transfer blade; manipulating the semiconductor wafer from the front opening unified pod to a second semiconductor processing unit operation; and lifting a second semiconductor wafer support device to support the semiconductor wafer, the second semiconductor wafer support device comprising: a plurality of second lift pins comprising: a support post configured to support the semiconductor wafer, the support post comprising a first end and a second end; and at least one stress reducing element coupled to one of the first end and the second end of the support post to reduce a contact stress between the plurality of second lift pins and the semiconductor wafer, wherein the stress reducing element comprises at least one second stress reducing feature.

18. The semiconductor wafer transfer method of claim 17, wherein the at least one second stress reducing feature comprises: a spring configured to contact the support post, wherein the spring is integral with the support post and is configured to absorb at least a portion of a contact stress between the first end of the plurality of second lift pins and the semiconductor wafer; or a resilient cap covering the second end of the support post, wherein the resilient cap absorbs at least a portion of the contact stress between the plurality of second lift pins and the semiconductor wafer; or the second end of the support post has an oblate spheroid shape; or a combination thereof.

19. The semiconductor wafer transfer method of claim 16, wherein the first semiconductor processing unit operation is configured to perform one of masking, deposition, etching, chemical mechanical polishing, ion implantation, or cleaning.

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