Electroluminescent display substrate, manufacturing method and display device containing the same

Abstract

The present invention discloses an electroluminescent display substrate, a manufacturing method and a display device including the same. In one embodiment, the electroluminescent display substrate includes: a display area, a fan-out area close to the display area and a pad area away from the display area, wherein the VDD signal line and the VSS signal line of the display substrate converge to the pad area through the fan-out area, and the fan-out area includes a covering area and an exposed area arranged in sequence from the display area to the pad area, wherein the covering area covers the VDD signal line, the VSS signal line and the first interlayer insulating layer structure exposed between the VDD signal line and the VSS signal line, and the exposed area exposes the VDD signal line, the VSS signal line and the first interlayer insulating layer structure, and the fan-out area further includes: a groove structure formed in the exposed first interlayer insulating layer structure, wherein the exposed VDD signal line and the VSS signal line protrude toward each other above the groove structure; and a shielding structure protruding from the covering area to above the exposed area.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an electroluminescent display substrate, a manufacturing method and a display device comprising the same. Background Art

[0002] In recent years, with the advancement of technology, displays have become an indispensable part of people's lives, work, leisure, and entertainment. Among them, electroluminescent display substrates, such as AMOLED, are a new flat-panel display technology with great development potential and are attracting significant attention from the industry. They offer advantages such as light weight, high luminous efficiency, low power consumption, self-luminescence, excellent low-temperature characteristics, and flexibility.

[0003] For the cathode on the electroluminescent display substrate, one implementation method is to use a mask for evaporation. As the number of evaporation cycles of the cathode mask increases, the cathode mask will be affected by the temperature of the evaporation chamber and deform due to thermal expansion and contraction, resulting in a larger cathode shadow in the later stages of evaporation. The larger cathode shadow will affect the reliability of the display panel. Another problem is that the fan-out area of ​​the display substrate has a metal trace line connected to the signal input terminal, which has an exposed metal area. A large cathode shadow can cause the exposed metal line to short-circuit with the cathode, resulting in defects. Summary of the Invention

[0004] An object of the present invention is to provide an electroluminescent display substrate, a manufacturing method and a display device including the same, so as to solve at least one of the problems existing in the prior art.

[0005] To this end, a first aspect of the present invention provides an electroluminescent display substrate, comprising:

[0006] a display area, a fan-out area close to the display area, and a pad area far from the display area, wherein the VDD signal line and the VSS signal line of the display substrate converge to the pad area through the fan-out area, and the fan-out area includes a covering area and an exposed area arranged in sequence from the display area to the pad area, wherein the covering area covers the VDD signal line, the VSS signal line, and the first interlayer insulating layer structure exposed between the VDD signal line and the VSS signal line, and the exposed area exposes the VDD signal line, the VSS signal line, and the first interlayer insulating layer structure.

[0007] The fan-out area also includes:

[0008] a trench structure formed in the exposed first interlayer insulating layer structure, wherein the exposed VDD signal line and the exposed VSS signal line protrude toward each other above the trench structure so that cathode metal formed on the exposed VDD signal line and the exposed VSS signal line is disconnected from the cathode metal formed in the trench structure;

[0009] A shielding structure protruding from the covering area to above the exposed area disconnects the cathode metal formed on the covering area from the cathode metal formed on the exposed VDD signal line and the VSS signal line.

[0010] In a specific embodiment, the coverage area includes:

[0011] a first planarization layer structure formed on the VDD signal line and the VSS signal line, wherein the shielding structure is formed on the first planarization layer structure;

[0012] A first pixel defining layer structure covers the blocking structure, wherein the cathode metal formed on the covering area is formed on the first pixel defining layer structure.

[0013] In a specific embodiment, the pad area includes:

[0014] a pad formed on the first interlayer insulating layer structure;

[0015] A second planarization layer structure covers the pad, wherein the second planarization layer structure and the first planarization layer structure are arranged on the same layer.

[0016] In a specific embodiment, it also includes:

[0017] The first barrier wall formed between the covering area and the pad area is used to define the farthest position where the cathode metal extends toward the pad area in the exposed area.

[0018] In a specific embodiment, the first barrier wall comprises:

[0019] A third planarization layer structure, a second pixel definition layer structure and a support structure are stacked in a direction away from the first interlayer insulating layer structure, wherein the third planarization layer structure is arranged on the same layer as the first planarization layer structure, and the second pixel definition layer structure is arranged on the same layer as the first pixel definition layer structure.

[0020] In a specific embodiment, it also includes:

[0021] A second barrier wall is formed between the pad area and the first barrier wall, and the second barrier wall includes a fourth planarization layer structure and a third pixel definition layer structure stacked in a direction away from the first interlayer insulating layer structure, wherein the fourth planarization layer structure is arranged on the same layer as the third planarization layer structure, and the third pixel definition layer structure is arranged on the same layer as the second pixel definition layer structure, and the height of the second barrier wall is less than the height of the first barrier wall.

[0022] In a specific embodiment, a substrate is further included, and the display area includes an active area of ​​a thin film transistor, a gate insulation layer, a gate, a second interlayer insulation layer structure and a first source-drain electrode arranged on the substrate, wherein the first interlayer insulation layer structure and the second interlayer insulation layer structure are arranged on the same layer, and the first source-drain electrode is arranged on the same layer as the VDD signal line and the VSS signal line.

[0023] In a specific embodiment, the display area further includes:

[0024] a fifth planarization layer structure covering the first source-drain electrode, wherein the fifth planarization layer structure and the first planarization layer structure are provided on the same layer;

[0025] a second source-drain electrode formed on the fifth planarization layer structure, wherein the second source-drain electrode is provided on the same layer as the shielding structure;

[0026] A fourth pixel defining layer structure is formed on the second source-drain electrode and an electroluminescent device surrounded by the fourth pixel defining layer, wherein the cathode of the electroluminescent device is arranged in the same layer as the cathode metal, and the fourth pixel defining layer structure is arranged in the same layer as the first pixel defining layer structure.

[0027] A second aspect of the present invention provides a method for manufacturing an electroluminescent display substrate, comprising:

[0028] A display area, a fan-out area close to the display area, and a pad area far from the display area are formed, wherein the VDD signal line and the VSS signal line of the display substrate converge to the pad area through the fan-out area, and the fan-out area includes a covering area and an exposed area arranged in sequence from the display area to the pad area, wherein the covering area covers the VDD signal line, the VSS signal line, and the first interlayer insulating layer structure exposed between the VDD signal line and the VSS signal line, and the exposed area exposes the VDD signal line, the VSS signal line, and the first interlayer insulating layer structure.

[0029] Wherein, forming the fan-out area further includes:

[0030] forming a trench structure in the exposed first interlayer insulating layer structure, wherein the exposed VDD signal line and the exposed VSS signal line protrude toward each other above the trench structure, so that cathode metal formed on the exposed VDD signal line and the exposed VSS signal line is disconnected from the cathode metal formed in the trench structure;

[0031] A shielding structure is formed to protrude from the covering area to above the exposed area, so that the cathode metal formed on the covering area is disconnected from the cathode metal formed on the exposed VDD signal line and the VSS signal line.

[0032] In a specific embodiment, forming the fan-out region includes:

[0033] forming a first interlayer insulating layer structure;

[0034] forming a VDD signal line and a VSS signal line on the first interlayer insulating layer structure;

[0035] At a location where an exposed area is to be formed, the first interlayer insulating layer structure is etched using the VDD signal line and the VSS signal line as a mask to form a trench structure, wherein the trench structure forms a concave shape relative to the mask;

[0036] forming a first planarization layer structure on the VDD signal line and the VSS signal line;

[0037] forming a shielding structure on the first planarization layer structure near an edge of the exposed area to be formed;

[0038] forming a first pixel defining layer structure to cover the shielding structure;

[0039] Etching the first pixel defining layer structure and the first planarization layer structure to form the exposed area and the covered area, wherein the first planarization layer structure forms a concave shape relative to the shielding structure;

[0040] A cathode metal is formed on the exposed area and the covered area.

[0041] In a specific embodiment, forming the pad area includes:

[0042] forming a pad on the first interlayer insulating layer structure;

[0043] A second planarization layer structure is formed covering the pad, wherein the second planarization layer structure and the first planarization layer structure are formed by a single patterning process.

[0044] In a specific embodiment, it also includes:

[0045] A first barrier wall is formed between the covering area and the pad area to limit the farthest position where the cathode metal extends toward the pad area in the exposed area.

[0046] In a specific embodiment, forming the first barrier wall includes:

[0047] A third planarization layer structure, a second pixel definition layer structure and a support structure are formed in sequence in a direction away from the first interlayer insulating layer structure, wherein the third planarization layer structure and the first planarization layer structure are formed using a single patterning process, and the second pixel definition layer structure and the first pixel definition layer structure are formed using a single patterning process.

[0048] In a specific embodiment, it also includes:

[0049] A second barrier wall is formed between the pad area and the first barrier wall, wherein the second barrier wall includes a fourth planarization layer structure and a third pixel definition layer structure formed in sequence in a direction away from the first interlayer insulating layer structure, wherein the fourth planarization layer structure and the third planarization layer structure are formed using a single patterning process, and the third pixel definition layer structure and the second pixel definition layer structure are formed using a single patterning process, and the height of the second barrier wall is less than the height of the first barrier wall.

[0050] In a specific embodiment, forming the display area includes:

[0051] forming an active region, a gate insulating layer and a gate of a thin film transistor on a substrate;

[0052] forming a second interlayer insulating layer structure on the gate, wherein the second interlayer insulating layer structure and the first interlayer insulating layer structure are formed by a single patterning process;

[0053] forming a first source-drain electrode of the thin film transistor on the second interlayer insulating layer structure, wherein the first source-drain electrode, the VDD signal line, and the VSS signal line are formed by a single patterning process;

[0054] forming a fifth planarization layer structure on the first source-drain electrode, wherein the fifth planarization layer structure and the first planarization layer structure are formed by a single patterning process;

[0055] forming a second source-drain electrode on the fifth planarization layer structure, wherein the second source-drain electrode and the shielding structure are formed by a single patterning process;

[0056] A fourth pixel defining layer structure and an electroluminescent device surrounded by the fourth pixel defining layer are formed on the second source-drain electrode, wherein a cathode of the electroluminescent device and the cathode metal are formed by a single patterning process.

[0057] A third aspect of the present invention provides an electroluminescent display device, comprising the electroluminescent display substrate described above.

[0058] The beneficial effects of the present invention are as follows:

[0059] The present invention discloses an electroluminescent display substrate, a manufacturing method, and a display device including the same. By forming a "roof-like" structure in the direction from the covered area of ​​the display substrate toward the exposed area and in the direction from the VDD signal line to the VSS signal line in the exposed area, the risk of short circuit is eliminated. Therefore, when performing cathode metal evaporation, there is no need to worry about the number of times the cathode mask plate can be used, thereby increasing the number of times the mask plate of the display substrate can be used and reducing the cleaning frequency, thereby improving work efficiency and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings;

[0061] Figures 1A-1C 1A is a schematic structural diagram of a common perforated display substrate, wherein 1A is a top view, 1B is a cross-sectional view along line AA', and 1C is a cross-sectional view along line BB'.

[0062] Figures 2A-2C 2A is a schematic structural diagram of an electroluminescent display substrate according to an embodiment of the present disclosure, wherein 2B is a cross-sectional view along AA', and 2C is a cross-sectional view along BB'.

[0063] Figures 3A-3B 3A is a schematic structural diagram of an electroluminescent display substrate according to an embodiment of the present disclosure, wherein 3A is a top view and 3B is a cross-sectional view along line BB'.

[0064] Figure 4 A schematic cross-sectional view of a partial structure of a display area of ​​an electroluminescent display substrate according to an embodiment of the present disclosure is shown.

[0065] Figures 5A-5B , 6A-6B, 7A-7B, Figure 8 、 Figures 9A-9B 、 Figures 10A-10B 、 Figures 11A-11B 、 Figure 12 as well as Figures 13A-13B Cross-sectional views corresponding to process steps in a method for manufacturing an electroluminescent display substrate according to an embodiment of the present disclosure are shown, wherein A shows a fan-out area and a pad area, and B shows a display area. DETAILED DESCRIPTION

[0066] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0067] The terms “on,” “formed on,” and “disposed on” used in the present disclosure may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.

[0068] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0069] In this disclosure, unless otherwise specified, the term "co-layer arrangement" refers to two layers, components, members, elements, or parts that can be formed by the same manufacturing process (e.g., patterning process, etc.), and the two layers, components, members, elements, or parts are generally formed from the same material. For example, co-layer arrangement of two or more functional layers means that these co-layered functional layers can be formed using the same material layer and the same manufacturing process, thereby simplifying the manufacturing process of the display substrate.

[0070] In this disclosure, unless otherwise specified, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The expression "one-time patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

[0071] Figure 1A This is a top perspective diagram of an electroluminescent display substrate developed by the applicant. The electroluminescent display substrate 1 includes a display area (also called AA area) 10 and a peripheral circuit area, such as Figure 1A As shown, the peripheral circuit area includes a fan-out area 12 near the display area 10 and a pad area 14 away from the display area. In addition, the peripheral circuit area may also include a gate driver circuit GOA. The VDD signal line 101 and VSS signal line 102 of the display substrate converge to the pad area 14 through the fan-out area 12 and are electrically connected to the corresponding pins of the driver IC (not shown) on the pad area.

[0072] Figure 1B and 1C are along Figure 1A Schematic diagram of the cross section along line AA' and line BB'.

[0073] The active area of ​​the thin film transistor, the gate insulating layer and the gate electrode (not shown) are formed on the substrate where the display area 10 is formed. Then, an interlayer insulating layer 100 (also called an interlayer dielectric layer ILD) is formed, for example, by a deposition process, which covers the entire display substrate.

[0074] On the interlayer insulating layer 100, source and drain electrodes (not shown), a VDD signal line 101, and a VSS signal line 102 of a thin film transistor are formed by, for example, an evaporation process. Figure 1A As shown, the VDD signal line 101 and the VSS signal line 102 extend from the display area 10 through the fan-out area 12 to the pad area 14. In the fan-out area 12, the interlayer insulating layer 100 is exposed between the VDD signal line 101 and the VSS signal line 102. Figure 1B shown.

[0075] like Figure 1C As shown, in the pad region 14 , a pad 140 is formed on the interlayer insulating layer 100 .

[0076] Next, a planarization layer (PLN) 104 covering the display substrate is formed.

[0077] In the display area 10 , an anode of the electroluminescent element is formed on the planarization layer 104 and is electrically connected to one of the source and drain electrodes below through a via hole in the planarization layer; and a pixel definition layer 105 surrounding the anode.

[0078] Next, cathode metal deposition is performed.

[0079] The planarization layer in the display area 10 extends to the fan-out area 12, forming a cover area 120 of the fan-out area, covering the VDD signal line, the VSS signal line, and the interlayer insulating layer exposed between the VDD signal line and the VSS signal line. However, in the direction from the cover area 120 of the fan-out area toward the pad area, since metal traces (such as the VDD signal line / VSS signal line) are required to lead out and connect the signal input terminal, the VDD signal line, the VSS signal line, and the interlayer insulating layer therebetween need to be exposed. To this end, an opening needs to be formed in the planarization layer of the fan-out area, thereby forming an exposed area 122, as shown in FIG. Figure 1C shown.

[0080] However, when performing cathode metal evaporation, it is necessary to ensure that the evaporated cathode metal does not short-circuit the exposed VDD signal line and the VSS signal line, and does not short-circuit the cathode metal evaporated on the covering area 120 with the VDD signal line and / or VSS signal line exposed in the exposed area 122.

[0081] The solution currently proposed by the applicant is to limit the evaporation cathode shadow to the covered area 120, extending at most to the junction of the covered area 120 and the exposed area 122. However, as the number of evaporation cycles of the cathode mask increases, the cathode mask will be affected by the temperature of the evaporation chamber and deform due to thermal expansion and contraction, causing the cathode shadow to increase in the later stages of evaporation, thereby causing the aforementioned short-circuit risk. To this end, the number of evaporation cycles must be reduced, and the mask must be removed from the evaporation chamber and cleaned promptly after a limited number of uses, which inevitably reduces efficiency and increases costs.

[0082] To this end, the present invention provides an electroluminescent display substrate 2, such as Figures 2A-2C shown. Figure 2A FIG. 1 shows a top perspective view of a display substrate according to an embodiment of the present invention. Figure 2B for Figure 2A A schematic cross-sectional view of the display substrate along line AA', Figure 2C for Figure 2A Schematic cross-sectional view of the display substrate along line BB'.

[0083] like Figure 2A As shown, the display substrate includes:

[0084] A display area 20, a fan-out area 21 close to the display area, and a pad area 22 away from the display area, wherein the VDD signal line 23 and the VSS signal line 24 of the display substrate converge to the pad area 22 through the fan-out area 21, and the fan-out area 21 includes a covering area 210 and an exposed area 212 arranged in sequence from the display area to the pad area, wherein the covering area 210 covers the VDD signal line 23, the VSS signal line (which can be reflected in another cross-sectional view in the direction perpendicular to the paper) and the first interlayer insulating layer structure 25 exposed between the VDD signal line and the VSS signal line, and the exposed area 212 exposes the VDD signal line, the VSS signal line and the first interlayer insulating layer structure 25.

[0085] The fan-out area 21 further includes:

[0086] A trench structure 250 is formed in the exposed first interlayer insulating layer structure 25, wherein the exposed VDD signal line and VSS signal line protrude toward each other above the trench structure. Figure 2B As shown, the cathode metal 26 formed on the exposed VDD signal line and VSS signal line is disconnected from the cathode metal 26 formed in the trench structure.

[0087] The method for forming such a trench structure will be described later with reference to a specific embodiment.

[0088] The shielding structure 27 protruding from the covered area 210 to the exposed area 212, such as Figure 2C As shown, the cathode metal 26 formed on the covering area is disconnected from the cathode metal 26 formed on the exposed VDD signal line and VSS signal line.

[0089] The method for forming such a shielding structure will be described later with reference to a specific embodiment.

[0090] Through the above structure, a structure similar to an "eaves" is formed in the direction from the covering area to the exposed area and in the direction from the VDD signal line to the VSS signal line in the exposed area. When performing cathode metal evaporation, there is no need to worry about the number of times the cathode mask is used, because even if the cathode shadow becomes larger due to deformation of the mask, cathode metal will not be formed on the side wall of the groove structure below the signal line and on the side wall below the shielding structure, so that the cathode metal 26 formed on the exposed VDD signal line and VSS signal line is not connected to the cathode metal 26 formed on the bottom wall of the groove structure, and the cathode metal 26 formed on the covering area is also not connected to the cathode metal 26 formed on the exposed VDD signal line and VSS signal line, thereby eliminating the risk of short circuit. Furthermore, the display substrate of the present invention can increase the number of times the mask is used and reduce the cleaning frequency, thereby improving work efficiency and reducing costs.

[0091] In a specific embodiment, Figure 2C As shown, the coverage area 210 includes:

[0092] A first planarization layer structure 2100 is formed on the VDD signal line 23 and the VSS signal line 24 , wherein the shielding structure 27 is formed on the first planarization layer structure 2100 .

[0093] The first pixel defining layer structure 2105 covers the shielding structure 27 , wherein the cathode metal 26 formed on the covering area is formed on the first pixel defining layer structure 2105 .

[0094] The first interlayer insulating layer structure 25 may be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.

[0095] The first planarization layer structure 2100 may be made of an organic insulating material such as polyimide or epoxy resin.

[0096] The material of the first pixel defining layer structure 2105 may include organic insulating materials such as polyimide and epoxy resin.

[0097] The material of the blocking structure 27 can be selected in consideration of the materials of the first pixel defining layer structure and the first planarizing layer structure, that is, a material with a large etching selectivity ratio to the materials of the first pixel defining layer structure and the first planarizing layer structure can be selected, such as a metal material.

[0098] In a specific embodiment, Figure 2C As shown, the pad area 22 includes:

[0099] a pad 220 formed on the first interlayer insulating layer structure 25;

[0100] A second planarization layer structure 2200 covering the pad, wherein the second planarization layer structure 2200 and the first planarization layer structure 2100 may be provided on the same layer.

[0101] In an embodiment of the present invention, two or more functional layers are arranged in the same layer, which means that these functional layers arranged in the same layer can be formed using the same material layer and the same preparation process (such as patterning process, etc.), thereby simplifying the preparation process of the display substrate.

[0102] In a preferred embodiment of the present invention, Figure 3A and 3B As shown, the display substrate 2 further includes:

[0103] A first barrier wall 28 is formed between the cover area and the pad area. This barrier wall can be used to limit the maximum extension of the cathode metal toward the pad area within the exposed area. In addition, the first barrier wall 28 can prevent moisture from entering the display area from the pad area.

[0104] exist Figure 3B In the example shown, the first barrier wall 28 comprises:

[0105] A third planarization layer structure 2800 , a second pixel defining layer structure 2805 and a support structure 2810 are sequentially formed in a direction away from the first interlayer insulating layer structure.

[0106] The third planarization layer structure 2800 can be disposed on the same layer as the first planarization layer structure 2100, and the materials used for both are the same. The second pixel definition layer structure 2805 can be disposed on the same layer as the first pixel definition layer structure 2105, and the materials used for both are the same.

[0107] The support structure 2810 has a certain height. When the display substrate is covered with structures such as polarizers and cover plates, the support structure 2810 can support the polarizers and cover plates to prevent them from collapsing or other adverse phenomena.

[0108] More preferably, the display substrate according to the present invention further comprises:

[0109] A second barrier wall 29 is formed between the pad area 22 and the first barrier wall 28 .

[0110] The second barrier wall 29 includes a fourth planarization layer structure 2900 and a third pixel definition layer structure 2905 stacked in a direction away from the first interlayer insulating layer structure. The fourth planarization layer structure 2900 can be provided on the same layer as the third planarization layer structure 2800, and the materials used for both layers are the same. The third pixel definition layer structure 2905 can be provided on the same layer as the second pixel definition layer structure 2805, and the materials used for both layers are the same.

[0111] More preferably, as shown in the figure, the height of the second barrier wall 29 is smaller than that of the first barrier wall 28. In this way, when water vapor moves from the pad area toward the display area, it first passes through the lower barrier wall and then the higher barrier wall, which helps the water vapor condense outside the barrier wall and minimizes the water vapor from entering the display area.

[0112] The above embodiments only describe the layer structures of the fan-out region and the pad region of the display substrate. In fact, part of the structure of the display region can also be formed simultaneously with the structures of the fan-out region and the pad region.

[0113] In a specific embodiment, Figure 4 As shown, the display substrate 2 further includes a substrate 200. For example, when the display substrate is a flexible display substrate, the provided base substrate may be a flexible substrate such as polyimide (PI); when the display substrate is a rigid substrate, the base substrate may be a rigid substrate such as glass or quartz.

[0114] The display area 20 includes an active area 201 of a thin film transistor, a gate insulating layer 202 , a gate electrode 203 , a second interlayer insulating layer structure 204 , and a first source-drain electrode 205 , which are disposed on the substrate 200 .

[0115] For example, the active region 201 may be made of materials such as polysilicon and metal oxide.

[0116] The gate insulating layer 202 may be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.

[0117] The gate 203 is made of a material including aluminum, titanium, cobalt or other metals or alloy materials.

[0118] The second interlayer insulating layer structure 204 can be provided on the same layer as the first interlayer insulating layer structure 25 and made of the same material, that is, inorganic insulating material.

[0119] The first source-drain electrode 205 is provided in the same layer as the VDD signal line 23 and the VSS signal line 24 and is made of the same material. The first source-drain electrode 205 can be formed as a single-layer metal structure or a multi-layer metal structure, such as a three-layer metal structure. For example, in one embodiment, it includes a stacked titanium material layer, an aluminum material layer, and a titanium material layer, but the present invention is not limited to this.

[0120] In one example, the display area further includes:

[0121] a fifth planarization layer structure 206 covering the first source / drain electrode 205 , wherein the fifth planarization layer structure 206 may be provided on the same layer as the first planarization layer structure 2100 ;

[0122] a second source-drain electrode 207 formed on the fifth planarization layer structure 206 , wherein the second source-drain electrode is provided on the same layer as the shielding structure 27 ;

[0123] A fourth pixel defining layer structure 208 and an electroluminescent device 209 surrounded by the fourth pixel defining layer are formed on the second source-drain electrode 207 , wherein the electroluminescent device 209 includes an anode 2090 , a light-emitting layer 2093 and a cathode 2095 .

[0124] The fourth pixel defining layer structure 208 may be provided on the same layer as the first pixel defining layer structure 2105 .

[0125] The anode of the light emitting device is electrically connected to one of the second source and drain metals (eg, the drain electrode).

[0126] For example, the material of the anode 2090 includes metal oxides such as ITO and IZO, or metals such as Ag, Al, Mo, or alloys thereof.

[0127] The material of the light-emitting layer 2093 is an organic material. The material of the light-emitting layer can be selected as a light-emitting material that can emit a certain color of light (such as red light, blue light or green light, etc.) according to needs.

[0128] Cathode 2095 can be made of metals such as Mg, Ca, Li, or Al, or their alloys; metal oxides such as IZO and ZTO; or conductive organic materials such as PEDOT / PSS (poly(3,4-ethylenedioxythiophene) / polystyrene sulfonate). Cathode 2095 can be provided on the same layer as cathode metal 26 in the fan-out region.

[0129] At least one embodiment of the present invention further provides a method for manufacturing an electroluminescent display substrate, comprising:

[0130] A display area, a fan-out area close to the display area, and a pad area far from the display area are formed, wherein the VDD signal line and the VSS signal line of the display substrate converge to the pad area through the fan-out area, and the fan-out area includes a covering area and an exposed area arranged in sequence from the display area to the pad area, wherein the covering area covers the VDD signal line, the VSS signal line, and the first interlayer insulating layer structure exposed between the VDD signal line and the VSS signal line, and the exposed area exposes the VDD signal line, the VSS signal line, and the first interlayer insulating layer structure.

[0131] Wherein, forming the fan-out area further includes:

[0132] forming a trench structure in the exposed first interlayer insulating layer structure, wherein the exposed VDD signal line and the exposed VSS signal line protrude toward each other above the trench structure, so that cathode metal formed on the exposed VDD signal line and the exposed VSS signal line is disconnected from the cathode metal formed in the trench structure;

[0133] A shielding structure is formed to protrude from the covering area to above the exposed area, so that the cathode metal formed on the covering area is disconnected from the cathode metal formed on the exposed VDD signal line and the VSS signal line.

[0134] Through the above-mentioned manufacturing method, a structure similar to an "eaves" is formed in the direction from the covering area to the exposed area and in the direction from the VDD signal line to the VSS signal line in the exposed area. When performing cathode metal evaporation, there is no need to worry about the number of times the cathode mask plate is used, because even if the cathode shadow becomes larger due to deformation of the mask plate, cathode metal will not be formed on the side wall of the groove structure below the signal line and on the side wall below the shielding structure, so that the cathode metal formed on the exposed VDD signal line and VSS signal line is not connected to the cathode metal formed on the bottom wall of the groove structure, and the cathode metal formed on the covering area is also not connected to the cathode metal formed on the exposed VDD signal line and VSS signal line, thereby eliminating the risk of short circuit. Furthermore, the display substrate of the present invention can increase the number of times the mask plate is used and reduce the cleaning frequency, thereby improving work efficiency and reducing costs.

[0135] Below, to form Figures 2A-2C and Figure 4 Taking the display substrate shown as an example, the manufacturing method of the display substrate provided by the embodiment of the present invention is introduced.

[0136] A manufacturing method according to one embodiment of the present invention includes:

[0137] S500, forming an active region 201, a gate insulating layer 202 and a gate electrode 203 of a thin film transistor in a display region on a substrate 200, as shown in FIG. Figure 5B As shown. Figure 5A As shown, the gate insulating layer 202 in the display area extends to the fan-out area and the pad area on the substrate 200 .

[0138] For example, when the display substrate is a flexible display substrate, the provided base substrate may be a flexible substrate such as polyimide (PI); when the display substrate is a rigid substrate, the base substrate may be a rigid substrate such as glass or quartz.

[0139] For example, Figure 5B As shown, an active region 201 is formed on a substrate by a patterning process; a gate insulating layer 202 is formed on the active layer by deposition or the like; and a gate electrode 203 is formed on the gate insulating layer by a patterning process.

[0140] For example, the active region 201 may be made of materials such as polysilicon and metal oxide.

[0141] The gate insulating layer 202 may be made of inorganic insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.

[0142] The gate 203 is made of a material including aluminum, titanium, cobalt or other metals or alloy materials.

[0143] S501 , forming a first interlayer insulating layer structure 25 in the fan-out region 21 and the pad region 22 , and forming a second interlayer insulating layer structure 204 in the display region 20 .

[0144] like Figure 6A As shown, a first interlayer insulating layer structure 25 is formed on the gate insulating layer 202 in the fan-out region 21 and the pad region 22; Figure 6B As shown in the display region 20 , a second interlayer insulating layer structure 204 is formed.

[0145] In a specific example, an interlayer insulating layer can be formed in the display area 20, the fan-out area 21 and the pad area 22 by deposition or the like, forming the first interlayer insulating layer structure 25 in the fan-out area and the pad area and forming the second interlayer insulating layer structure 204 in the display area.

[0146] In the display area, such as Figure 6B As shown, the gate insulating layer 202 and the interlayer insulating layer are etched to form a via hole exposing the active area 201 .

[0147] S502 , forming a VDD signal line and a VSS signal line on the interlayer insulating layer.

[0148] like Figure 7A As shown in FIG. 2 , the signal lines (only the VDD signal line 23 is shown in the figure) extend from the display area 20 to the fan-out area 21. Figure 7B As shown, a first source-drain electrode 205 is also formed in the display area 20 .

[0149] For example, in one embodiment, the VDD signal line 23 , the VSS signal line 24 and the first source-drain electrode 205 may be formed simultaneously by sputtering or evaporation.

[0150] The first source-drain electrode 205 may be formed as a single-layer metal structure or a multi-layer metal structure, such as a three-layer metal structure. For example, in one example, it includes a stacked titanium material layer, an aluminum material layer, and a titanium material layer, but the present invention is not limited thereto.

[0151] S504 , using the VDD signal line and the VSS signal line as masks, etching the first interlayer insulating layer structure 25 at the location where the exposed area is to be formed to form a trench structure 250 , wherein the trench structure forms a concave shape relative to the mask.

[0152] like Figure 8 As shown, an etchant having a higher etching rate for the interlayer insulating layer than for the metal can be selected to etch the first interlayer insulating layer structure 25 , so that the etching process can form a trench structure 250 that is concave relative to the mask.

[0153] S506 , forming a planarization layer on the display area 20 , the fan-out area 21 and the pad area 22 .

[0154] like Figure 9A and 9B As shown, a deposition process may be used to form the planarization layer.

[0155] The planarization layer in the display area (ie, the fifth planarization layer structure 206 ) has a via hole, so that the second source-drain electrode formed later is electrically connected to the first source-drain electrode 205 through the via hole.

[0156] S508 , forming a shielding structure 27 on the planarization layer (ie, the first planarization layer structure 2100 ) of the fan-out area 21 near the edge of the exposed area to be formed, and forming a second source-drain electrode 207 on the planarization layer of the display area 20 .

[0157] like Figure 10A and 10B As shown, a single patterning process may be used to form the second source-drain electrode 207 in the display area 20 and the shielding structure 27 in the fan-out area 21 .

[0158] An anode 2090 of the light-emitting device is formed on the second source-drain electrode 207 and electrically connected to the second source-drain electrode 207. In one specific example, another planarization layer is formed to cover the second source-drain electrode. This other planarization layer has a via hole, through which the anode of the light-emitting device to be formed is electrically connected to the second source-drain electrode.

[0159] S510, forming a pixel definition layer, covering the shielding structure 27 in the fan-out area 21, such as Figure 11A As shown, the display area 20 is exposed as shown in FIG. Figure 11B Anode 2090 is shown.

[0160] In one specific example, the pixel defining layer is formed using a patterning process.

[0161] For example, the material of the anode 2090 includes metal oxides such as ITO and IZO, or metals such as Ag, Al, Mo, or alloys thereof.

[0162] In addition, a light-emitting layer 2093 is formed on the formed anode 2090 .

[0163] The material of the light-emitting layer 2093 is an organic material. The material of the light-emitting layer can be selected as a light-emitting material that can emit a certain color of light (such as red light, blue light or green light, etc.) according to needs.

[0164] S512, etching the pixel definition layer and the planarization layer in the fan-out area 21. The area adjacent to the display area where the planarization layer is retained is called the cover area 210. The planarization layer in the cover area 210 is the first planarization layer structure 2100, and the pixel definition layer is the first pixel definition layer structure 2105. The area where the signal line and the interlayer insulating layer are exposed is called the exposed area 212, wherein the first planarization layer structure 2100 forms a concave shape relative to the shielding structure 27, as shown in FIG. Figure 12 shown.

[0165] An etchant having a higher etching rate for the planarization layer and the pixel definition layer than for the metal can be selected to etch the first pixel definition layer structure and the first planarization layer structure, so that the etching process can form the first planarization layer structure into a concave shape relative to the blocking structure.

[0166] S514, forming a cathode metal 26 on the exposed area 212 and the covered area 210 and forming a cathode 2095 on the display area 20, as shown in FIG. Figure 13A and 13B shown.

[0167] The material of cathode 2095 may include metals such as Mg, Ca, Li or Al or their alloys, or metal oxides such as IZO and ZTO, or organic materials with conductive properties such as PEDOT / PSS (poly (3,4-ethylenedioxythiophene) / polystyrene sulfonate).

[0168] In a specific example, the cathode 2095 and the cathode metal 26 in the fan-out region 21 can be formed using a single patterning process.

[0169] In one embodiment, the manufacturing method further comprises:

[0170] Simultaneously with step S502 , a pad 220 is formed on the first interlayer insulating layer structure 25 in the pad region 22 .

[0171] At the same time as step S506, Figure 9A and 9B The planarization layer formed by the deposition process is shown to extend to the pad region 22 and cover the pad 220 .

[0172] Then, in the etching step of step S512 , the planarization layer remaining on the pad is referred to as a second planarization layer structure 2200 .

[0173] In one embodiment, the manufacturing method further comprises:

[0174] A first barrier wall 28 is formed between the covering area 210 and the pad area 22 to define the farthest position of the cathode metal 26 extending toward the pad area 22 in the exposed area 212 .

[0175] In a specific example, forming the first barrier wall 28 includes:

[0176] A third planarization layer structure 2800 , a second pixel defining layer structure 2805 and a support structure 2810 are sequentially formed in a direction away from the first interlayer insulating layer structure 25 .

[0177] In one example, before the etching step of step S512, a patterned support structure 2810 is formed, and in the etching step of step S512, the support structure is used as a mask so that the pixel definition layer and the planarization layer thereunder are also retained, forming the third planarization layer structure 2800 and the second pixel definition layer structure 2805.

[0178] Preferably, the production method further comprises:

[0179] A second barrier wall 29 is formed between the pad area 22 and the first barrier wall 28 .

[0180] In a specific example, in the etching step of step S512 , a mask process is used so that the pixel definition layer and the planarization layer thereunder are also retained, thereby forming the fourth planarization layer structure 2900 and the third pixel definition layer structure 2905 .

[0181] In this process, since the first barrier wall 28 has the support structure 2810 , its height is greater than that of the second barrier wall 29 .

[0182] The display substrate provided by the embodiments of the present disclosure or the display substrate obtained by the preparation method provided by the embodiments of the present disclosure can be used in a display device, and the display device can be any product or component that requires a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, a vehicle-mounted central control gear lever, etc. The embodiments of the present disclosure are not limited to this.

[0183] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in this field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present invention are still within the scope of protection of the present invention.

Claims

1. An electroluminescent display substrate, comprising: a display area, a fan-out area close to the display area, and a pad area far from the display area, wherein the VDD signal line and the VSS signal line of the display substrate converge to the pad area through the fan-out area, and the fan-out area includes a covering area and an exposed area arranged in sequence from the display area to the pad area, wherein the covering area covers the VDD signal line, the VSS signal line, and the first interlayer insulating layer structure exposed between the VDD signal line and the VSS signal line, and the exposed area exposes the VDD signal line, the VSS signal line, and the first interlayer insulating layer structure. It is characterized in that the fan-out area also includes: a trench structure formed in the exposed first interlayer insulating layer structure, wherein the exposed VDD signal line and the exposed VSS signal line protrude toward each other above the trench structure so that cathode metal formed on the exposed VDD signal line and the exposed VSS signal line is disconnected from the cathode metal formed in the trench structure; A shielding structure protruding from the covering area to above the exposed area disconnects the cathode metal formed on the covering area from the cathode metal formed on the exposed VDD signal line and the VSS signal line.

2. The electroluminescent display substrate according to claim 1, wherein: The coverage area includes: a first planarization layer structure formed on the VDD signal line and the VSS signal line, wherein the shielding structure is formed on the first planarization layer structure; A first pixel defining layer structure covers the blocking structure, wherein the cathode metal formed on the covering area is formed on the first pixel defining layer structure.

3. The electroluminescent display substrate according to claim 2, wherein: The pad area includes: a pad formed on the first interlayer insulating layer structure; A second planarization layer structure covers the pad, wherein the second planarization layer structure and the first planarization layer structure are arranged on the same layer.

4. The electroluminescent display substrate according to claim 2 or 3, characterized in that: Also includes: The first barrier wall formed between the covering area and the pad area is used to define the farthest position where the cathode metal extends toward the pad area in the exposed area.

5. The electroluminescent display substrate according to claim 4, characterized in that: The first barrier wall comprises: A third planarization layer structure, a second pixel definition layer structure and a support structure are stacked in a direction away from the first interlayer insulating layer structure, wherein the third planarization layer structure is arranged on the same layer as the first planarization layer structure, and the second pixel definition layer structure is arranged on the same layer as the first pixel definition layer structure.

6. The electroluminescent display substrate according to claim 5, characterized in that: Also includes: A second barrier wall is formed between the pad area and the first barrier wall, and the second barrier wall includes a fourth planarization layer structure and a third pixel definition layer structure stacked in a direction away from the first interlayer insulating layer structure, wherein the fourth planarization layer structure is arranged on the same layer as the third planarization layer structure, and the third pixel definition layer structure is arranged on the same layer as the second pixel definition layer structure, and the height of the second barrier wall is less than the height of the first barrier wall.

7. The electroluminescent display substrate according to claim 2, wherein: It also includes a substrate, and the display area includes an active area of ​​a thin film transistor, a gate insulation layer, a gate, a second interlayer insulation layer structure and a first source-drain electrode arranged on the substrate, wherein the first interlayer insulation layer structure and the second interlayer insulation layer structure are arranged on the same layer, and the first source-drain electrode and the VDD signal line and the VSS signal line are arranged on the same layer.

8. The electroluminescent display substrate according to claim 7, wherein: The display area further includes: a fifth planarization layer structure covering the first source-drain electrode, wherein the fifth planarization layer structure and the first planarization layer structure are provided on the same layer; a second source-drain electrode formed on the fifth planarization layer structure, wherein the second source-drain electrode is provided on the same layer as the shielding structure; A fourth pixel defining layer structure is formed on the second source-drain electrode and an electroluminescent device surrounded by the fourth pixel defining layer, wherein the cathode of the electroluminescent device is arranged in the same layer as the cathode metal, and the fourth pixel defining layer structure is arranged in the same layer as the first pixel defining layer structure.

9. A method for manufacturing an electroluminescent display substrate, characterized in that: include: A display area, a fan-out area close to the display area, and a pad area far from the display area are formed, wherein the VDD signal line and the VSS signal line of the display substrate converge to the pad area through the fan-out area, and the fan-out area includes a covering area and an exposed area arranged in sequence from the display area to the pad area, wherein the covering area covers the VDD signal line, the VSS signal line, and the first interlayer insulating layer structure exposed between the VDD signal line and the VSS signal line, and the exposed area exposes the VDD signal line, the VSS signal line, and the first interlayer insulating layer structure. Wherein, forming the fan-out area further includes: forming a trench structure in the exposed first interlayer insulating layer structure, wherein the exposed VDD signal line and the exposed VSS signal line protrude toward each other above the trench structure, so that cathode metal formed on the exposed VDD signal line and the exposed VSS signal line is disconnected from the cathode metal formed in the trench structure; A shielding structure is formed to protrude from the covering area to above the exposed area, so that the cathode metal formed on the covering area is disconnected from the cathode metal formed on the exposed VDD signal line and the VSS signal line.

10. The method according to claim 9, characterized in that The fan-out area is formed by: forming a first interlayer insulating layer structure; forming a VDD signal line and a VSS signal line on the first interlayer insulating layer structure; At a location where an exposed area is to be formed, the first interlayer insulating layer structure is etched using the VDD signal line and the VSS signal line as a mask to form a trench structure, wherein the trench structure forms a concave shape relative to the mask; forming a first planarization layer structure on the VDD signal line and the VSS signal line; forming a shielding structure on the first planarization layer structure near an edge of the exposed area to be formed; forming a first pixel defining layer structure to cover the shielding structure; Etching the first pixel defining layer structure and the first planarization layer structure to form the exposed area and the covered area, wherein the first planarization layer structure forms a concave shape relative to the shielding structure; A cathode metal is formed on the exposed area and the covered area.

11. The method according to claim 10, characterized in that Forming the pad area includes: forming a pad on the first interlayer insulating layer structure; A second planarization layer structure is formed covering the pad, wherein the second planarization layer structure and the first planarization layer structure are formed by a single patterning process.

12. The method according to claim 10 or 11, characterized in that Also includes: A first barrier wall is formed between the covering area and the pad area to limit the farthest position where the cathode metal extends toward the pad area in the exposed area.

13. The method according to claim 12, characterized in that Forming the first barrier wall includes: A third planarization layer structure, a second pixel definition layer structure and a support structure are formed in sequence in a direction away from the first interlayer insulating layer structure, wherein the third planarization layer structure and the first planarization layer structure are formed using a single patterning process, and the second pixel definition layer structure and the first pixel definition layer structure are formed using a single patterning process.

14. The method according to claim 13, wherein: Also includes: A second barrier wall is formed between the pad area and the first barrier wall, wherein the second barrier wall includes a fourth planarization layer structure and a third pixel definition layer structure formed in sequence in a direction away from the first interlayer insulating layer structure, wherein the fourth planarization layer structure and the third planarization layer structure are formed using a single patterning process, and the third pixel definition layer structure and the second pixel definition layer structure are formed using a single patterning process, and the height of the second barrier wall is less than the height of the first barrier wall.

15. The method according to claim 10, characterized in that Forming the display area includes: forming an active region, a gate insulating layer and a gate of a thin film transistor on a substrate; forming a second interlayer insulating layer structure on the gate, wherein the second interlayer insulating layer structure and the first interlayer insulating layer structure are formed by a single patterning process; forming a first source-drain electrode of the thin film transistor on the second interlayer insulating layer structure, wherein the first source-drain electrode, the VDD signal line, and the VSS signal line are formed by a single patterning process; forming a fifth planarization layer structure on the first source-drain electrode, wherein the fifth planarization layer structure and the first planarization layer structure are formed by a single patterning process; forming a second source-drain electrode on the fifth planarization layer structure, wherein the second source-drain electrode and the shielding structure are formed by a single patterning process; A fourth pixel defining layer structure and an electroluminescent device surrounded by the fourth pixel defining layer are formed on the second source-drain electrode, wherein a cathode of the electroluminescent device and the cathode metal are formed by a single patterning process.

16. An electroluminescent display device comprising the electroluminescent display substrate according to any one of claims 1 to 8.

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