Display substrate, display panel, and display device

Abstract

A display substrate, a display panel, and a display device are provided. The display substrate includes a display pixel region and a first virtual pixel region, and a plurality of virtual sub-pixel structures disposed on a substrate and located in the first virtual pixel region. At least one virtual sub-pixel structure includes a first compensation capacitor and a second compensation capacitor. A first scan signal line is electrically connected to the gates of fourth transistors of pixel driving circuits of each sub-pixel in a row of sub-pixels, and the first scan signal line is also electrically connected to the first compensation capacitor of at least one virtual sub-pixel structure. A second scan signal line is electrically connected to the gates of second transistors of pixel driving circuits of each sub-pixel in a row of sub-pixels, and the second scan signal line is also electrically connected to the second compensation capacitor of at least one virtual sub-pixel structure.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display substrate, a display panel, and a display device. Background Art

[0002] With the increasing diverse usage requirements of users for display devices and the emergence of the design requirement of a high screen-to-body ratio for display devices, display devices with a full-screen design are becoming more and more popular among consumers. In a full-screen design, an opening can be formed in the display screen, and a hardware module such as a camera can be placed in the opening, thereby realizing the full-screen design. In this design, there are many missing normally emitting pixels in the row where the opening is located, resulting in a large difference in load between the row where the opening is located and other rows, affecting the charging time of the pixel circuit, and thus having an adverse effect on the display effect.

[0003] The above information disclosed in this part is only for understanding the background of the technical concept of the present disclosure. Therefore, the above information may include information that does not constitute the prior art. Summary of the Invention

[0004] In one aspect, a display substrate is provided. The display substrate includes a display pixel region and a first virtual pixel region, and the display substrate includes:

[0005] A substrate;

[0006] A plurality of sub-pixels disposed on the substrate and located in the display pixel region. The plurality of sub-pixels are arranged in an array along a first direction and a second direction. Each sub-pixel includes a pixel driving circuit. The pixel driving circuit includes a driving transistor, a second transistor, and a fourth transistor. Each of the driving transistor, the second transistor, and the fourth transistor includes a gate, a first pole, and a second pole. A first pole of the second transistor is electrically connected to one of the first pole and the second pole of the driving transistor. A second pole of the second transistor is electrically connected to the gate of the driving transistor. The fourth transistor is used to control the writing of a data signal;

[0007] A plurality of virtual sub-pixel structures disposed on the substrate and located in the first virtual pixel region. At least one virtual sub-pixel structure includes a first compensation capacitor and a second compensation capacitor; and

[0008] A first scan signal line and a second scan signal line disposed on the substrate. The first scan signal line is used to supply a first scan signal to the gate of the fourth transistor. The second scan signal line is used to supply a second scan signal to the gate of the second transistor. The first scan signal line and the second scan signal line both extend through the display pixel region and the first virtual pixel region.

[0009] Among them, the first scanning signal line is electrically connected to the gates of the fourth transistors of the pixel driving circuits of each sub-pixel in a row of sub-pixels, and the first scanning signal line is also electrically connected to the first compensation capacitor of the at least one virtual sub-pixel structure; and

[0010] The second scanning signal line is electrically connected to the gates of the second transistors of the pixel driving circuits of each sub-pixel in a row of sub-pixels, and the second scanning signal line is also electrically connected to the second compensation capacitor of the at least one virtual sub-pixel structure.

[0011] According to some exemplary embodiments, the display substrate includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer disposed on the substrate, and the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, and the third conductive layer are sequentially disposed away from the substrate; the active layer of the fourth transistor is located in the first semiconductor layer, and the gate of the fourth transistor is located in the first conductive layer; the active layer of the second transistor is located in the second semiconductor layer, the gate of the second transistor includes a bottom gate and a top gate, the bottom gate of the second transistor is located in the second conductive layer, and the top gate of the second transistor is located in the third conductive layer; in the first virtual pixel region, the display substrate includes: a first compensation structure located in the first conductive layer; a second compensation structure located in the second conductive layer; and a third compensation structure located in the third conductive layer.

[0012] According to some exemplary embodiments, the first compensation capacitor includes at least a part of the first compensation structure and at least a part of the second compensation structure; the second compensation capacitor includes at least a part of the second compensation structure and at least a part of the third compensation structure.

[0013] According to some exemplary embodiments, the first compensation capacitor includes a first compensation sub-capacitor and a second compensation sub-capacitor, the first compensation sub-capacitor and the second compensation sub-capacitor are connected in parallel, and the first compensation sub-capacitor includes at least a part of the first compensation structure and at least a part of the second compensation structure; and / or, the second compensation capacitor includes a third compensation sub-capacitor and a fourth compensation sub-capacitor, the third compensation sub-capacitor and the fourth compensation sub-capacitor are connected in parallel, and the third compensation sub-capacitor includes at least a part of the second compensation structure and at least a part of the third compensation structure.

[0014] According to some exemplary embodiments, the first scanning signal line is located in the first conductive layer, and the first compensation structure is electrically connected to the first scanning signal line.

[0015] According to some exemplary embodiments, the display substrate further includes a first voltage line disposed on the substrate for transmitting a first voltage; the second compensation structure is electrically connected to the first voltage line.

[0016] According to some exemplary embodiments, the orthographic projection of the first compensation structure on the substrate at least partially overlaps with the orthographic projection of the second compensation structure on the substrate.

[0017] According to some exemplary embodiments, the second scan signal line includes a first sub-scan signal line located in the second conductive layer and a second sub-scan signal line located in the third conductive layer; the third compensation structure is electrically connected to the second scan signal line.

[0018] According to some exemplary embodiments, the orthographic projection of the third compensation structure on the substrate at least partially overlaps with the orthographic projection of the second compensation structure on the substrate.

[0019] According to some exemplary embodiments, the first compensation structure includes a first main body portion, the second compensation structure includes a second main body portion, and the orthographic projection of the second main body portion on the substrate covers the orthographic projection of the first main body portion on the substrate.

[0020] According to some exemplary embodiments, the third compensation structure includes a third main body portion, and the orthographic projection of the second main body portion on the substrate covers the orthographic projection of the third main body portion on the substrate.

[0021] According to some exemplary embodiments, the area of the overlapping region between the first main body portion and the second main body portion is more than 70% of the area of the orthographic projection of the second main body portion on the substrate; and / or, the area of the overlapping region between the third main body portion and the second main body portion is more than 70% of the area of the orthographic projection of the second main body portion on the substrate.

[0022] According to some exemplary embodiments, the first scan signal line extends in a first direction, and the ratio of the dimension of the orthographic projection of the first main body portion on the substrate in a second direction to the dimension of the orthographic projection of the first scan signal line on the substrate in the second direction is greater than or equal to 5; and / or, the second scan signal line extends in the first direction, and the ratio of the dimension of the orthographic projection of the third main body portion on the substrate in the second direction to the dimension of the orthographic projection of the second scan signal line on the substrate in the second direction is greater than or equal to 5.

[0023] According to some exemplary embodiments, the display substrate includes: a fourth conductive layer located on a side of the third conductive layer away from the substrate, and a fifth conductive layer located on a side of the fourth conductive layer away from the substrate; the first voltage line is located in the fifth conductive layer, the display substrate includes a compensation connection portion located in the fourth conductive layer, and the second compensation structure is electrically connected to the first voltage line through the compensation connection portion.

[0024] According to some exemplary embodiments, the display substrate further includes a fifth compensation structure, the fifth compensation structure is located in the fifth conductive layer, and the fifth compensation structure is electrically connected to the first voltage line; and the fourth compensation sub-capacitor includes at least a part of the third compensation structure and at least a part of the fifth compensation structure.

[0025] According to some exemplary embodiments, a positive projection of the third compensation structure on the substrate at least partially overlaps with a positive projection of the fifth compensation structure on the substrate.

[0026] According to some exemplary embodiments, the fifth compensation structure includes a fifth main body portion, and a positive projection of the third main body portion on the substrate covers a positive projection of the fifth main body portion on the substrate.

[0027] According to some exemplary embodiments, the display substrate further includes a sixth conductive layer located on a side of the first semiconductor layer close to the substrate; the display substrate further includes a fourth compensation structure located in the sixth conductive layer, and a positive projection of the first compensation structure on the substrate at least partially overlaps with a positive projection of the fourth compensation structure on the substrate.

[0028] According to some exemplary embodiments, the second compensation sub-capacitor includes at least a part of the first compensation structure and at least a part of the fourth compensation structure.

[0029] According to some exemplary embodiments, the fourth compensation structure includes a fourth main body portion, and a positive projection of the first main body portion on the substrate covers a positive projection of the fourth main body portion on the substrate.

[0030] According to some exemplary embodiments, a dimension of the fifth main body portion of the fifth compensation structure in a first direction is greater than a dimension of the first voltage line in the first direction.

[0031] According to some exemplary embodiments, a ratio of a dimension of the fifth main body portion of the fifth compensation structure in the first direction to a dimension of the first voltage line in the first direction is greater than or equal to 3.

[0032] According to some exemplary embodiments, in two adjacent virtual sub-pixel structures, the two fifth main portions are connected to each other, and the orthographic projection of the two connected fifth main portions on the substrate is in a rectangular shape.

[0033] According to some exemplary embodiments, for two adjacent sub-pixels in the first direction, the orthographic projection of their pixel driving circuits on the substrate is axisymmetric with respect to a first axis of symmetry, and the first axis of symmetry extends along the second direction.

[0034] According to some exemplary embodiments, for two adjacent virtual sub-pixel structures in the first direction, the orthographic projection of the two virtual sub-pixel structures on the substrate is axisymmetric with respect to a second axis of symmetry, and the second axis of symmetry extends along the second direction.

[0035] According to some exemplary embodiments, at least one of the first scan signal line and the second scan signal line includes a first compensation signal line and a second compensation signal line. The first compensation signal line is electrically connected to multiple sub-pixels and at least one first virtual sub-pixel structure in one row of sub-pixels, and the second compensation signal line is electrically connected to multiple sub-pixels and at least one first virtual sub-pixel structure in another row of sub-pixels; and the number of sub-pixels electrically connected by the first compensation signal line is less than the number of sub-pixels electrically connected by the second compensation signal line, and the number of first virtual sub-pixel structures electrically connected by the first compensation signal line is more than the number of first virtual sub-pixel structures electrically connected by the second compensation signal line.

[0036] According to some exemplary embodiments, both the first scan signal line and the second scan signal line extend along the first direction; and in the first virtual pixel region, the multiple virtual sub-pixel structures are arranged along the first direction and the second direction, and the number of virtual sub-pixel structures in the same row first increases and then decreases along the second direction.

[0037] On the other hand, a display panel is provided, including the display substrate as described above.

[0038] In yet another aspect, a display device is provided, including the display substrate or the display panel as described above. Description of the Drawings

[0039] By referring to the accompanying drawings and describing the exemplary embodiments of the present disclosure in detail, the features and advantages of the present disclosure will become more obvious.

[0040] Figure 1 is a plan view of a display device according to some embodiments of the present disclosure;

[0041] Figure 2is a schematic cross-sectional view taken along line AA' in Figure 1 of a display device according to some exemplary embodiments of the present disclosure;

[0042] Figure 3 is a partial enlarged view of an opening portion in a display substrate according to some exemplary embodiments of the present disclosure in Figure 1 ;

[0043] Figure 4 is a partial enlarged view of portion I in a display substrate according to some exemplary embodiments of the present disclosure in Figure 3 ;

[0044] Figure 5 is a partial enlarged view of portion II in a display substrate according to some exemplary embodiments of the present disclosure in Figure 3 ;

[0045] Figure 6 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure;

[0046] Figure 7 is a plan view showing an exemplary embodiment of sub-pixels in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure;

[0047] Figure 8A and Figure 8B are respectively equivalent circuit diagrams of a load compensation unit (i.e., a first virtual pixel structure) of a display substrate according to some exemplary embodiments of the present disclosure;

[0048] Figure 9 is a plan view showing an exemplary embodiment of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0049] Figures 10 to 17 is a plan view showing some film layers of an exemplary embodiment of a virtual sub-pixel structure in Figure 9 ;

[0050] Figure 18 is a schematic diagram showing a cross-sectional structure taken along line BB' in Figure 7 of a display substrate according to some exemplary embodiments of the present disclosure;

[0051] Figure 19 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure;

[0052] Figure 20 is a plan view showing an exemplary embodiment of sub-pixels in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure;

[0053] Figure 21A and Figure 21B are equivalent circuit diagrams of a load compensation unit (i.e., a first virtual pixel structure) of a display substrate according to some exemplary embodiments of the present disclosure;

[0054] Figure 22 is a plan view showing an exemplary embodiment of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure;

[0055] Figures 23 to 32 shows Figure 22 a plan view of some film layers of an exemplary embodiment of the virtual sub-pixel structure in ;

[0056] Figure 33 is a plan view showing an exemplary embodiment of a sub-pixel in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure, in which a plan view of two adjacent sub-pixels in the display pixel region is schematically shown;

[0057] Figure 34 is a plan view showing an exemplary embodiment of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure, in which a plan view of two adjacent virtual sub-pixel structures in a first virtual pixel region is schematically shown;

[0058] Figures 35 to 42 shows Figure 34 a plan view of some film layers of an exemplary embodiment of two adjacent virtual sub-pixel structures in ;

[0059] Figure 43 is a plan view showing an exemplary embodiment of a sub-pixel in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure, in which a plan view of two adjacent sub-pixels in the display pixel region is schematically shown;

[0060] Figure 44 is a plan view showing an exemplary embodiment of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure, in which a plan view of two adjacent virtual sub-pixel structures in a first virtual pixel region is schematically shown; and

[0061] Figures 45 to 54 shows Figure 44 a plan view of some film layers of an exemplary embodiment of two adjacent virtual sub-pixel structures in . Detailed implementation manners

[0062] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0063] It should be noted that in the drawings, for the purpose of clarity and / or description, the sizes and relative sizes of elements may be enlarged. Thus, the sizes and relative sizes of the respective elements do not have to be limited to the sizes and relative sizes shown in the drawings. In the description and drawings, the same or similar reference numerals indicate the same or similar components.

[0064] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be intervening elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there are no intervening elements. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connection" may refer to physical connection, electrical connection, communication connection, and / or fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any combination and all combinations of one or more of the listed related items.

[0065] It should be noted that although terms such as "first", "second", etc. may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as the second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of the present disclosure.

[0066] For ease of description, spatial relationship terms such as "above", "below", "left", "right", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatial relationship terms are intended to cover other different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is inverted, the element described as "below" or "beneath" another element or feature will be oriented "above" or "on top of" the other element or feature.

[0067] In this document, terms such as "substantially", "about", "approximate", "substantially the same", and other similar terms are used as approximate terms rather than terms of degree, and they are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximate" as used herein includes the stated value and represents an acceptable deviation range for the particular value determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0068] It should be noted that in this document, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then patterning the film layer by using the same mask through a single patterning process. Depending on the different specific patterns, the single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures, and / or parts located in "the same layer" are composed of the same material and are formed through the same patterning process. Generally, multiple elements, components, structures, and / or parts located in "the same layer" have substantially the same thickness.

[0069] Those skilled in the art should understand that, in this text, unless otherwise specified, the expressions "continuously extend", "integral structure", "monolithic structure" or similar expressions mean that multiple elements, components, structures and / or parts are located on the same layer and are usually formed by the same lithography process during manufacturing. There are no gaps or breaks between these elements, components, structures and / or parts, but a continuously extending structure.

[0070] Embodiments of the present disclosure provide at least a display substrate, a display panel, and a display device. The display substrate includes a display substrate, the display substrate includes a display pixel region and a first virtual pixel region, and the display substrate includes: a substrate; a plurality of sub-pixels disposed on the substrate and located in the display pixel region, the plurality of sub-pixels are arranged in an array along a first direction and a second direction, each sub-pixel includes a pixel driving circuit, the pixel driving circuit includes a driving transistor, a second transistor, and a fourth transistor, each of the driving transistor, the second transistor, and the fourth transistor includes a gate, a first pole, and a second pole, the second transistor is electrically connected between one of the first pole and the second pole of the driving transistor and the gate, and the fourth transistor is used to control the writing of a data signal; a plurality of virtual sub-pixel structures disposed on the substrate and located in the first virtual pixel region, at least one virtual sub-pixel structure includes a first compensation capacitor and a second compensation capacitor; and a first scan signal line and a second scan signal line disposed on the substrate, the first scan signal line is used to supply a first scan signal to the gate of the fourth transistor, the second scan signal line is used to supply a second scan signal to the gate of the second transistor, the first scan signal line and the second scan signal line both extend through the display pixel region and the first virtual pixel region, wherein the first scan signal line is electrically connected to the gates of the fourth transistors of the pixel driving circuits of each sub-pixel in a row of sub-pixels, and the first scan signal line is also electrically connected to the first compensation capacitor of the at least one virtual sub-pixel structure; and the second scan signal line is electrically connected to the gates of the second transistors of the pixel driving circuits of each sub-pixel in a row of sub-pixels, and the second scan signal line is also electrically connected to the second compensation capacitor of the at least one virtual sub-pixel structure. By providing compensation capacitors in the virtual pixel region, the loads on different scan signal lines can be made uniform, avoiding display differences and ensuring display quality.

[0071] Figure 1 A plan view of a display device according to an exemplary embodiment of the present disclosure is shown. For example, the display device includes a display substrate. The display substrate may be an electroluminescent display substrate, such as an OLED display substrate.

[0072] As Figure 1As shown, the display substrate includes a display area AA and at least one opening located in the display area AA. It should be noted that the "opening" described herein is an area on the display substrate for installing hardware structures. For the convenience of description, it is referred to as an opening in this article, but the opening includes, but is not limited to, the following forms: through holes, grooves, openings, etc. Optionally, the hardware structure may include one or more of the following structures: a front camera, a HOME key, a receiver, or a speaker. The specific installation method of the hardware structure is not particularly limited in the embodiments of the present disclosure.

[0073] For example, the at least one opening may include two openings. For the convenience of description, the two openings may be respectively referred to as a first opening TH1 and a second opening TH2. The first opening TH1 may be generally circular in shape, and the second opening TH2 may be in a combined shape of a rounded rectangle and a semicircle. The first opening TH1 and the second opening TH2 are spaced apart, and a solid portion is provided in the spaced area SR between the first opening TH1 and the second opening TH2. For example, the display substrate may include a substrate 1 and various film layers provided on the substrate 1. In the area where the first opening TH1 and the second opening TH2 are located, at least some of the various film layers provided on the substrate 1 are not provided. In the spaced area SR, at least some of the various film layers on the substrate 1 are provided. The combination of the first opening TH1, the spaced area SR, and the second opening TH2 projects orthogonally onto the substrate 1 in a racetrack shape.

[0074] It should be noted that Figure 1 two openings are taken as an example for illustration. It should be understood that the embodiments of the present disclosure are not limited thereto. In other embodiments, fewer (for example, one) or more openings may be provided. In addition, the shape of the opening may be determined according to the shape of the hardware structure to be installed. For example, the cross-section of the opening in the direction parallel to the substrate of the display substrate may have one or more of the following shapes: circular, oval, rectangular, rounded rectangular, square, rhombus, trapezoid, etc.

[0075] In the embodiments of the present disclosure, by providing an opening in the display area, a hardware structure such as a camera is installed in the opening, that is, the orthogonal projection of a hardware structure such as a camera on the substrate falls into the at least one opening. In this way, functions such as under-screen photography can be realized, thereby improving the screen-to-body ratio and achieving the effect of a full-screen.

[0076] Continuing to refer to Figure 1 , the display area AA may include a first display area AA1 and a second display area AA2. For example, the first display area AA1 and the second display area AA2 do not overlap with each other. For example, the second display area AA2 at least partially surrounds (for example, completely surrounds) the first display area AA1.

[0077] For example, the first display area AA1 may correspond to the area where the first opening TH1 and the second opening TH2 are located. For a display substrate with an under-screen camera, some sub-pixels may be arranged in the first display area AA1 to improve the display performance of the display substrate. To increase the light transmittance of the display area of the display substrate corresponding to the under-screen camera, the unit area distribution density (PPI) of the light-emitting devices in the display area corresponding to the under-screen camera may be less than that of the light-emitting devices in other display areas of the display substrate. That is, the first display area AA1 is formed as a low pixel density area, and the second display area AA2 is formed as a high pixel density area. Of course, for a display substrate with an under-screen camera, display pixels may also not be arranged in the first display area AA1. The embodiments of the present disclosure do not impose special restrictions on this.

[0078] Figure 2 is a schematic cross-sectional view taken along the line AA' in Figure 1 of a display device according to some exemplary embodiments of the present disclosure. As Figure 2 shown, the display substrate may include a substrate 1. The camera 2 may be disposed on the back surface of the substrate 1 located in the first display area AA1 (shown as the lower side in Figure 2 , for example, the side opposite to the light-emitting direction during display), and the first display area AA1 may meet the imaging requirements of the camera 2 for light transmittance.

[0079] For example, the light transmittance of the first display area AA1 is greater than that of the second display area AA2. The camera 2 is, for example, an image camera or an infrared camera, etc. The camera 2 is configured to receive light from the display side of the display substrate ( Figure 2 the upper side in, for example, the light-emitting direction during display, or the direction where the human eye is located during display), so as to perform operations such as image shooting, distance sensing, and light intensity sensing. These lights, for example, pass through the first display area AA1 and then irradiate onto the camera, and thus are sensed by the camera.

[0080] In addition, the display substrate may further include a driving circuit layer, a light-emitting device layer, and a packaging layer disposed on the substrate 1. For example, Figure 2 the driving circuit layer 3, the light-emitting device layer 4, and the packaging layer 5 are schematically shown in. The driving circuit layer 3 includes a driving circuit structure, and the light-emitting device layer 4 includes light-emitting devices such as OLEDs. The driving circuit structure controls the light-emitting devices of each sub-pixel to emit light to achieve the display function. The driving circuit structure includes thin-film transistors, storage capacitors, and various signal lines. The various signal lines include scan signal lines, data signal lines, a first voltage line, a second voltage line, etc., so as to provide various signals such as scan signals, data signals, and power supply voltages for the pixel driving circuits in each sub-pixel.

[0081] Figure 3 is a partial enlarged view of an opening portion in a display substrate according to some exemplary embodiments of the present disclosure in Figure 1 . Figure 4 is a partial enlarged view of a portion I in a display substrate according to some exemplary embodiments of the present disclosure in Figure 3 . Figure 5 is a partial enlarged view of a portion II in a display substrate according to some exemplary embodiments of the present disclosure in Figure 3 .

[0082] With reference to Figures 1 to 5 , the display substrate may include a display pixel region and a virtual pixel region.

[0083] It should be noted that, in this article, the expression "display pixel region" means: in this region, a plurality of pixels capable of emitting light to display an image are provided; the expression "virtual pixel region" means: in this region, some pixel structures are provided, and these pixel structures may be similar to the structures of the plurality of pixels in the "display pixel region", however, these pixel structures are not used for emitting light to display an image.

[0084] With reference to Figure 3 , the display pixel region may include a display pixel region DP1, and the display pixel region DP1 may be located in a second display region AA2. In the display pixel region DP1, a plurality of pixels PX may be provided. The plurality of pixels PX may be arranged in an array along a first direction X and a second direction Y on a substrate 1. For example, each of the plurality of pixels PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. For the convenience of understanding, the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may be respectively described as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, however, the embodiments of the present disclosure are not limited thereto.

[0085] It should be understood that, in the embodiments of the present disclosure, each sub-pixel located in the display pixel region DP1 includes a pixel driving circuit and a light-emitting device. For example, the light-emitting device may be an OLED light-emitting device, including an anode, an organic light-emitting layer, and a cathode which are stacked. The pixel driving circuit may include a plurality of thin film transistors and at least one storage capacitor.

[0086] The virtual pixel region may include a first virtual pixel region DMP1, and the first virtual pixel region DMP1 may be located in the spacer region SR. In the first virtual pixel region DMP1, a plurality of first virtual pixel structures DMPX1 may be provided. The plurality of first virtual pixel structures DMPX1 may be arranged in an array along a first direction X and a second direction Y on the substrate 1. Corresponding to the plurality of sub-pixels located in the display pixel region DP1, the plurality of first virtual pixel structures DMPX1 may include a plurality of virtual sub-pixel structures DMPX11, DMPX12, and DMPX13. It should be noted that in the embodiments of the present disclosure, herein, the virtual sub-pixel structures do not emit light, and they are respectively labeled as DMPX11, DMPX12, and DMPX13 here only for the need to correspond to the above-mentioned plurality of sub-pixels PX1, PX2, and PX3. The embodiments of the present disclosure are not limited thereto.

[0087] It should be noted that although in the illustrated embodiment, the first direction X and the second direction Y are perpendicular to each other, the embodiments of the present disclosure are not limited thereto.

[0088] The above describes the embodiments of the present disclosure in terms of the implementation manner of the display device of the "hole-opening screen". It should be noted that the embodiments of the present disclosure are not limited to the display device of the "hole-opening screen", and the present disclosure may also include the implementation manner of the display device of "under-screen camera". That is to say, in the embodiments of the present disclosure, the display substrate may include the above-mentioned display pixel region and virtual pixel region. For example, the display pixel region DP1 and the first virtual pixel region DMP1. The display substrate may not include the above-mentioned opening. The first virtual pixel region DMP1 may correspond to the region where the under-screen camera is provided.

[0089] Next, taking the 7T1C pixel driving circuit as an example, the structure of the pixel driving circuit of the sub-pixels located in the display pixel region DP1 will be described in detail. However, the embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit. Without conflict, other known pixel driving circuit structures can be applied to the embodiments of the present disclosure.

[0090] Figure 6 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. Figure 7 is a plan view showing an exemplary implementation manner of sub-pixels in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure.

[0091] With reference to Figure 6 and Figure 7, the pixel driving circuit may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0092] The display substrate may further include a plurality of signal lines. For example, the plurality of signal lines include: a first scan signal line 61 and a second scan signal line 61N for transmitting scan signals, a first reset signal line 62 and a second reset signal line 62N for transmitting reset control signals, a light emission control line 63 for transmitting light emission control signals, a data signal line 64 for transmitting data signals, a first voltage line 65 for transmitting a first voltage, an initialization voltage line 66 for transmitting an initialization voltage, and a second voltage line 67 for transmitting a second voltage. For example, the first voltage may be a VDD voltage, the second voltage may be a VSS voltage, and the first voltage may be higher than the second voltage.

[0093] In an embodiment of the present disclosure, a driving circuit (LTPO) including low temperature polycrystalline silicon semiconductor transistors and oxide semiconductor transistors is included, wherein the active layers of the first transistor T1 and the second transistor T2 are both formed of an oxide semiconductor material such as Figure 6 shown, which can improve the voltage stability at the node N1 in the pixel driving circuit, thereby improving the display performance of the display panel. Moreover, the first transistor T1 and the second transistor T2 both have a double gate structure, so that the stability and the uniformity of the threshold voltage (Vth) of the first transistor T1 and the second transistor T2 are both improved, thereby being able to further improve the performance of the display panel.

[0094] In an embodiment of the present disclosure, in order to distinguish the scan signals transmitted to the second transistor T2 and the fourth transistor T4, the signal line for transmitting the scan signal to the gate of the second transistor T2 having a double gate structure is called the second scan signal line 61N, and the signal line for transmitting the scan signal to the gate of the fourth transistor T4 is called the first scan signal line 61. Similarly, in order to distinguish the scan signals transmitted to the first transistor T1 and the seventh transistor T7, the signal line for transmitting the scan signal to the gate of the first transistor T1 having a double gate structure is called the second reset signal line 62N, and the signal line for transmitting the scan signal to the gate of the seventh transistor T7 is called the first reset signal line 62.

[0095] Referring to Figure 6 and Figure 7, the gate G1 of the first transistor T1 is electrically connected to the second reset signal line 62N, and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line 66. Moreover, the drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3, as Figure 6 shown, the drain D1 of the first transistor T1, one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected at the node N1. The first transistor T1 is turned on according to the reset control signal transmitted through the second reset signal line 62N to transmit the initialization voltage signal Vint to the gate G1 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, the first transistor T1 is also referred to as the initialization transistor.

[0096] The gate G2 of the second transistor T2 is electrically connected to the second scan signal line 61N, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on according to the scan signal transmitted through the second scan signal line 61N to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing the diode connection of the third transistor T3.

[0097] The gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3. The third transistor T3 receives a data signal according to the switching operation of the fourth transistor T4 to supply a driving current Id to the OLED. That is, the third transistor T3 is also referred to as the driving transistor.

[0098] The gate G4 of the fourth transistor T4 is electrically connected to the first scan signal line 61, the source S4 of the fourth transistor T4 is electrically connected to the data signal line 64, and the drain D4 of the fourth transistor T4 is electrically connected to the node N2, that is, electrically connected to the source S3 of the third transistor T3. The fourth transistor T4 is turned on according to the scan signal transmitted through the first scan signal line 61 to perform a switching operation to transmit the data signal to the source S3 of the third transistor T3.

[0099] The gate G5 of the fifth transistor T5 is electrically connected to the light emission control line 63, and the source S5 of the fifth transistor T5 is electrically connected to the first voltage line 65. Moreover, the drain D5 of the fifth transistor T5 is electrically connected to the node N2.

[0100] The gate G6 of the sixth transistor T6 is electrically connected to the light emission control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, that is, electrically connected to the anode of the light emitting element OLED. The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on according to the light emission control signal transmitted through the light emission control line 63 to transmit the first voltage to the OLED, thereby allowing the drive current Id to flow into the OLED.

[0101] The gate G7 of the seventh transistor T7 is electrically connected to the first reset signal line 62, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line 66.

[0102] One end (hereinafter referred to as the first capacitive electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1, and the other end (hereinafter referred to as the second capacitive electrode) Cst2 is electrically connected to the first voltage line 65.

[0103] The anode of the OLED is electrically connected to the node N4, and the cathode is electrically connected to the second voltage line 67 to receive the second voltage VSS. Accordingly, the OLED receives the drive current Id from the third transistor T3 to emit light, thereby displaying an image.

[0104] It should be noted that in Figure 6 , each of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 is a p-channel field effect transistor. However, the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 may be n-channel field effect transistors.

[0105] In operation, in the initialization stage, a reset control signal having a low level is supplied through the second reset signal line 62N. Subsequently, the first transistor T1 is turned on based on the low level of the reset control signal, and the initialization voltage signal Vint from the initialization voltage line 66 is transmitted through the first transistor T1 to the gate G1 of the third transistor T3. Therefore, the third transistor T3 is initialized due to the initialization voltage signal Vint.

[0106] In the data programming stage, a scan signal having a low level is supplied through the first scan signal line 61 and the second scan signal line 61N. Subsequently, the fourth transistor T4 and the second transistor T2 are turned on based on the low level of the scan signal. Therefore, the third transistor T3 is placed in a diode-connected state and biased in the forward direction through the turned-on second transistor T2.

[0107] Subsequently, a compensation voltage +Vth obtained by subtracting the threshold voltage Vth of the third transistor T3 from the data signal supplied via the data signal line 64 (e.g., Vth is a negative value) is applied to the gate G3 of the third transistor T3. Subsequently, the first voltage VDD and the compensation voltage +Vth are applied to the two terminals of the storage capacitor Cst, such that charges corresponding to the voltage difference between the corresponding terminals are stored in the storage capacitor Cst.

[0108] In the light emission stage, the light emission control signal from the light emission control line 63 changes from a high level to a low level. Subsequently, in the light emission stage, the fifth transistor T5 and the sixth transistor T6 are turned on based on the low level of the light emission control signal.

[0109] Subsequently, a drive current is generated based on the difference between the voltage of the gate G3 of the third transistor T3 and the first voltage VDD. A drive current Id corresponding to the difference between the drive current and the bypass current is supplied to the OLED through the sixth transistor T6.

[0110] In the light emission stage, based on the current-voltage relationship of the third transistor T3, the gate-source voltage of the third transistor T3 is maintained at (+Vth) - VDD due to the storage capacitor Cst. The drive current Id is proportional to (-VDD)2. Therefore, the drive current Id can be unaffected by the variation of the threshold voltage Vth of the third transistor T3.

[0111] Figure 18 is a schematic diagram showing a cross-sectional structure of a display substrate taken along Figure 7 the line BB' in

[0112] With reference to Figure 7 and Figure 18 The display substrate includes a substrate 10 and a plurality of film layers provided on the substrate 10. In some embodiments, the plurality of film layers at least include a first semiconductor layer 20, a first conductive layer 30, a second conductive layer 40, a second semiconductor layer 50, a third conductive layer 60, a fourth conductive layer 70, and a fifth conductive layer 80. The first semiconductor layer 20, the first conductive layer 30, the second conductive layer 40, the second semiconductor layer 50, the third conductive layer 60, the fourth conductive layer 70, and the fifth conductive layer 80 are sequentially disposed away from the substrate 10.

[0113] For example, the first semiconductor layer 20 may be formed of a semiconductor material such as low-temperature polysilicon, and its film thickness may be in the range of 400 to 800 angstroms, for example, 500 angstroms. The second semiconductor layer 50 may be formed of an oxide semiconductor material, such as a polysilicon oxide semiconductor material like IGZO, and its film thickness may be in the range of 300 to 600 angstroms, for example, 400 angstroms. The first conductive layer 30, the second conductive layer 40, and the third conductive layer 60 may be formed of a conductive material for forming the gate of a thin-film transistor. For example, the conductive material may be Mo, and its film thickness may be in the range of 20000 to 3000 angstroms, for example, 2500 angstroms. The fourth conductive layer 70 and the fifth conductive layer 80 may be formed of a conductive material for forming the source and drain of a thin-film transistor. For example, the conductive material may include Ti, Al, etc., and may have a stacked structure formed of Ti / Al / Ti. Its film thickness may be in the range of 7000 to 9000 angstroms. For example, in the case where the fourth conductive layer 70 or the fifth conductive layer 80 has a stacked structure formed of Ti / Al / Ti, the thickness of each layer of Ti / Al / Ti may be approximately 500 angstroms, 5500 angstroms, and 500 angstroms, respectively.

[0114] The display substrate includes a second scan signal line 61N, a first scan signal line 61, a second reset signal line 62N, a first reset signal line 62, a light emission control line 63, and an initialization voltage line 66 that are arranged along the row direction to respectively apply a scan signal, a reset control signal, a light emission control signal, and an initialization voltage signal Vint to sub-pixels. The display substrate may further include a data signal line 64 and a first voltage line 65 that intersect with the second scan signal line 61N, the first scan signal line 61, the second reset signal line 62N, the first reset signal line 62, the light emission control line 63, and the initialization voltage line 66 to respectively apply a data signal and a driving voltage VDD to sub-pixels.

[0115] Combined with the above description of Figure 6 The pixel driving circuit of the display substrate may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0116] Combined with reference to Figure 6 and Figure 7 , the first transistor T1 and the second transistor T2 may be formed along the second semiconductor layer as shown in Figure 7 . The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed along the first semiconductor layer 20 as shown in Figure 7 .

[0117] As shown in Figure 7As shown, the first semiconductor layer 20 may have a curved or bent shape and may include a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, a fifth active layer 20e corresponding to the fifth transistor T5, a sixth active layer 20f corresponding to the sixth transistor T6, and a seventh active layer 20g corresponding to the seventh transistor T7.

[0118] For example, the first semiconductor layer 20 may include polysilicon, such as a low-temperature polysilicon material. The active layer of each transistor may include a channel region, a source region, and a drain region. The channel region may be undoped or doped with a different doping type from the source region and the drain region, and thus has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0119] The third transistor T3 includes a third active layer 20c and a third gate G3. The third active layer 20c may include a third source region, a third drain region, and a third channel region connecting the third source region and the third drain region. The third source region and the third drain region extend in opposite two directions with respect to the third channel region.

[0120] The fourth transistor T4 includes a fourth active layer 20d and a fourth gate G4. The fourth active layer 20d may include a fourth source region, a fourth drain region, and a fourth channel region connecting the fourth source region and the fourth drain region. The fourth source region and the fourth drain region extend in opposite two directions with respect to the fourth channel region.

[0121] The fifth transistor T5 includes a fifth active layer 20e and a fifth gate G5. The fifth active layer 20e may include a fifth source region, a fifth drain region, and a fifth channel region connecting the fifth source region and the fifth drain region. The fifth source region and the fifth drain region extend in opposite two directions with respect to the fifth channel region.

[0122] The sixth transistor T6 includes a sixth active layer 20f and a sixth gate G6. The sixth active layer 20f may include a sixth source region, a sixth drain region, and a sixth channel region connecting the sixth source region and the sixth drain region. The sixth source region and the sixth drain region extend in opposite two directions with respect to the sixth channel region.

[0123] The seventh transistor T7 includes a seventh active layer 20g and a seventh gate G7. The seventh active layer 20g may include a seventh source region, a seventh drain region, and a seventh channel region connecting the seventh source region and the seventh drain region. The seventh source region and the seventh drain region extend in opposite two directions with respect to the seventh channel region.

[0124] As Figure 7As shown, the second semiconductor layer 50 includes a first active layer 20a corresponding to the first transistor T1 and a second active layer 20b corresponding to the second transistor T2. For example, the first active layer 20a of the first transistor T1 and the second active layer 20b of the second transistor T2 are in the same extending direction as that of the data line, that is, both extend in the up-down direction in the figure.

[0125] For example, the second semiconductor layer 50 may include an oxide semiconductor material. The active layer of each transistor may include a channel region, a source region, and a drain region. The channel region may not be doped or may have a doping type different from that of the source region and the drain region, and thus has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0126] The first active layer 20a of the first transistor T1 includes a first source region, a first drain region, and a first channel region connecting the first source region and the first drain region. The first source region and the first drain region extend in opposite two directions with respect to the first channel region.

[0127] The second active layer 20b of the second transistor T2 includes a second source region, a second drain region, and a second channel region connecting the second source region and the second drain region. The second source region and the second drain region extend in opposite two directions with respect to the second channel region.

[0128] Continuing to refer to Figure 7 , the second scan signal line 61N includes a first sub-scan signal line 61N1 located in the second conductive layer 40 and a second sub-scan signal line 61N2 located in the third conductive layer 60. The overlapping part of the first sub-scan signal line 61N1 and the second active layer 20b forms the bottom gate of the second transistor T2, and the overlapping part of the second sub-scan signal line 61N2 and the second active layer 20b forms the top gate of the second transistor T2. In this way, the second transistor T2 with a double-gate structure can be formed. It should be understood that in the embodiments of the present disclosure, the first sub-scan signal line 61N1 located in the second conductive layer 40 and the second sub-scan signal line 61N2 located in the third conductive layer 60 can be electrically connected, that is, both are supplied with the first scan signal, so as to form the second scan signal line 61N. Through such a parallel routing method, the stability of the signal transmitted on the second scan signal line 61N can be improved.

[0129] Similarly, the second reset signal line 62N includes a first sub-reset signal line 62N1 located in the second conductive layer 40 and a second sub-reset signal line 62N2 located in the third conductive layer 60. The overlapping portion of the first sub-reset signal line 62N1 and the first active layer 20a forms the bottom gate of the first transistor T1, and the overlapping portion of the second sub-reset signal line 62N2 and the first active layer 20a forms the top gate of the first transistor T1. In this way, the first transistor T1 with a double-gate structure can be formed. It should be understood that in the embodiments of the present disclosure, the first sub-reset signal line 62N1 located in the second conductive layer 40 and the second sub-reset signal line 62N2 located in the third conductive layer 60 can be electrically connected, that is, both are supplied with the first reset signal, so as to form the second reset signal line 62N. By such a parallel routing method, the stability of the signal transmitted on the second reset signal line 62N can be improved.

[0130] In the embodiments of the present disclosure, the plurality of film layers may further include an insulating film layer located between two adjacent film layers among the first semiconductor layer 20, the first conductive layer 30, the second conductive layer 40, the second semiconductor layer 50, the third conductive layer 60, the fourth conductive layer 70, and the fifth conductive layer 80. Below, other film layers (such as insulating film layers) of the display substrate according to the embodiments of the present disclosure will be described in conjunction with Figure 18 the description of other film layers (such as insulating film layers) of the display substrate according to the embodiments of the present disclosure.

[0131] In an exemplary embodiment, the display substrate may include a barrier layer BL1 provided on the substrate 10; and a first buffer layer BL2 provided on the side of the barrier layer BL1 away from the substrate 10.

[0132] For example, the barrier layer BL1 may be formed of silicon oxide and have a thickness of about 5500 angstroms. The first buffer layer BL2 may be formed of silicon nitride and have a thickness of about 1000 angstroms; alternatively, the first buffer layer BL2 may be composed of a stack of silicon nitride and silicon oxide. For example, the first buffer layer BL2 may include a first buffer sub-layer provided on the barrier layer BL1 and a second buffer sub-layer provided on the side of the first buffer sub-layer away from the substrate 10. The first buffer sub-layer includes a silicon nitride material, and the second buffer sub-layer includes a silicon oxide material.

[0133] The display substrate may include a first gate insulating layer GI1 provided between the first semiconductor layer 20 and the first conductive layer 30. For example, the first gate insulating layer GI1 may be formed of silicon oxide.

[0134] The display substrate may include a first interlayer insulating layer ILD1 provided between the first conductive layer 30 and the second conductive layer 40.

[0135] The display substrate may include a second gate insulating layer GI2 disposed between the second conductive layer 40 and the second semiconductor layer 50. For example, the second gate insulating layer GI2 may be formed of silicon oxide. In this way, the second gate insulating layer GI2 formed of silicon oxide may block the penetration of hydrogen (H) into the oxide semiconductor transistors (i.e., T1, T2), so as to improve the performance of the oxide semiconductor transistors (i.e., T1, T2).

[0136] The display substrate may include a third gate insulating layer GI3 disposed between the second semiconductor layer 50 and the third conductive layer 60. For example, the third gate insulating layer GI3 may be formed of silicon oxide. In this way, the third gate insulating layer GI3 formed of silicon oxide may block the penetration of hydrogen (H) into the oxide semiconductor transistors (i.e., T1, T2), so as to improve the performance of the oxide semiconductor transistors (i.e., T1, T2).

[0137] The display substrate may include an interlayer insulating layer ILD2 disposed between the third conductive layer 60 and the fourth conductive layer 70. For example, the interlayer insulating layer ILD2 may be formed of a single layer of silicon oxide, or may be formed of a stacked structure formed of silicon oxide and silicon nitride.

[0138] The display substrate may further include an insulating layer, such as a passivation layer PVX and a planarization layer PLN, disposed between the fourth conductive layer 70 and the fifth conductive layer 80.

[0139] Return reference Figure 1 and Figure 3 , a plurality of sub-pixels are arranged in an array on the substrate 1, that is, multiple rows and multiple columns of sub-pixels are formed on the substrate 1. In Figure 1 , two rows of sub-pixels respectively electrically connected to the scan signal lines 61A and 61B are schematically shown.

[0140] For multiple rows of sub-pixels, since at least one opening is formed on the substrate 1, the number of sub-pixels included in each row of sub-pixels is inconsistent.

[0141] In an embodiment of the present disclosure, the row of sub-pixels with the most sub-pixels in the display substrate may be used as a reference sub-pixel row. For example, Figure 1 the row of sub-pixels electrically connected to the scan signal line 61A in Figure 1 is used as a reference value based on the number of sub-pixels in the reference sub-pixel row, and the row of sub-pixels with the number of sub-pixels less than the reference value is used as a compensation sub-pixel row. For example,

[0142] It should be noted that the scanning signal lines 61A and 61B can be any one of the first scanning signal line 61 and the second scanning signal line 61N described above. For example, the scanning signal lines 61A and 61B can both be the first scanning signal line 61, or the scanning signal lines 61A and 61B can both be the second scanning signal line 61N.

[0143] For convenience of description, the scanning signal line electrically connected to the compensation sub-pixel row can be referred to as the compensation scanning signal line, and the scanning signal line electrically connected to the reference sub-pixel row can be referred to as the reference scanning signal line. It should be understood that the display substrate may include multiple rows of compensation sub-pixel rows and multiple rows of reference sub-pixel rows. Correspondingly, the display substrate may include multiple reference scanning signal lines and multiple compensation scanning signal lines.

[0144] The number of sub-pixels electrically connected to the compensation scanning signal line is less than the number of sub-pixels electrically connected to the reference scanning signal line. In this way, the load on the compensation scanning signal line is less than the load on the reference scanning signal line. Therefore, it is necessary to perform load compensation on the compensation scanning signal line so that the load on the compensation scanning signal line is consistent with the load on the reference scanning signal line, thereby avoiding display differences and ensuring display quality.

[0145] It should be noted that the number of sub-pixels electrically connected to at least two of the compensation scanning signal lines may also be different. In this way, the loads on at least two of the compensation scanning signal lines may also be different from each other. Therefore, it is necessary to perform different load compensations on each of the compensation scanning signal lines so that the loads on each of the compensation scanning signal lines are consistent, thereby avoiding display differences and ensuring display quality.

[0146] It should also be noted that the number of sub-pixels electrically connected to each compensation scanning signal line is related to factors such as the number of openings, the shape of the openings, and the arrangement of the sub-pixels.

[0147] In an embodiment of the present disclosure, a load compensation unit may be provided in the first virtual pixel region DMP1, and the load compensation unit may be electrically connected to the compensation scanning signal line to compensate for the load on the compensation scanning signal line.

[0148] In an embodiment of the present disclosure, the fewer the number of sub-pixels in the compensation sub-pixel row, the smaller the load on the scanning signal line providing the scanning signal for it, and the greater the load to be compensated. Therefore, optionally, in the display substrate provided in the embodiment of the present disclosure, the greater the number of sub-pixels connected to the scanning signal line corresponding to the load compensation unit, the smaller the compensation load value of the load compensation unit. Load compensation units with different compensation load values are used to compensate for scanning signal lines with different numbers of sub-pixels, so as to make the loads on different scanning signal lines uniform, avoid display differences, and ensure display quality.

[0149] For example, the number of sub-pixels included in the reference sub-pixel row is N, and the number of sub-pixels included in the compensation sub-pixel row is M. When compensating the load on the scanning signal line, the value of the load to be compensated can be determined according to the difference between the number of sub-pixels included in the compensation sub-pixel row to be compensated and the number of sub-pixels included in the reference sub-pixel row (i.e., N - M).

[0150] In the embodiments of the present disclosure, the fewer the number of sub-pixels electrically connected to the compensation scanning signal line, the greater the load to be compensated, and correspondingly, the more the number of the first virtual sub-pixel structures electrically connected thereto. For example, the at least one scanning signal line (such as the above-mentioned compensation scanning signal line) may include a first scanning signal line and a second scanning signal line. The first scanning signal line is electrically connected to a plurality of sub-pixels and at least one first virtual sub-pixel structure in a row of sub-pixels, and the second scanning signal line is electrically connected to a plurality of sub-pixels and at least one first virtual sub-pixel structure in another row of sub-pixels. The number of sub-pixels electrically connected to the first scanning signal line is less than the number of sub-pixels electrically connected to the second scanning signal line. Correspondingly, the number of the first virtual sub-pixel structures electrically connected to the first scanning signal line is more than the number of the first virtual sub-pixel structures electrically connected to the second scanning signal line.

[0151] With reference to Figure 1 and Figure 3 , the apertures TH1 and TH2 have the largest size at their centers. Correspondingly, the number of missing sub-pixels in a row of sub-pixels extending along the centers of the apertures TH1 and TH2 is the largest, and the number of missing sub-pixels in a row of sub-pixels extending along the edges of the apertures TH1 and TH2 is relatively small. Thus, in the first virtual pixel region DMP1, the plurality of virtual sub-pixel structures DMPX1 are arranged along the first direction X and the second direction Y, and the number of virtual sub-pixel structures DMPX1 in the same row increases first and then decreases along the second direction Y, that is, the number of virtual sub-pixel structures in a row extending along the centers of the apertures TH1 and TH2 is the largest, and in the direction from the center of the aperture towards the edge of the aperture, the number of virtual sub-pixel structures in the same row gradually decreases.

[0152] It should be noted that in this article, the expression "center" refers to the geometric center or centroid of the pattern.

[0153] In the embodiments of the present disclosure, the load compensation unit can be formed by designing the first virtual pixel structure DMPX1.

[0154] Figure 8A and Figure 8B are respectively equivalent circuit diagrams of the load compensation unit (i.e., the first virtual pixel structure) of the display substrate according to some exemplary embodiments of the present disclosure. Figure 9It is a plan view showing an exemplary embodiment of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure. Figures 10 to 17 It shows Figure 9 a plan view of some film layers of an exemplary embodiment of the virtual sub-pixel structure in. For example, Figures 10 to 17 it schematically shows a first conductive layer, a second conductive layer, a combination of the first conductive layer and the second conductive layer, a third conductive layer, a combination of the first conductive layer, the second conductive layer and the third conductive layer, a fourth conductive layer, a combination of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer, and a fifth conductive layer located in the first virtual pixel region, respectively.

[0155] As described above, corresponding to a plurality of sub-pixels located in the display pixel region DP1, the plurality of first virtual pixel structures DMPX1 may include a plurality of virtual sub-pixel structures DMPX11, DMPX12 and DMPX13. At least one of the plurality of virtual sub-pixel structures DMPX11, DMPX12 and DMPX13 may include a first compensation capacitor C1 and a second compensation capacitor C2.

[0156] In an embodiment of the present disclosure, at least one first scan signal line 61 is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the at least one first scan signal line 61 is also electrically connected to the first compensation capacitor C1 of the at least one virtual sub-pixel structure. In this way, the first compensation capacitor C1 can compensate for the load on the first scan signal line 61. At least one second scan signal line 61N is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the at least one second scan signal line 61N is also electrically connected to the second compensation capacitor C2 of the at least one virtual sub-pixel structure. In this way, the second compensation capacitor C2 can compensate for the load on the second scan signal line 61N.

[0157] For example, the first scan signal line 61 is located in the first conductive layer 30, the second scan signal line 61N is at least located in the second conductive layer 40, or the second scan signal line 61N includes portions respectively located in the second conductive layer 40 and the third conductive layer 60.

[0158] In an embodiment of the present disclosure, by designing a compensation capacitor in the virtual pixel region, which is electrically connected to the scan signal line, in this way, the load on the first scan signal line and the second scan signal line can be compensated, so that the loads on different scan signal lines are uniform, avoiding display differences and ensuring display quality.

[0159] In an embodiment of the present disclosure, the capacitance values of the compensation capacitors C1 and C2 of the virtual sub-pixel structure are designed to be relatively large. Through such a design, the loads on the first scan signal line and the second scan signal line belonging to the compensation scan signal lines can be compensated, so that the loads on different scan signal lines are uniform, avoiding display differences and ensuring the display quality.

[0160] With reference to Figures 9 to 17 , in the first virtual pixel region DMP1, the display substrate may include a first reset signal line 62, a light emission control line 63, and a first compensation structure 100a located in the first conductive layer 30. That is, the first compensation structure 100a is located in the first conductive layer 30.

[0161] The first compensation structure 100a includes a first main body portion 110a, a first compensation structure protrusion 111a, and a second compensation structure protrusion 112a. The orthographic projection of the first main body portion 110a on the substrate has a generally rectangular shape. The "generally rectangular" here may include a rectangle, a square, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, and other shapes. The first compensation structure protrusion 111a and the second compensation structure protrusion 112a are respectively located on opposite sides of the first main body portion 110a. The first compensation structure protrusion 111a and the second compensation structure protrusion 112a protrude in opposite directions with respect to the first main body portion 110a. For example, the first compensation structure protrusion 111a extends leftward with respect to the first main body portion 110a in the first direction X, and the second compensation structure protrusion 112a extends rightward with respect to the first main body portion 110a in the first direction X.

[0162] The first dimension H1a of the positive projection of the first main body portion 110a on the substrate along the second direction Y is greater than the second dimension H2a of the positive projection of the first compensation structure protruding portion 111a on the substrate along the second direction Y, and the first dimension H1a of the positive projection of the first main body portion 110a on the substrate along the second direction Y is greater than the third dimension H3a of the positive projection of the second compensation structure protruding portion 112a on the substrate along the second direction Y. For example, the second dimension H2a of the positive projection of the first compensation structure protruding portion 111a on the substrate along the second direction Y is substantially equal to the third dimension H3a of the positive projection of the second compensation structure protruding portion 112a on the substrate along the second direction Y, or rather, the ratio of the second dimension H2a to the third dimension H3a is between 0.8 and 1.2. The first dimension H1a of the positive projection of the first main body portion 110a on the substrate along the second direction Y is much greater than the second dimension H2a of the positive projection of the first compensation structure protruding portion 111a on the substrate along the second direction Y. For example, the ratio of the first dimension H1a to the second dimension H2a or the third dimension H3a is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

[0163] In the first virtual pixel region DMP1, the display substrate may include a first reset signal line 62 and a light emission control line 63 located in the first conductive layer 30. In this article, the same expressions and reference numerals are used to describe the first reset signal line 62 and the light emission control line 63, indicating that the first reset signal line 62 and the light emission control line 63 extend from the display pixel region DP1 to the first virtual pixel region DMP1 respectively.

[0164] In an embodiment of the present disclosure, the first compensation structure 100a located in the first virtual pixel region DMP1 is electrically connected to the first scan signal line 61 located in the display pixel region DP1. For example, the first scan signal line 61 located in the display pixel region DP1 extends from the display pixel region DP1 to the first virtual pixel region DMP1. The width of a part of the first scan signal line 61 located in the first virtual pixel region DMP1 is wider than the width of the part of the first scan signal line 61 located in the display pixel region DP1, that is, the first main body portion 110a is formed. The width of another part of the first scan signal line 61 located in the first virtual pixel region DMP1 (i.e., the first compensation structure protruding portion 111a and the second compensation structure protruding portion 112a) is substantially equal to the width of the part of the first scan signal line 61 located in the display pixel region DP1, or rather, the ratio of the two is between 0.8 and 1.2.

[0165] Refer to Figure 11, in the first virtual pixel region DMP1, the display substrate may include a second compensation structure 200a located in the second conductive layer 40. That is, the second compensation structure 200a is located in the second conductive layer 40. The second compensation structure 200a includes a second main body portion 210a and a second compensation structure connection portion 211a. The orthographic projection of the second main body portion 210a on the substrate has a generally rectangular shape. The "generally rectangular" here may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, and a rectangle with at least one chamfered corner. The second compensation structure connection portion 211a protrudes in one direction relative to the second main body portion 210a. For example, the second compensation structure connection portion 211a protrudes upward relative to the second main body portion 210a.

[0166] With reference to Figures 10 to 12 , the orthographic projections of the first compensation structure 100a and the second compensation structure 200a on the substrate at least partially overlap. For example, the orthographic projection of the first main body portion 110a on the substrate overlaps at least partially with the orthographic projection of the second main body portion 210a on the substrate. In an embodiment of the present disclosure, the overlapping area of the first main body portion 110a and the second main body portion 210a is designed to be relatively large. For example, the orthographic projection of the second main body portion 210a on the substrate substantially covers the orthographic projection of the first main body portion 110a on the substrate. In Figure 12 , the dashed box 130a schematically shows the overlapping region of the first main body portion 110a and the second main body portion 210a. For example, the area of the overlapping region 130a of the first main body portion 110a and the second main body portion 210a is substantially equal to the area of the orthographic projection of the first main body portion 110a on the substrate. Or rather, the ratio of the area of the overlapping region 130a to the area of the orthographic projection of the first main body portion 110a on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 130a to the area of the orthographic projection of the second main body portion 210a on the substrate is between 0.7 and 1, that is, most (for example, more than 70%) of the second main body portion 210a overlaps with the first main body portion 110a.

[0167] For example, the orthographic projection of the first main body portion 110a on the substrate has a dimension W1a along the first direction X and a dimension H1a along the second direction Y, and the orthographic projection of the second main body portion 210a on the substrate has a dimension W7a along the first direction X and a dimension H7a along the second direction Y. The dimension W1a may be smaller than the dimension W7a, and the dimension H1a may be smaller than the dimension H7a. For example, the ratio of the dimension W1a to the dimension W7a may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of the dimension H1a to the dimension H7a may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

[0168] Reference Figure 13 and Figure 14 In the first virtual pixel region DMP1, the display substrate may include a third compensation structure 300a located in the third conductive layer 60. That is, the third compensation structure 300a is located in the third conductive layer 60.

[0169] The third compensation structure 300a includes a third main body portion 310a, a third compensation structure protrusion 311a, and a fourth compensation structure protrusion 312a. The orthographic projection of the third main body portion 310a on the substrate has a generally rectangular shape. The "generally rectangular" here may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, etc. The third compensation structure protrusion 311a and the fourth compensation structure protrusion 312a are respectively located on opposite sides of the third main body portion 310a. The third compensation structure protrusion 311a and the fourth compensation structure protrusion 312a protrude in opposite directions with respect to the third main body portion 310a. For example, the third compensation structure protrusion 311a extends leftward with respect to the third main body portion 310a in the first direction X, and the fourth compensation structure protrusion 312a extends rightward with respect to the third main body portion 310a in the first direction X.

[0170] The first dimension H4a of the orthographic projection of the third main body portion 310a on the substrate along the second direction Y is greater than the second dimension H5a of the orthographic projection of the third compensation structure protrusion 311a on the substrate along the second direction Y, and the first dimension H4a of the orthographic projection of the third main body portion 310a on the substrate along the second direction Y is greater than the third dimension H6a of the orthographic projection of the fourth compensation structure protrusion 312a on the substrate along the second direction Y. For example, the second dimension H5a of the orthographic projection of the third compensation structure protrusion 311a on the substrate along the second direction Y is substantially equal to the third dimension H6a of the orthographic projection of the fourth compensation structure protrusion 312a on the substrate along the second direction Y, or rather, the ratio of the second dimension H5a to the third dimension H6a is between 0.8 and 1.2. The first dimension H4a of the orthographic projection of the third main body portion 310a on the substrate along the second direction Y is much greater than the second dimension H5a of the orthographic projection of the third compensation structure protrusion 311a on the substrate along the second direction Y. For example, the ratio of the first dimension H4a to the second dimension H5a or the third dimension H6a is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

[0171] In an embodiment of the present disclosure, a third compensation structure 300a located in the first virtual pixel region DMP1 is electrically connected to a second scanning signal line 61N located in the display pixel region DP1. For example, the second scanning signal line 61N located in the display pixel region DP1 extends from the display pixel region DP1 to the first virtual pixel region DMP1. The width of a part of the second scanning signal line 61N located in the first virtual pixel region DMP1 is wider than the width of the part of the second scanning signal line 61N located in the display pixel region DP1, that is, the third main body portion 310a is formed. The width of another part of the second scanning signal line 61N located in the first virtual pixel region DMP1 (i.e., the third compensation structure protrusion 311a and the fourth compensation structure protrusion 312a) is substantially equal to the width of the part of the second scanning signal line 61N located in the display pixel region DP1, or rather, the ratio between the two is between 0.8 and 1.2.

[0172] With reference to Figures 13 to 14 , the orthographic projections of the second compensation structure 200a and the third compensation structure 300a on the substrate at least partially overlap. For example, the orthographic projection of the second main body portion 210a on the substrate at least partially overlaps with the orthographic projection of the third main body portion 310a on the substrate. In an embodiment of the present disclosure, the overlapping area of the second main body portion 210a and the third main body portion 310a is designed to be relatively large. For example, the orthographic projection of the second main body portion 210a on the substrate substantially covers the orthographic projection of the third main body portion 310a on the substrate. In Figure 14 , the dashed box 150a schematically shows the overlapping region of the third main body portion 310a and the second main body portion 210a. For example, the area of the overlapping region 150a of the third main body portion 310a and the second main body portion 210a is substantially equal to the area of the orthographic projection of the third main body portion 310a on the substrate. Or rather, the ratio of the area of the overlapping region 150a to the area of the orthographic projection of the third main body portion 310a on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 150a to the area of the orthographic projection of the second main body portion 210a on the substrate is between 0.7 and 1, that is, most (for example, more than 70%) of the second main body portion 210a overlaps with the third main body portion 310a.

[0173] For example, the orthographic projection of the third main body portion 310a on the substrate has a dimension W4a along the first direction X and a dimension H4a along the second direction Y. The dimension W4a can be smaller than the dimension W7a, and the dimension H1a can be smaller than the dimension H4a. For example, the ratio of the dimension W4a to the dimension W7a can be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of the dimension H4a to the dimension H7a can be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

[0174] Referring to Figures 15 to 17 , in the first virtual pixel region DMP1, the display substrate may further include an initialization voltage line 66 and a compensation connection portion 160a located in the fourth conductive layer 70. Herein, the same reference numerals and descriptions are used for the initialization voltage line 66, indicating that the initialization voltage line 66 extends from the display pixel region DP1 to the first virtual pixel region DMP1. In the first virtual pixel region DMP1, the display substrate may further include a data signal line 64 and a first voltage line 65 located in the fifth conductive layer 80. Herein, the same reference numerals and descriptions are used for the data signal line 64 and the first voltage line 65, indicating that the data signal line 64 and the first voltage line 65 respectively extend from the display pixel region DP1 to the first virtual pixel region DMP1.

[0175] With reference to Figure 9 , Figures 15 to 17 , one end of the compensation connection portion 160a is electrically connected to the second compensation structure 200a through a via 1601a, and the other end is electrically connected to the first voltage line 65 through a via 1602a. For example, the via 1601a exposes a part of the second compensation structure connection portion 211a, and the compensation connection portion 160a located in the fourth conductive layer 70 is electrically connected to the second compensation structure connection portion 211a located in the second conductive layer 40 through the via 1601a. The via 1602a exposes a part of the compensation connection portion 160a, and the first voltage line 65 located in the fifth conductive layer 80 is electrically connected to the compensation connection portion 160a located in the fourth conductive layer 70 through the via 1602a. Through the compensation connection portion 160a, the second compensation structure 200a can be electrically connected to the first voltage line 65. In this way, the first voltage (such as the VDD voltage) can be transmitted to the second compensation structure 200a.

[0176] In an embodiment of the present disclosure, the first compensation structure 100a located in the first conductive layer 30 is electrically connected to the first scan signal line 61, that is, the first compensation structure 100a is supplied with the second scan signal. The second compensation structure 200a located in the second conductive layer 40 is electrically connected to the first voltage line 65, that is, the second compensation structure 200a is supplied with the first voltage. And, the first compensation structure 100a and the second compensation structure 200a have a large overlapping area. In this way, a first compensation capacitor C1 can be formed between the first compensation structure 100a and the second compensation structure 200a, as Figure 8A shown, which schematically shows the first compensation capacitor C1. That is, one plate of the first compensation capacitor C1 is the first compensation structure 100a, especially the first main body portion 110a of the first compensation structure 100a; the other plate is the second compensation structure 200a, especially the second main body portion 210a of the second compensation structure 200a.

[0177] The capacitance value of the first compensation capacitor C1 is related to the overlapping area between the first compensation structure 100a and the second compensation structure 200a. As described above, the overlapping area between the first compensation structure 100a and the second compensation structure 200a is designed to be large. Correspondingly, the capacitance value of the first compensation capacitor C1 is also large. The first compensation capacitor C1 is a load applied to the first scan signal line 61. Since the capacitance value of the first compensation capacitor C1 is large, the load applied to the first scan signal line 61 is also large, thereby achieving the purpose of compensating the load on the second scan signal line.

[0178] In an embodiment of the present disclosure, the third compensation structure 300a in the third conductive layer 60 is electrically connected to the second scan signal line 61N, that is, the third compensation structure 300a is supplied with the second scan signal. The second compensation structure 200a in the second conductive layer 40 is electrically connected to the first voltage line 65, that is, the second compensation structure 200a is supplied with the first voltage. And, the third compensation structure 300a and the second compensation structure 200a have a large overlapping area. In this way, a second compensation capacitor C2 can be formed between the third compensation structure 300a and the second compensation structure 200a, as Figure 8B shown, which schematically shows the second compensation capacitor C2. That is to say, one plate of the second compensation capacitor C2 is the third compensation structure 300a, especially the third main body portion 310a of the third compensation structure 300a; the other plate is the second compensation structure 200a, especially the second main body portion 210a of the second compensation structure 200a.

[0179] The capacitance value of the second compensation capacitor C2 is related to the overlapping area between the third compensation structure 300a and the second compensation structure 200a. As described above, the overlapping area between the third compensation structure 300a and the second compensation structure 200a is designed to be large. Correspondingly, the capacitance value of the second compensation capacitor C2 is also large. The second compensation capacitor C2 is a load applied to the second scan signal line 61N. Since the capacitance value of the second compensation capacitor C2 is large, the load applied to the second scan signal line 61N is also large, thereby achieving the purpose of compensating the load on the first scan signal line.

[0180] In an embodiment of the present disclosure, for the first scanning signal line 61 that extends through the display pixel region DP1 and the regions where the openings TH1 and TH2 are located (including the first virtual pixel region DMP1), the number of display sub-pixels electrically connected thereto is less than the number of display sub-pixels electrically connected to a reference scanning signal line, resulting in a smaller load on such a first scanning signal line 61 (i.e., the above-mentioned compensation scanning signal line) than on the reference scanning signal line. For such a first scanning signal line 61, in the first display pixel region DP1, the first scanning signal line 61 located in the first conductive layer 30 is spaced apart (i.e., non-overlapping) from the components located in the second conductive layer 40 and the third conductive layer 60; in the first virtual pixel region DMP1, as described above, a first compensation capacitor C1 is formed, and the capacitance value of the first compensation capacitor C1 is relatively large. In this way, the first compensation capacitor C1 can compensate for the load on such a first scanning signal line 61 (i.e., the above-mentioned compensation scanning signal line), so that the loads on each of the first scanning signal lines 61 are consistent, which is beneficial to improving the display performance.

[0181] In an embodiment of the present disclosure, for the second scanning signal line 61N that extends through the display pixel region DP1 and the regions where the openings TH1 and TH2 are located (including the first virtual pixel region DMP1), the number of display sub-pixels electrically connected thereto is less than the number of display sub-pixels electrically connected to a reference scanning signal line, resulting in a smaller load on such a second scanning signal line 61N (i.e., the above-mentioned compensation scanning signal line) than on the reference scanning signal line. For such a second scanning signal line 61N, in the first display pixel region DP1, although the first sub-scanning signal line 61N1 and the second sub-scanning signal line 61N2 partially overlap, both the first sub-scanning signal line 61N1 and the second sub-scanning signal line 61N2 are supplied with the first scanning signal, that is, almost no parasitic capacitance is formed between the first sub-scanning signal line 61N1 and the second sub-scanning signal line 61N2; in the first virtual pixel region DMP1, as described above, a second compensation capacitor C2 is formed, and the capacitance value of the second compensation capacitor C2 is relatively large. In this way, the second compensation capacitor C2 can compensate for the load on such a second scanning signal line 61N (i.e., the above-mentioned compensation scanning signal line), so that the loads on each of the second scanning signal lines 61N are consistent, which is beneficial to improving the display performance.

[0182] Figure 19 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. Figure 20 is a plan view showing an exemplary embodiment of sub-pixels in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure. It should be noted that the following will focus on Figure 19 and Figure 20The differences between the illustrated embodiments and the above-described embodiments are as follows. For the similarities between them, reference may be made to the above description and will not be elaborated herein. That is to say, in this document, in the absence of conflict, the various embodiments or implementation manners may be combined with each other.

[0183] With reference to Figure 19 and Figure 20 , the pixel driving circuit may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0184] The display substrate may further include a plurality of signal lines. For example, the plurality of signal lines include: a first scan signal line 61 and a second scan signal line 61N for transmitting scan signals, a second reset signal line 62N for transmitting a reset control signal, a light emission control line 63 for transmitting a light emission control signal, a data signal line 64 for transmitting data signals, a first voltage line 65 for transmitting a first voltage, a first initialization voltage line 66 and a second initialization voltage line 68 for transmitting initialization voltages, and a second voltage line 67 for transmitting a second voltage. For example, the first voltage may be a VDD voltage, the second voltage may be a VSS voltage, and the first voltage may be higher than the second voltage.

[0185] Continuing to refer to Figure 19 and Figure 20 , the gate G1 of the first transistor T1 is electrically connected to the second reset signal line 62N, and the source S1 of the first transistor T1 is electrically connected to the first initialization voltage line 66. And the drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3. As Figure 19 shown, the drain D1 of the first transistor T1, one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected at a node N1. The first transistor T1 is turned on according to the reset control signal transmitted through the second reset signal line 62N to transmit the first initialization voltage signal Vint1 to the gate G1 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, the first transistor T1 is also referred to as an initialization transistor.

[0186] The gate G2 of the second transistor T2 is electrically connected to the second scan signal line 61N, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on according to the scan signal transmitted through the second scan signal line 61N to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing diode connection of the third transistor T3.

[0187] The gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3. The third transistor T3 receives a data signal according to the switching operation of the fourth transistor T4 to supply a driving current Id to the OLED. That is, the third transistor T3 is also referred to as a driving transistor.

[0188] The gate G4 of the fourth transistor T4 is electrically connected to the first scan signal line 61, the source S4 of the fourth transistor T4 is electrically connected to the data signal line 64, and the drain D4 of the fourth transistor T4 is electrically connected to the node N2, that is, electrically connected to the source S3 of the third transistor T3. The fourth transistor T4 is turned on according to the scan signal transmitted through the first scan signal line 61 to perform a switching operation to transmit the data signal to the source S3 of the third transistor T3.

[0189] The gate G5 of the fifth transistor T5 is electrically connected to the light emission control line 63, the source S5 of the fifth transistor T5 is electrically connected to the first voltage line 65. And the drain D5 of the fifth transistor T5 is electrically connected to the node N2.

[0190] The gate G6 of the sixth transistor T6 is electrically connected to the light emission control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, that is, electrically connected to the anode of the light emitting element OLED. The fifth transistor T5 and the sixth transistor T6 are turned on concurrently (e.g., simultaneously) according to the light emission control signal transmitted through the light emission control line 63 to transmit the first voltage to the OLED, thereby allowing the driving current Id to flow into the OLED.

[0191] The gate G7 of the seventh transistor T7 is electrically connected to the first scan signal line 61, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the second initialization voltage line 68.

[0192] One end (hereinafter referred to as the first capacitive electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1, and the other end (hereinafter referred to as the second capacitive electrode) Cst2 is electrically connected to the first voltage line 65.

[0193] The anode of the OLED is electrically connected to node N4, and the cathode is electrically connected to the second voltage line 67 to receive the second voltage VSS. Accordingly, the OLED receives the driving current Id from the third transistor T3 to emit light, thereby displaying an image.

[0194] That is to say, in this embodiment, two initialization voltage lines 66 and 68 are provided. The first initialization voltage line 66 transmits the first initialization voltage signal Vint1 to the first transistor T1, and the second initialization voltage line 68 transmits the second initialization voltage signal Vint2 to the seventh transistor T7. In this way, the initialization voltage signals transmitted to the first transistor T1 and the seventh transistor T7 can be adjusted respectively, which is beneficial to improving the display performance of the display panel.

[0195] Figure 21A and Figure 21B are equivalent circuit diagrams of the load compensation unit (i.e., the first virtual pixel structure) of the display substrate according to some exemplary embodiments of the present disclosure. Figure 22 is a plan view showing an exemplary embodiment of the virtual sub-pixel structure of the display substrate according to some exemplary embodiments of the present disclosure. Figures 23 to 32 is showing Figure 22 some film layers of the exemplary embodiment of the virtual sub-pixel structure in Figures 23 to 32 schematically show the sixth conductive layer, the first conductive layer, the combination of the sixth conductive layer and the first conductive layer, the second conductive layer, the combination of the sixth conductive layer, the first conductive layer and the second conductive layer, the third conductive layer, the combination of the sixth conductive layer, the first conductive layer, the second conductive layer and the third conductive layer, the fourth conductive layer, the combination of the sixth conductive layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer, and the fifth conductive layer located in the first virtual pixel region respectively.

[0196] As described above, corresponding to the multiple sub-pixels located in the display pixel region DP1, the multiple first virtual pixel structures DMPX1 may include multiple virtual sub-pixel structures DMPX11, DMPX12, and DMPX13. At least one of the multiple virtual sub-pixel structures DMPX11, DMPX12, and DMPX13 may include a first compensation capacitor C1 and a second compensation capacitor C2.

[0197] In an embodiment of the present disclosure, at least one first scan signal line 61 is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the at least one first scan signal line 61 is also electrically connected to the first compensation capacitor C1 of the at least one virtual sub-pixel structure. In this way, the first compensation capacitor C1 can compensate for the load on the first scan signal line 61. At least one second scan signal line 61N is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels, and the at least one second scan signal line 61N is also electrically connected to the second compensation capacitor C2 of the at least one virtual sub-pixel structure. In this way, the second compensation capacitor C2 can compensate for the load on the second scan signal line 61N.

[0198] For example, the first scan signal line 61 is located in the first conductive layer 30, and the second scan signal line 61N is at least located in the second conductive layer 40, or the second scan signal line 61N includes portions respectively located in the second conductive layer 40 and the third conductive layer 60.

[0199] In an embodiment of the present disclosure, by designing a compensation capacitor in the virtual pixel region, the compensation capacitor is electrically connected to the scan signal line. In this way, the loads on the first scan signal line and the second scan signal line can be compensated, so that the loads on different scan signal lines are uniform, avoiding display differences and ensuring display quality.

[0200] In an embodiment of the present disclosure, the capacitance values of the compensation capacitors C1 and C2 of the virtual sub-pixel structure are designed to be relatively large. Through such a design, the loads on the first scan signal line and the second scan signal line belonging to the compensation scan signal line can be compensated, so that the loads on different scan signal lines are uniform, avoiding display differences and ensuring display quality.

[0201] With reference to Figures 19 to 32 , the display substrate includes a plurality of film layers disposed on the substrate. In some embodiments, the plurality of film layers at least include a sixth conductive layer 90, a first semiconductor layer 20, a first conductive layer 30, a second conductive layer 40, a second semiconductor layer 50, a third conductive layer 60, a fourth conductive layer 70, and a fifth conductive layer 80. The sixth conductive layer 90, the first semiconductor layer 20, the first conductive layer 30, the second conductive layer 40, the second semiconductor layer 50, the third conductive layer 60, the fourth conductive layer 70, and the fifth conductive layer 80 are sequentially disposed away from the substrate 10.

[0202] In the first virtual pixel region DMP1, the display substrate may include a fourth compensation structure 400b located in the sixth conductive layer 90. For example, the sixth conductive layer 90 may be a light-shielding layer, that is, the fourth compensation structure 400b is located in the light-shielding layer.

[0203] The fourth compensation structure 400b may include a fourth main body portion 410b, and the orthographic projection of the fourth main body portion 410b on the substrate has a substantially rectangular shape. The "substantially rectangular" here may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, etc.

[0204] It should be understood that the sixth conductive layer 90 may further include other structures or portions for shielding the semiconductor layer.

[0205] The display substrate may include a light-emitting control line 63 and a first compensation structure 100b located in the first conductive layer 30. That is, the first compensation structure 100b is located in the first conductive layer 30.

[0206] The first compensation structure 100b includes a first main body portion 110b, a first compensation structure protrusion 111b, and a second compensation structure protrusion 112b. The orthographic projection of the first main body portion 110b on the substrate has a substantially rectangular shape. The "substantially rectangular" here may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, etc. The first compensation structure protrusion 111b and the second compensation structure protrusion 112b are respectively located on opposite sides of the first main body portion 110b. The first compensation structure protrusion 111b and the second compensation structure protrusion 112b protrude in opposite directions with respect to the first main body portion 110b. For example, the first compensation structure protrusion 111b extends leftward with respect to the first main body portion 110b in the first direction X, and the second compensation structure protrusion 112b extends rightward with respect to the first main body portion 110b in the first direction X.

[0207] The first dimension H1b of the positive projection of the first main body portion 110b on the substrate along the second direction Y is greater than the second dimension H2b of the positive projection of the first compensation structure protruding portion 111b on the substrate along the second direction Y, and the first dimension H1b of the positive projection of the first main body portion 110b on the substrate along the second direction Y is greater than the third dimension H3b of the positive projection of the second compensation structure protruding portion 112b on the substrate along the second direction Y. For example, the second dimension H2b of the positive projection of the first compensation structure protruding portion 111b on the substrate along the second direction Y is substantially equal to the third dimension H3b of the positive projection of the second compensation structure protruding portion 112b on the substrate along the second direction Y, or rather, the ratio of the second dimension H2b to the third dimension H3b is between 0.8 and 1.2. The first dimension H1b of the positive projection of the first main body portion 110b on the substrate along the second direction Y is much greater than the second dimension H2b of the positive projection of the first compensation structure protruding portion 111b on the substrate along the second direction Y. For example, the ratio of the first dimension H1b to the second dimension H2b or the third dimension H3b is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

[0208] In an embodiment of the present disclosure, the first compensation structure 100b located in the first virtual pixel region DMP1 is electrically connected to the first scan signal line 61 located in the display pixel region DP1. For example, the first scan signal line 61 located in the display pixel region DP1 extends from the display pixel region DP1 to the first virtual pixel region DMP1. The width of a part of the first scan signal line 61 located in the first virtual pixel region DMP1 is wider than the width of the part of the first scan signal line 61 located in the display pixel region DP1, that is, the first main body portion 110b is formed. The width of another part of the first scan signal line 61 located in the first virtual pixel region DMP1 (i.e., the first compensation structure protruding portion 111b and the second compensation structure protruding portion 112b) is substantially equal to the width of the part of the first scan signal line 61 located in the display pixel region DP1, or rather, the ratio between the two is between 0.8 and 1.2.

[0209] The positive projections of the first compensation structure 100b and the fourth compensation structure 400b on the substrate at least partially overlap. For example, the positive projection of the first main body portion 110b on the substrate at least partially overlaps with the positive projection of the fourth main body portion 410b on the substrate. In an embodiment of the present disclosure, the overlapping area of the first main body portion 110b and the fourth main body portion 410b is designed to be relatively large. For example, the positive projection of the first main body portion 110b on the substrate substantially covers the positive projection of the fourth main body portion 410b on the substrate. In Figure 25In [description], the dashed box 120b schematically shows the overlapping region of the first main body portion 110b and the fourth main body portion 410b. For example, the area of the overlapping region 120b of the first main body portion 110b and the fourth main body portion 410b is substantially equal to the area of the orthographic projection of the fourth main body portion 410b on the substrate. Or rather, the ratio of the area of the overlapping region 120b to the area of the orthographic projection of the fourth main body portion 410b on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 120b to the area of the orthographic projection of the first main body portion 110b on the substrate is between 0.3 and 1, or between 0.35 and 0.8, or between 0.4 and 0.6.

[0210] In the first virtual pixel region DMP1, the display substrate may include a second compensation structure 200b, a first initialization voltage line 66, and a first sub-reset signal line 62N1 located in the second conductive layer 40. That is, the second compensation structure 200b is located in the second conductive layer 40. The second compensation structure 200b includes a second main body portion 210b. The orthographic projection of the second main body portion 210b on the substrate has a substantially rectangular shape. The "substantially rectangular" here may include shapes such as rectangles, squares, rectangles with at least one rounded corner, and rectangles with at least one chamfered corner.

[0211] The orthographic projections of the first compensation structure 100b and the second compensation structure 200b on the substrate at least partially overlap. For example, the orthographic projection of the first main body portion 110b on the substrate and the orthographic projection of the second main body portion 210b on the substrate at least partially overlap. In the embodiments of the present disclosure, the overlapping area of the first main body portion 110b and the second main body portion 210b is designed to be relatively large. For example, the orthographic projection of the second main body portion 210b on the substrate substantially covers the orthographic projection of the first main body portion 110b on the substrate. In Figure 27 In [description], the dashed box 130b schematically shows the overlapping region of the first main body portion 110b and the second main body portion 210b. For example, the area of the overlapping region 130b of the first main body portion 110b and the second main body portion 210b is substantially equal to the area of the orthographic projection of the first main body portion 110b on the substrate. Or rather, the ratio of the area of the overlapping region 130b to the area of the orthographic projection of the first main body portion 110b on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 130b to the area of the orthographic projection of the second main body portion 210b on the substrate is between 0.7 and 1, that is, most (for example, more than 70%) of the second main body portion 210b overlaps with the first main body portion 110b.

[0212] For example, the orthographic projection of the first main body portion 110b on the substrate has a size W1b in the first direction X and a size H1b in the second direction Y, and the orthographic projection of the second main body portion 210b on the substrate has a size W7b in the first direction X and a size H7b in the second direction Y. The size W1b may be smaller than the size W7b, and the size H1b may be smaller than the size H7b. For example, the ratio of the size W1b to the size W7b may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of the size H1b to the size H7b may be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

[0213] In the first virtual pixel region DMP1, the display substrate may include a third compensation structure 300b and a second sub-reset signal line 62N2 located in the third conductive layer 60. That is, the third compensation structure 300b is located in the third conductive layer 60.

[0214] The third compensation structure 300b includes a third main body portion 310b, a third compensation structure protrusion 311b, and a fourth compensation structure protrusion 312b. The orthographic projection of the third main body portion 310b on the substrate has a shape of a substantially rectangle or a rectangle with a missing corner. Here, the "substantially rectangle" may include a rectangle, a square, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, and other shapes. The third compensation structure protrusion 311b and the fourth compensation structure protrusion 312b are respectively located on opposite sides of the third main body portion 310b. The third compensation structure protrusion 311b and the fourth compensation structure protrusion 312b protrude in opposite directions with respect to the third main body portion 310b. For example, the third compensation structure protrusion 311b extends leftward with respect to the third main body portion 310b in the first direction X, and the fourth compensation structure protrusion 312b extends rightward with respect to the third main body portion 310b in the first direction X.

[0215] The first dimension H4b of the positive projection of the third main body portion 310b on the substrate along the second direction Y is greater than the second dimension H5b of the positive projection of the third compensation structure protruding portion 311b on the substrate along the second direction Y. The first dimension H4b of the positive projection of the third main body portion 310b on the substrate along the second direction Y is greater than the third dimension H6b of the positive projection of the fourth compensation structure protruding portion 312b on the substrate along the second direction Y. For example, the second dimension H5b of the positive projection of the third compensation structure protruding portion 311b on the substrate along the second direction Y is substantially equal to the third dimension H6b of the positive projection of the fourth compensation structure protruding portion 312b on the substrate along the second direction Y. Or rather, the ratio of the second dimension H5b to the third dimension H6b is between 0.8 and 1.2. The first dimension H4b of the positive projection of the third main body portion 310b on the substrate along the second direction Y is much greater than the second dimension H5b of the positive projection of the third compensation structure protruding portion 311b on the substrate along the second direction Y. For example, the ratio of the first dimension H4b to the second dimension H5b or the third dimension H6b is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

[0216] In an embodiment of the present disclosure, the third compensation structure 300b located in the first virtual pixel region DMP1 is electrically connected to the second scanning signal line 61N located in the display pixel region DP1. For example, the second scanning signal line 61N located in the display pixel region DP1 extends from the display pixel region DP1 to the first virtual pixel region DMP1. The width of a part of the second scanning signal line 61N located in the first virtual pixel region DMP1 is wider than the width of the part of the second scanning signal line 61N located in the display pixel region DP1, that is, the third main body portion 310b is formed. The width of another part of the second scanning signal line 61N located in the first virtual pixel region DMP1 (i.e., the third compensation structure protruding portion 311b and the fourth compensation structure protruding portion 312b) is substantially equal to the width of the part of the second scanning signal line 61N located in the display pixel region DP1. Or rather, the ratio of the two is between 0.8 and 1.2.

[0217] The positive projections of the second compensation structure 200b and the third compensation structure 300b on the substrate at least partially overlap. For example, the positive projection of the second main body portion 210b on the substrate at least partially overlaps with the positive projection of the third main body portion 310b on the substrate. In an embodiment of the present disclosure, the overlapping area of the second main body portion 210b and the third main body portion 310b is designed to be relatively large. For example, the positive projection of the second main body portion 210b on the substrate substantially covers the positive projection of the third main body portion 310b on the substrate. In Figure 29In [description], the dashed box 150b schematically shows the overlapping region of the third main body portion 310b and the second main body portion 210b. For example, the area of the overlapping region 150b of the third main body portion 310b and the second main body portion 210b is substantially equal to the area of the orthographic projection of the third main body portion 310b on the substrate. In other words, the ratio of the area of the overlapping region 150b to the area of the orthographic projection of the third main body portion 310b on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 150b to the area of the orthographic projection of the second main body portion 210b on the substrate is between 0.7 and 1, that is, most (e.g., more than 70%) of the second main body portion 210b overlaps with the third main body portion 310b.

[0218] For example, the orthographic projection of the third main body portion 310b on the substrate has a dimension W4b along the first direction X and a dimension H4b along the second direction Y. The dimension W4b can be smaller than the dimension W7b, and the dimension H1b can be smaller than the dimension H4b. For example, the ratio of the dimension W4b to the dimension W7b can be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of the dimension H4b to the dimension H7b can be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

[0219] In the first virtual pixel region DMP1, the display substrate may further include a second initialization voltage line 68, a compensation connection portion 160b, and a first transfer portion 161b located in the fourth conductive layer 70. In the first virtual pixel region DMP1, the display substrate may further include a data signal line 64, a first voltage line 65, a fifth compensation structure 500b, and a second transfer portion 420b located in the fifth conductive layer 80. In this article, the same expressions and reference numerals are used to describe the data signal line 64 and the first voltage line 65, indicating that the data signal line 64 and the first voltage line 65 extend from the display pixel region DP1 to the first virtual pixel region DMP1 respectively.

[0220] The fifth compensation structure 500b includes a fifth main body portion 510b. The orthographic projection of the fifth main body portion 510b on the substrate has a substantially rectangular shape. Here, "substantially rectangular" may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, etc.

[0221] For example, the fifth main body portion 510b may be formed as an integral structure with the first voltage line 65, that is, the fifth main body portion 510b may be a part of the first voltage line 65, or in other words, the fifth main body portion 510b is a widened portion of the first voltage line 65.

[0222] The size W8b of the positive projection of the fifth main body portion 510b on the substrate along the first direction X is greater than the size W9b of the positive projection of the first voltage line 65 on the substrate along the first direction X. For example, the ratio of the size W8b to the size W9b is greater than or equal to 3, or greater than or equal to 4, or between 3 and 30, or between 3 and 10, or between 3 and 8.

[0223] The positive projections of the fifth compensation structure 500b and the third compensation structure 300b on the substrate at least partially overlap. For example, the positive projection of the fifth main body portion 510b on the substrate at least partially overlaps with the positive projection of the third main body portion 310b on the substrate. In the embodiments of the present disclosure, the overlapping area of the fifth main body portion 510b and the third main body portion 310b is designed to be relatively large. For example, the positive projection of the third main body portion 310b on the substrate substantially covers the positive projection of the fifth main body portion 510b on the substrate. In Figure 22 FIG., the dashed box 180b schematically shows the overlapping region of the fifth main body portion 510b and the third main body portion 310b. For example, the area of the overlapping region 180b of the fifth main body portion 510b and the third main body portion 310b is slightly larger than the area of the positive projection of the fifth main body portion 510b on the substrate. Or rather, the ratio of the area of the overlapping region 180b to the area of the positive projection of the fifth main body portion 510b on the substrate is between 1.1 and 1.9. The ratio of the area of the overlapping region 180b to the area of the positive projection of the third main body portion 310b on the substrate is between 0.4 and 0.7, or between 0.4 and 0.6.

[0224] One end of the compensation connection portion 160b is electrically connected to the second compensation structure 200b through the via 1601b, and the other end is electrically connected to the first voltage line 65 through the via 1602b.

[0225] For example, the positive projection of the third main body portion 310b on the substrate has a rectangular shape with a missing corner. In this way, most of the second main body portion 210b is covered by the third main body portion 310b, and the missing corner portion of the third main body portion 310b can expose the second main body portion 210b located below it. The via 1601b further exposes the second main body portion 210b, and the compensation connection portion 160b in the fourth conductive layer 70 is electrically connected to the second main body portion 210b in the second conductive layer 40 through this via 1601b. The via 1602b exposes a part of the compensation connection portion 160b, and the first voltage line 65 in the fifth conductive layer 80 is electrically connected to the compensation connection portion 160b in the fourth conductive layer 70 through this via 1602b. Through the compensation connection portion 160b, the second compensation structure 200b can be electrically connected to the first voltage line 65. In this way, the first voltage (such as the VDD voltage) can be transmitted to the second compensation structure 200b.

[0226] In an embodiment of the present disclosure, the fourth compensation structure in the sixth conductive layer 90 may be supplied with the first voltage; the first compensation structure 100b in the first conductive layer 30 is electrically connected to the first scanning signal line 61, that is, the first compensation structure 100b is supplied with the second scanning signal; the second compensation structure 200b in the second conductive layer 40 is electrically connected to the first voltage line 65, that is, the second compensation structure 200b is supplied with the first voltage. Moreover, there is an overlapping area with an increased area between the fourth compensation structure 400b and the first compensation structure 100b, and there is an overlapping area with a relatively large area between the first compensation structure 100b and the second compensation structure 200b. In this way, a capacitor can be formed between the fourth compensation structure 400b and the first compensation structure 100b and between the first compensation structure 100b and the second compensation structure 200b respectively, and these two capacitors are connected in parallel to form the first compensation capacitor C1, as Figure 21A shown, which schematically shows the first compensation capacitor C1. That is to say, the first compensation capacitor C1 includes two capacitors connected in parallel. For example, the first compensation sub-capacitor C11 and the second compensation sub-capacitor C12 are connected in parallel. One plate of one capacitor (for example, the second compensation sub-capacitor C12) is the fourth compensation structure 400b, especially the fourth main body portion 410b of the fourth compensation structure 400b, and the other plate is the first compensation structure 100b, especially the first main body portion 110b of the first compensation structure 100b; one plate of the other capacitor (for example, the first compensation sub-capacitor C11) is the first compensation structure 100b, especially the first main body portion 110b of the first compensation structure 100b, and the other plate is the second compensation structure 200b, especially the second main body portion 210b of the second compensation structure 200b.

[0227] The capacitance value of the first compensation capacitor C1 is related to the overlapping area between the fourth compensation structure 400b and the first compensation structure 100b and the overlapping area between the first compensation structure 100b and the second compensation structure 200b. As described above, the overlapping area between the fourth compensation structure 400b and the first compensation structure 100b and the overlapping area between the first compensation structure 100b and the second compensation structure 200b are designed to be relatively large. Correspondingly, the capacitance value of the first compensation capacitor C1 is also relatively large. The first compensation capacitor C1 is a load applied to the first scanning signal line 61. Since the capacitance value of the first compensation capacitor C1 is relatively large, the load applied to the first scanning signal line 61 is also relatively large, so as to achieve the purpose of compensating the load on the first scanning signal line.

[0228] In this embodiment, the first compensation capacitor C1 includes two capacitors connected in parallel. Accordingly, the capacitance value of the first compensation capacitor C1 can be further increased. In addition, the areas of the first compensation structure and the second compensation structure themselves can be appropriately reduced, which is conducive to realizing a display panel with a high PPI.

[0229] In an embodiment of the present disclosure, the second compensation structure 200b located in the second conductive layer 40 is electrically connected to the first voltage line 65, that is, the second compensation structure 200b is supplied with the first voltage; the third compensation structure 300b located in the third conductive layer 60 is electrically connected to the second scan signal line 61N, that is, the third compensation structure 300b is supplied with the second scan signal; the fifth compensation structure 500b located in the fifth conductive layer 80 is electrically connected to the first voltage line 65, that is, the fifth compensation structure 500b is supplied with the first voltage. And, there is an overlapping area with an increased area between the second compensation structure 200b and the third compensation structure 300b, and there is an overlapping area with a relatively large area between the fifth compensation structure 500b and the third compensation structure 300b. In this way, capacitors can be formed between the second compensation structure 200b and the third compensation structure 300b and between the fifth compensation structure 500b and the third compensation structure 300b respectively, and these two capacitors are connected in parallel to form the second compensation capacitor C2, as Figure 21B shown, which schematically shows the second compensation capacitor C2. That is to say, the second compensation capacitor C2 includes two capacitors connected in parallel. For example, a third compensation sub-capacitor C21 and a fourth compensation sub-capacitor C22, and the third compensation sub-capacitor C21 and the fourth compensation sub-capacitor C22 are connected in parallel. One plate of one capacitor (for example, the third compensation sub-capacitor C21) is the second compensation structure 200b, especially the second main body portion 210b of the second compensation structure 200b, and the other plate is the third compensation structure 300b, especially the third main body portion 310b of the third compensation structure 300b; one plate of the other capacitor (for example, the fourth compensation sub-capacitor C22) is the third compensation structure 300b, especially the third main body portion 310b of the third compensation structure 300b, and the other plate is the fifth compensation structure 500b, especially the fifth main body portion 510b of the fifth compensation structure 500b.

[0230] The capacitance value of the second compensation capacitor C2 is related to the overlapping areas between the second compensation structure 200b and the third compensation structure 300b, and between the fifth compensation structure 500b and the third compensation structure 300b. As described above, the overlapping areas between the second compensation structure 200b and the third compensation structure 300b, and between the fifth compensation structure 500b and the third compensation structure 300b are designed to be relatively large. Correspondingly, the capacitance value of the second compensation capacitor C2 is also relatively large. This second compensation capacitor C2 is a load applied to the second scan signal line 61N. Since the capacitance value of the second compensation capacitor C2 is relatively large, the load applied to the second scan signal line 61N is also relatively large, thereby achieving the purpose of compensating the load on the second scan signal line.

[0231] In this embodiment, the second compensation capacitor C2 includes two capacitors connected in parallel. Correspondingly, the capacitance value of the second compensation capacitor C2 can be further increased. In addition, the areas of the second compensation structure and the third compensation structure themselves can be appropriately reduced, which is beneficial to realizing a display panel with a high PPI.

[0232] It should be noted that, in this embodiment, the second connection part 420b is electrically connected to the first connection part 161 through the via 1604b, and the first connection part 161 is electrically connected to other components through the via 1603, which will not be elaborated here.

[0233] Figure 33 It is a plan view showing an exemplary embodiment of sub-pixels in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure, in which a plan view of two adjacent sub-pixels in the display pixel region is schematically shown. Figure 34 It is a plan view showing an exemplary embodiment of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure, in which a plan view of two adjacent virtual sub-pixel structures in the first virtual pixel region is schematically shown. Figures 35 to 42 It shows Figure 34 a plan view of some film layers of an exemplary embodiment of two adjacent virtual sub-pixel structures in Figures 35 to 42 For example, it schematically shows the first conductive layer, the second conductive layer, the combination of the first conductive layer and the second conductive layer, the third conductive layer, the combination of the first conductive layer, the second conductive layer and the third conductive layer, the fourth conductive layer, the combination of the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer, and the fifth conductive layer located in the first virtual pixel region, respectively.

[0234] It should be noted that the following will focus on describing Figures 33 to 42The differences between the illustrated embodiments and the above-described embodiments are as follows. For their similarities, reference may be made to the above description and will not be elaborated herein. That is to say, in this document, in the absence of conflicts, the various embodiments or implementation manners may be combined with each other.

[0235] With reference to Figures 33 to 42 , the pixel driving circuit may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0236] The display substrate may further include a plurality of signal lines. For example, the plurality of signal lines include: a first scan signal line 61 and a second scan signal line 61N for transmitting scan signals, a second reset signal line 62N for transmitting a reset control signal, a light emission control line 63 for transmitting a light emission control signal, a data signal line 64 for transmitting data signals, a first voltage line 65 for transmitting a first voltage, a first initialization voltage line 66 and a second initialization voltage line 68 for transmitting an initialization voltage, and a second voltage line 67 for transmitting a second voltage. For example, the first voltage may be a VDD voltage, the second voltage may be a VSS voltage, and the first voltage may be higher than the second voltage.

[0237] For example, in the display pixel region, between two adjacent sub-pixels, there is a first axis of symmetry AX1, and the orthographic projections of the two adjacent sub-pixels on the substrate are axisymmetric with respect to the first axis of symmetry AX1. It should be noted that in this document, the axis of symmetry represents a virtual line rather than a physical line.

[0238] For example, in the first virtual pixel region, between two adjacent virtual sub-pixel structures, there is a second axis of symmetry AX2, and the orthographic projections of the two adjacent virtual sub-pixel structures on the substrate are axisymmetric with respect to the second axis of symmetry AX2.

[0239] With reference to Figures 33 to 42 , in the first virtual pixel region DMP1, the display substrate may include a light emission control line 63 and a first compensation structure 100c located in the first conductive layer 30. That is, the first compensation structure 100c is located in the first conductive layer 30.

[0240] The first compensation structure 100c includes a first main body portion 110c, a first compensation structure protrusion 111c, and a second compensation structure protrusion 112c. The orthographic projection of the first main body portion 110c on the substrate has a substantially rectangular shape. Here, the "substantially rectangular" can include shapes such as rectangles, squares, rectangles with at least one rounded corner, rectangles with at least one chamfered corner, etc. The first compensation structure protrusion 111c and the second compensation structure protrusion 112c are respectively located on opposite sides of the first main body portion 110c. The first compensation structure protrusion 111c and the second compensation structure protrusion 112c protrude in opposite directions with respect to the first main body portion 110c.

[0241] The first dimension H1c of the orthographic projection of the first main body portion 110c on the substrate along the second direction Y is greater than the second dimension H2c of the orthographic projection of the first compensation structure protrusion 111c on the substrate along the second direction Y, and the first dimension H1c of the orthographic projection of the first main body portion 110c on the substrate along the second direction Y is greater than the third dimension H3c of the orthographic projection of the second compensation structure protrusion 112c on the substrate along the second direction Y. For example, the second dimension H2c of the orthographic projection of the first compensation structure protrusion 111c on the substrate along the second direction Y is substantially equal to the third dimension H3c of the orthographic projection of the second compensation structure protrusion 112c on the substrate along the second direction Y, or rather, the ratio of the second dimension H2c to the third dimension H3c is between 0.8 and 1.2. The first dimension H1c of the orthographic projection of the first main body portion 110c on the substrate along the second direction Y is much greater than the second dimension H2c of the orthographic projection of the first compensation structure protrusion 111c on the substrate along the second direction Y. For example, the ratio of the first dimension H1c to the second dimension H2c or the third dimension H3c is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

[0242] In two adjacent virtual sub-pixel structures, the two first compensation structures 100c are axially symmetric with respect to the second axis of symmetry AX2.

[0243] The second compensation structure protrusions 112c of the two first compensation structures 100c are connected to each other. In an embodiment of the present disclosure, the first compensation structure 100c located in the first virtual pixel region DMP1 is electrically connected to the first scanning signal line 61 located in the display pixel region DP1. For example, the first scanning signal line 61 located in the display pixel region DP1 extends from the display pixel region DP1 to the first virtual pixel region DMP1. The width of a part of the first scanning signal line 61 located in the first virtual pixel region DMP1 is wider than the width of the part of the first scanning signal line 61 located in the display pixel region DP1, that is, the first main body portion 110c is formed. The width of another part of the first scanning signal line 61 located in the first virtual pixel region DMP1 (that is, the first compensation structure protrusion 111c and the second compensation structure protrusion 112c) is substantially equal to the width of the part of the first scanning signal line 61 located in the display pixel region DP1, or rather, the ratio between the two is between 0.8 and 1.2.

[0244] In the first virtual pixel region DMP1, the display substrate may include a second compensation structure 200c located in the second conductive layer 40. That is, the second compensation structure 200c is located in the second conductive layer 40. The second compensation structure 200c includes a second main body portion 210c and a second compensation structure connection portion 211c. The orthographic projection of the second main body portion 210c on the substrate has a substantially rectangular shape. The "substantially rectangular" here may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, etc. The second compensation structure connection portion 211c protrudes in one direction with respect to the second main body portion 210c.

[0245] For example, in the first virtual pixel region DMP1, the second compensation structures 200c between adjacent sub-pixel structures are arranged at intervals.

[0246] In two adjacent virtual sub-pixel structures, the two second compensation structures 200c are axisymmetric with respect to the second axis of symmetry AX2.

[0247] The orthographic projections of the first compensation structure 100c and the second compensation structure 200c on the substrate at least partially overlap. For example, the orthographic projection of the first main body portion 110c on the substrate at least partially overlaps with the orthographic projection of the second main body portion 210c on the substrate. In an embodiment of the present disclosure, the overlapping area of the first main body portion 110c and the second main body portion 210c is designed to be relatively large. For example, the orthographic projection of the second main body portion 210c on the substrate substantially covers the orthographic projection of the first main body portion 110c on the substrate. The dashed box 130c schematically shows the overlapping area of the first main body portion 110c and the second main body portion 210c. For example, the area of the overlapping area 130c of the first main body portion 110c and the second main body portion 210c is substantially equal to the area of the orthographic projection of the first main body portion 110c on the substrate. Or rather, the ratio of the area of the overlapping area 130c to the area of the orthographic projection of the first main body portion 110c on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping area 130c to the area of the orthographic projection of the second main body portion 210c on the substrate is between 0.7 and 1, that is, most (for example, more than 70%) of the second main body portion 210c overlaps with the first main body portion 110c.

[0248] For example, the orthographic projection of the first main body portion 110c on the substrate has a dimension W1c along the first direction X and a dimension H1c along the second direction Y, and the orthographic projection of the second main body portion 210c on the substrate has a dimension W7c along the first direction X and a dimension H7c along the second direction Y. The dimension W1c can be smaller than the dimension W7c, and the dimension H1c can be smaller than the dimension H7c. For example, the ratio of the dimension W1c to the dimension W7c can be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of the dimension H1c to the dimension H7c can be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

[0249] In the first virtual pixel region DMP1, the display substrate may include a third compensation structure 300c located in the third conductive layer 60. That is, the third compensation structure 300c is located in the third conductive layer 60.

[0250] The third compensation structure 300c includes a third main body portion 310c, a third compensation structure protruding portion 311c, and a fourth compensation structure protruding portion 312c. The orthographic projection of the third main body portion 310c on the substrate has a generally rectangular shape. Here, the "generally rectangular" can include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, etc. The third compensation structure protruding portion 311c and the fourth compensation structure protruding portion 312c are respectively located on opposite sides of the third main body portion 310c. The third compensation structure protruding portion 311c and the fourth compensation structure protruding portion 312c protrude in opposite directions with respect to the third main body portion 310c.

[0251] The first dimension H4c of the orthographic projection of the third main body portion 310c on the substrate along the second direction Y is greater than the second dimension H5c of the orthographic projection of the third compensation structure protruding portion 311c on the substrate along the second direction Y, and the first dimension H4c of the orthographic projection of the third main body portion 310c on the substrate along the second direction Y is greater than the third dimension H6c of the orthographic projection of the fourth compensation structure protruding portion 312c on the substrate along the second direction Y. For example, the second dimension H5c of the orthographic projection of the third compensation structure protruding portion 311c on the substrate along the second direction Y is substantially equal to the third dimension H6c of the orthographic projection of the fourth compensation structure protruding portion 312c on the substrate along the second direction Y, or rather, the ratio of the second dimension H5c to the third dimension H6c is between 0.8 and 1.2. The first dimension H4c of the orthographic projection of the third main body portion 310c on the substrate along the second direction Y is much greater than the second dimension H5c of the orthographic projection of the third compensation structure protruding portion 311c on the substrate along the second direction Y. For example, the ratio of the first dimension H4c to the second dimension H5c or the third dimension H6c is greater than or equal to 5, or greater than or equal to 8, or between 5 and 30, or between 8 and 20, or between 6 and 15.

[0252] In two adjacent virtual sub-pixel structures, the two third compensation structures 300c are axisymmetric with respect to the second axis of symmetry AX2.

[0253] The fourth compensation structure protrusions 312c of the two third compensation structures 300c are connected to each other. In an embodiment of the present disclosure, the third compensation structure 300c located in the first virtual pixel region DMP1 is electrically connected to the second scanning signal line 61N located in the display pixel region DP1. For example, the second scanning signal line 61N located in the display pixel region DP1 extends from the display pixel region DP1 to the first virtual pixel region DMP1. The width of a part of the second scanning signal line 61N located in the first virtual pixel region DMP1 is wider than the width of the part of the second scanning signal line 61N located in the display pixel region DP1, that is, the third main body 310c is formed. The width of another part of the second scanning signal line 61N located in the first virtual pixel region DMP1 (i.e., the third compensation structure protrusion 311c and the fourth compensation structure protrusion 312c) is basically equal to the width of the part of the second scanning signal line 61N located in the display pixel region DP1, or rather, the ratio between the two is between 0.8 and 1.2.

[0254] The positive projections of the second compensation structure 200c and the third compensation structure 300c on the substrate at least partially overlap. For example, the positive projection of the second main body 210c on the substrate at least partially overlaps with the positive projection of the third main body 310c on the substrate. In an embodiment of the present disclosure, the overlapping area of the second main body 210c and the third main body 310c is designed to be relatively large. For example, the positive projection of the second main body 210c on the substrate basically covers the positive projection of the third main body 310c on the substrate. The dashed box 150c schematically shows the overlapping area of the third main body 310c and the second main body 210c. For example, the area of the overlapping area 150c of the third main body 310c and the second main body 210c is basically equal to the area of the positive projection of the third main body 310c on the substrate. Or rather, the ratio of the area of the overlapping area 150c to the area of the positive projection of the third main body 310c on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping area 150c to the area of the positive projection of the second main body 210c on the substrate is between 0.7 and 1, that is, most (for example, more than 70%) of the second main body 210c overlaps with the third main body 310c.

[0255] For example, the positive projection of the third main body 310c on the substrate has a dimension W4c along the first direction X and a dimension H4c along the second direction Y. The dimension W4c can be smaller than the dimension W7c, and the dimension H1c can be smaller than the dimension H4c. For example, the ratio of the dimension W4c to the dimension W7c can be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9. The ratio of the dimension H4c to the dimension H7c can be between 0.7 and 1, or between 0.7 and 0.95, or between 0.8 and 0.9.

[0256] In the first virtual pixel region DMP1, the display substrate may further include a second initialization voltage line 68 and a compensation connection portion 160c located in the fourth conductive layer 70. In the first virtual pixel region DMP1, the display substrate may further include a data signal line 64, a first voltage line 65, and a fifth compensation structure 500c located in the fifth conductive layer 80.

[0257] In two adjacent virtual sub-pixel structures, the two compensation connection portions 160c are spaced apart from each other, and the two compensation connection portions 160c are axisymmetric with respect to the second axis of symmetry AX2.

[0258] The fifth compensation structure 500c includes a fifth main body portion 510c. The orthographic projection of the fifth main body portion 510c on the substrate has a substantially rectangular shape. Here, "substantially rectangular" may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, and a rectangle with at least one chamfered corner.

[0259] For example, the fifth main body portion 510c may be formed as an integral structure with the first voltage line 65, that is, the fifth main body portion 510c may be a part of the first voltage line 65, or rather, the fifth main body portion 510c is a widened portion of the first voltage line 65.

[0260] The dimension W8c of the orthographic projection of the fifth main body portion 510c on the substrate along the first direction X is greater than the dimension W9c of the orthographic projection of the first voltage line 65 on the substrate along the first direction X. For example, the ratio of the dimension W8c to the dimension W9c is greater than or equal to 3, or greater than or equal to 4, or between 3 and 30, or between 3 and 10, or between 3 and 8.

[0261] In two adjacent virtual sub-pixel structures, the two fifth compensation structures 500c are axisymmetric with respect to the second axis of symmetry AX2. For example, the two fifth main body portions 510 are axisymmetric with respect to the second axis of symmetry AX2.

[0262] In two adjacent virtual sub-pixel structures, the two fifth main body portions 510c are connected to each other to form an integral structure. For example, the orthographic projection of the two connected fifth main body portions 510c on the substrate has a rectangular shape. The fifth main body portion 510c itself has a relatively large area. In two adjacent virtual sub-pixel structures, the two fifth main body portions 510c form an integral structure, which is beneficial to the planarization of the film layer covering the fifth conductive layer, and thus beneficial to the subsequent formation process of the anode layer.

[0263] One end of the compensation connection part 160c is electrically connected to the second compensation structure 200c through the via 1601c, and the other end is electrically connected to the first voltage line 65 through the via 1602c. For example, the via 1601c exposes a part of the second compensation structure connection part 211c. The compensation connection part 160c located in the fourth conductive layer 70 is electrically connected to the second compensation structure connection part 211c located in the second conductive layer 40 through the via 1601c. The via 1602c exposes a part of the compensation connection part 160c. The first voltage line 65 located in the fifth conductive layer 80 is electrically connected to the compensation connection part 160c located in the fourth conductive layer 70 through the via 1602c. Through the compensation connection part 160c, the second compensation structure 200c can be electrically connected to the first voltage line 65. In this way, the first voltage (such as the VDD voltage) can be transmitted to the second compensation structure 200c.

[0264] In an embodiment of the present disclosure, the first compensation structure 100c located in the first conductive layer 30 is electrically connected to the first scan signal line 61, that is, the first compensation structure 100c is supplied with the first scan signal. The second compensation structure 200c located in the second conductive layer 40 is electrically connected to the first voltage line 65, that is, the second compensation structure 200c is supplied with the first voltage. And, the first compensation structure 100c and the second compensation structure 200c have a large overlapping area. In this way, a first compensation capacitor C1 can be formed between the first compensation structure 100c and the second compensation structure 200c, as Figure 8A shown, which schematically shows the first compensation capacitor C1. That is to say, one plate of the first compensation capacitor C1 is the first compensation structure 100c, especially the first main body part 110c of the first compensation structure 100c; the other plate is the second compensation structure 200c, especially the second main body part 210c of the second compensation structure 200c.

[0265] The capacitance value of the first compensation capacitor C1 is related to the overlapping area between the first compensation structure 100c and the second compensation structure 200c. As described above, the overlapping area between the first compensation structure 100c and the second compensation structure 200c is designed to be large. Correspondingly, the capacitance value of the first compensation capacitor C1 is also large. The first compensation capacitor C1 is a load applied to the first scan signal line 61. Since the capacitance value of the first compensation capacitor C1 is large, the load applied to the first scan signal line 61 is also large, so as to achieve the purpose of compensating the load on the first scan signal line.

[0266] In an embodiment of the present disclosure, the second compensation structure 200c located in the second conductive layer 40 is electrically connected to the first voltage line 65, that is, the second compensation structure 200c is supplied with the first voltage; the third compensation structure 300c located in the third conductive layer 60 is electrically connected to the second scan signal line 61N, that is, the third compensation structure 300c is supplied with the second scan signal; the fifth compensation structure 500c located in the fifth conductive layer 80 is electrically connected to the first voltage line 65, that is, the fifth compensation structure 500c is supplied with the first voltage. Moreover, there is an overlapping area with an increased area between the second compensation structure 200c and the third compensation structure 300c, and there is an overlapping area with a relatively large area between the fifth compensation structure 500c and the third compensation structure 300c. In this way, capacitors can be formed between the second compensation structure 200c and the third compensation structure 300c and between the fifth compensation structure 500c and the third compensation structure 300c respectively, and these two capacitors are connected in parallel to form the second compensation capacitor C2, as Figure 21B shown, which schematically shows the second compensation capacitor C2. That is to say, the second compensation capacitor C2 includes two capacitors connected in parallel. One plate of one capacitor is the second compensation structure 200c, particularly the second main body portion 210c of the second compensation structure 200c, and the other plate is the third compensation structure 300c, particularly the third main body portion 310c of the third compensation structure 300c; one plate of the other capacitor is the third compensation structure 300c, particularly the third main body portion 310c of the third compensation structure 300c, and the other plate is the fifth compensation structure 500c, particularly the fifth main body portion 510c of the fifth compensation structure 500c.

[0267] The capacitance value of the second compensation capacitor C2 is related to the overlapping area between the second compensation structure 200c and the third compensation structure 300c and the overlapping area between the fifth compensation structure 500c and the third compensation structure 300c. As described above, the overlapping area between the second compensation structure 200c and the third compensation structure 300c and the overlapping area between the fifth compensation structure 500c and the third compensation structure 300c are designed to be relatively large. Correspondingly, the capacitance value of the second compensation capacitor C2 is also relatively large. The second compensation capacitor C2 is a load applied to the second scan signal line 61N. Since the capacitance value of the second compensation capacitor C2 is relatively large, the load applied to the second scan signal line 61N is also relatively large, thereby achieving the purpose of compensating the load on the second scan signal line.

[0268] In this embodiment, the second compensation capacitor C2 includes two capacitors connected in parallel. Correspondingly, the capacitance value of the second compensation capacitor C2 can be further increased. In addition, the areas of the second compensation structure and the third compensation structure themselves can be appropriately reduced, which is beneficial to realizing a display panel with a high PPI.

[0269] Figure 43 is a plan view showing an exemplary embodiment of sub-pixels in a display pixel region of a display substrate according to some exemplary embodiments of the present disclosure, in which a plan view of two adjacent sub-pixels in the display pixel region is schematically shown. Figure 44 is a plan view showing an exemplary embodiment of a virtual sub-pixel structure of a display substrate according to some exemplary embodiments of the present disclosure, in which a plan view of two adjacent virtual sub-pixel structures in a first virtual pixel region is schematically shown. Figures 45 to 54 is showing Figure 44 a plan view of some film layers of an exemplary embodiment of two adjacent virtual sub-pixel structures in. For example, Figures 45 to 54 schematically shows, respectively, a sixth conductive layer, a first conductive layer, a combination of the sixth conductive layer and the first conductive layer, a second conductive layer, a combination of the sixth conductive layer, the first conductive layer and the second conductive layer, a third conductive layer, a combination of the sixth conductive layer, the first conductive layer, the second conductive layer and the third conductive layer, a fourth conductive layer, a combination of the sixth conductive layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer, and a fifth conductive layer located in the first virtual pixel region.

[0270] It should be noted that the differences between the embodiments shown below Figures 43 to 54 and the above embodiments will be described in detail. The similarities between them can be referred to the above description and will not be repeated here. That is to say, in this article, in the case of no conflict, each embodiment or implementation manner can be combined with each other.

[0271] With reference to Figures 43 to 54 , the pixel driving circuit may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0272] The display substrate may further include a plurality of signal lines. For example, the plurality of signal lines include: a first scan signal line 61 and a second scan signal line 61N for transmitting scan signals, a second reset signal line 62N for transmitting a reset control signal, a light emission control line 63 for transmitting a light emission control signal, a data signal line 64 for transmitting data signals, a first voltage line 65 for transmitting a first voltage, a first initialization voltage line 66 and a second initialization voltage line 68 for transmitting an initialization voltage, and a second voltage line 67 for transmitting a second voltage. For example, the first voltage may be a VDD voltage, the second voltage may be a VSS voltage, and the first voltage may be higher than the second voltage.

[0273] For example, in the display pixel region, between two adjacent sub-pixels, there is a first axis of symmetry AX1, and the orthographic projections of the two adjacent sub-pixels on the substrate are axisymmetric with respect to the first axis of symmetry AX1.

[0274] For example, in the first virtual pixel region, between two adjacent virtual sub-pixel structures, there is a second axis of symmetry AX2, and the orthographic projections of the two adjacent virtual sub-pixel structures on the substrate are axisymmetric with respect to the second axis of symmetry AX2.

[0275] With reference to Figures 43 to 54 , the display substrate includes a plurality of film layers disposed on the substrate. In some embodiments, the plurality of film layers at least include a sixth conductive layer 90, a first semiconductor layer 20, a first conductive layer 30, a second conductive layer 40, a second semiconductor layer 50, a third conductive layer 60, a fourth conductive layer 70, and a fifth conductive layer 80. The sixth conductive layer 90, the first semiconductor layer 20, the first conductive layer 30, the second conductive layer 40, the second semiconductor layer 50, the third conductive layer 60, the fourth conductive layer 70, and the fifth conductive layer 80 are sequentially disposed away from the substrate 10.

[0276] In the first virtual pixel region DMP1, the display substrate may include a fourth compensation structure 400d located in the sixth conductive layer 90. For example, the sixth conductive layer 90 may be a light-shielding layer, that is, the fourth compensation structure 400d is located in the light-shielding layer.

[0277] The fourth compensation structure 400d may include a fourth main body portion 410d, a fifth compensation structure protrusion 411d, and a sixth compensation structure protrusion 412d. The orthographic projection of the fourth main body portion 410d on the substrate has a substantially rectangular shape. Here, "substantially rectangular" may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, and a rectangle with at least one chamfered corner. The fifth compensation structure protrusion 411d and the sixth compensation structure protrusion 412d are respectively located on opposite sides of the fourth main body portion 410d. The fifth compensation structure protrusion 411d and the sixth compensation structure protrusion 412d protrude in opposite directions with respect to the fourth main body portion 410d. The sixth compensation structure protrusions 412d of two fourth compensation structures 400d are connected to each other.

[0278] In two adjacent virtual sub-pixel structures, the two fourth compensation structures 400d are axisymmetric with respect to the second axis of symmetry AX2. That is, the orthographic projections of the two fourth compensation structures 400d on the substrate are axisymmetric with respect to the second axis of symmetry AX2.

[0279] With reference to Figures 43 to 54, in the first virtual pixel region DMP1, the display substrate may include a light-emitting control line 63 and a first compensation structure 100d located in the first conductive layer 30. That is, the first compensation structure 100d is located in the first conductive layer 30.

[0280] The first compensation structure 100d includes a first main body portion 110d, a first compensation structure protruding portion 111d, and a second compensation structure protruding portion 112d. The orthographic projection of the first main body portion 110d on the substrate has a substantially rectangular shape. The "substantially rectangular" here may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, and a rectangle with at least one chamfered corner. The second compensation structure protruding portion 112d is spaced apart from the first main body portion 110d, for example, spaced apart in the first direction Y, and the second compensation structure protruding portion 112d extends substantially along the first direction X. The first compensation structure protruding portion 111d extends along the second direction Y of the substrate and is used to connect the first main body portion 110d and the second compensation structure protruding portion 112d.

[0281] In two adjacent virtual sub-pixel structures, the two first compensation structures 100d are axially symmetric with respect to the second axis of symmetry AX2. That is, the orthographic projections of the two first compensation structures 100d on the substrate are axially symmetric with respect to the second axis of symmetry AX2.

[0282] The second compensation structure protruding portions 112d of the two first compensation structures 100d are connected to each other to form a structure extending along the first direction X. In an embodiment of the present disclosure, the first compensation structure 100d located in the first virtual pixel region DMP1 is electrically connected to the first scanning signal line 61 located in the display pixel region DP1. For example, the first scanning signal line 61 located in the display pixel region DP1 extends from the display pixel region DP1 to the first virtual pixel region DMP1. A part of the first scanning signal line 61 located in the first virtual pixel region DMP1 is formed as the second compensation structure protruding portion 112d. That is, the width of this part (i.e., the second compensation structure protruding portion 112d) of the first scanning signal line 61 located in the first virtual pixel region DMP1 is substantially equal to the width of the part of the first scanning signal line 61 located in the display pixel region DP1, or rather, the ratio of the two is between 0.8 and 1.2.

[0283] The orthographic projections of the first compensation structure 100d and the fourth compensation structure 400d on the substrate at least partially overlap. For example, the orthographic projection of the first main body portion 110d on the substrate at least partially overlaps with the orthographic projection of the fourth main body portion 410d on the substrate. In an embodiment of the present disclosure, the overlapping area of the first main body portion 110d and the fourth main body portion 410d is designed to be relatively large. For example, the orthographic projection of the first main body portion 110d on the substrate substantially covers the orthographic projection of the fourth main body portion 410d on the substrate. The dashed box 120d schematically shows the overlapping area of the first main body portion 110d and the fourth main body portion 410d. For example, the area of the overlapping area 120d of the first main body portion 110d and the fourth main body portion 410d is substantially equal to the area of the orthographic projection of the fourth main body portion 410d on the substrate. Or rather, the ratio of the area of the overlapping area 120d to the area of the orthographic projection of the fourth main body portion 410d on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping area 120d to the area of the orthographic projection of the first main body portion 110d on the substrate is between 0.3 and 1, or between 0.35 and 0.9, or between 0.6 and 0.8.

[0284] In the first virtual pixel region DMP1, the display substrate may include a second compensation structure 200d located in the second conductive layer 40. That is, the second compensation structure 200d is located in the second conductive layer 40. The second compensation structure 200d includes a second main body portion 210d and a second compensation structure connection portion 211d. The orthographic projection of the second main body portion 210d on the substrate has a substantially rectangular shape. The "substantially rectangular" here may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, etc. The second compensation structure connection portion 211d protrudes in one direction relative to the second main body portion 210d.

[0285] For example, in the first virtual pixel region DMP1, the second compensation structures 200d between adjacent virtual sub-pixel structures are spaced apart from each other.

[0286] In two adjacent virtual sub-pixel structures, the two second compensation structures 200d are axisymmetric with respect to the second axis of symmetry AX2. That is, the orthographic projections of the two second compensation structures 200d on the substrate are axisymmetric with respect to the second axis of symmetry AX2.

[0287] The orthographic projections of the first compensation structure 100d and the second compensation structure 200d on the substrate at least partially overlap. For example, the orthographic projection of the first main body portion 110d on the substrate at least partially overlaps with the orthographic projection of the second main body portion 210d on the substrate. In an embodiment of the present disclosure, the overlapping area of the first main body portion 110d and the second main body portion 210d is designed to be relatively large. For example, the orthographic projection of the second main body portion 210d on the substrate substantially covers the orthographic projection of the first main body portion 110d on the substrate. The dashed box 130d schematically shows the overlapping area of the first main body portion 110d and the second main body portion 210d. For example, the area of the overlapping area 130d of the first main body portion 110d and the second main body portion 210d is substantially equal to the area of the orthographic projection of the first main body portion 110d on the substrate. Or rather, the ratio of the area of the overlapping area 130d to the area of the orthographic projection of the first main body portion 110d on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping area 130d to the area of the orthographic projection of the second main body portion 210d on the substrate is between 0.7 and 1, that is, most (for example, more than 70%) of the second main body portion 210d overlaps with the first main body portion 110d.

[0288] In the first virtual pixel region DMP1, the display substrate may include a third compensation structure 300d located in the third conductive layer 60. That is, the third compensation structure 300d is located in the third conductive layer 60.

[0289] The third compensation structure 300d includes a third main body portion 310d, a third compensation structure protrusion 311d, and a fourth compensation structure protrusion 312d. The orthographic projection of the third main body portion 310d on the substrate has a substantially rectangular shape. The "substantially rectangular" here may include shapes such as a rectangle, a square, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, etc. The third compensation structure protrusion 311d and the fourth compensation structure protrusion 312d are respectively located on opposite sides of the third main body portion 310d. The third compensation structure protrusion 311d and the fourth compensation structure protrusion 312d protrude in opposite directions with respect to the third main body portion 310d.

[0290] In two adjacent virtual sub-pixel structures, the two third compensation structures 300d are axially symmetric with respect to the second axis of symmetry AX2.

[0291] The fourth compensation structure protrusions 312d of the two third compensation structures 300d are connected to each other. In an embodiment of the present disclosure, the third compensation structure 300d located in the first virtual pixel region DMP1 is electrically connected to the second scan signal line 61N located in the display pixel region DP1. For example, the second scan signal line 61N located in the display pixel region DP1 extends from the display pixel region DP1 to the first virtual pixel region DMP1. The width of a part of the second scan signal line 61N located in the first virtual pixel region DMP1 is wider than the width of the part of the second scan signal line 61N located in the display pixel region DPI, that is, the third main body portion 310d is formed. The width of another part of the second scan signal line 61N located in the first virtual pixel region DMP1 (that is, the third compensation structure protrusion 311d and the fourth compensation structure protrusion 312d) is substantially equal to the width of the part of the second scan signal line 61N located in the display pixel region DPI, or rather, the ratio between the two is between 0.8 and 1.2.

[0292] The positive projections of the second compensation structure 200d and the third compensation structure 300d on the substrate at least partially overlap. For example, the positive projection of the second main body portion 210d on the substrate at least partially overlaps with the positive projection of the third main body portion 310d on the substrate. In an embodiment of the present disclosure, the overlapping area of the second main body portion 210d and the third main body portion 310d is designed to be relatively large. For example, the positive projection of the second main body portion 210d on the substrate substantially covers the positive projection of the third main body portion 310d on the substrate. The dashed box 150d schematically shows the overlapping region of the third main body portion 310d and the second main body portion 210d. For example, the area of the overlapping region 150d of the third main body portion 310d and the second main body portion 210d is substantially equal to the area of the positive projection of the third main body portion 310d on the substrate. Or rather, the ratio of the area of the overlapping region 150d to the area of the positive projection of the third main body portion 310d on the substrate is between 0.8 and 1.2. The ratio of the area of the overlapping region 150d to the area of the positive projection of the second main body portion 210d on the substrate is between 0.7 and 1, that is, most (for example, more than 70%) of the second main body portion 210d overlaps with the third main body portion 310d.

[0293] In the first virtual pixel region DMP1, the display substrate may further include a second initialization voltage line 68 and a compensation connection portion 160d located in the fourth conductive layer 70. In the first virtual pixel region DMP1, the display substrate may further include a data signal line 64, a first voltage line 65, and a fifth compensation structure 500d located in the fifth conductive layer 80.

[0294] In two adjacent virtual sub-pixel structures, two compensation connection portions 160d are connected to each other through a connection structure extending along the first direction X, and the two compensation connection portions 160d are axially symmetric with respect to the second axis of symmetry AX2.

[0295] The fifth compensation structure 500d includes a fifth main body portion 510d. The orthographic projection of the fifth main body portion 510d on the substrate has a substantially rectangular shape. The "substantially rectangular" here may include shapes such as rectangles, squares, rectangles with at least one rounded corner, rectangles with at least one chamfered corner, etc.

[0296] For example, the fifth main body portion 510d can be formed as an integral structure with the first voltage line 65, that is, the fifth main body portion 510d can be a part of the first voltage line 65, or rather, the fifth main body portion 510d is a widened portion of the first voltage line 65.

[0297] In two adjacent virtual sub-pixel structures, two fifth compensation structures 500d are axially symmetric with respect to the second axis of symmetry AX2. For example, two fifth main body portions 510 are axially symmetric with respect to the second axis of symmetry AX2. That is, the orthographic projections of the two fifth compensation structures 500d on the substrate are axially symmetric with respect to the second axis of symmetry AX2. For example, the orthographic projections of the two fifth main body portions 510 on the substrate are axially symmetric with respect to the second axis of symmetry AX2.

[0298] In two adjacent virtual sub-pixel structures, two fifth main body portions 510d are connected to each other to form an integral structure. The fifth main body portion 510d itself has a relatively large area. In two adjacent virtual sub-pixel structures, the two fifth main body portions 510d form an integral structure, which is beneficial to the planarization of the film layer covering the fifth conductive layer, and thus beneficial to the subsequent formation process of the anode layer.

[0299] One end of the compensation connection portion 160d is electrically connected to the second compensation structure 200d through a via 1601d, and the other end is electrically connected to the first voltage line 65 through a via 1602d. For example, the via 1601d exposes a part of the second compensation structure connection portion 211d. The compensation connection portion 160d located in the fourth conductive layer 70 is electrically connected to the second compensation structure connection portion 211d located in the second conductive layer 40 through the via 1601d. The via 1602d exposes a part of the compensation connection portion 160d. The first voltage line 65 located in the fifth conductive layer 80 is electrically connected to the compensation connection portion 160d located in the fourth conductive layer 70 through the via 1602d. Through the compensation connection portion 160d, the second compensation structure 200d can be electrically connected to the first voltage line 65. In this way, the first voltage (such as the VDD voltage) can be transmitted to the second compensation structure 200d.

[0300] In an embodiment of the present disclosure, the fourth compensation structure 400d located in the sixth conductive layer 90 may be supplied with the first voltage; the first compensation structure 100d located in the first conductive layer 30 is electrically connected to the first scan signal line 61, that is, the first compensation structure 100d is supplied with the first scan signal; the second compensation structure 200d located in the second conductive layer 40 is electrically connected to the first voltage line 65, that is, the second compensation structure 200d is supplied with the first voltage. Moreover, there is an overlapping area with an increased area between the fourth compensation structure 400d and the first compensation structure 100d, and there is an overlapping area with a relatively large area between the first compensation structure 100d and the second compensation structure 200d. In this way, a capacitance can be formed between the fourth compensation structure 400d and the first compensation structure 100d and between the first compensation structure 100d and the second compensation structure 200d respectively, and these two capacitances are connected in parallel to form the first compensation capacitor C1, as Figure 21A shown, which schematically shows the first compensation capacitor C1. That is to say, the first compensation capacitor C1 includes two capacitances connected in parallel. One plate of one capacitance is the fourth compensation structure 400d, particularly the fourth main body portion 410d of the fourth compensation structure 400d, and the other plate is the first compensation structure 100d, particularly the first main body portion 110d of the first compensation structure 100d; one plate of the other capacitance is the first compensation structure 100d, particularly the first main body portion 110d of the first compensation structure 100d, and the other plate is the second compensation structure 200d, particularly the second main body portion 210d of the second compensation structure 200d.

[0301] The capacitance value of the first compensation capacitor C1 is related to the overlapping area between the fourth compensation structure 400d and the first compensation structure 100d and the overlapping area between the first compensation structure 100d and the second compensation structure 200d. As described above, the overlapping area between the fourth compensation structure 400d and the first compensation structure 100d and the overlapping area between the first compensation structure 100d and the second compensation structure 200d are designed to be relatively large. Correspondingly, the capacitance value of the first compensation capacitor C1 is also relatively large. The first compensation capacitor C1 is a load applied to the first scan signal line 61. Since the capacitance value of the first compensation capacitor C1 is relatively large, the load applied to the first scan signal line 61 is also relatively large, thereby achieving the purpose of compensating the load on the first scan signal line.

[0302] In this embodiment, the first compensation capacitor C1 includes two capacitances connected in parallel. Correspondingly, the capacitance value of the first compensation capacitor C1 can be further increased. In addition, the areas of the first compensation structure and the second compensation structure themselves can be appropriately reduced, which is beneficial to realizing a display panel with a high PPI.

[0303] In an embodiment of the present disclosure, a second compensation structure 200d in the second conductive layer 40 is electrically connected to the first voltage line 65, that is, the second compensation structure 200d is supplied with the first voltage; a third compensation structure 300d in the third conductive layer 60 is electrically connected to the second scan signal line 61N, that is, the third compensation structure 300d is supplied with the second scan signal; a fifth compensation structure 500d in the fifth conductive layer 80 is electrically connected to the first voltage line 65, that is, the fifth compensation structure 500d is supplied with the first voltage. Moreover, there is an overlapping region with an increased area between the second compensation structure 200d and the third compensation structure 300d, and there is an overlapping region with a relatively large area between the fifth compensation structure 500d and the third compensation structure 300d. In this way, capacitors can be formed between the second compensation structure 200d and the third compensation structure 300d and between the fifth compensation structure 500d and the third compensation structure 300d respectively, and these two capacitors are connected in parallel to form a second compensation capacitor C2, as Figure 21B shown, which schematically shows the second compensation capacitor C2. That is to say, the second compensation capacitor C2 includes two capacitors connected in parallel. One plate of one capacitor is the second compensation structure 200d, especially the second main body portion 210d of the second compensation structure 200d, and the other plate is the third compensation structure 300d, especially the third main body portion 310d of the third compensation structure 300d; one plate of the other capacitor is the third compensation structure 300d, especially the third main body portion 310d of the third compensation structure 300d, and the other plate is the fifth compensation structure 500d, especially the fifth main body portion 510d of the fifth compensation structure 500d.

[0304] The capacitance value of the second compensation capacitor C2 is related to the overlapping area between the second compensation structure 200d and the third compensation structure 300d and the overlapping area between the fifth compensation structure 500d and the third compensation structure 300d. As described above, the overlapping area between the second compensation structure 200d and the third compensation structure 300d and the overlapping area between the fifth compensation structure 500d and the third compensation structure 300d are designed to be relatively large. Correspondingly, the capacitance value of the second compensation capacitor C2 is also relatively large. The second compensation capacitor C2 is a load applied to the second scan signal line 61N. Since the capacitance value of the second compensation capacitor C2 is relatively large, the load applied to the second scan signal line 61N is also relatively large, thereby achieving the purpose of compensating the load on the second scan signal line.

[0305] In this embodiment, the second compensation capacitor C2 includes two capacitors connected in parallel. Correspondingly, the capacitance value of the second compensation capacitor C2 can be further increased. In addition, the areas of the second compensation structure and the third compensation structure themselves can be appropriately reduced, which is beneficial to realizing a display panel with a high PPI.

[0306] At least some embodiments of the present disclosure also provide a display panel, which includes the display substrate as described above. For example, the display panel may be an OLED display panel.

[0307] Referring Figure 1 , at least some embodiments of the present disclosure also provide a display device. The display device may include the display substrate as described above.

[0308] The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e - book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head - mounted device, electronic clothing, an electronic bracelet, an electronic necklace, electronic accessories, an electronic tattoo, or a smart watch), a television, etc.

[0309] It should be understood that the display panel and the display device according to the embodiments of the present disclosure have all the characteristics and advantages of the above - mentioned display substrate. For details, reference may be made to the above description and will not be elaborated herein.

[0310] Although some embodiments of the general technical concept of the present disclosure have been shown and described, those of ordinary skill in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general technical concept. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, the display substrate comprising a display pixel region and a first virtual pixel region, characterized in that, the display substrate comprises: a substrate substrate; a plurality of sub-pixels disposed on the substrate substrate and located in the display pixel region, the plurality of sub-pixels being arranged in an array along a first direction and a second direction, each sub-pixel comprising a pixel driving circuit, the pixel driving circuit comprising a driving transistor, a second transistor and a fourth transistor, each of the driving transistor, the second transistor and the fourth transistor comprising a gate, a first pole and a second pole, a first pole of the second transistor being electrically connected to one of the first pole and the second pole of the driving transistor, a second pole of the second transistor being electrically connected to the gate of the driving transistor, and the fourth transistor being configured to control writing of a data signal; a plurality of virtual sub-pixel structures disposed on the substrate substrate and located in the first virtual pixel region, at least one virtual sub-pixel structure comprising a first compensation capacitor and a second compensation capacitor; and a first scan signal line and a second scan signal line disposed on the substrate substrate, the first scan signal line being configured to supply a first scan signal to a gate of the fourth transistor, the second scan signal line being configured to supply a second scan signal to a gate of the second transistor, and both the first scan signal line and the second scan signal line extending through the display pixel region and the first virtual pixel region, wherein the first scan signal line is electrically connected to the gates of the fourth transistors of the pixel driving circuits of each sub-pixel in a row of sub-pixels, and the first scan signal line is further electrically connected to the first compensation capacitor of the at least one virtual sub-pixel structure; and the second scan signal line is electrically connected to the gates of the second transistors of the pixel driving circuits of each sub-pixel in a row of sub-pixels, and the second scan signal line is further electrically connected to the second compensation capacitor of the at least one virtual sub-pixel structure.

2. The display substrate according to claim 1, wherein, the display substrate comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer and a third conductive layer disposed on the substrate substrate, the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer and the third conductive layer being sequentially disposed away from the substrate substrate; an active layer of the fourth transistor is located in the first semiconductor layer, and a gate of the fourth transistor is located in the first conductive layer; an active layer of the second transistor is located in the second semiconductor layer, a gate of the second transistor comprises a bottom gate and a top gate, the bottom gate of the second transistor is located in the second conductive layer, and the top gate of the second transistor is located in the third conductive layer; in the first virtual pixel region, the display substrate comprises: a first compensation structure located in the first conductive layer; a second compensation structure located in the second conductive layer; and a third compensation structure located in the third conductive layer.

3. The display substrate according to claim 2, wherein, The first compensation capacitor includes at least a part of the first compensation structure and at least a part of the second compensation structure; The second compensation capacitor includes at least a part of the second compensation structure and at least a part of the third compensation structure.

4. The display substrate according to claim 2, wherein, The first compensation capacitor includes a first compensation sub-capacitor and a second compensation sub-capacitor, the first compensation sub-capacitor and the second compensation sub-capacitor are connected in parallel, and the first compensation sub-capacitor includes at least a part of the first compensation structure and at least a part of the second compensation structure; and / or, The second compensation capacitor includes a third compensation sub-capacitor and a fourth compensation sub-capacitor, the third compensation sub-capacitor and the fourth compensation sub-capacitor are connected in parallel, and the third compensation sub-capacitor includes at least a part of the second compensation structure and at least a part of the third compensation structure.

5. The display substrate according to claim 4, wherein, The first scan signal line is located in the first conductive layer, and the first compensation structure is electrically connected to the first scan signal line.

6. The display substrate according to claim 5, wherein, The display substrate further includes a first voltage line disposed on the substrate for transmitting a first voltage; The second compensation structure is electrically connected to the first voltage line.

7. The display substrate according to claim 6, wherein, The orthographic projection of the first compensation structure on the substrate at least partially overlaps with the orthographic projection of the second compensation structure on the substrate.

8. The display substrate according to claim 7, wherein, The second scan signal line includes a first sub-scan signal line located in the second conductive layer and a second sub-scan signal line located in the third conductive layer; The third compensation structure is electrically connected to the second scan signal line.

9. The display substrate according to claim 8, wherein, The orthographic projection of the third compensation structure on the substrate at least partially overlaps with the orthographic projection of the second compensation structure on the substrate.

10. The display substrate according to claim 8 or 9, wherein, The first compensation structure includes a first main body portion, the second compensation structure includes a second main body portion, and the orthographic projection of the second main body portion on the substrate covers the orthographic projection of the first main body portion on the substrate.

11. The display substrate according to claim 10, wherein, The third compensation structure includes a third main body portion, and the orthographic projection of the second main body portion on the substrate covers the orthographic projection of the third main body portion on the substrate.

12. The display substrate according to claim 11, wherein, The area of the overlapping region of the first main body portion and the second main body portion is more than 70% of the area of the orthographic projection of the second main body portion on the substrate; and / or, The area of the overlapping region of the third main body portion and the second main body portion is more than 70% of the area of the orthographic projection of the second main body portion on the substrate.

13. The display substrate according to claim 12, wherein, The first scanning signal line extends in a first direction, and the ratio of the size of the positive projection of the first main body portion on the substrate along a second direction to the size of the positive projection of the first scanning signal line on the substrate along the second direction is greater than or equal to 5; and / or, The second scanning signal line extends in a first direction, and the ratio of the size of the positive projection of the third main body portion on the substrate along a second direction to the size of the positive projection of the second scanning signal line on the substrate along the second direction is greater than or equal to 5.

14. The display substrate according to claim 6, wherein, The display substrate includes: a fourth conductive layer on a side of the third conductive layer away from the substrate, and a fifth conductive layer on a side of the fourth conductive layer away from the substrate; The first voltage line is located in the fifth conductive layer, the display substrate includes a compensation connection portion in the fourth conductive layer, and the second compensation structure is electrically connected to the first voltage line through the compensation connection portion.

15. The display substrate according to claim 14, wherein, The display substrate further includes a fifth compensation structure located in the fifth conductive layer, and the fifth compensation structure is electrically connected to the first voltage line; and The fourth compensation sub-capacitor includes at least a part of the third compensation structure and at least a part of the fifth compensation structure.

16. The display substrate according to claim 15, wherein, The positive projection of the third compensation structure on the substrate at least partially overlaps with the positive projection of the fifth compensation structure on the substrate.

17. The display substrate according to claim 16, wherein, The fifth compensation structure includes a fifth main body portion, the third compensation structure includes a third main body portion, and the positive projection of the third main body portion on the substrate covers the positive projection of the fifth main body portion on the substrate.

18. The display substrate according to any one of claims 4, 15-17, wherein, The display substrate further includes a sixth conductive layer on a side of the first semiconductor layer close to the substrate; The display substrate further includes a fourth compensation structure in the sixth conductive layer, and the positive projection of the first compensation structure on the substrate at least partially overlaps with the positive projection of the fourth compensation structure on the substrate.

19. The display substrate according to claim 18, wherein, The second compensation sub-capacitor includes at least a part of the first compensation structure and at least a part of the fourth compensation structure.

20. The display substrate according to claim 19, wherein, The fourth compensation structure includes a fourth main body portion, the first compensation structure includes a first main body portion, and the positive projection of the first main body portion on the substrate covers the positive projection of the fourth main body portion on the substrate.

21. The display substrate according to claim 17, wherein, The size of the fifth main body portion of the fifth compensation structure along the first direction is greater than the size of the first voltage line along the first direction.

22. The display substrate according to claim 21, wherein, The ratio of the dimension of the fifth main body portion of the fifth compensation structure in the first direction to the dimension of the first voltage line in the first direction is greater than or equal to 3.

23. The display substrate according to claim 17, 21 or 22, wherein, In two adjacent virtual sub-pixel structures, the two fifth main body portions are connected to each other, and the orthographic projection of the two connected fifth main body portions on the substrate is in a rectangular shape.

24. The display substrate according to any one of claims 1-4, wherein, For two sub-pixels adjacent in the first direction, the orthographic projection of their pixel driving circuits on the substrate is axisymmetric with respect to a first axis of symmetry, and the first axis of symmetry extends in the second direction.

25. The display substrate according to any one of claims 1-4, wherein, For two virtual sub-pixel structures adjacent in the first direction, the orthographic projection of the two virtual sub-pixel structures on the substrate is axisymmetric with respect to a second axis of symmetry, and the second axis of symmetry extends in the second direction.

26. The display substrate according to any one of claims 1-4, wherein, At least one of the first scan signal line and the second scan signal line includes a first compensation signal line and a second compensation signal line. The first compensation signal line is electrically connected to multiple sub-pixels in one row of sub-pixels and at least one first virtual sub-pixel structure, and the second compensation signal line is electrically connected to multiple sub-pixels in another row of sub-pixels and at least one first virtual sub-pixel structure; and The number of sub-pixels electrically connected by the first compensation signal line is less than the number of sub-pixels electrically connected by the second compensation signal line, and the number of first virtual sub-pixel structures electrically connected by the first compensation signal line is more than the number of first virtual sub-pixel structures electrically connected by the second compensation signal line.

27. The display substrate according to any one of claims 1-4, wherein, Both the first scan signal line and the second scan signal line extend in the first direction; and In the first virtual pixel region, the multiple virtual sub-pixel structures are arranged in the first direction and the second direction, and the number of virtual sub-pixel structures in the same row first increases and then decreases in the second direction.

28. A display panel, comprising the display substrate according to any one of claims 1-27.

29. A display device, comprising the display substrate according to any one of claims 1-27 or the display panel according to claim 28.

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