Semiconductor structure preparation method and semiconductor structure

Abstract

The embodiments of the present disclosure provide a method for preparing a semiconductor structure and a semiconductor structure. The method for preparing the semiconductor structure includes: providing a semiconductor substrate, on which a groove is formed; introducing a first germanium source gas or a mixed gas of a first germanium source gas and a first silicon source gas to form a filling layer on the surface of the groove; introducing a boron source gas, a second germanium source gas, and a second silicon source gas to form doped polysilicon, and depositing it in the groove formed with the filling layer to form a conductor filling structure. The method for preparing the semiconductor structure of the embodiments of the present disclosure enables a uniform germanium seed layer or a germanium silicon seed layer to be formed on the surface of the groove, so that subsequent filling is more complete, voids are avoided, and the stability and electrical performance of the semiconductor structure are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device having a plurality of repeated memory cells, each of which includes a capacitor.

[0003] In existing capacitors, germanium-doped polysilicon is deposited to fill the upper electrode in the capacitor to form a conductor structure that serves as a grounding function. However, as the size of DRAM continues to shrink, existing germanium-doped polysilicon is prone to forming gaps, which will greatly affect the stability of the capacitor structure and the conductive performance of the capacitor.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0005] One purpose of the present disclosure is to provide a method for preparing a semiconductor structure, so that the conductor filling structure is filled more completely, thereby improving the stability and electrical performance of the semiconductor structure.

[0006] Another object of the present disclosure is to provide a semiconductor structure having stable electrical properties.

[0007] According to one aspect of the present disclosure, a method for preparing a semiconductor structure is provided, comprising: providing a semiconductor substrate having a groove formed thereon; introducing a first germanium source gas or a mixed gas of a first germanium source gas and a first silicon source gas to form a filling layer on the surface of the groove; introducing a boron source gas, a second germanium source gas, and a second silicon source gas to form doped polysilicon, and depositing the doped polysilicon in the groove having the filling layer formed thereon to form a conductor filling structure.

[0008] According to an exemplary embodiment of the present disclosure, the flow rate of the first germanium source gas is 10 sccm to 300 sccm, and the flow rate of the first silicon source gas is 0 sccm to 3000 sccm.

[0009] According to an exemplary embodiment of the present disclosure, the flow rate of the boron source gas is 10 sccm to 1000 sccm, the flow rate of the second germanium source gas is 100 sccm to 3000 sccm, and the flow rate of the second silicon source gas is 100 sccm to 3000 sccm.

[0010] According to an exemplary embodiment of the present disclosure, the reaction temperature of introducing the first germanium source gas or the mixed gas of the first germanium source gas and the first silicon source gas to form a filling layer on the groove surface is 270° C. to 370° C., and the reaction pressure is 25 mTorr to 200 mTorr.

[0011] According to an exemplary embodiment of the present disclosure, the boron source gas, the second germanium source gas and the second silicon source gas are introduced to form doped polysilicon, and deposited in the groove formed with the filling layer to form a semiconductor filling structure. The reaction temperature is 350°C to 400°C, and the reaction pressure is 100mTorr to 400mTorr.

[0012] According to an exemplary embodiment of the present disclosure, the thickness of the filling layer is 0.2% to 1% of the thickness of the conductor filling structure.

[0013] According to an exemplary embodiment of the present disclosure, the thickness of the filling layer is 0.5 nm to 2 nm.

[0014] According to an exemplary embodiment of the present disclosure, the grain size of the filling layer is 0.1-1 nm.

[0015] According to an exemplary embodiment of the present disclosure, the grain size of the conductor filling structure is 1-50 nm.

[0016] According to an exemplary embodiment of the present disclosure, the first germanium source gas and the second germanium source gas are each GeH 4 and Ge 2 H 6 At least one of .

[0017] According to an exemplary embodiment of the present disclosure, the first silicon source gas and the second silicon source gas are each divided into SiH 4 and Si 2 H 6 At least one of .

[0018] According to an exemplary embodiment of the present disclosure, before the introduction of the first germanium source gas or the mixed gas of the first germanium source gas and the first silicon source gas to form a filling layer on the surface of the groove, the process further includes: cleaning the semiconductor substrate.

[0019] According to an exemplary embodiment of the present disclosure, the cleaning of the semiconductor substrate includes: placing the semiconductor substrate in an alkaline solution to remove oil stains and acidic impurities on the surface of the semiconductor substrate, and rinsing with clean water; placing the semiconductor substrate in an acidic solution to remove alkaline impurities on the surface of the semiconductor substrate, and rinsing with clean water; placing the semiconductor substrate in an organic solvent to remove residual impurities on the surface of the semiconductor substrate, and drying the semiconductor substrate.

[0020] According to an exemplary embodiment of the present disclosure, the cleaning of the semiconductor substrate includes: continuously purging the surface of the semiconductor substrate with nitrogen gas to reduce the impurity concentration on the surface of the semiconductor substrate.

[0021] According to an exemplary embodiment of the present disclosure, the cleaning of the semiconductor substrate further comprises: using nitrogen to purge a carrier that supports the semiconductor substrate, so as to reduce the water and oxygen concentration in the carrier.

[0022] According to an exemplary embodiment of the present disclosure, providing a semiconductor base includes: providing a semiconductor substrate, and forming a capacitor contact node on the semiconductor substrate; forming a stacked support layer and a sacrificial layer on the semiconductor substrate, and forming a capacitor hole at a position of the support layer and the sacrificial layer corresponding to the capacitor contact node; forming a lower electrode layer on the inner wall of the capacitor hole; forming a capacitor dielectric layer on the surface of the lower electrode layer; forming an upper electrode layer on the surface of the capacitor dielectric layer; wherein the capacitor hole after forming the upper electrode layer is the groove.

[0023] According to an exemplary embodiment of the present disclosure, the filling layer and the conductor filling structure are formed by low-pressure chemical vapor deposition.

[0024] According to another aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure is prepared by the method described in any one of the above embodiments.

[0025] It can be seen from the above technical solution that the present disclosure has at least one of the following advantages and positive effects:

[0026] In the preparation method of the disclosed embodiment, during the pre-filling stage, only the first germanium source gas or a mixed gas of the first germanium source gas and the first silicon source gas is introduced without simultaneously introducing the boron source gas, thereby avoiding the generation of hydrogen chloride gas and further avoiding the negative impact of the hydrogen chloride gas on the filling effect, so that a uniform germanium seed layer or a germanium silicon seed layer can be formed on the surface of the groove, making subsequent filling more complete, avoiding the generation of voids, and improving the stability of the semiconductor structure and the electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0028] Figure 1 is a flow chart of a method for preparing a semiconductor structure in some exemplary embodiments of the present disclosure;

[0029] Figure 2 It is a schematic diagram of introducing a first germanium source gas onto a semiconductor substrate having grooves formed thereon in some exemplary embodiments of the present disclosure;

[0030] Figure 3 A schematic diagram of forming a filling layer on the surface of a trench of a semiconductor substrate in some exemplary embodiments of the present disclosure, and continuing to introduce a boron source gas, a second germanium source gas, and a second silicon source gas;

[0031] Figure 4 is a schematic diagram of a semiconductor substrate having a conductor filling structure formed thereon in some exemplary embodiments of the present disclosure;

[0032] Figure 5 Schematic diagram of a semiconductor substrate with grooves formed therein in some other exemplary embodiments of the present disclosure;

[0033] Figure 6 A schematic diagram of a semiconductor substrate for forming a filling layer on the surface of a groove in some other exemplary embodiments of the present disclosure;

[0034] Figure 7 Schematic diagram of a semiconductor substrate with a conductor filling structure formed in a trench in some other exemplary embodiments of the present disclosure.

[0035] Description of reference numerals:

[0036] 1. Semiconductor base; 11. Semiconductor substrate; 12. Support layer; 13. Lower electrode layer; 14. Capacitor dielectric layer; 15. Upper electrode layer; 16. Capacitor contact node; 2. Groove; 3. Filling layer; 4. Conductor filling structure; d1. Thickness of filling layer; d2. Thickness of conductor filling structure. DETAILED DESCRIPTION

[0037] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0038] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which different exemplary structures that can implement multiple aspects of the present disclosure are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional direction of the structure to fall within the scope of the present disclosure. In addition, the terms "first", "second", etc. in the claims are used only as marks and are not numerical limitations on their objects.

[0039] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0040] In addition, in the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined. "Above" and "below" are technical terms indicating directions, which are only used to make the description clearer and have no limiting effect.

[0041] like Figures 1 to 7 As shown, the embodiment of the present disclosure provides a method for preparing a semiconductor structure. Figure 1 A flow chart showing a preparation method of some exemplary embodiments of the present disclosure is shown. Figure 2 It is a schematic diagram of introducing a first germanium source gas onto a semiconductor substrate having grooves formed thereon in some exemplary embodiments of the present disclosure; Figure 3 It is a schematic diagram of forming a filling layer on the surface of a groove of a semiconductor substrate in some exemplary embodiments of the present disclosure, and continuing to introduce a boron source gas, a second germanium source gas, and a second silicon source gas; Figure 4 Schematic diagram of a semiconductor substrate for forming a conductor filling structure in some exemplary embodiments of the present disclosure; in order to more clearly illustrate the formation process of the filling layer and the conductor filling structure, Figures 2 to 4 It can be understood that these are enlarged views and only show the formation of a filling layer and a conductor filling structure on the surface of a groove 2. These views are only schematic and have no limiting meaning. Figure 5 Schematic diagrams showing a semiconductor substrate having grooves formed therein in some other exemplary embodiments of the present disclosure; Figure 6A schematic diagram showing a semiconductor substrate with a filling layer formed on the surface of a groove in some other exemplary embodiments of the present disclosure; Figure 7 Schematic diagrams of semiconductor substrates with conductor filling structures formed in trenches in some other exemplary embodiments of the present disclosure are shown. Figures 1 to 4 As shown, the method for preparing the semiconductor structure of the embodiment of the present disclosure includes:

[0042] Step S200 : providing a semiconductor substrate 1 , on which a trench 2 is formed.

[0043] Step S400 : introducing a first germanium source gas or a mixed gas of the first germanium source gas and the first silicon source gas to form a filling layer 3 on the surface of the trench 2 .

[0044] Step S600 : introducing a boron source gas, a second germanium source gas and a second silicon source gas to form doped polysilicon, and depositing the doped polysilicon in the trench 2 where the filling layer 3 is formed, so as to form a conductor filling structure 4 .

[0045] In the preparation method of the disclosed embodiment, during the pre-filling stage, only the first germanium source gas or the mixed gas of the first germanium source gas and the first silicon source gas is introduced without introducing the boron source gas at the same time, so that the generation of hydrogen chloride gas can be avoided, and the negative impact of the hydrogen chloride gas on the filling effect can be avoided, so that a uniform germanium seed layer or a germanium silicon seed layer can be formed on the surface of the groove 2, so that the subsequent filling is more complete, the generation of gaps can be avoided, and the stability and electrical performance of the semiconductor structure are improved.

[0046] The following is a detailed description of the method for preparing the semiconductor structure according to the embodiment of the present disclosure.

[0047] Step S200 : providing a semiconductor substrate 1 , on which a trench 2 is formed.

[0048] like Figure 2 As shown, the semiconductor base 1 of the embodiment of the present disclosure includes a semiconductor substrate 11 and a functional layer located on the semiconductor substrate 11, and a groove 2 is opened on the functional layer.

[0049] In some embodiments, the material of the semiconductor substrate 11 of the embodiment of the present disclosure may be silicon, silicon carbide, silicon nitride, silicon on insulator, stacked silicon on insulator, stacked silicon germanium on insulator, silicon germanium on insulator, or germanium on insulator, etc. The semiconductor substrate 11 may also be implanted with certain doping particles to change electrical parameters according to design requirements.

[0050] In some embodiments, the functional layer may be a capacitor structure, and the groove 2 is a capacitor hole of the capacitor structure. Figure 5 As shown, the preparation method of the embodiment of the present disclosure also includes the following steps:

[0051] Step S101 : providing a semiconductor substrate 11 , and forming a capacitor contact node 16 on the semiconductor substrate 11 .

[0052] Step S102: forming a stacked support layer 12 and a sacrificial layer on the semiconductor substrate 11, and forming capacitor holes at positions of corresponding contact nodes of the support layer 12 and the sacrificial layer.

[0053] The sacrificial layer is arranged on the supporting layer 12, and the supporting layer 12 and the sacrificial layer can be formed by an atomic layer deposition process (Atomic Layer Deposition) or a chemical vapor deposition process (Chemical Vapor Deposition). The material of the supporting layer 12 may include silicon nitride, silicon oxide or silicon oxynitride, and the material of the sacrificial layer may include silicon nitride, silicon oxide or silicon oxynitride. Through capacitor holes are formed on the supporting layer 12 and the sacrificial layer by an etching process. In the embodiment disclosed in the present invention, only one layer of supporting layer 12 is shown by way of example. In the capacitor structure, there may also be multiple layers of supporting layers 12 and sacrificial layers alternately stacked, and the sacrificial layer will be removed in the process of forming the capacitor structure. After removing the sacrificial layer, the supporting layer 12 is used as a supporting frame in the subsequent process to improve the mechanical strength of the capacitor structure and avoid damage to the capacitor structure by subsequent processes.

[0054] The specific structure of the capacitor structure can be known by those skilled in the art according to the known technology, and will not be described in detail here. Figures 5 to 7 The capacitor structure in FIG. 1 is merely an exemplary schematic diagram.

[0055] Step S103: forming a lower electrode layer 13 on the inner wall of the capacitor hole.

[0056] Step S104 : forming a capacitor dielectric layer 14 on the surface of the lower electrode layer 13 .

[0057] Step S105 : forming an upper electrode layer 15 on the surface of the capacitor dielectric layer 14 .

[0058] The lower electrode layer 13 and the upper electrode layer 15 are formed by an atomic layer deposition process or a chemical vapor deposition process, wherein the materials of the lower electrode layer 13 and the upper electrode layer 15 may be the same. In some embodiments, the materials of the lower electrode layer 13 and the upper electrode layer 15 may include at least one of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, etc. The capacitor dielectric layer 14 may be a high-K dielectric layer, and the material of the capacitor dielectric layer 14 may include at least one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, and AlOx.

[0059] After the above step S105 , the capacitor hole filled with the upper electrode layer 15 can serve as the groove 2 in step S200 .

[0060] Step S400 : introducing a first germanium source gas or a mixed gas of the first germanium source gas and the first silicon source gas to form a filling layer 3 on the surface of the trench 2 .

[0061] The semiconductor substrate 1 is placed in a machine platform. Figure 3 and Figure 6 As shown, in some embodiments, a first germanium source gas is introduced into the machine, and in other embodiments, a mixed gas of the first germanium source gas and the first silicon source gas is introduced into the machine to pre-fill the groove 2 of the semiconductor substrate 1, and a filling layer 3 is formed on the surface of the groove 2. When the first germanium source gas is introduced, the filling layer 3 includes a germanium seed layer, and when the mixed gas of the first germanium source gas and the first silicon source gas is introduced, the filling layer 3 is a seed layer including germanium silicon. That is, the filling layer 3 can form a thin layer with a smaller grain size on the surface of the groove 2, and the thin layer can be tightly combined with the surface of the groove 2 to avoid the subsequent conductor filling structure 4 and the surface of the groove 2. In addition, when pre-filling, the boron source gas is not introduced, and when the filling layer 3 is formed, impurity gases such as hydrogen chloride will not be generated, which avoids the impurity gas from affecting the adhesion of the filling layer 3 on the surface of the groove 2, and avoids the formation of holes inside the filling layer 3, so as to ensure the uniformity of the grain size of the filling layer 3.

[0062] In some embodiments, the flow rate of the first germanium source gas is 10 sccm to 300 sccm, for example, the flow rate can be 50 sccm, 100 sccm, 150 sccm, 200 sccm or 300 sccm, and the flow rate of the first silicon source gas is 0 sccm to 3000 sccm, for example, the flow rate can be 500 sccm, 1000 sccm, 1500 sccm, 2000 sccm or 2500 sccm. sccm (standard cubic centimeter per minute) is a volume flow unit: standard milliliter per minute. Those skilled in the art can set the gas flow value within the above range according to the actual process conditions, and no special limitation is made here.

[0063] In some embodiments, the grain size in the filling layer 3 is 0.1 to 1 nm. For example, the grain size may be 0.3 nm, 0.5 nm, 0.7 nm, 0.8 nm or 0.9 nm, which is not specifically limited here. The size of the grains in the filling layer 3 may be adjusted according to the process parameters. For example, during pre-filling, the flow rate of the first germanium source gas or the mixed gas of the first germanium source gas and the first silicon source gas may be adjusted, and the temperature and pressure in the machine during pre-filling may also be adjusted. In the disclosed embodiment, the grain size in the germanium seed layer or the germanium silicon seed layer in the filling layer 3 is between 0.1 and 1 nm, which can be fully attached to the surface of the groove 2 and form a uniform film layer to avoid the formation of a gap between the filling layer 3 and the surface of the groove 2.

[0064] In some embodiments, during pre-filling, a first germanium source gas or a mixed gas of the first germanium source gas and the first silicon source gas is introduced, and the reaction temperature for forming the filling layer 3 on the surface of the groove 2 is 270°C to 370°C, for example, the temperature may be 300°C, 320°C, 340°C, 350°C or 360°C, and the reaction pressure is 25mTorr to 200mTorr, for example, the reaction pressure may be 50mTorr, 100mTorr, 120mTorr, 150mTorr or 180mTorr. By regulating the temperature and pressure of the pre-filling, the size of the grains in the filling layer 3, the film thickness of the filling layer 3 and the uniformity of the film can be controlled. Therefore, the temperature and reaction pressure can be adjusted within the above range according to the actual situation, so that the filling layer 3 can be more stably formed on the surface of the groove 2. As for the setting of specific numerical values, no special limitation is made here.

[0065] In actual operation, before pre-filling the semiconductor substrate 1, the semiconductor substrate 1 needs to be cleaned. Therefore, in the embodiment of the present disclosure, before the first germanium source gas or the mixed gas of the first germanium source gas and the first silicon source gas is introduced to form the filling layer 3 on the surface of the groove 2, step S300 may be further included: cleaning the semiconductor substrate 1.

[0066] In the process of forming the trench 2 in the semiconductor substrate 1, different semiconductor processes, such as etching process, deposition process, etc., are used. Byproducts and impurities are generated after using these processes. In some embodiments, when the semiconductor substrate 1 is formed as shown in FIG. Figure 5 In the process of forming the capacitor hole (groove 2), the lower electrode layer 13, the capacitor dielectric layer 14 and the upper electrode layer 15 are formed by deposition process. In each process, byproducts and impurities are generated. For example, after the upper electrode layer 15 is formed, HCl and NH 3 Impurities such as MgO2 are attached to the surface of the semiconductor substrate 11 and the surface of the capacitor hole. In order to form the filling layer 3 more stably on the surface of the capacitor hole, these impurities need to be removed.

[0067] In some embodiments, cleaning the semiconductor substrate 1 may include:

[0068] Step S301: placing the semiconductor substrate 1 in an alkaline solution to remove oil stains and acidic impurities on the surface of the semiconductor substrate 1, and then rinsing with clean water.

[0069] The alkaline solution in the above steps may be Na 2 CO 3 Or an ammonia solution with a concentration of less than 5%. Using an alkaline solution to clean the surface of the semiconductor substrate 1 can effectively remove organic matter such as oil stains on the surface of the semiconductor substrate 1. Clean water can be high-purity deionized water to avoid the introduction of other impurities.

[0070] Step S302: placing the semiconductor substrate 1 in an acidic solution to remove alkaline impurities on the surface of the semiconductor substrate 1, and rinsing with clean water.

[0071] The acidic solution can be a hydrochloric acid solution, a sulfuric acid solution or a nitric acid solution, and the concentration of each is less than 5%. The acidic solution can not only neutralize the alkaline substances remaining on the surface of the semiconductor substrate 1, but also further remove inorganic compounds attached to the surface of the semiconductor substrate 1, such as various metal oxides. At the same time, controlling the concentration of the acidic solution to less than 5% can prevent the acidic solution from corroding the surface of the semiconductor substrate 1 and causing damage to the surface of the semiconductor substrate 1. Clean water can use high-purity deionized water to avoid introducing other impurities.

[0072] Step S303: placing the semiconductor substrate 1 in an organic solvent to remove residual impurities on the surface of the semiconductor substrate 1 and drying the semiconductor substrate 1 .

[0073] The organic solvent may be acetone, which can dissolve most non-polar substances, and the boiling point of acetone is 56° C., which is highly volatile. Therefore, placing the semiconductor substrate 1 in the acetone solvent can further remove non-polar impurities attached to the surface of the semiconductor substrate 1, and due to the volatility of acetone, after the semiconductor substrate 1 is taken out of the acetone, the acetone will evaporate quickly, and no other means are needed to remove the acetone. The organic solvent may also be toluene.

[0074] After the semiconductor substrate 1 is cleaned in the above steps, the surface of the semiconductor substrate 1 can be purged with an inert gas to further remove impurities attached to the surface of the semiconductor substrate 1. The inert gas can be Ar, N 2 or NF 3 , no special limitation is made here.

[0075] In some embodiments, before the cleaned semiconductor is sent into the machine, nitrogen is used to purge the carrier that supports the semiconductor substrate 1 to reduce the water and oxygen concentration in the carrier to prevent the impurities on the carrier from secondary contaminating the semiconductor substrate 1 .

[0076] The semiconductor substrate 1 is placed in the machine, and before pre-filling, nitrogen is introduced into the machine to make the oxygen concentration in the machine reach below 10ppm, so as to prevent the residual oxygen on the surface of the semiconductor substrate 1 from interfering with the polysilicon deposition in the subsequent process. After confirming that there is no abnormality in the machine, the inside of the machine is vacuumed to further remove the external impurity gas attached to the surface of the semiconductor substrate 1. In some embodiments, the machine can be a low pressure chemical vapor deposition (LPCVD) machine.

[0077] By cleaning the semiconductor substrate 1 and adjusting the machine, good conditions are provided for the subsequent formation of a stable filling layer 3 and a conductor filling structure 4 .

[0078] Step S600 : introducing a boron source gas, a second germanium source gas and a second silicon source gas to form doped polysilicon, and depositing the doped polysilicon in the trench 2 where the filling layer 3 is formed, so as to form a conductor filling structure 4 .

[0079] like Figure 4 and Figure 7 As shown, after forming the filling layer 3, a deposition process can be used to fill the trench 2 with a conductor filling structure 4. The second silicon source gas can react with the boron source gas and the second germanium source gas to form germanium-doped polysilicon, and the germanium-doped polysilicon forms the conductor filling structure 4.

[0080] In the process of forming the conductor filling structure 4 , the boron source gas is introduced to introduce the boron element, thereby adjusting the grain size and deposition speed of the conductor filling structure 4 .

[0081] In some embodiments, the first germanium source gas and the second germanium source gas may be GeH 4 and Ge 2 H 6 The first germanium source gas and the second germanium source gas may be of the same gas type, so as to reduce the operation of changing the gas and simplify the process.

[0082] In some embodiments, the first silicon source gas and the second silicon source gas are each SiH 4 and Si 2 H 6The first silicon source gas and the second silicon source gas may be of the same gas type to reduce the operation of changing the gas and simplify the process. The boron source gas may be BCl 3 .

[0083] In some embodiments, the flow rate of the boron source gas is 10 sccm to 1000 sccm, for example, the flow rate of the boron source gas can be 100 sccm, 200 sccm, 500 sccm, 800 sccm or 900 sccm, and the flow rate of the second germanium source gas is 100 sccm to 3000 sccm, for example, the flow rate of the second germanium source gas can be 500 sccm, 1000 sccm, 1500 sccm, 2000 sccm or 2500 sccm. The flow rate of the second silicon source gas is 100 sccm to 3000 sccm, for example, the flow rate of the second silicon source gas can be 500 sccm, 1000 sccm, 1500 sccm, 2000 sccm or 2500 sccm. Those skilled in the art can set the gas flow value within the above range according to the actual process conditions, and no special limitation is made here.

[0084] In some embodiments, the grain size of the conductor filling structure 4 is 1 to 50 nm. For example, the grain size may be 5 nm, 10 nm, 20 nm, 30 nm or 40 nm, which is not specifically limited here. The size of the grains filling the conductor structure can be adjusted according to the process parameters. For example, the flow rates of the boron source gas, the second germanium source gas and the second silicon source gas can be adjusted, and the temperature and pressure in the machine can also be adjusted. In the present disclosure, the grain size of the formed conductor filling structure 4 is in the range of 1 to 50 nm. The grain size is relatively small. For the groove 2 with a larger aspect ratio, the smaller grain size makes it easier to fill, and the formed conductor filling structure 4 is more compact and will not produce holes. The above-mentioned aspect ratio can be understood as Figure 7 In the cross section of the semiconductor substrate 1 shown, the ratio of the dimension of the groove 2 in the direction perpendicular to the semiconductor substrate 11 to the dimension in the direction parallel to the semiconductor substrate 11. In addition, since a uniform filling layer 3 has been formed on the surface of the groove 2, the filling layer 3 can not only be stably formed on the surface of the groove 2, but also be stably combined with the conductor filling structure 4. That is, no grain boundary dislocation or stress will be generated at the contact surface between the filling layer 3 and the conductor filling structure 4, thereby avoiding defects at the contact surface between the two, further improving the stability of the conductor filling structure 4, and compared with the conductor filling structure 4 directly contacting the surface of the groove 2, the conductor filling structure 4 of the embodiment of the present disclosure can be more stably filled in the groove 2.

[0085] In some embodiments, the reaction temperature for forming the semiconductor filling structure 4 in step S600 is 350°C to 400°C, for example, the temperature may be 360°C, 370°C, 380°C or 390°C, and the reaction pressure is 100mTorr to 400mTorr, for example, the pressure may be 150mTorr, 200mTorr, 250mTorr, 300mTorr or 350mTorr, and no special limitation is made here regarding the specific values. By increasing the reaction temperature and the reaction pressure, it is beneficial for the conductor filling structure 4 to form the above-mentioned smaller-sized grains, so that the doped polysilicon formed by the boron source gas, the second germanium source gas and the second silicon source gas during the deposition process can be filled into the bottom of the groove 2 where the filling layer 3 is formed, filling the groove 2, and filling more completely, avoiding the generation of holes inside the conductor filling structure 4, and avoiding the generation of gaps between the conductor filling structure 4 and the groove 2, thereby improving the stability and electrical performance of the semiconductor structure.

[0086] In some embodiments, the thickness d1 of the filling layer 3 is 0.5-2 nm. For example, the thickness d1 of the filling layer 3 may be 0.8 nm, 1 nm, 1.2 nm, 1.5 nm or 1.8 nm, which is not particularly limited herein. The thickness d1 of the filling layer 3 may be adjusted by regulating the flow rate of the first germanium source gas or the mixed gas of the first germanium source gas and the first silicon source gas, or by adjusting the reaction temperature and reaction pressure during pre-filling.

[0087] In some embodiments, the thickness d1 of the filling layer 3 is 0.2% to 1% of the thickness d2 of the conductor filling structure 4. Specifically, it can be 0.4%, 0.5%, 0.7% or 0.8%, which is not particularly limited here. It should be noted that the thickness d1 of the filling layer 3 can be understood as the thickness of the filling layer 3 in a direction parallel to the surface of the semiconductor substrate 11. The thickness d2 of the conductor filling structure 4 can be understood as the thickness of the conductor filling structure 4 filled in a trench 2 in a direction parallel to the surface of the semiconductor substrate 11, such as Figure 7 shown.

[0088] Therefore, the thickness d1 of the filling layer 3 of the embodiment of the present disclosure is much smaller than the thickness d2 of the conductor filling structure 4, that is, the amount of the filling layer 3 is very small compared to the amount of the conductor filling structure 4. Therefore, the filling layer 3 can not only be stably formed on the surface of the groove 2, but also be stably combined with the conductor filling structure 4 to improve the stability of the conductor filling structure 4. The filling layer 3 will not affect the electrical performance of the semiconductor structure.

[0089] In some embodiments, the deposition process used for the filling layer 3 and the conductor filling structure 4 can both be a low-pressure chemical vapor deposition process.

[0090] It should be noted that the semiconductor structure of the embodiment of the present disclosure may be a capacitor structure, the trench 2 is the capacitor hole in the above embodiment, and the filling layer 3 and the conductor filling structure 4 are the capacitor plates in the capacitor structure.

[0091] To sum up, in the preparation method of the embodiment of the present disclosure, during the pre-filling stage, only the first germanium source gas or the mixed gas of the first germanium source gas and the first silicon source gas is introduced without introducing the boron source gas at the same time, which can avoid the generation of hydrogen chloride gas and further avoid the negative impact of the hydrogen chloride gas on the filling effect, so that a uniform germanium seed layer or a germanium silicon seed layer can be formed on the surface of the groove 2, making the subsequent filling more complete, avoiding the generation of gaps, and improving the stability of the semiconductor structure and the electrical performance.

[0092] According to another aspect of the present disclosure, Figure 4 and Figure 7 As shown, a semiconductor structure is provided. The semiconductor structure of the embodiment of the present disclosure is prepared by the method of any of the above embodiments.

[0093] In some embodiments, Figure 4 As shown, the semiconductor structure includes a semiconductor substrate 1 , a trench 2 is formed on the semiconductor substrate 1 , a filling layer 3 is formed on the surface of the trench 2 , a conductor filling structure 4 is formed on the surface of the filling layer 3 , and the conductor filling structure 4 fills the trench 2 .

[0094] like Figure 7 As shown, in some embodiments, the semiconductor structure can be a capacitor structure. The capacitor structure includes: a semiconductor substrate 11, a support layer 12, a lower electrode layer 13, a capacitor dielectric layer 14, an upper electrode layer 15, a filling layer 3 and a conductor filling structure 4. The semiconductor substrate 11 is provided with a capacitor contact node 16. The lower electrode layer 13, the capacitor dielectric layer 14 and the upper electrode layer 15 form a columnar unit on the semiconductor substrate 11, such as Figure 7 As shown, the semiconductor structure of the embodiment of the present disclosure has a plurality of spaced columnar units, and the lower electrode layer 13 is in contact with the capacitor contact node 16, and a groove 2 is formed between two adjacent columnar units. The support layer 12 is arranged on the semiconductor substrate 11 at intervals and is located between adjacent lower electrode layers 13. The filling layer 3 is formed on the surface of the groove 2, and the filling layer 3 includes a germanium seed layer or a germanium silicon seed layer. The conductor filling structure 4 is filled in the groove 2 after the filling layer 3 is formed, and fills the groove 2. The conductor filling structure 4 is polysilicon doped with germanium. Other descriptions about the semiconductor structure are the same as the above method embodiment, and will not be repeated here.

[0095] The semiconductor structure of the embodiment of the present disclosure has a filling layer 3 first formed on the surface of the groove 2, so that a uniform germanium seed layer or germanium silicon seed layer can be formed on the surface of the groove 2, making the subsequent filling more complete, and the conductor filling structure 4 will not have gaps. Therefore, the semiconductor structure prepared using the embodiment of the present disclosure has more stable electrical properties.

[0096] It is understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein a groove is formed on the semiconductor substrate; Only the first germanium source gas or the mixed gas of the first germanium source gas and the first silicon source gas is introduced without introducing the boron source gas at the same time, so as to form a filling layer on the surface of the groove; Passing a boron source gas, a second germanium source gas, and a second silicon source gas to form doped polysilicon, and depositing the doped polysilicon in the trench where the filling layer is formed to form a conductor filling structure; The method of providing a semiconductor substrate comprises: Providing a semiconductor substrate, and forming a capacitor contact node on the semiconductor substrate; Forming a stacked support layer and a sacrificial layer on the semiconductor substrate, and forming capacitor holes at positions of the support layer and the sacrificial layer corresponding to the capacitor contact nodes; forming a lower electrode layer on the inner wall of the capacitor hole; forming a capacitor dielectric layer on the surface of the lower electrode layer; forming an upper electrode layer on the surface of the capacitor dielectric layer; Wherein, the capacitor hole after forming the upper electrode layer is the groove; Before the first germanium source gas or the mixed gas of the first germanium source gas and the first silicon source gas is introduced to form a filling layer on the surface of the groove, the method further includes: cleaning the semiconductor substrate; The cleaning of the semiconductor substrate comprises: Placing the semiconductor substrate in an alkaline solution to remove oil stains and acidic impurities on the surface of the semiconductor substrate, and then rinsing with clean water; Placing the semiconductor substrate in an acidic solution to remove alkaline impurities on the surface of the semiconductor substrate, and rinsing with clean water; The semiconductor substrate is placed in an organic solvent to remove residual impurities on the surface of the semiconductor substrate, and the semiconductor substrate is dried.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The flow rate of the first germanium source gas is 10 sccm-300 sccm, and the flow rate of the first silicon source gas is 0 sccm-3000 sccm.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The flow rate of the boron source gas is 10 sccm to 1000 sccm, the flow rate of the second germanium source gas is 100 sccm to 3000 sccm, and the flow rate of the second silicon source gas is 100 sccm to 3000 sccm.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The reaction temperature of introducing the first germanium source gas or the mixed gas of the first germanium source gas and the first silicon source gas to form a filling layer on the surface of the groove is 270° C. to 370° C., and the reaction pressure is 25 mTorr to 200 mTorr.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The boron source gas, the second germanium source gas and the second silicon source gas are introduced to form doped polysilicon, and deposited in the groove formed with the filling layer to form a semiconductor filling structure. The reaction temperature is 350°C~400°C and the reaction pressure is 100mTorr~400mTorr.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the filling layer is 0.2% to 1% of the thickness of the conductor filling structure.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The thickness of the filling layer is 0.5nm~2nm.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The grain size of the filling layer is 0.1-1 nm.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The grain size of the conductor filling structure is 1-50 nm.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first germanium source gas and the second germanium source gas are each at least one of GeH4 and Ge2H6.

11. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first silicon source gas and the second silicon source gas are each divided into at least one of SiH4 and Si2H6.

12. The method for preparing a semiconductor structure according to claim 1, characterized in that: The cleaning of the semiconductor substrate includes: continuously sweeping the surface of the semiconductor substrate with nitrogen gas to reduce the impurity concentration on the surface of the semiconductor substrate.

13. The method for preparing a semiconductor structure according to claim 1 or 12, characterized in that: The cleaning of the semiconductor substrate further comprises: using nitrogen to purge a carrier that supports the semiconductor substrate, so as to reduce the water and oxygen concentration in the carrier.

14. The method for preparing a semiconductor structure according to claim 1, characterized in that: The filling layer and the conductor filling structure are formed by low-pressure chemical vapor deposition.

15. A semiconductor structure, characterized in that: Prepared by the method according to any one of claims 1 to 14.

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